3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_mac.c - All code and routines pertaining to the MAC
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
58 #include "et131x_version.h"
59 #include "et131x_defs.h"
61 #include <linux/init.h>
62 #include <linux/module.h>
63 #include <linux/types.h>
64 #include <linux/kernel.h>
66 #include <linux/sched.h>
67 #include <linux/ptrace.h>
68 #include <linux/ctype.h>
69 #include <linux/string.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
73 #include <linux/delay.h>
75 #include <linux/bitops.h>
76 #include <linux/pci.h>
77 #include <asm/system.h>
79 #include <linux/netdevice.h>
80 #include <linux/etherdevice.h>
81 #include <linux/skbuff.h>
82 #include <linux/if_arp.h>
83 #include <linux/ioport.h>
84 #include <linux/crc32.h>
86 #include "et1310_phy.h"
87 #include "et131x_adapter.h"
91 #define COUNTER_WRAP_28_BIT 0x10000000
92 #define COUNTER_WRAP_22_BIT 0x400000
93 #define COUNTER_WRAP_16_BIT 0x10000
94 #define COUNTER_WRAP_12_BIT 0x1000
96 #define COUNTER_MASK_28_BIT (COUNTER_WRAP_28_BIT - 1)
97 #define COUNTER_MASK_22_BIT (COUNTER_WRAP_22_BIT - 1)
98 #define COUNTER_MASK_16_BIT (COUNTER_WRAP_16_BIT - 1)
99 #define COUNTER_MASK_12_BIT (COUNTER_WRAP_12_BIT - 1)
102 * et1310_config_mac_regs1 - Initialize the first part of MAC regs
103 * @adapter: pointer to our adapter structure
105 void et1310_config_mac_regs1(struct et131x_adapter
*adapter
)
107 struct mac_regs __iomem
*macregs
= &adapter
->regs
->mac
;
112 /* First we need to reset everything. Write to MAC configuration
113 * register 1 to perform reset.
115 writel(0xC00F0000, ¯egs
->cfg1
);
117 /* Next lets configure the MAC Inter-packet gap register */
118 ipg
= 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
119 ipg
|= 0x50 << 8; /* ifg enforce 0x50 */
120 writel(ipg
, ¯egs
->ipg
);
122 /* Next lets configure the MAC Half Duplex register */
123 /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
124 writel(0x00A1F037, ¯egs
->hfdp
);
126 /* Next lets configure the MAC Interface Control register */
127 writel(0, ¯egs
->if_ctrl
);
129 /* Let's move on to setting up the mii management configuration */
130 writel(0x07, ¯egs
->mii_mgmt_cfg
); /* Clock reset 0x7 */
132 /* Next lets configure the MAC Station Address register. These
133 * values are read from the EEPROM during initialization and stored
134 * in the adapter structure. We write what is stored in the adapter
135 * structure to the MAC Station Address registers high and low. This
136 * station address is used for generating and checking pause control
139 station2
= (adapter
->addr
[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT
) |
140 (adapter
->addr
[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT
);
141 station1
= (adapter
->addr
[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT
) |
142 (adapter
->addr
[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT
) |
143 (adapter
->addr
[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT
) |
145 writel(station1
, ¯egs
->station_addr_1
);
146 writel(station2
, ¯egs
->station_addr_2
);
148 /* Max ethernet packet in bytes that will passed by the mac without
149 * being truncated. Allow the MAC to pass 4 more than our max packet
150 * size. This is 4 for the Ethernet CRC.
152 * Packets larger than (registry_jumbo_packet) that do not contain a
153 * VLAN ID will be dropped by the Rx function.
155 writel(adapter
->registry_jumbo_packet
+ 4, ¯egs
->max_fm_len
);
157 /* clear out MAC config reset */
158 writel(0, ¯egs
->cfg1
);
162 * et1310_config_mac_regs2 - Initialize the second part of MAC regs
163 * @adapter: pointer to our adapter structure
165 void et1310_config_mac_regs2(struct et131x_adapter
*adapter
)
168 struct mac_regs __iomem
*mac
= &adapter
->regs
->mac
;
174 ctl
= readl(&adapter
->regs
->txmac
.ctl
);
175 cfg1
= readl(&mac
->cfg1
);
176 cfg2
= readl(&mac
->cfg2
);
177 ifctrl
= readl(&mac
->if_ctrl
);
179 /* Set up the if mode bits */
181 if (adapter
->linkspeed
== TRUEPHY_SPEED_1000MBPS
) {
184 ifctrl
&= ~(1 << 24);
190 /* We need to enable Rx/Tx */
191 cfg1
|= CFG1_RX_ENABLE
| CFG1_TX_ENABLE
| CFG1_TX_FLOW
;
192 /* Initialize loop back to off */
193 cfg1
&= ~(CFG1_LOOPBACK
| CFG1_RX_FLOW
);
194 if (adapter
->flowcontrol
== FLOW_RXONLY
||
195 adapter
->flowcontrol
== FLOW_BOTH
)
196 cfg1
|= CFG1_RX_FLOW
;
197 writel(cfg1
, &mac
->cfg1
);
199 /* Now we need to initialize the MAC Configuration 2 register */
200 /* preamble 7, check length, huge frame off, pad crc, crc enable
205 /* Turn on duplex if needed */
206 if (adapter
->duplex_mode
)
209 ifctrl
&= ~(1 << 26);
210 if (!adapter
->duplex_mode
)
211 ifctrl
|= (1<<26); /* Enable ghd */
213 writel(ifctrl
, &mac
->if_ctrl
);
214 writel(cfg2
, &mac
->cfg2
);
219 cfg1
= readl(&mac
->cfg1
);
220 } while ((cfg1
& CFG1_WAIT
) != CFG1_WAIT
&& delay
< 100);
223 dev_warn(&adapter
->pdev
->dev
,
224 "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
229 ctl
|= 0x09; /* TX mac enable, FC disable */
230 writel(ctl
, &adapter
->regs
->txmac
.ctl
);
232 /* Ready to start the RXDMA/TXDMA engine */
233 if (adapter
->flags
& fMP_ADAPTER_LOWER_POWER
) {
234 et131x_rx_dma_enable(adapter
);
235 et131x_tx_dma_enable(adapter
);
239 void et1310_config_rxmac_regs(struct et131x_adapter
*adapter
)
241 struct rxmac_regs __iomem
*rxmac
= &adapter
->regs
->rxmac
;
246 /* Disable the MAC while it is being configured (also disable WOL) */
247 writel(0x8, &rxmac
->ctrl
);
249 /* Initialize WOL to disabled. */
250 writel(0, &rxmac
->crc0
);
251 writel(0, &rxmac
->crc12
);
252 writel(0, &rxmac
->crc34
);
254 /* We need to set the WOL mask0 - mask4 next. We initialize it to
255 * its default Values of 0x00000000 because there are not WOL masks
258 writel(0, &rxmac
->mask0_word0
);
259 writel(0, &rxmac
->mask0_word1
);
260 writel(0, &rxmac
->mask0_word2
);
261 writel(0, &rxmac
->mask0_word3
);
263 writel(0, &rxmac
->mask1_word0
);
264 writel(0, &rxmac
->mask1_word1
);
265 writel(0, &rxmac
->mask1_word2
);
266 writel(0, &rxmac
->mask1_word3
);
268 writel(0, &rxmac
->mask2_word0
);
269 writel(0, &rxmac
->mask2_word1
);
270 writel(0, &rxmac
->mask2_word2
);
271 writel(0, &rxmac
->mask2_word3
);
273 writel(0, &rxmac
->mask3_word0
);
274 writel(0, &rxmac
->mask3_word1
);
275 writel(0, &rxmac
->mask3_word2
);
276 writel(0, &rxmac
->mask3_word3
);
278 writel(0, &rxmac
->mask4_word0
);
279 writel(0, &rxmac
->mask4_word1
);
280 writel(0, &rxmac
->mask4_word2
);
281 writel(0, &rxmac
->mask4_word3
);
283 /* Lets setup the WOL Source Address */
284 sa_lo
= (adapter
->addr
[2] << ET_WOL_LO_SA3_SHIFT
) |
285 (adapter
->addr
[3] << ET_WOL_LO_SA4_SHIFT
) |
286 (adapter
->addr
[4] << ET_WOL_LO_SA5_SHIFT
) |
288 writel(sa_lo
, &rxmac
->sa_lo
);
290 sa_hi
= (u32
) (adapter
->addr
[0] << ET_WOL_HI_SA1_SHIFT
) |
292 writel(sa_hi
, &rxmac
->sa_hi
);
294 /* Disable all Packet Filtering */
295 writel(0, &rxmac
->pf_ctrl
);
297 /* Let's initialize the Unicast Packet filtering address */
298 if (adapter
->packet_filter
& ET131X_PACKET_TYPE_DIRECTED
) {
299 et1310_setup_device_for_unicast(adapter
);
300 pf_ctrl
|= 4; /* Unicast filter */
302 writel(0, &rxmac
->uni_pf_addr1
);
303 writel(0, &rxmac
->uni_pf_addr2
);
304 writel(0, &rxmac
->uni_pf_addr3
);
307 /* Let's initialize the Multicast hash */
308 if (!(adapter
->packet_filter
& ET131X_PACKET_TYPE_ALL_MULTICAST
)) {
309 pf_ctrl
|= 2; /* Multicast filter */
310 et1310_setup_device_for_multicast(adapter
);
313 /* Runt packet filtering. Didn't work in version A silicon. */
314 pf_ctrl
|= (NIC_MIN_PACKET_SIZE
+ 4) << 16;
315 pf_ctrl
|= 8; /* Fragment filter */
317 if (adapter
->registry_jumbo_packet
> 8192)
318 /* In order to transmit jumbo packets greater than 8k, the
319 * FIFO between RxMAC and RxDMA needs to be reduced in size
320 * to (16k - Jumbo packet size). In order to implement this,
321 * we must use "cut through" mode in the RxMAC, which chops
322 * packets down into segments which are (max_size * 16). In
323 * this case we selected 256 bytes, since this is the size of
324 * the PCI-Express TLP's that the 1310 uses.
326 * seg_en on, fc_en off, size 0x10
328 writel(0x41, &rxmac
->mcif_ctrl_max_seg
);
330 writel(0, &rxmac
->mcif_ctrl_max_seg
);
332 /* Initialize the MCIF water marks */
333 writel(0, &rxmac
->mcif_water_mark
);
335 /* Initialize the MIF control */
336 writel(0, &rxmac
->mif_ctrl
);
338 /* Initialize the Space Available Register */
339 writel(0, &rxmac
->space_avail
);
341 /* Initialize the the mif_ctrl register
342 * bit 3: Receive code error. One or more nibbles were signaled as
343 * errors during the reception of the packet. Clear this
344 * bit in Gigabit, set it in 100Mbit. This was derived
345 * experimentally at UNH.
346 * bit 4: Receive CRC error. The packet's CRC did not match the
347 * internally generated CRC.
348 * bit 5: Receive length check error. Indicates that frame length
349 * field value in the packet does not match the actual data
350 * byte length and is not a type field.
351 * bit 16: Receive frame truncated.
352 * bit 17: Drop packet enable
354 if (adapter
->linkspeed
== TRUEPHY_SPEED_100MBPS
)
355 writel(0x30038, &rxmac
->mif_ctrl
);
357 writel(0x30030, &rxmac
->mif_ctrl
);
359 /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
360 * filter is always enabled since it is where the runt packets are
361 * supposed to be dropped. For version A silicon, runt packet
362 * dropping doesn't work, so it is disabled in the pf_ctrl register,
363 * but we still leave the packet filter on.
365 writel(pf_ctrl
, &rxmac
->pf_ctrl
);
366 writel(0x9, &rxmac
->ctrl
);
369 void et1310_config_txmac_regs(struct et131x_adapter
*adapter
)
371 struct txmac_regs
*txmac
= &adapter
->regs
->txmac
;
373 /* We need to update the Control Frame Parameters
374 * cfpt - control frame pause timer set to 64 (0x40)
375 * cfep - control frame extended pause timer set to 0x0
377 if (adapter
->flowcontrol
== FLOW_NONE
)
378 writel(0, &txmac
->cf_param
);
380 writel(0x40, &txmac
->cf_param
);
383 void et1310_config_macstat_regs(struct et131x_adapter
*adapter
)
385 struct macstat_regs __iomem
*macstat
=
386 &adapter
->regs
->macstat
;
388 /* Next we need to initialize all the macstat registers to zero on
391 writel(0, &macstat
->txrx_0_64_byte_frames
);
392 writel(0, &macstat
->txrx_65_127_byte_frames
);
393 writel(0, &macstat
->txrx_128_255_byte_frames
);
394 writel(0, &macstat
->txrx_256_511_byte_frames
);
395 writel(0, &macstat
->txrx_512_1023_byte_frames
);
396 writel(0, &macstat
->txrx_1024_1518_byte_frames
);
397 writel(0, &macstat
->txrx_1519_1522_gvln_frames
);
399 writel(0, &macstat
->rx_bytes
);
400 writel(0, &macstat
->rx_packets
);
401 writel(0, &macstat
->rx_fcs_errs
);
402 writel(0, &macstat
->rx_multicast_packets
);
403 writel(0, &macstat
->rx_broadcast_packets
);
404 writel(0, &macstat
->rx_control_frames
);
405 writel(0, &macstat
->rx_pause_frames
);
406 writel(0, &macstat
->rx_unknown_opcodes
);
407 writel(0, &macstat
->rx_align_errs
);
408 writel(0, &macstat
->rx_frame_len_errs
);
409 writel(0, &macstat
->rx_code_errs
);
410 writel(0, &macstat
->rx_carrier_sense_errs
);
411 writel(0, &macstat
->rx_undersize_packets
);
412 writel(0, &macstat
->rx_oversize_packets
);
413 writel(0, &macstat
->rx_fragment_packets
);
414 writel(0, &macstat
->rx_jabbers
);
415 writel(0, &macstat
->rx_drops
);
417 writel(0, &macstat
->tx_bytes
);
418 writel(0, &macstat
->tx_packets
);
419 writel(0, &macstat
->tx_multicast_packets
);
420 writel(0, &macstat
->tx_broadcast_packets
);
421 writel(0, &macstat
->tx_pause_frames
);
422 writel(0, &macstat
->tx_deferred
);
423 writel(0, &macstat
->tx_excessive_deferred
);
424 writel(0, &macstat
->tx_single_collisions
);
425 writel(0, &macstat
->tx_multiple_collisions
);
426 writel(0, &macstat
->tx_late_collisions
);
427 writel(0, &macstat
->tx_excessive_collisions
);
428 writel(0, &macstat
->tx_total_collisions
);
429 writel(0, &macstat
->tx_pause_honored_frames
);
430 writel(0, &macstat
->tx_drops
);
431 writel(0, &macstat
->tx_jabbers
);
432 writel(0, &macstat
->tx_fcs_errs
);
433 writel(0, &macstat
->tx_control_frames
);
434 writel(0, &macstat
->tx_oversize_frames
);
435 writel(0, &macstat
->tx_undersize_frames
);
436 writel(0, &macstat
->tx_fragments
);
437 writel(0, &macstat
->carry_reg1
);
438 writel(0, &macstat
->carry_reg2
);
440 /* Unmask any counters that we want to track the overflow of.
441 * Initially this will be all counters. It may become clear later
442 * that we do not need to track all counters.
444 writel(0xFFFFBE32, &macstat
->carry_reg1_mask
);
445 writel(0xFFFE7E8B, &macstat
->carry_reg2_mask
);
448 void et1310_config_flow_control(struct et131x_adapter
*adapter
)
450 if (adapter
->duplex_mode
== 0) {
451 adapter
->flowcontrol
= FLOW_NONE
;
453 char remote_pause
, remote_async_pause
;
455 et1310_phy_access_mii_bit(adapter
,
456 TRUEPHY_BIT_READ
, 5, 10, &remote_pause
);
457 et1310_phy_access_mii_bit(adapter
,
458 TRUEPHY_BIT_READ
, 5, 11,
459 &remote_async_pause
);
461 if ((remote_pause
== TRUEPHY_BIT_SET
) &&
462 (remote_async_pause
== TRUEPHY_BIT_SET
)) {
463 adapter
->flowcontrol
= adapter
->wanted_flow
;
464 } else if ((remote_pause
== TRUEPHY_BIT_SET
) &&
465 (remote_async_pause
== TRUEPHY_BIT_CLEAR
)) {
466 if (adapter
->wanted_flow
== FLOW_BOTH
)
467 adapter
->flowcontrol
= FLOW_BOTH
;
469 adapter
->flowcontrol
= FLOW_NONE
;
470 } else if ((remote_pause
== TRUEPHY_BIT_CLEAR
) &&
471 (remote_async_pause
== TRUEPHY_BIT_CLEAR
)) {
472 adapter
->flowcontrol
= FLOW_NONE
;
473 } else {/* if (remote_pause == TRUEPHY_CLEAR_BIT &&
474 remote_async_pause == TRUEPHY_SET_BIT) */
475 if (adapter
->wanted_flow
== FLOW_BOTH
)
476 adapter
->flowcontrol
= FLOW_RXONLY
;
478 adapter
->flowcontrol
= FLOW_NONE
;
484 * et1310_update_macstat_host_counters - Update the local copy of the statistics
485 * @adapter: pointer to the adapter structure
487 void et1310_update_macstat_host_counters(struct et131x_adapter
*adapter
)
489 struct ce_stats
*stats
= &adapter
->stats
;
490 struct macstat_regs __iomem
*macstat
=
491 &adapter
->regs
->macstat
;
493 stats
->tx_collisions
+= readl(&macstat
->tx_total_collisions
);
494 stats
->tx_first_collisions
+= readl(&macstat
->tx_single_collisions
);
495 stats
->tx_deferred
+= readl(&macstat
->tx_deferred
);
496 stats
->tx_excessive_collisions
+=
497 readl(&macstat
->tx_multiple_collisions
);
498 stats
->tx_late_collisions
+= readl(&macstat
->tx_late_collisions
);
499 stats
->tx_underflows
+= readl(&macstat
->tx_undersize_frames
);
500 stats
->tx_max_pkt_errs
+= readl(&macstat
->tx_oversize_frames
);
502 stats
->rx_align_errs
+= readl(&macstat
->rx_align_errs
);
503 stats
->rx_crc_errs
+= readl(&macstat
->rx_code_errs
);
504 stats
->rcvd_pkts_dropped
+= readl(&macstat
->rx_drops
);
505 stats
->rx_overflows
+= readl(&macstat
->rx_oversize_packets
);
506 stats
->rx_code_violations
+= readl(&macstat
->rx_fcs_errs
);
507 stats
->rx_length_errs
+= readl(&macstat
->rx_frame_len_errs
);
508 stats
->rx_other_errs
+= readl(&macstat
->rx_fragment_packets
);
512 * et1310_handle_macstat_interrupt
513 * @adapter: pointer to the adapter structure
515 * One of the MACSTAT counters has wrapped. Update the local copy of
516 * the statistics held in the adapter structure, checking the "wrap"
517 * bit for each counter.
519 void et1310_handle_macstat_interrupt(struct et131x_adapter
*adapter
)
524 /* Read the interrupt bits from the register(s). These are Clear On
527 carry_reg1
= readl(&adapter
->regs
->macstat
.carry_reg1
);
528 carry_reg2
= readl(&adapter
->regs
->macstat
.carry_reg2
);
530 writel(carry_reg1
, &adapter
->regs
->macstat
.carry_reg1
);
531 writel(carry_reg2
, &adapter
->regs
->macstat
.carry_reg2
);
533 /* We need to do update the host copy of all the MAC_STAT counters.
534 * For each counter, check it's overflow bit. If the overflow bit is
535 * set, then increment the host version of the count by one complete
536 * revolution of the counter. This routine is called when the counter
537 * block indicates that one of the counters has wrapped.
539 if (carry_reg1
& (1 << 14))
540 adapter
->stats
.rx_code_violations
+= COUNTER_WRAP_16_BIT
;
541 if (carry_reg1
& (1 << 8))
542 adapter
->stats
.rx_align_errs
+= COUNTER_WRAP_12_BIT
;
543 if (carry_reg1
& (1 << 7))
544 adapter
->stats
.rx_length_errs
+= COUNTER_WRAP_16_BIT
;
545 if (carry_reg1
& (1 << 2))
546 adapter
->stats
.rx_other_errs
+= COUNTER_WRAP_16_BIT
;
547 if (carry_reg1
& (1 << 6))
548 adapter
->stats
.rx_crc_errs
+= COUNTER_WRAP_16_BIT
;
549 if (carry_reg1
& (1 << 3))
550 adapter
->stats
.rx_overflows
+= COUNTER_WRAP_16_BIT
;
551 if (carry_reg1
& (1 << 0))
552 adapter
->stats
.rcvd_pkts_dropped
+= COUNTER_WRAP_16_BIT
;
553 if (carry_reg2
& (1 << 16))
554 adapter
->stats
.tx_max_pkt_errs
+= COUNTER_WRAP_12_BIT
;
555 if (carry_reg2
& (1 << 15))
556 adapter
->stats
.tx_underflows
+= COUNTER_WRAP_12_BIT
;
557 if (carry_reg2
& (1 << 6))
558 adapter
->stats
.tx_first_collisions
+= COUNTER_WRAP_12_BIT
;
559 if (carry_reg2
& (1 << 8))
560 adapter
->stats
.tx_deferred
+= COUNTER_WRAP_12_BIT
;
561 if (carry_reg2
& (1 << 5))
562 adapter
->stats
.tx_excessive_collisions
+= COUNTER_WRAP_12_BIT
;
563 if (carry_reg2
& (1 << 4))
564 adapter
->stats
.tx_late_collisions
+= COUNTER_WRAP_12_BIT
;
565 if (carry_reg2
& (1 << 2))
566 adapter
->stats
.tx_collisions
+= COUNTER_WRAP_12_BIT
;
569 void et1310_setup_device_for_multicast(struct et131x_adapter
*adapter
)
571 struct rxmac_regs __iomem
*rxmac
= &adapter
->regs
->rxmac
;
580 /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
581 * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
582 * specified) then we should pass NO multi-cast addresses to the
585 if (adapter
->packet_filter
& ET131X_PACKET_TYPE_MULTICAST
) {
586 /* Loop through our multicast array and set up the device */
587 for (nIndex
= 0; nIndex
< adapter
->multicast_addr_count
;
589 result
= ether_crc(6, adapter
->multicast_list
[nIndex
]);
591 result
= (result
& 0x3F800000) >> 23;
594 hash1
|= (1 << result
);
595 } else if ((31 < result
) && (result
< 64)) {
597 hash2
|= (1 << result
);
598 } else if ((63 < result
) && (result
< 96)) {
600 hash3
|= (1 << result
);
603 hash4
|= (1 << result
);
608 /* Write out the new hash to the device */
609 pm_csr
= readl(&adapter
->regs
->global
.pm_csr
);
610 if ((pm_csr
& ET_PM_PHY_SW_COMA
) == 0) {
611 writel(hash1
, &rxmac
->multi_hash1
);
612 writel(hash2
, &rxmac
->multi_hash2
);
613 writel(hash3
, &rxmac
->multi_hash3
);
614 writel(hash4
, &rxmac
->multi_hash4
);
618 void et1310_setup_device_for_unicast(struct et131x_adapter
*adapter
)
620 struct rxmac_regs __iomem
*rxmac
= &adapter
->regs
->rxmac
;
626 /* Set up unicast packet filter reg 3 to be the first two octets of
627 * the MAC address for both address
629 * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
630 * MAC address for second address
632 * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
633 * MAC address for first address
635 uni_pf3
= (adapter
->addr
[0] << ET_UNI_PF_ADDR2_1_SHIFT
) |
636 (adapter
->addr
[1] << ET_UNI_PF_ADDR2_2_SHIFT
) |
637 (adapter
->addr
[0] << ET_UNI_PF_ADDR1_1_SHIFT
) |
640 uni_pf2
= (adapter
->addr
[2] << ET_UNI_PF_ADDR2_3_SHIFT
) |
641 (adapter
->addr
[3] << ET_UNI_PF_ADDR2_4_SHIFT
) |
642 (adapter
->addr
[4] << ET_UNI_PF_ADDR2_5_SHIFT
) |
645 uni_pf1
= (adapter
->addr
[2] << ET_UNI_PF_ADDR1_3_SHIFT
) |
646 (adapter
->addr
[3] << ET_UNI_PF_ADDR1_4_SHIFT
) |
647 (adapter
->addr
[4] << ET_UNI_PF_ADDR1_5_SHIFT
) |
650 pm_csr
= readl(&adapter
->regs
->global
.pm_csr
);
651 if ((pm_csr
& ET_PM_PHY_SW_COMA
) == 0) {
652 writel(uni_pf1
, &rxmac
->uni_pf_addr1
);
653 writel(uni_pf2
, &rxmac
->uni_pf_addr2
);
654 writel(uni_pf3
, &rxmac
->uni_pf_addr3
);