drivers/misc/sgi-gru/gruhandles.h

   1 /*
   2  * SN Platform GRU Driver
   3  *
   4  *              GRU HANDLE DEFINITION
   5  *
   6  *  Copyright (c) 2008 Silicon Graphics, Inc.  All Rights Reserved.
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; if not, write to the Free Software
  20  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21  */
  22
  23 #ifndef __GRUHANDLES_H__
  24 #define __GRUHANDLES_H__
  25 #include "gru_instructions.h"
  26
  27 /*
  28  * Manifest constants for GRU Memory Map
  29  */
  30 #define GRU_GSEG0_BASE          0
  31 #define GRU_MCS_BASE            (64 * 1024 * 1024)
  32 #define GRU_SIZE                (128UL * 1024 * 1024)
  33
  34 /* Handle & resource counts */
  35 #define GRU_NUM_CB              128
  36 #define GRU_NUM_DSR_BYTES       (32 * 1024)
  37 #define GRU_NUM_TFM             16
  38 #define GRU_NUM_TGH             24
  39 #define GRU_NUM_CBE             128
  40 #define GRU_NUM_TFH             128
  41 #define GRU_NUM_CCH             16
  42
  43 /* Maximum resource counts that can be reserved by user programs */
  44 #define GRU_NUM_USER_CBR        GRU_NUM_CBE
  45 #define GRU_NUM_USER_DSR_BYTES  GRU_NUM_DSR_BYTES
  46
  47 /* Bytes per handle & handle stride. Code assumes all cb, tfh, cbe handles
  48  * are the same */
  49 #define GRU_HANDLE_BYTES        64
  50 #define GRU_HANDLE_STRIDE       256
  51
  52 /* Base addresses of handles */
  53 #define GRU_TFM_BASE            (GRU_MCS_BASE + 0x00000)
  54 #define GRU_TGH_BASE            (GRU_MCS_BASE + 0x08000)
  55 #define GRU_CBE_BASE            (GRU_MCS_BASE + 0x10000)
  56 #define GRU_TFH_BASE            (GRU_MCS_BASE + 0x18000)
  57 #define GRU_CCH_BASE            (GRU_MCS_BASE + 0x20000)
  58
  59 /* User gseg constants */
  60 #define GRU_GSEG_STRIDE         (4 * 1024 * 1024)
  61 #define GSEG_BASE(a)            ((a) & ~(GRU_GSEG_PAGESIZE - 1))
  62
  63 /* Data segment constants */
  64 #define GRU_DSR_AU_BYTES        1024
  65 #define GRU_DSR_CL              (GRU_NUM_DSR_BYTES / GRU_CACHE_LINE_BYTES)
  66 #define GRU_DSR_AU_CL           (GRU_DSR_AU_BYTES / GRU_CACHE_LINE_BYTES)
  67 #define GRU_DSR_AU              (GRU_NUM_DSR_BYTES / GRU_DSR_AU_BYTES)
  68
  69 /* Control block constants */
  70 #define GRU_CBR_AU_SIZE         2
  71 #define GRU_CBR_AU              (GRU_NUM_CBE / GRU_CBR_AU_SIZE)
  72
  73 /* Convert resource counts to the number of AU */
  74 #define GRU_DS_BYTES_TO_AU(n)   DIV_ROUND_UP(n, GRU_DSR_AU_BYTES)
  75 #define GRU_CB_COUNT_TO_AU(n)   DIV_ROUND_UP(n, GRU_CBR_AU_SIZE)
  76
  77 /* UV limits */
  78 #define GRU_CHIPLETS_PER_HUB    2
  79 #define GRU_HUBS_PER_BLADE      1
  80 #define GRU_CHIPLETS_PER_BLADE  (GRU_HUBS_PER_BLADE * GRU_CHIPLETS_PER_HUB)
  81
  82 /* User GRU Gseg offsets */
  83 #define GRU_CB_BASE             0
  84 #define GRU_CB_LIMIT            (GRU_CB_BASE + GRU_HANDLE_STRIDE * GRU_NUM_CBE)
  85 #define GRU_DS_BASE             0x20000
  86 #define GRU_DS_LIMIT            (GRU_DS_BASE + GRU_NUM_DSR_BYTES)
  87
  88 /* Convert a GRU physical address to the chiplet offset */
  89 #define GSEGPOFF(h)             ((h) & (GRU_SIZE - 1))
  90
  91 /* Convert an arbitrary handle address to the beginning of the GRU segment */
  92 #define GRUBASE(h)              ((void *)((unsigned long)(h) & ~(GRU_SIZE - 1)))
  93
  94 /* Test a valid handle address to determine the type */
  95 #define TYPE_IS(hn, h)          ((h) >= GRU_##hn##_BASE && (h) <        \
  96                 GRU_##hn##_BASE + GRU_NUM_##hn * GRU_HANDLE_STRIDE &&   \
  97                 (((h) & (GRU_HANDLE_STRIDE - 1)) == 0))
  98
  99
 100 /* General addressing macros. */
 101 static inline void *get_gseg_base_address(void *base, int ctxnum)
 102 {
 103         return (void *)(base + GRU_GSEG0_BASE + GRU_GSEG_STRIDE * ctxnum);
 104 }
 105
 106 static inline void *get_gseg_base_address_cb(void *base, int ctxnum, int line)
 107 {
 108         return (void *)(get_gseg_base_address(base, ctxnum) +
 109                         GRU_CB_BASE + GRU_HANDLE_STRIDE * line);
 110 }
 111
 112 static inline void *get_gseg_base_address_ds(void *base, int ctxnum, int line)
 113 {
 114         return (void *)(get_gseg_base_address(base, ctxnum) + GRU_DS_BASE +
 115                         GRU_CACHE_LINE_BYTES * line);
 116 }
 117
 118 static inline struct gru_tlb_fault_map *get_tfm(void *base, int ctxnum)
 119 {
 120         return (struct gru_tlb_fault_map *)(base + GRU_TFM_BASE +
 121                                         ctxnum * GRU_HANDLE_STRIDE);
 122 }
 123
 124 static inline struct gru_tlb_global_handle *get_tgh(void *base, int ctxnum)
 125 {
 126         return (struct gru_tlb_global_handle *)(base + GRU_TGH_BASE +
 127                                         ctxnum * GRU_HANDLE_STRIDE);
 128 }
 129
 130 static inline struct gru_control_block_extended *get_cbe(void *base, int ctxnum)
 131 {
 132         return (struct gru_control_block_extended *)(base + GRU_CBE_BASE +
 133                                         ctxnum * GRU_HANDLE_STRIDE);
 134 }
 135
 136 static inline struct gru_tlb_fault_handle *get_tfh(void *base, int ctxnum)
 137 {
 138         return (struct gru_tlb_fault_handle *)(base + GRU_TFH_BASE +
 139                                         ctxnum * GRU_HANDLE_STRIDE);
 140 }
 141
 142 static inline struct gru_context_configuration_handle *get_cch(void *base,
 143                                         int ctxnum)
 144 {
 145         return (struct gru_context_configuration_handle *)(base +
 146                                 GRU_CCH_BASE + ctxnum * GRU_HANDLE_STRIDE);
 147 }
 148
 149 static inline unsigned long get_cb_number(void *cb)
 150 {
 151         return (((unsigned long)cb - GRU_CB_BASE) % GRU_GSEG_PAGESIZE) /
 152                                         GRU_HANDLE_STRIDE;
 153 }
 154
 155 /* byte offset to a specific GRU chiplet. (p=pnode, c=chiplet (0 or 1)*/
 156 static inline unsigned long gru_chiplet_paddr(unsigned long paddr, int pnode,
 157                                                         int chiplet)
 158 {
 159         return paddr + GRU_SIZE * (2 * pnode  + chiplet);
 160 }
 161
 162 static inline void *gru_chiplet_vaddr(void *vaddr, int pnode, int chiplet)
 163 {
 164         return vaddr + GRU_SIZE * (2 * pnode  + chiplet);
 165 }
 166
 167
 168
 169 /*
 170  * Global TLB Fault Map
 171  *      Bitmap of outstanding TLB misses needing interrupt/polling service.
 172  *
 173  */
 174 struct gru_tlb_fault_map {
 175         unsigned long fault_bits[BITS_TO_LONGS(GRU_NUM_CBE)];
 176         unsigned long fill0[2];
 177         unsigned long done_bits[BITS_TO_LONGS(GRU_NUM_CBE)];
 178         unsigned long fill1[2];
 179 };
 180
 181 /*
 182  * TGH - TLB Global Handle
 183  *      Used for TLB flushing.
 184  *
 185  */
 186 struct gru_tlb_global_handle {
 187         unsigned int cmd:1;             /* DW 0 */
 188         unsigned int delresp:1;
 189         unsigned int opc:1;
 190         unsigned int fill1:5;
 191
 192         unsigned int fill2:8;
 193
 194         unsigned int status:2;
 195         unsigned long fill3:2;
 196         unsigned int state:3;
 197         unsigned long fill4:1;
 198
 199         unsigned int cause:3;
 200         unsigned long fill5:37;
 201
 202         unsigned long vaddr:64;         /* DW 1 */
 203
 204         unsigned int asid:24;           /* DW 2 */
 205         unsigned int fill6:8;
 206
 207         unsigned int pagesize:5;
 208         unsigned int fill7:11;
 209
 210         unsigned int global:1;
 211         unsigned int fill8:15;
 212
 213         unsigned long vaddrmask:39;     /* DW 3 */
 214         unsigned int fill9:9;
 215         unsigned int n:10;
 216         unsigned int fill10:6;
 217
 218         unsigned int ctxbitmap:16;      /* DW4 */
 219         unsigned long fill11[3];
 220 };
 221
 222 enum gru_tgh_cmd {
 223         TGHCMD_START
 224 };
 225
 226 enum gru_tgh_opc {
 227         TGHOP_TLBNOP,
 228         TGHOP_TLBINV
 229 };
 230
 231 enum gru_tgh_status {
 232         TGHSTATUS_IDLE,
 233         TGHSTATUS_EXCEPTION,
 234         TGHSTATUS_ACTIVE
 235 };
 236
 237 enum gru_tgh_state {
 238         TGHSTATE_IDLE,
 239         TGHSTATE_PE_INVAL,
 240         TGHSTATE_INTERRUPT_INVAL,
 241         TGHSTATE_WAITDONE,
 242         TGHSTATE_RESTART_CTX,
 243 };
 244
 245 /*
 246  * TFH - TLB Global Handle
 247  *      Used for TLB dropins into the GRU TLB.
 248  *
 249  */
 250 struct gru_tlb_fault_handle {
 251         unsigned int cmd:1;             /* DW 0 - low 32*/
 252         unsigned int delresp:1;
 253         unsigned int fill0:2;
 254         unsigned int opc:3;
 255         unsigned int fill1:9;
 256
 257         unsigned int status:2;
 258         unsigned int fill2:2;
 259         unsigned int state:3;
 260         unsigned int fill3:1;
 261
 262         unsigned int cause:6;
 263         unsigned int cb_int:1;
 264         unsigned int fill4:1;
 265
 266         unsigned int indexway:12;       /* DW 0 - high 32 */
 267         unsigned int fill5:4;
 268
 269         unsigned int ctxnum:4;
 270         unsigned int fill6:12;
 271
 272         unsigned long missvaddr:64;     /* DW 1 */
 273
 274         unsigned int missasid:24;       /* DW 2 */
 275         unsigned int fill7:8;
 276         unsigned int fillasid:24;
 277         unsigned int dirty:1;
 278         unsigned int gaa:2;
 279         unsigned long fill8:5;
 280
 281         unsigned long pfn:41;           /* DW 3 */
 282         unsigned int fill9:7;
 283         unsigned int pagesize:5;
 284         unsigned int fill10:11;
 285
 286         unsigned long fillvaddr:64;     /* DW 4 */
 287
 288         unsigned long fill11[3];
 289 };
 290
 291 enum gru_tfh_opc {
 292         TFHOP_NOOP,
 293         TFHOP_RESTART,
 294         TFHOP_WRITE_ONLY,
 295         TFHOP_WRITE_RESTART,
 296         TFHOP_EXCEPTION,
 297         TFHOP_USER_POLLING_MODE = 7,
 298 };
 299
 300 enum tfh_status {
 301         TFHSTATUS_IDLE,
 302         TFHSTATUS_EXCEPTION,
 303         TFHSTATUS_ACTIVE,
 304 };
 305
 306 enum tfh_state {
 307         TFHSTATE_INACTIVE,
 308         TFHSTATE_IDLE,
 309         TFHSTATE_MISS_UPM,
 310         TFHSTATE_MISS_FMM,
 311         TFHSTATE_HW_ERR,
 312         TFHSTATE_WRITE_TLB,
 313         TFHSTATE_RESTART_CBR,
 314 };
 315
 316 /* TFH cause bits */
 317 enum tfh_cause {
 318         TFHCAUSE_NONE,
 319         TFHCAUSE_TLB_MISS,
 320         TFHCAUSE_TLB_MOD,
 321         TFHCAUSE_HW_ERROR_RR,
 322         TFHCAUSE_HW_ERROR_MAIN_ARRAY,
 323         TFHCAUSE_HW_ERROR_VALID,
 324         TFHCAUSE_HW_ERROR_PAGESIZE,
 325         TFHCAUSE_INSTRUCTION_EXCEPTION,
 326         TFHCAUSE_UNCORRECTIBLE_ERROR,
 327 };
 328
 329 /* GAA values */
 330 #define GAA_RAM                         0x0
 331 #define GAA_NCRAM                       0x2
 332 #define GAA_MMIO                        0x1
 333 #define GAA_REGISTER                    0x3
 334
 335 /* GRU paddr shift for pfn. (NOTE: shift is NOT by actual pagesize) */
 336 #define GRU_PADDR_SHIFT                 12
 337
 338 /*
 339  * Context Configuration handle
 340  *      Used to allocate resources to a GSEG context.
 341  *
 342  */
 343 struct gru_context_configuration_handle {
 344         unsigned int cmd:1;                     /* DW0 */
 345         unsigned int delresp:1;
 346         unsigned int opc:3;
 347         unsigned int unmap_enable:1;
 348         unsigned int req_slice_set_enable:1;
 349         unsigned int req_slice:2;
 350         unsigned int cb_int_enable:1;
 351         unsigned int tlb_int_enable:1;
 352         unsigned int tfm_fault_bit_enable:1;
 353         unsigned int tlb_int_select:4;
 354
 355         unsigned int status:2;
 356         unsigned int state:2;
 357         unsigned int reserved2:4;
 358
 359         unsigned int cause:4;
 360         unsigned int tfm_done_bit_enable:1;
 361         unsigned int unused:3;
 362
 363         unsigned int dsr_allocation_map;
 364
 365         unsigned long cbr_allocation_map;       /* DW1 */
 366
 367         unsigned int asid[8];                   /* DW 2 - 5 */
 368         unsigned short sizeavail[8];            /* DW 6 - 7 */
 369 } __attribute__ ((packed));
 370
 371 enum gru_cch_opc {
 372         CCHOP_START = 1,
 373         CCHOP_ALLOCATE,
 374         CCHOP_INTERRUPT,
 375         CCHOP_DEALLOCATE,
 376         CCHOP_INTERRUPT_SYNC,
 377 };
 378
 379 enum gru_cch_status {
 380         CCHSTATUS_IDLE,
 381         CCHSTATUS_EXCEPTION,
 382         CCHSTATUS_ACTIVE,
 383 };
 384
 385 enum gru_cch_state {
 386         CCHSTATE_INACTIVE,
 387         CCHSTATE_MAPPED,
 388         CCHSTATE_ACTIVE,
 389         CCHSTATE_INTERRUPTED,
 390 };
 391
 392 /* CCH Exception cause */
 393 enum gru_cch_cause {
 394         CCHCAUSE_REGION_REGISTER_WRITE_ERROR = 1,
 395         CCHCAUSE_ILLEGAL_OPCODE = 2,
 396         CCHCAUSE_INVALID_START_REQUEST = 3,
 397         CCHCAUSE_INVALID_ALLOCATION_REQUEST = 4,
 398         CCHCAUSE_INVALID_DEALLOCATION_REQUEST = 5,
 399         CCHCAUSE_INVALID_INTERRUPT_REQUEST = 6,
 400         CCHCAUSE_CCH_BUSY = 7,
 401         CCHCAUSE_NO_CBRS_TO_ALLOCATE = 8,
 402         CCHCAUSE_BAD_TFM_CONFIG = 9,
 403         CCHCAUSE_CBR_RESOURCES_OVERSUBSCRIPED = 10,
 404         CCHCAUSE_DSR_RESOURCES_OVERSUBSCRIPED = 11,
 405         CCHCAUSE_CBR_DEALLOCATION_ERROR = 12,
 406 };
 407 /*
 408  * CBE - Control Block Extended
 409  *      Maintains internal GRU state for active CBs.
 410  *
 411  */
 412 struct gru_control_block_extended {
 413         unsigned int reserved0:1;       /* DW 0  - low */
 414         unsigned int imacpy:3;
 415         unsigned int reserved1:4;
 416         unsigned int xtypecpy:3;
 417         unsigned int iaa0cpy:2;
 418         unsigned int iaa1cpy:2;
 419         unsigned int reserved2:1;
 420         unsigned int opccpy:8;
 421         unsigned int exopccpy:8;
 422
 423         unsigned int idef2cpy:22;       /* DW 0  - high */
 424         unsigned int reserved3:10;
 425
 426         unsigned int idef4cpy:22;       /* DW 1 */
 427         unsigned int reserved4:10;
 428         unsigned int idef4upd:22;
 429         unsigned int reserved5:10;
 430
 431         unsigned long idef1upd:64;      /* DW 2 */
 432
 433         unsigned long idef5cpy:64;      /* DW 3 */
 434
 435         unsigned long idef6cpy:64;      /* DW 4 */
 436
 437         unsigned long idef3upd:64;      /* DW 5 */
 438
 439         unsigned long idef5upd:64;      /* DW 6 */
 440
 441         unsigned int idef2upd:22;       /* DW 7 */
 442         unsigned int reserved6:10;
 443
 444         unsigned int ecause:20;
 445         unsigned int cbrstate:4;
 446         unsigned int cbrexecstatus:8;
 447 };
 448
 449 enum gru_cbr_state {
 450         CBRSTATE_INACTIVE,
 451         CBRSTATE_IDLE,
 452         CBRSTATE_PE_CHECK,
 453         CBRSTATE_QUEUED,
 454         CBRSTATE_WAIT_RESPONSE,
 455         CBRSTATE_INTERRUPTED,
 456         CBRSTATE_INTERRUPTED_MISS_FMM,
 457         CBRSTATE_BUSY_INTERRUPT_MISS_FMM,
 458         CBRSTATE_INTERRUPTED_MISS_UPM,
 459         CBRSTATE_BUSY_INTERRUPTED_MISS_UPM,
 460         CBRSTATE_REQUEST_ISSUE,
 461         CBRSTATE_BUSY_INTERRUPT,
 462 };
 463
 464 /* CBE cbrexecstatus bits  - defined in gru_instructions.h*/
 465 /* CBE ecause bits  - defined in gru_instructions.h */
 466
 467 /*
 468  * Convert a processor pagesize into the strange encoded pagesize used by the
 469  * GRU. Processor pagesize is encoded as log of bytes per page. (or PAGE_SHIFT)
 470  *      pagesize        log pagesize    grupagesize
 471  *        4k                    12      0
 472  *       16k                    14      1
 473  *       64k                    16      2
 474  *      256k                    18      3
 475  *        1m                    20      4
 476  *        2m                    21      5
 477  *        4m                    22      6
 478  *       16m                    24      7
 479  *       64m                    26      8
 480  *      ...
 481  */
 482 #define GRU_PAGESIZE(sh)        ((((sh) > 20 ? (sh) + 2 : (sh)) >> 1) - 6)
 483 #define GRU_SIZEAVAIL(sh)       (1UL << GRU_PAGESIZE(sh))
 484
 485 /* minimum TLB purge count to ensure a full purge */
 486 #define GRUMAXINVAL             1024UL
 487
 488 int cch_allocate(struct gru_context_configuration_handle *cch);
 489 int cch_start(struct gru_context_configuration_handle *cch);
 490 int cch_interrupt(struct gru_context_configuration_handle *cch);
 491 int cch_deallocate(struct gru_context_configuration_handle *cch);
 492 int cch_interrupt_sync(struct gru_context_configuration_handle *cch);
 493 int tgh_invalidate(struct gru_tlb_global_handle *tgh, unsigned long vaddr,
 494         unsigned long vaddrmask, int asid, int pagesize, int global, int n,
 495         unsigned short ctxbitmap);
 496 void tfh_write_only(struct gru_tlb_fault_handle *tfh, unsigned long pfn,
 497         unsigned long vaddr, int asid, int dirty, int pagesize);
 498 void tfh_write_restart(struct gru_tlb_fault_handle *tfh, unsigned long paddr,
 499         int gaa, unsigned long vaddr, int asid, int dirty, int pagesize);
 500 void tfh_restart(struct gru_tlb_fault_handle *tfh);
 501 void tfh_user_polling_mode(struct gru_tlb_fault_handle *tfh);
 502 void tfh_exception(struct gru_tlb_fault_handle *tfh);
 503
 504 #endif /* __GRUHANDLES_H__ */