2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
35 #define ATHEROS_VENDOR_ID 0x168c
37 #define AR5416_DEVID_PCI 0x0023
38 #define AR5416_DEVID_PCIE 0x0024
39 #define AR9160_DEVID_PCI 0x0027
40 #define AR9280_DEVID_PCI 0x0029
41 #define AR9280_DEVID_PCIE 0x002a
42 #define AR9285_DEVID_PCIE 0x002b
43 #define AR2427_DEVID_PCIE 0x002c
45 #define AR5416_AR9100_DEVID 0x000b
47 #define AR_SUBVENDOR_ID_NOG 0x0e11
48 #define AR_SUBVENDOR_ID_NEW_A 0x7065
49 #define AR5416_MAGIC 0x19641014
51 #define AR5416_DEVID_AR9287_PCI 0x002D
52 #define AR5416_DEVID_AR9287_PCIE 0x002E
54 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
55 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
56 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
58 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
60 #define ATH_DEFAULT_NOISE_FLOOR -95
62 #define ATH9K_RSSI_BAD -128
64 /* Register read/write primitives */
65 #define REG_WRITE(_ah, _reg, _val) \
66 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
68 #define REG_READ(_ah, _reg) \
69 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
71 #define SM(_v, _f) (((_v) << _f##_S) & _f)
72 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
73 #define REG_RMW(_a, _r, _set, _clr) \
74 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
75 #define REG_RMW_FIELD(_a, _r, _f, _v) \
77 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
78 #define REG_SET_BIT(_a, _r, _f) \
79 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
80 #define REG_CLR_BIT(_a, _r, _f) \
81 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
83 #define DO_DELAY(x) do { \
84 if ((++(x) % 64) == 0) \
88 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
90 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
91 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
92 INI_RA((iniarray), r, (column))); \
97 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
98 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
99 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
100 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
101 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
102 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
103 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
105 #define AR_GPIOD_MASK 0x00001FFF
106 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
108 #define BASE_ACTIVATE_DELAY 100
109 #define RTC_PLL_SETTLE_DELAY 100
110 #define COEF_SCALE_S 24
111 #define HT40_CHANNEL_CENTER_SHIFT 10
113 #define ATH9K_ANTENNA0_CHAINMASK 0x1
114 #define ATH9K_ANTENNA1_CHAINMASK 0x2
116 #define ATH9K_NUM_DMA_DEBUG_REGS 8
117 #define ATH9K_NUM_QUEUES 10
119 #define MAX_RATE_POWER 63
120 #define AH_WAIT_TIMEOUT 100000 /* (us) */
121 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
122 #define AH_TIME_QUANTUM 10
123 #define AR_KEYTABLE_SIZE 128
124 #define POWER_UP_TIME 10000
125 #define SPUR_RSSI_THRESH 40
127 #define CAB_TIMEOUT_VAL 10
128 #define BEACON_TIMEOUT_VAL 10
129 #define MIN_BEACON_TIMEOUT_VAL 1
132 #define INIT_CONFIG_STATUS 0x00000000
133 #define INIT_RSSI_THR 0x00000700
134 #define INIT_BCON_CNTRL_REG 0x00000000
136 #define TU_TO_USEC(_tu) ((_tu) << 10)
141 ATH9K_MODE_11NA_HT20
,
142 ATH9K_MODE_11NG_HT20
,
143 ATH9K_MODE_11NA_HT40PLUS
,
144 ATH9K_MODE_11NA_HT40MINUS
,
145 ATH9K_MODE_11NG_HT40PLUS
,
146 ATH9K_MODE_11NG_HT40MINUS
,
151 ATH9K_HW_CAP_MIC_AESCCM
= BIT(0),
152 ATH9K_HW_CAP_MIC_CKIP
= BIT(1),
153 ATH9K_HW_CAP_MIC_TKIP
= BIT(2),
154 ATH9K_HW_CAP_CIPHER_AESCCM
= BIT(3),
155 ATH9K_HW_CAP_CIPHER_CKIP
= BIT(4),
156 ATH9K_HW_CAP_CIPHER_TKIP
= BIT(5),
157 ATH9K_HW_CAP_VEOL
= BIT(6),
158 ATH9K_HW_CAP_BSSIDMASK
= BIT(7),
159 ATH9K_HW_CAP_MCAST_KEYSEARCH
= BIT(8),
160 ATH9K_HW_CAP_HT
= BIT(9),
161 ATH9K_HW_CAP_GTT
= BIT(10),
162 ATH9K_HW_CAP_FASTCC
= BIT(11),
163 ATH9K_HW_CAP_RFSILENT
= BIT(12),
164 ATH9K_HW_CAP_CST
= BIT(13),
165 ATH9K_HW_CAP_ENHANCEDPM
= BIT(14),
166 ATH9K_HW_CAP_AUTOSLEEP
= BIT(15),
167 ATH9K_HW_CAP_4KB_SPLITTRANS
= BIT(16),
170 enum ath9k_capability_type
{
171 ATH9K_CAP_CIPHER
= 0,
173 ATH9K_CAP_TKIP_SPLIT
,
175 ATH9K_CAP_MCAST_KEYSRCH
,
179 struct ath9k_hw_capabilities
{
180 u32 hw_caps
; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
181 DECLARE_BITMAP(wireless_modes
, ATH9K_MODE_MAX
); /* ATH9K_MODE_* */
184 u16 low_5ghz_chan
, high_5ghz_chan
;
185 u16 low_2ghz_chan
, high_2ghz_chan
;
189 u16 tx_triglevel_max
;
196 struct ath9k_ops_config
{
197 int dma_beacon_response_time
;
198 int sw_beacon_response_time
;
199 int additional_swba_backoff
;
201 int cwm_ignore_extcca
;
202 u8 pcie_powersave_enable
;
212 int serialize_regmode
;
213 bool rx_intr_mitigation
;
214 #define SPUR_DISABLE 0
215 #define SPUR_ENABLE_IOCTL 1
216 #define SPUR_ENABLE_EEPROM 2
217 #define AR_EEPROM_MODAL_SPURS 5
218 #define AR_SPUR_5413_1 1640
219 #define AR_SPUR_5413_2 1200
220 #define AR_NO_SPUR 0x8000
221 #define AR_BASE_FREQ_2GHZ 2300
222 #define AR_BASE_FREQ_5GHZ 4900
223 #define AR_SPUR_FEEQ_BOUND_HT40 19
224 #define AR_SPUR_FEEQ_BOUND_HT20 10
226 u16 spurchans
[AR_EEPROM_MODAL_SPURS
][2];
231 ATH9K_INT_RX
= 0x00000001,
232 ATH9K_INT_RXDESC
= 0x00000002,
233 ATH9K_INT_RXNOFRM
= 0x00000008,
234 ATH9K_INT_RXEOL
= 0x00000010,
235 ATH9K_INT_RXORN
= 0x00000020,
236 ATH9K_INT_TX
= 0x00000040,
237 ATH9K_INT_TXDESC
= 0x00000080,
238 ATH9K_INT_TIM_TIMER
= 0x00000100,
239 ATH9K_INT_TXURN
= 0x00000800,
240 ATH9K_INT_MIB
= 0x00001000,
241 ATH9K_INT_RXPHY
= 0x00004000,
242 ATH9K_INT_RXKCM
= 0x00008000,
243 ATH9K_INT_SWBA
= 0x00010000,
244 ATH9K_INT_BMISS
= 0x00040000,
245 ATH9K_INT_BNR
= 0x00100000,
246 ATH9K_INT_TIM
= 0x00200000,
247 ATH9K_INT_DTIM
= 0x00400000,
248 ATH9K_INT_DTIMSYNC
= 0x00800000,
249 ATH9K_INT_GPIO
= 0x01000000,
250 ATH9K_INT_CABEND
= 0x02000000,
251 ATH9K_INT_TSFOOR
= 0x04000000,
252 ATH9K_INT_GENTIMER
= 0x08000000,
253 ATH9K_INT_CST
= 0x10000000,
254 ATH9K_INT_GTT
= 0x20000000,
255 ATH9K_INT_FATAL
= 0x40000000,
256 ATH9K_INT_GLOBAL
= 0x80000000,
257 ATH9K_INT_BMISC
= ATH9K_INT_TIM
|
262 ATH9K_INT_COMMON
= ATH9K_INT_RXNOFRM
|
274 ATH9K_INT_NOCARD
= 0xffffffff
277 #define CHANNEL_CW_INT 0x00002
278 #define CHANNEL_CCK 0x00020
279 #define CHANNEL_OFDM 0x00040
280 #define CHANNEL_2GHZ 0x00080
281 #define CHANNEL_5GHZ 0x00100
282 #define CHANNEL_PASSIVE 0x00200
283 #define CHANNEL_DYN 0x00400
284 #define CHANNEL_HALF 0x04000
285 #define CHANNEL_QUARTER 0x08000
286 #define CHANNEL_HT20 0x10000
287 #define CHANNEL_HT40PLUS 0x20000
288 #define CHANNEL_HT40MINUS 0x40000
290 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
291 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
292 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
293 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
294 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
295 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
296 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
297 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
298 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
299 #define CHANNEL_ALL \
308 struct ath9k_channel
{
309 struct ieee80211_channel
*chan
;
314 bool oneTimeCalsDone
;
317 int16_t rawNoiseFloor
;
320 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
321 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
322 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
323 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
324 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
325 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
326 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
327 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
328 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
329 #define IS_CHAN_A_5MHZ_SPACED(_c) \
330 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
331 (((_c)->channel % 20) != 0) && \
332 (((_c)->channel % 10) != 0))
334 /* These macros check chanmode and not channelFlags */
335 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
336 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
337 ((_c)->chanmode == CHANNEL_G_HT20))
338 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
339 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
340 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
341 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
342 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
344 enum ath9k_power_mode
{
347 ATH9K_PM_NETWORK_SLEEP
,
351 enum ath9k_tp_scale
{
352 ATH9K_TP_SCALE_MAX
= 0,
360 SER_REG_MODE_OFF
= 0,
362 SER_REG_MODE_AUTO
= 2,
365 struct ath9k_beacon_state
{
369 #define ATH9K_BEACON_PERIOD 0x0000ffff
370 #define ATH9K_BEACON_ENA 0x00800000
371 #define ATH9K_BEACON_RESET_TSF 0x01000000
372 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
375 u16 bs_cfpmaxduration
;
378 u16 bs_bmissthreshold
;
379 u32 bs_sleepduration
;
380 u32 bs_tsfoor_threshold
;
383 struct chan_centers
{
390 ATH9K_RESET_POWER_ON
,
395 struct ath9k_hw_version
{
407 /* Generic TSF timer definitions */
409 #define ATH_MAX_GEN_TIMER 16
411 #define AR_GENTMR_BIT(_index) (1 << (_index))
414 * Using de Bruijin sequence to to look up 1's index in a 32 bit number
415 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
417 #define debruijn32 0x077CB531U
419 struct ath_gen_timer_configuration
{
426 struct ath_gen_timer
{
427 void (*trigger
)(void *arg
);
428 void (*overflow
)(void *arg
);
433 struct ath_gen_timer_table
{
434 u32 gen_timer_index
[32];
435 struct ath_gen_timer
*timers
[ATH_MAX_GEN_TIMER
];
437 unsigned long timer_bits
;
443 * struct ath_hw_private_ops - callbacks used internally by hardware code
445 * This structure contains private callbacks designed to only be used internally
446 * by the hardware core.
448 * @init_cal_settings: Initializes calibration settings
449 * @init_mode_regs: Initializes mode registers
450 * @macversion_supported: If this specific mac revision is supported
452 * @rf_set_freq: change frequency
453 * @spur_mitigate_freq: spur mitigation
454 * @rf_alloc_ext_banks:
455 * @rf_free_ext_banks:
457 * @compute_pll_control: compute the PLL control value to use for
458 * AR_RTC_PLL_CONTROL for a given channel
460 struct ath_hw_private_ops
{
461 void (*init_cal_settings
)(struct ath_hw
*ah
);
462 void (*init_mode_regs
)(struct ath_hw
*ah
);
463 bool (*macversion_supported
)(u32 macversion
);
466 int (*rf_set_freq
)(struct ath_hw
*ah
,
467 struct ath9k_channel
*chan
);
468 void (*spur_mitigate_freq
)(struct ath_hw
*ah
,
469 struct ath9k_channel
*chan
);
470 int (*rf_alloc_ext_banks
)(struct ath_hw
*ah
);
471 void (*rf_free_ext_banks
)(struct ath_hw
*ah
);
472 bool (*set_rf_regs
)(struct ath_hw
*ah
,
473 struct ath9k_channel
*chan
,
475 void (*set_channel_regs
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
476 void (*init_bb
)(struct ath_hw
*ah
,
477 struct ath9k_channel
*chan
);
478 int (*process_ini
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
479 void (*olc_init
)(struct ath_hw
*ah
);
480 void (*set_rfmode
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
481 void (*mark_phy_inactive
)(struct ath_hw
*ah
);
482 void (*set_delta_slope
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
483 bool (*rfbus_req
)(struct ath_hw
*ah
);
484 void (*rfbus_done
)(struct ath_hw
*ah
);
485 void (*enable_rfkill
)(struct ath_hw
*ah
);
486 void (*restore_chainmask
)(struct ath_hw
*ah
);
487 void (*set_diversity
)(struct ath_hw
*ah
, bool value
);
488 u32 (*compute_pll_control
)(struct ath_hw
*ah
,
489 struct ath9k_channel
*chan
);
493 * struct ath_hw_ops - callbacks used by hardware code and driver code
495 * This structure contains callbacks designed to to be used internally by
496 * hardware code and also by the lower level driver.
498 * @config_pci_powersave:
501 void (*config_pci_powersave
)(struct ath_hw
*ah
,
507 struct ieee80211_hw
*hw
;
508 struct ath_common common
;
509 struct ath9k_hw_version hw_version
;
510 struct ath9k_ops_config config
;
511 struct ath9k_hw_capabilities caps
;
512 struct ath9k_channel channels
[38];
513 struct ath9k_channel
*curchan
;
516 struct ar5416_eeprom_def def
;
517 struct ar5416_eeprom_4k map4k
;
518 struct ar9287_eeprom map9287
;
520 const struct eeprom_ops
*eep_ops
;
521 enum ath9k_eep_map eep_map
;
525 bool need_an_top2_fixup
;
534 enum nl80211_iftype opmode
;
535 enum ath9k_power_mode power_mode
;
537 struct ath9k_nfcal_hist nfCalHist
[NUM_NF_READINGS
];
538 struct ath9k_pacal_info pacal_info
;
539 struct ar5416Stats stats
;
540 struct ath9k_tx_queue_info txq
[ATH9K_NUM_TX_QUEUES
];
542 int16_t curchan_rad_index
;
543 enum ath9k_int imask
;
545 u32 txok_interrupt_mask
;
546 u32 txerr_interrupt_mask
;
547 u32 txdesc_interrupt_mask
;
548 u32 txeol_interrupt_mask
;
549 u32 txurn_interrupt_mask
;
554 enum ath9k_cal_types supp_cals
;
555 struct ath9k_cal_list iq_caldata
;
556 struct ath9k_cal_list adcgain_caldata
;
557 struct ath9k_cal_list adcdc_calinitdata
;
558 struct ath9k_cal_list adcdc_caldata
;
559 struct ath9k_cal_list
*cal_list
;
560 struct ath9k_cal_list
*cal_list_last
;
561 struct ath9k_cal_list
*cal_list_curr
;
562 #define totalPowerMeasI meas0.unsign
563 #define totalPowerMeasQ meas1.unsign
564 #define totalIqCorrMeas meas2.sign
565 #define totalAdcIOddPhase meas0.unsign
566 #define totalAdcIEvenPhase meas1.unsign
567 #define totalAdcQOddPhase meas2.unsign
568 #define totalAdcQEvenPhase meas3.unsign
569 #define totalAdcDcOffsetIOddPhase meas0.sign
570 #define totalAdcDcOffsetIEvenPhase meas1.sign
571 #define totalAdcDcOffsetQOddPhase meas2.sign
572 #define totalAdcDcOffsetQEvenPhase meas3.sign
574 u32 unsign
[AR5416_MAX_CHAINS
];
575 int32_t sign
[AR5416_MAX_CHAINS
];
578 u32 unsign
[AR5416_MAX_CHAINS
];
579 int32_t sign
[AR5416_MAX_CHAINS
];
582 u32 unsign
[AR5416_MAX_CHAINS
];
583 int32_t sign
[AR5416_MAX_CHAINS
];
586 u32 unsign
[AR5416_MAX_CHAINS
];
587 int32_t sign
[AR5416_MAX_CHAINS
];
591 u32 sta_id1_defaults
;
597 } enable_32kHz_clock
;
599 /* Private to hardware code */
600 struct ath_hw_private_ops private_ops
;
601 /* Accessed by the lower level driver */
602 struct ath_hw_ops ops
;
604 /* Used to program the radio on non single-chip devices */
605 u32
*analogBank0Data
;
606 u32
*analogBank1Data
;
607 u32
*analogBank2Data
;
608 u32
*analogBank3Data
;
609 u32
*analogBank6Data
;
610 u32
*analogBank6TPCData
;
611 u32
*analogBank7Data
;
615 int16_t txpower_indexoffset
;
624 struct ar5416AniState
*curani
;
625 struct ar5416AniState ani
[255];
626 int totalSizeDesired
[5];
630 enum ath9k_ani_cmd ani_function
;
632 /* Bluetooth coexistance */
633 struct ath_btcoex_hw btcoex_hw
;
639 u32 originalGain
[22];
644 struct ar5416IniArray iniModes
;
645 struct ar5416IniArray iniCommon
;
646 struct ar5416IniArray iniBank0
;
647 struct ar5416IniArray iniBB_RfGain
;
648 struct ar5416IniArray iniBank1
;
649 struct ar5416IniArray iniBank2
;
650 struct ar5416IniArray iniBank3
;
651 struct ar5416IniArray iniBank6
;
652 struct ar5416IniArray iniBank6TPC
;
653 struct ar5416IniArray iniBank7
;
654 struct ar5416IniArray iniAddac
;
655 struct ar5416IniArray iniPcieSerdes
;
656 struct ar5416IniArray iniModesAdditional
;
657 struct ar5416IniArray iniModesRxGain
;
658 struct ar5416IniArray iniModesTxGain
;
659 struct ar5416IniArray iniModes_9271_1_0_only
;
660 struct ar5416IniArray iniCckfirNormal
;
661 struct ar5416IniArray iniCckfirJapan2484
;
662 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271
;
663 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271
;
664 struct ar5416IniArray iniModes_9271_ANI_reg
;
665 struct ar5416IniArray iniModes_high_power_tx_gain_9271
;
666 struct ar5416IniArray iniModes_normal_power_tx_gain_9271
;
668 u32 intr_gen_timer_trigger
;
669 u32 intr_gen_timer_thresh
;
670 struct ath_gen_timer_table hw_gen_timers
;
673 static inline struct ath_common
*ath9k_hw_common(struct ath_hw
*ah
)
678 static inline struct ath_regulatory
*ath9k_hw_regulatory(struct ath_hw
*ah
)
680 return &(ath9k_hw_common(ah
)->regulatory
);
683 static inline struct ath_hw_private_ops
*ath9k_hw_private_ops(struct ath_hw
*ah
)
685 return &ah
->private_ops
;
688 static inline struct ath_hw_ops
*ath9k_hw_ops(struct ath_hw
*ah
)
693 /* Initialization, Detach, Reset */
694 const char *ath9k_hw_probe(u16 vendorid
, u16 devid
);
695 void ath9k_hw_deinit(struct ath_hw
*ah
);
696 int ath9k_hw_init(struct ath_hw
*ah
);
697 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
698 bool bChannelChange
);
699 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
);
700 bool ath9k_hw_getcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
701 u32 capability
, u32
*result
);
702 bool ath9k_hw_setcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
703 u32 capability
, u32 setting
, int *status
);
704 u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
, struct ath9k_channel
*chan
);
706 /* Key Cache Management */
707 bool ath9k_hw_keyreset(struct ath_hw
*ah
, u16 entry
);
708 bool ath9k_hw_keysetmac(struct ath_hw
*ah
, u16 entry
, const u8
*mac
);
709 bool ath9k_hw_set_keycache_entry(struct ath_hw
*ah
, u16 entry
,
710 const struct ath9k_keyval
*k
,
712 bool ath9k_hw_keyisvalid(struct ath_hw
*ah
, u16 entry
);
714 /* GPIO / RFKILL / Antennae */
715 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
);
716 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
);
717 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
719 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
);
720 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
);
721 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
);
723 /* General Operation */
724 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
);
725 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
);
726 bool ath9k_get_channel_edges(struct ath_hw
*ah
, u16 flags
, u16
*low
, u16
*high
);
727 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
729 u32 frameLen
, u16 rateix
, bool shortPreamble
);
730 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
731 struct ath9k_channel
*chan
,
732 struct chan_centers
*centers
);
733 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
);
734 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
);
735 bool ath9k_hw_phy_disable(struct ath_hw
*ah
);
736 bool ath9k_hw_disable(struct ath_hw
*ah
);
737 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
);
738 void ath9k_hw_setmac(struct ath_hw
*ah
, const u8
*mac
);
739 void ath9k_hw_setopmode(struct ath_hw
*ah
);
740 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
);
741 void ath9k_hw_setbssidmask(struct ath_hw
*ah
);
742 void ath9k_hw_write_associd(struct ath_hw
*ah
);
743 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
);
744 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
);
745 void ath9k_hw_reset_tsf(struct ath_hw
*ah
);
746 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
);
747 u64
ath9k_hw_extend_tsf(struct ath_hw
*ah
, u32 rstamp
);
748 void ath9k_hw_init_global_settings(struct ath_hw
*ah
);
749 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
);
750 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
);
751 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
752 const struct ath9k_beacon_state
*bs
);
754 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
);
756 /* Interrupt Handling */
757 bool ath9k_hw_intrpend(struct ath_hw
*ah
);
758 bool ath9k_hw_getisr(struct ath_hw
*ah
, enum ath9k_int
*masked
);
759 enum ath9k_int
ath9k_hw_set_interrupts(struct ath_hw
*ah
, enum ath9k_int ints
);
761 /* Generic hw timer primitives */
762 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
763 void (*trigger
)(void *),
764 void (*overflow
)(void *),
767 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
768 struct ath_gen_timer
*timer
,
771 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
);
773 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
);
774 void ath_gen_timer_isr(struct ath_hw
*hw
);
775 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
);
777 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
);
780 void ath9k_hw_htc_resetinit(struct ath_hw
*ah
);
783 void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
, u32 coef_scaled
,
784 u32
*coef_mantissa
, u32
*coef_exponent
);
786 void ar9002_hw_attach_phy_ops(struct ath_hw
*ah
);
787 void ar5008_hw_attach_phy_ops(struct ath_hw
*ah
);
789 #define ATH_PCIE_CAP_LINK_CTRL 0x70
790 #define ATH_PCIE_CAP_LINK_L0S 1
791 #define ATH_PCIE_CAP_LINK_L1 2