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x86, apic: Fix spurious error interrupts triggering on all non-boot APs
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / sky2.c
blob5520f161d76f3f7ca3f5638ab92c3b9364ec4515
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
33 #include <linux/ip.h>
34 #include <net/ip.h>
35 #include <linux/tcp.h>
36 #include <linux/in.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
43
44 #include <asm/irq.h>
45
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
48 #endif
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.26"
54 #define PFX DRV_NAME " "
55
56 /*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3.
60 */
61
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
66
67 /* This is the worst case number of transmit list elements for a single skb:
68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
71 #define TX_MAX_PENDING 4096
72 #define TX_DEF_PENDING 127
73
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
79
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
89
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
144 { 0 }
145 };
146
147 MODULE_DEVICE_TABLE(pci, sky2_id_table);
148
149 /* Avoid conditionals by using array */
150 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
151 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
152 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
153
154 static void sky2_set_multicast(struct net_device *dev);
155
156 /* Access to PHY via serial interconnect */
157 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
158 {
159 int i;
160
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
164
165 for (i = 0; i < PHY_RETRIES; i++) {
166 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
167 if (ctrl == 0xffff)
168 goto io_error;
169
170 if (!(ctrl & GM_SMI_CT_BUSY))
171 return 0;
172
173 udelay(10);
174 }
175
176 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
177 return -ETIMEDOUT;
178
179 io_error:
180 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
181 return -EIO;
182 }
183
184 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
185 {
186 int i;
187
188 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
189 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
190
191 for (i = 0; i < PHY_RETRIES; i++) {
192 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
193 if (ctrl == 0xffff)
194 goto io_error;
195
196 if (ctrl & GM_SMI_CT_RD_VAL) {
197 *val = gma_read16(hw, port, GM_SMI_DATA);
198 return 0;
199 }
200
201 udelay(10);
202 }
203
204 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
205 return -ETIMEDOUT;
206 io_error:
207 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
208 return -EIO;
209 }
210
211 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
212 {
213 u16 v;
214 __gm_phy_read(hw, port, reg, &v);
215 return v;
216 }
217
218
219 static void sky2_power_on(struct sky2_hw *hw)
220 {
221 /* switch power to VCC (WA for VAUX problem) */
222 sky2_write8(hw, B0_POWER_CTRL,
223 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
224
225 /* disable Core Clock Division, */
226 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
227
228 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
229 /* enable bits are inverted */
230 sky2_write8(hw, B2_Y2_CLK_GATE,
231 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
232 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
233 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
234 else
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
236
237 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
238 u32 reg;
239
240 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
241
242 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
243 /* set all bits to 0 except bits 15..12 and 8 */
244 reg &= P_ASPM_CONTROL_MSK;
245 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
246
247 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
248 /* set all bits to 0 except bits 28 & 27 */
249 reg &= P_CTL_TIM_VMAIN_AV_MSK;
250 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
251
252 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
253
254 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
255 reg = sky2_read32(hw, B2_GP_IO);
256 reg |= GLB_GPIO_STAT_RACE_DIS;
257 sky2_write32(hw, B2_GP_IO, reg);
258
259 sky2_read32(hw, B2_GP_IO);
260 }
261
262 /* Turn on "driver loaded" LED */
263 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
264 }
265
266 static void sky2_power_aux(struct sky2_hw *hw)
267 {
268 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
269 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
270 else
271 /* enable bits are inverted */
272 sky2_write8(hw, B2_Y2_CLK_GATE,
273 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
274 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
275 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
276
277 /* switch power to VAUX if supported and PME from D3cold */
278 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
279 pci_pme_capable(hw->pdev, PCI_D3cold))
280 sky2_write8(hw, B0_POWER_CTRL,
281 (PC_VAUX_ENA | PC_VCC_ENA |
282 PC_VAUX_ON | PC_VCC_OFF));
283
284 /* turn off "driver loaded LED" */
285 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
286 }
287
288 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
289 {
290 u16 reg;
291
292 /* disable all GMAC IRQ's */
293 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
294
295 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
296 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
298 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
299
300 reg = gma_read16(hw, port, GM_RX_CTRL);
301 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
302 gma_write16(hw, port, GM_RX_CTRL, reg);
303 }
304
305 /* flow control to advertise bits */
306 static const u16 copper_fc_adv[] = {
307 [FC_NONE] = 0,
308 [FC_TX] = PHY_M_AN_ASP,
309 [FC_RX] = PHY_M_AN_PC,
310 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
311 };
312
313 /* flow control to advertise bits when using 1000BaseX */
314 static const u16 fiber_fc_adv[] = {
315 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
316 [FC_TX] = PHY_M_P_ASYM_MD_X,
317 [FC_RX] = PHY_M_P_SYM_MD_X,
318 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
319 };
320
321 /* flow control to GMA disable bits */
322 static const u16 gm_fc_disable[] = {
323 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
324 [FC_TX] = GM_GPCR_FC_RX_DIS,
325 [FC_RX] = GM_GPCR_FC_TX_DIS,
326 [FC_BOTH] = 0,
327 };
328
329
330 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
331 {
332 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
333 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
334
335 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
336 !(hw->flags & SKY2_HW_NEWER_PHY)) {
337 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
338
339 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
340 PHY_M_EC_MAC_S_MSK);
341 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
342
343 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
344 if (hw->chip_id == CHIP_ID_YUKON_EC)
345 /* set downshift counter to 3x and enable downshift */
346 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
347 else
348 /* set master & slave downshift counter to 1x */
349 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
350
351 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
352 }
353
354 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
355 if (sky2_is_copper(hw)) {
356 if (!(hw->flags & SKY2_HW_GIGABIT)) {
357 /* enable automatic crossover */
358 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
359
360 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
361 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
362 u16 spec;
363
364 /* Enable Class A driver for FE+ A0 */
365 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
366 spec |= PHY_M_FESC_SEL_CL_A;
367 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
368 }
369 } else {
370 /* disable energy detect */
371 ctrl &= ~PHY_M_PC_EN_DET_MSK;
372
373 /* enable automatic crossover */
374 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
375
376 /* downshift on PHY 88E1112 and 88E1149 is changed */
377 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
378 (hw->flags & SKY2_HW_NEWER_PHY)) {
379 /* set downshift counter to 3x and enable downshift */
380 ctrl &= ~PHY_M_PC_DSC_MSK;
381 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
382 }
383 }
384 } else {
385 /* workaround for deviation #4.88 (CRC errors) */
386 /* disable Automatic Crossover */
387
388 ctrl &= ~PHY_M_PC_MDIX_MSK;
389 }
390
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 /* special setup for PHY 88E1112 Fiber */
394 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
395 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
396
397 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
398 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
399 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
400 ctrl &= ~PHY_M_MAC_MD_MSK;
401 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
402 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
403
404 if (hw->pmd_type == 'P') {
405 /* select page 1 to access Fiber registers */
406 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
407
408 /* for SFP-module set SIGDET polarity to low */
409 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
410 ctrl |= PHY_M_FIB_SIGD_POL;
411 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
412 }
413
414 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
415 }
416
417 ctrl = PHY_CT_RESET;
418 ct1000 = 0;
419 adv = PHY_AN_CSMA;
420 reg = 0;
421
422 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
423 if (sky2_is_copper(hw)) {
424 if (sky2->advertising & ADVERTISED_1000baseT_Full)
425 ct1000 |= PHY_M_1000C_AFD;
426 if (sky2->advertising & ADVERTISED_1000baseT_Half)
427 ct1000 |= PHY_M_1000C_AHD;
428 if (sky2->advertising & ADVERTISED_100baseT_Full)
429 adv |= PHY_M_AN_100_FD;
430 if (sky2->advertising & ADVERTISED_100baseT_Half)
431 adv |= PHY_M_AN_100_HD;
432 if (sky2->advertising & ADVERTISED_10baseT_Full)
433 adv |= PHY_M_AN_10_FD;
434 if (sky2->advertising & ADVERTISED_10baseT_Half)
435 adv |= PHY_M_AN_10_HD;
436
437 } else { /* special defines for FIBER (88E1040S only) */
438 if (sky2->advertising & ADVERTISED_1000baseT_Full)
439 adv |= PHY_M_AN_1000X_AFD;
440 if (sky2->advertising & ADVERTISED_1000baseT_Half)
441 adv |= PHY_M_AN_1000X_AHD;
442 }
443
444 /* Restart Auto-negotiation */
445 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
446 } else {
447 /* forced speed/duplex settings */
448 ct1000 = PHY_M_1000C_MSE;
449
450 /* Disable auto update for duplex flow control and duplex */
451 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
452
453 switch (sky2->speed) {
454 case SPEED_1000:
455 ctrl |= PHY_CT_SP1000;
456 reg |= GM_GPCR_SPEED_1000;
457 break;
458 case SPEED_100:
459 ctrl |= PHY_CT_SP100;
460 reg |= GM_GPCR_SPEED_100;
461 break;
462 }
463
464 if (sky2->duplex == DUPLEX_FULL) {
465 reg |= GM_GPCR_DUP_FULL;
466 ctrl |= PHY_CT_DUP_MD;
467 } else if (sky2->speed < SPEED_1000)
468 sky2->flow_mode = FC_NONE;
469 }
470
471 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
472 if (sky2_is_copper(hw))
473 adv |= copper_fc_adv[sky2->flow_mode];
474 else
475 adv |= fiber_fc_adv[sky2->flow_mode];
476 } else {
477 reg |= GM_GPCR_AU_FCT_DIS;
478 reg |= gm_fc_disable[sky2->flow_mode];
479
480 /* Forward pause packets to GMAC? */
481 if (sky2->flow_mode & FC_RX)
482 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
483 else
484 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
485 }
486
487 gma_write16(hw, port, GM_GP_CTRL, reg);
488
489 if (hw->flags & SKY2_HW_GIGABIT)
490 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
491
492 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
493 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
494
495 /* Setup Phy LED's */
496 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
497 ledover = 0;
498
499 switch (hw->chip_id) {
500 case CHIP_ID_YUKON_FE:
501 /* on 88E3082 these bits are at 11..9 (shifted left) */
502 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
503
504 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
505
506 /* delete ACT LED control bits */
507 ctrl &= ~PHY_M_FELP_LED1_MSK;
508 /* change ACT LED control to blink mode */
509 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
510 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
511 break;
512
513 case CHIP_ID_YUKON_FE_P:
514 /* Enable Link Partner Next Page */
515 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
516 ctrl |= PHY_M_PC_ENA_LIP_NP;
517
518 /* disable Energy Detect and enable scrambler */
519 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
520 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
521
522 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
523 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
524 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
525 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
526
527 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
528 break;
529
530 case CHIP_ID_YUKON_XL:
531 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
532
533 /* select page 3 to access LED control register */
534 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
535
536 /* set LED Function Control register */
537 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
538 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
539 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
540 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
541 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
542
543 /* set Polarity Control register */
544 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
545 (PHY_M_POLC_LS1_P_MIX(4) |
546 PHY_M_POLC_IS0_P_MIX(4) |
547 PHY_M_POLC_LOS_CTRL(2) |
548 PHY_M_POLC_INIT_CTRL(2) |
549 PHY_M_POLC_STA1_CTRL(2) |
550 PHY_M_POLC_STA0_CTRL(2)));
551
552 /* restore page register */
553 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
554 break;
555
556 case CHIP_ID_YUKON_EC_U:
557 case CHIP_ID_YUKON_EX:
558 case CHIP_ID_YUKON_SUPR:
559 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
560
561 /* select page 3 to access LED control register */
562 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
563
564 /* set LED Function Control register */
565 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
566 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
567 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
568 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
569 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
570
571 /* set Blink Rate in LED Timer Control Register */
572 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
573 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
574 /* restore page register */
575 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
576 break;
577
578 default:
579 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
580 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
581
582 /* turn off the Rx LED (LED_RX) */
583 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
584 }
585
586 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
587 /* apply fixes in PHY AFE */
588 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
589
590 /* increase differential signal amplitude in 10BASE-T */
591 gm_phy_write(hw, port, 0x18, 0xaa99);
592 gm_phy_write(hw, port, 0x17, 0x2011);
593
594 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
595 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
596 gm_phy_write(hw, port, 0x18, 0xa204);
597 gm_phy_write(hw, port, 0x17, 0x2002);
598 }
599
600 /* set page register to 0 */
601 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
602 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
603 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
604 /* apply workaround for integrated resistors calibration */
605 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
606 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
607 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
608 /* apply fixes in PHY AFE */
609 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
610
611 /* apply RDAC termination workaround */
612 gm_phy_write(hw, port, 24, 0x2800);
613 gm_phy_write(hw, port, 23, 0x2001);
614
615 /* set page register back to 0 */
616 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
617 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
618 hw->chip_id < CHIP_ID_YUKON_SUPR) {
619 /* no effect on Yukon-XL */
620 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
621
622 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
623 sky2->speed == SPEED_100) {
624 /* turn on 100 Mbps LED (LED_LINK100) */
625 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
626 }
627
628 if (ledover)
629 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
630
631 }
632
633 /* Enable phy interrupt on auto-negotiation complete (or link up) */
634 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
635 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
636 else
637 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
638 }
639
640 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
641 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
642
643 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
644 {
645 u32 reg1;
646
647 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
648 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
649 reg1 &= ~phy_power[port];
650
651 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
652 reg1 |= coma_mode[port];
653
654 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
655 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
656 sky2_pci_read32(hw, PCI_DEV_REG1);
657
658 if (hw->chip_id == CHIP_ID_YUKON_FE)
659 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
660 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
661 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
662 }
663
664 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
665 {
666 u32 reg1;
667 u16 ctrl;
668
669 /* release GPHY Control reset */
670 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
671
672 /* release GMAC reset */
673 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
674
675 if (hw->flags & SKY2_HW_NEWER_PHY) {
676 /* select page 2 to access MAC control register */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
678
679 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
680 /* allow GMII Power Down */
681 ctrl &= ~PHY_M_MAC_GMIF_PUP;
682 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
683
684 /* set page register back to 0 */
685 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
686 }
687
688 /* setup General Purpose Control Register */
689 gma_write16(hw, port, GM_GP_CTRL,
690 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
691 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
692 GM_GPCR_AU_SPD_DIS);
693
694 if (hw->chip_id != CHIP_ID_YUKON_EC) {
695 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
696 /* select page 2 to access MAC control register */
697 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
698
699 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
700 /* enable Power Down */
701 ctrl |= PHY_M_PC_POW_D_ENA;
702 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
703
704 /* set page register back to 0 */
705 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
706 }
707
708 /* set IEEE compatible Power Down Mode (dev. #4.99) */
709 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
710 }
711
712 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
713 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
714 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
715 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
716 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
717 }
718
719 /* Enable Rx/Tx */
720 static void sky2_enable_rx_tx(struct sky2_port *sky2)
721 {
722 struct sky2_hw *hw = sky2->hw;
723 unsigned port = sky2->port;
724 u16 reg;
725
726 reg = gma_read16(hw, port, GM_GP_CTRL);
727 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
728 gma_write16(hw, port, GM_GP_CTRL, reg);
729 }
730
731 /* Force a renegotiation */
732 static void sky2_phy_reinit(struct sky2_port *sky2)
733 {
734 spin_lock_bh(&sky2->phy_lock);
735 sky2_phy_init(sky2->hw, sky2->port);
736 sky2_enable_rx_tx(sky2);
737 spin_unlock_bh(&sky2->phy_lock);
738 }
739
740 /* Put device in state to listen for Wake On Lan */
741 static void sky2_wol_init(struct sky2_port *sky2)
742 {
743 struct sky2_hw *hw = sky2->hw;
744 unsigned port = sky2->port;
745 enum flow_control save_mode;
746 u16 ctrl;
747 u32 reg1;
748
749 /* Bring hardware out of reset */
750 sky2_write16(hw, B0_CTST, CS_RST_CLR);
751 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
752
753 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
754 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
755
756 /* Force to 10/100
757 * sky2_reset will re-enable on resume
758 */
759 save_mode = sky2->flow_mode;
760 ctrl = sky2->advertising;
761
762 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
763 sky2->flow_mode = FC_NONE;
764
765 spin_lock_bh(&sky2->phy_lock);
766 sky2_phy_power_up(hw, port);
767 sky2_phy_init(hw, port);
768 spin_unlock_bh(&sky2->phy_lock);
769
770 sky2->flow_mode = save_mode;
771 sky2->advertising = ctrl;
772
773 /* Set GMAC to no flow control and auto update for speed/duplex */
774 gma_write16(hw, port, GM_GP_CTRL,
775 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
776 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
777
778 /* Set WOL address */
779 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
780 sky2->netdev->dev_addr, ETH_ALEN);
781
782 /* Turn on appropriate WOL control bits */
783 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
784 ctrl = 0;
785 if (sky2->wol & WAKE_PHY)
786 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
787 else
788 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
789
790 if (sky2->wol & WAKE_MAGIC)
791 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
792 else
793 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
794
795 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
796 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
797
798 /* Turn on legacy PCI-Express PME mode */
799 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
800 reg1 |= PCI_Y2_PME_LEGACY;
801 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
802
803 /* block receiver */
804 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
805
806 }
807
808 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
809 {
810 struct net_device *dev = hw->dev[port];
811
812 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
813 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
814 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
815 /* Yukon-Extreme B0 and further Extreme devices */
816 /* enable Store & Forward mode for TX */
817
818 if (dev->mtu <= ETH_DATA_LEN)
819 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
820 TX_JUMBO_DIS | TX_STFW_ENA);
821
822 else
823 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
824 TX_JUMBO_ENA| TX_STFW_ENA);
825 } else {
826 if (dev->mtu <= ETH_DATA_LEN)
827 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
828 else {
829 /* set Tx GMAC FIFO Almost Empty Threshold */
830 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
831 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
832
833 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
834
835 /* Can't do offload because of lack of store/forward */
836 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
837 }
838 }
839 }
840
841 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
842 {
843 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
844 u16 reg;
845 u32 rx_reg;
846 int i;
847 const u8 *addr = hw->dev[port]->dev_addr;
848
849 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
850 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
851
852 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
853
854 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
855 /* WA DEV_472 -- looks like crossed wires on port 2 */
856 /* clear GMAC 1 Control reset */
857 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
858 do {
859 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
860 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
861 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
862 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
863 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
864 }
865
866 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
867
868 /* Enable Transmit FIFO Underrun */
869 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
870
871 spin_lock_bh(&sky2->phy_lock);
872 sky2_phy_power_up(hw, port);
873 sky2_phy_init(hw, port);
874 spin_unlock_bh(&sky2->phy_lock);
875
876 /* MIB clear */
877 reg = gma_read16(hw, port, GM_PHY_ADDR);
878 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
879
880 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
881 gma_read16(hw, port, i);
882 gma_write16(hw, port, GM_PHY_ADDR, reg);
883
884 /* transmit control */
885 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
886
887 /* receive control reg: unicast + multicast + no FCS */
888 gma_write16(hw, port, GM_RX_CTRL,
889 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
890
891 /* transmit flow control */
892 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
893
894 /* transmit parameter */
895 gma_write16(hw, port, GM_TX_PARAM,
896 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
897 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
898 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
899 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
900
901 /* serial mode register */
902 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
903 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
904
905 if (hw->dev[port]->mtu > ETH_DATA_LEN)
906 reg |= GM_SMOD_JUMBO_ENA;
907
908 gma_write16(hw, port, GM_SERIAL_MODE, reg);
909
910 /* virtual address for data */
911 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
912
913 /* physical address: used for pause frames */
914 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
915
916 /* ignore counter overflows */
917 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
918 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
919 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
920
921 /* Configure Rx MAC FIFO */
922 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
923 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
924 if (hw->chip_id == CHIP_ID_YUKON_EX ||
925 hw->chip_id == CHIP_ID_YUKON_FE_P)
926 rx_reg |= GMF_RX_OVER_ON;
927
928 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
929
930 if (hw->chip_id == CHIP_ID_YUKON_XL) {
931 /* Hardware errata - clear flush mask */
932 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
933 } else {
934 /* Flush Rx MAC FIFO on any flow control or error */
935 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
936 }
937
938 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
939 reg = RX_GMF_FL_THR_DEF + 1;
940 /* Another magic mystery workaround from sk98lin */
941 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
942 hw->chip_rev == CHIP_REV_YU_FE2_A0)
943 reg = 0x178;
944 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
945
946 /* Configure Tx MAC FIFO */
947 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
948 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
949
950 /* On chips without ram buffer, pause is controled by MAC level */
951 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
952 /* Pause threshold is scaled by 8 in bytes */
953 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
954 hw->chip_rev == CHIP_REV_YU_FE2_A0)
955 reg = 1568 / 8;
956 else
957 reg = 1024 / 8;
958 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
959 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
960
961 sky2_set_tx_stfwd(hw, port);
962 }
963
964 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
965 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
966 /* disable dynamic watermark */
967 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
968 reg &= ~TX_DYN_WM_ENA;
969 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
970 }
971 }
972
973 /* Assign Ram Buffer allocation to queue */
974 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
975 {
976 u32 end;
977
978 /* convert from K bytes to qwords used for hw register */
979 start *= 1024/8;
980 space *= 1024/8;
981 end = start + space - 1;
982
983 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
984 sky2_write32(hw, RB_ADDR(q, RB_START), start);
985 sky2_write32(hw, RB_ADDR(q, RB_END), end);
986 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
987 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
988
989 if (q == Q_R1 || q == Q_R2) {
990 u32 tp = space - space/4;
991
992 /* On receive queue's set the thresholds
993 * give receiver priority when > 3/4 full
994 * send pause when down to 2K
995 */
996 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
997 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
998
999 tp = space - 2048/8;
1000 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1001 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
1002 } else {
1003 /* Enable store & forward on Tx queue's because
1004 * Tx FIFO is only 1K on Yukon
1005 */
1006 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1007 }
1008
1009 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1010 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1011 }
1012
1013 /* Setup Bus Memory Interface */
1014 static void sky2_qset(struct sky2_hw *hw, u16 q)
1015 {
1016 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1017 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1018 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1019 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1020 }
1021
1022 /* Setup prefetch unit registers. This is the interface between
1023 * hardware and driver list elements
1024 */
1025 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1026 dma_addr_t addr, u32 last)
1027 {
1028 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1029 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1030 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1031 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1032 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1033 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1034
1035 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1036 }
1037
1038 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1039 {
1040 struct sky2_tx_le *le = sky2->tx_le + *slot;
1041
1042 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1043 le->ctrl = 0;
1044 return le;
1045 }
1046
1047 static void tx_init(struct sky2_port *sky2)
1048 {
1049 struct sky2_tx_le *le;
1050
1051 sky2->tx_prod = sky2->tx_cons = 0;
1052 sky2->tx_tcpsum = 0;
1053 sky2->tx_last_mss = 0;
1054
1055 le = get_tx_le(sky2, &sky2->tx_prod);
1056 le->addr = 0;
1057 le->opcode = OP_ADDR64 | HW_OWNER;
1058 sky2->tx_last_upper = 0;
1059 }
1060
1061 /* Update chip's next pointer */
1062 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1063 {
1064 /* Make sure write' to descriptors are complete before we tell hardware */
1065 wmb();
1066 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1067
1068 /* Synchronize I/O on since next processor may write to tail */
1069 mmiowb();
1070 }
1071
1072
1073 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1074 {
1075 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1076 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1077 le->ctrl = 0;
1078 return le;
1079 }
1080
1081 /* Build description to hardware for one receive segment */
1082 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1083 dma_addr_t map, unsigned len)
1084 {
1085 struct sky2_rx_le *le;
1086
1087 if (sizeof(dma_addr_t) > sizeof(u32)) {
1088 le = sky2_next_rx(sky2);
1089 le->addr = cpu_to_le32(upper_32_bits(map));
1090 le->opcode = OP_ADDR64 | HW_OWNER;
1091 }
1092
1093 le = sky2_next_rx(sky2);
1094 le->addr = cpu_to_le32(lower_32_bits(map));
1095 le->length = cpu_to_le16(len);
1096 le->opcode = op | HW_OWNER;
1097 }
1098
1099 /* Build description to hardware for one possibly fragmented skb */
1100 static void sky2_rx_submit(struct sky2_port *sky2,
1101 const struct rx_ring_info *re)
1102 {
1103 int i;
1104
1105 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1106
1107 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1108 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1109 }
1110
1111
1112 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1113 unsigned size)
1114 {
1115 struct sk_buff *skb = re->skb;
1116 int i;
1117
1118 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1119 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1120 return -EIO;
1121
1122 pci_unmap_len_set(re, data_size, size);
1123
1124 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1125 re->frag_addr[i] = pci_map_page(pdev,
1126 skb_shinfo(skb)->frags[i].page,
1127 skb_shinfo(skb)->frags[i].page_offset,
1128 skb_shinfo(skb)->frags[i].size,
1129 PCI_DMA_FROMDEVICE);
1130 return 0;
1131 }
1132
1133 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1134 {
1135 struct sk_buff *skb = re->skb;
1136 int i;
1137
1138 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1139 PCI_DMA_FROMDEVICE);
1140
1141 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1142 pci_unmap_page(pdev, re->frag_addr[i],
1143 skb_shinfo(skb)->frags[i].size,
1144 PCI_DMA_FROMDEVICE);
1145 }
1146
1147 /* Tell chip where to start receive checksum.
1148 * Actually has two checksums, but set both same to avoid possible byte
1149 * order problems.
1150 */
1151 static void rx_set_checksum(struct sky2_port *sky2)
1152 {
1153 struct sky2_rx_le *le = sky2_next_rx(sky2);
1154
1155 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1156 le->ctrl = 0;
1157 le->opcode = OP_TCPSTART | HW_OWNER;
1158
1159 sky2_write32(sky2->hw,
1160 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1161 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1162 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1163 }
1164
1165 /*
1166 * The RX Stop command will not work for Yukon-2 if the BMU does not
1167 * reach the end of packet and since we can't make sure that we have
1168 * incoming data, we must reset the BMU while it is not doing a DMA
1169 * transfer. Since it is possible that the RX path is still active,
1170 * the RX RAM buffer will be stopped first, so any possible incoming
1171 * data will not trigger a DMA. After the RAM buffer is stopped, the
1172 * BMU is polled until any DMA in progress is ended and only then it
1173 * will be reset.
1174 */
1175 static void sky2_rx_stop(struct sky2_port *sky2)
1176 {
1177 struct sky2_hw *hw = sky2->hw;
1178 unsigned rxq = rxqaddr[sky2->port];
1179 int i;
1180
1181 /* disable the RAM Buffer receive queue */
1182 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1183
1184 for (i = 0; i < 0xffff; i++)
1185 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1186 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1187 goto stopped;
1188
1189 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1190 sky2->netdev->name);
1191 stopped:
1192 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1193
1194 /* reset the Rx prefetch unit */
1195 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1196 mmiowb();
1197 }
1198
1199 /* Clean out receive buffer area, assumes receiver hardware stopped */
1200 static void sky2_rx_clean(struct sky2_port *sky2)
1201 {
1202 unsigned i;
1203
1204 memset(sky2->rx_le, 0, RX_LE_BYTES);
1205 for (i = 0; i < sky2->rx_pending; i++) {
1206 struct rx_ring_info *re = sky2->rx_ring + i;
1207
1208 if (re->skb) {
1209 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1210 kfree_skb(re->skb);
1211 re->skb = NULL;
1212 }
1213 }
1214 }
1215
1216 /* Basic MII support */
1217 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1218 {
1219 struct mii_ioctl_data *data = if_mii(ifr);
1220 struct sky2_port *sky2 = netdev_priv(dev);
1221 struct sky2_hw *hw = sky2->hw;
1222 int err = -EOPNOTSUPP;
1223
1224 if (!netif_running(dev))
1225 return -ENODEV; /* Phy still in reset */
1226
1227 switch (cmd) {
1228 case SIOCGMIIPHY:
1229 data->phy_id = PHY_ADDR_MARV;
1230
1231 /* fallthru */
1232 case SIOCGMIIREG: {
1233 u16 val = 0;
1234
1235 spin_lock_bh(&sky2->phy_lock);
1236 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1237 spin_unlock_bh(&sky2->phy_lock);
1238
1239 data->val_out = val;
1240 break;
1241 }
1242
1243 case SIOCSMIIREG:
1244 spin_lock_bh(&sky2->phy_lock);
1245 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1246 data->val_in);
1247 spin_unlock_bh(&sky2->phy_lock);
1248 break;
1249 }
1250 return err;
1251 }
1252
1253 #ifdef SKY2_VLAN_TAG_USED
1254 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1255 {
1256 if (onoff) {
1257 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1258 RX_VLAN_STRIP_ON);
1259 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1260 TX_VLAN_TAG_ON);
1261 } else {
1262 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1263 RX_VLAN_STRIP_OFF);
1264 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1265 TX_VLAN_TAG_OFF);
1266 }
1267 }
1268
1269 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1270 {
1271 struct sky2_port *sky2 = netdev_priv(dev);
1272 struct sky2_hw *hw = sky2->hw;
1273 u16 port = sky2->port;
1274
1275 netif_tx_lock_bh(dev);
1276 napi_disable(&hw->napi);
1277
1278 sky2->vlgrp = grp;
1279 sky2_set_vlan_mode(hw, port, grp != NULL);
1280
1281 sky2_read32(hw, B0_Y2_SP_LISR);
1282 napi_enable(&hw->napi);
1283 netif_tx_unlock_bh(dev);
1284 }
1285 #endif
1286
1287 /* Amount of required worst case padding in rx buffer */
1288 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1289 {
1290 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1291 }
1292
1293 /*
1294 * Allocate an skb for receiving. If the MTU is large enough
1295 * make the skb non-linear with a fragment list of pages.
1296 */
1297 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1298 {
1299 struct sk_buff *skb;
1300 int i;
1301
1302 skb = netdev_alloc_skb(sky2->netdev,
1303 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
1304 if (!skb)
1305 goto nomem;
1306
1307 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1308 unsigned char *start;
1309 /*
1310 * Workaround for a bug in FIFO that cause hang
1311 * if the FIFO if the receive buffer is not 64 byte aligned.
1312 * The buffer returned from netdev_alloc_skb is
1313 * aligned except if slab debugging is enabled.
1314 */
1315 start = PTR_ALIGN(skb->data, 8);
1316 skb_reserve(skb, start - skb->data);
1317 } else
1318 skb_reserve(skb, NET_IP_ALIGN);
1319
1320 for (i = 0; i < sky2->rx_nfrags; i++) {
1321 struct page *page = alloc_page(GFP_ATOMIC);
1322
1323 if (!page)
1324 goto free_partial;
1325 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1326 }
1327
1328 return skb;
1329 free_partial:
1330 kfree_skb(skb);
1331 nomem:
1332 return NULL;
1333 }
1334
1335 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1336 {
1337 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1338 }
1339
1340 /*
1341 * Allocate and setup receiver buffer pool.
1342 * Normal case this ends up creating one list element for skb
1343 * in the receive ring. Worst case if using large MTU and each
1344 * allocation falls on a different 64 bit region, that results
1345 * in 6 list elements per ring entry.
1346 * One element is used for checksum enable/disable, and one
1347 * extra to avoid wrap.
1348 */
1349 static int sky2_rx_start(struct sky2_port *sky2)
1350 {
1351 struct sky2_hw *hw = sky2->hw;
1352 struct rx_ring_info *re;
1353 unsigned rxq = rxqaddr[sky2->port];
1354 unsigned i, size, thresh;
1355
1356 sky2->rx_put = sky2->rx_next = 0;
1357 sky2_qset(hw, rxq);
1358
1359 /* On PCI express lowering the watermark gives better performance */
1360 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1361 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1362
1363 /* These chips have no ram buffer?
1364 * MAC Rx RAM Read is controlled by hardware */
1365 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1366 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 ||
1367 hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1368 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1369
1370 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1371
1372 if (!(hw->flags & SKY2_HW_NEW_LE))
1373 rx_set_checksum(sky2);
1374
1375 /* Space needed for frame data + headers rounded up */
1376 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1377
1378 /* Stopping point for hardware truncation */
1379 thresh = (size - 8) / sizeof(u32);
1380
1381 sky2->rx_nfrags = size >> PAGE_SHIFT;
1382 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1383
1384 /* Compute residue after pages */
1385 size -= sky2->rx_nfrags << PAGE_SHIFT;
1386
1387 /* Optimize to handle small packets and headers */
1388 if (size < copybreak)
1389 size = copybreak;
1390 if (size < ETH_HLEN)
1391 size = ETH_HLEN;
1392
1393 sky2->rx_data_size = size;
1394
1395 /* Fill Rx ring */
1396 for (i = 0; i < sky2->rx_pending; i++) {
1397 re = sky2->rx_ring + i;
1398
1399 re->skb = sky2_rx_alloc(sky2);
1400 if (!re->skb)
1401 goto nomem;
1402
1403 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1404 dev_kfree_skb(re->skb);
1405 re->skb = NULL;
1406 goto nomem;
1407 }
1408
1409 sky2_rx_submit(sky2, re);
1410 }
1411
1412 /*
1413 * The receiver hangs if it receives frames larger than the
1414 * packet buffer. As a workaround, truncate oversize frames, but
1415 * the register is limited to 9 bits, so if you do frames > 2052
1416 * you better get the MTU right!
1417 */
1418 if (thresh > 0x1ff)
1419 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1420 else {
1421 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1422 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1423 }
1424
1425 /* Tell chip about available buffers */
1426 sky2_rx_update(sky2, rxq);
1427
1428 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1429 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1430 /*
1431 * Disable flushing of non ASF packets;
1432 * must be done after initializing the BMUs;
1433 * drivers without ASF support should do this too, otherwise
1434 * it may happen that they cannot run on ASF devices;
1435 * remember that the MAC FIFO isn't reset during initialization.
1436 */
1437 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1438 }
1439
1440 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1441 /* Enable RX Home Address & Routing Header checksum fix */
1442 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1443 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1444
1445 /* Enable TX Home Address & Routing Header checksum fix */
1446 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1447 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1448 }
1449
1450
1451
1452 return 0;
1453 nomem:
1454 sky2_rx_clean(sky2);
1455 return -ENOMEM;
1456 }
1457
1458 static int sky2_alloc_buffers(struct sky2_port *sky2)
1459 {
1460 struct sky2_hw *hw = sky2->hw;
1461
1462 /* must be power of 2 */
1463 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1464 sky2->tx_ring_size *
1465 sizeof(struct sky2_tx_le),
1466 &sky2->tx_le_map);
1467 if (!sky2->tx_le)
1468 goto nomem;
1469
1470 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1471 GFP_KERNEL);
1472 if (!sky2->tx_ring)
1473 goto nomem;
1474
1475 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1476 &sky2->rx_le_map);
1477 if (!sky2->rx_le)
1478 goto nomem;
1479 memset(sky2->rx_le, 0, RX_LE_BYTES);
1480
1481 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1482 GFP_KERNEL);
1483 if (!sky2->rx_ring)
1484 goto nomem;
1485
1486 return 0;
1487 nomem:
1488 return -ENOMEM;
1489 }
1490
1491 static void sky2_free_buffers(struct sky2_port *sky2)
1492 {
1493 struct sky2_hw *hw = sky2->hw;
1494
1495 if (sky2->rx_le) {
1496 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1497 sky2->rx_le, sky2->rx_le_map);
1498 sky2->rx_le = NULL;
1499 }
1500 if (sky2->tx_le) {
1501 pci_free_consistent(hw->pdev,
1502 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1503 sky2->tx_le, sky2->tx_le_map);
1504 sky2->tx_le = NULL;
1505 }
1506 kfree(sky2->tx_ring);
1507 kfree(sky2->rx_ring);
1508
1509 sky2->tx_ring = NULL;
1510 sky2->rx_ring = NULL;
1511 }
1512
1513 /* Bring up network interface. */
1514 static int sky2_up(struct net_device *dev)
1515 {
1516 struct sky2_port *sky2 = netdev_priv(dev);
1517 struct sky2_hw *hw = sky2->hw;
1518 unsigned port = sky2->port;
1519 u32 imask, ramsize;
1520 int cap, err;
1521 struct net_device *otherdev = hw->dev[sky2->port^1];
1522
1523 /*
1524 * On dual port PCI-X card, there is an problem where status
1525 * can be received out of order due to split transactions
1526 */
1527 if (otherdev && netif_running(otherdev) &&
1528 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1529 u16 cmd;
1530
1531 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1532 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1533 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1534
1535 }
1536
1537 netif_carrier_off(dev);
1538
1539 err = sky2_alloc_buffers(sky2);
1540 if (err)
1541 goto err_out;
1542
1543 tx_init(sky2);
1544
1545 sky2_mac_init(hw, port);
1546
1547 /* Register is number of 4K blocks on internal RAM buffer. */
1548 ramsize = sky2_read8(hw, B2_E_0) * 4;
1549 if (ramsize > 0) {
1550 u32 rxspace;
1551
1552 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1553 if (ramsize < 16)
1554 rxspace = ramsize / 2;
1555 else
1556 rxspace = 8 + (2*(ramsize - 16))/3;
1557
1558 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1559 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1560
1561 /* Make sure SyncQ is disabled */
1562 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1563 RB_RST_SET);
1564 }
1565
1566 sky2_qset(hw, txqaddr[port]);
1567
1568 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1569 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1570 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1571
1572 /* Set almost empty threshold */
1573 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1574 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1575 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1576
1577 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1578 sky2->tx_ring_size - 1);
1579
1580 #ifdef SKY2_VLAN_TAG_USED
1581 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1582 #endif
1583
1584 err = sky2_rx_start(sky2);
1585 if (err)
1586 goto err_out;
1587
1588 /* Enable interrupts from phy/mac for port */
1589 imask = sky2_read32(hw, B0_IMSK);
1590 imask |= portirq_msk[port];
1591 sky2_write32(hw, B0_IMSK, imask);
1592 sky2_read32(hw, B0_IMSK);
1593
1594 if (netif_msg_ifup(sky2))
1595 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1596
1597 return 0;
1598
1599 err_out:
1600 sky2_free_buffers(sky2);
1601 return err;
1602 }
1603
1604 /* Modular subtraction in ring */
1605 static inline int tx_inuse(const struct sky2_port *sky2)
1606 {
1607 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1608 }
1609
1610 /* Number of list elements available for next tx */
1611 static inline int tx_avail(const struct sky2_port *sky2)
1612 {
1613 return sky2->tx_pending - tx_inuse(sky2);
1614 }
1615
1616 /* Estimate of number of transmit list elements required */
1617 static unsigned tx_le_req(const struct sk_buff *skb)
1618 {
1619 unsigned count;
1620
1621 count = (skb_shinfo(skb)->nr_frags + 1)
1622 * (sizeof(dma_addr_t) / sizeof(u32));
1623
1624 if (skb_is_gso(skb))
1625 ++count;
1626 else if (sizeof(dma_addr_t) == sizeof(u32))
1627 ++count; /* possible vlan */
1628
1629 if (skb->ip_summed == CHECKSUM_PARTIAL)
1630 ++count;
1631
1632 return count;
1633 }
1634
1635 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1636 {
1637 if (re->flags & TX_MAP_SINGLE)
1638 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1639 pci_unmap_len(re, maplen),
1640 PCI_DMA_TODEVICE);
1641 else if (re->flags & TX_MAP_PAGE)
1642 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1643 pci_unmap_len(re, maplen),
1644 PCI_DMA_TODEVICE);
1645 re->flags = 0;
1646 }
1647
1648 /*
1649 * Put one packet in ring for transmit.
1650 * A single packet can generate multiple list elements, and
1651 * the number of ring elements will probably be less than the number
1652 * of list elements used.
1653 */
1654 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1655 struct net_device *dev)
1656 {
1657 struct sky2_port *sky2 = netdev_priv(dev);
1658 struct sky2_hw *hw = sky2->hw;
1659 struct sky2_tx_le *le = NULL;
1660 struct tx_ring_info *re;
1661 unsigned i, len;
1662 dma_addr_t mapping;
1663 u32 upper;
1664 u16 slot;
1665 u16 mss;
1666 u8 ctrl;
1667
1668 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1669 return NETDEV_TX_BUSY;
1670
1671 len = skb_headlen(skb);
1672 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1673
1674 if (pci_dma_mapping_error(hw->pdev, mapping))
1675 goto mapping_error;
1676
1677 slot = sky2->tx_prod;
1678 if (unlikely(netif_msg_tx_queued(sky2)))
1679 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1680 dev->name, slot, skb->len);
1681
1682 /* Send high bits if needed */
1683 upper = upper_32_bits(mapping);
1684 if (upper != sky2->tx_last_upper) {
1685 le = get_tx_le(sky2, &slot);
1686 le->addr = cpu_to_le32(upper);
1687 sky2->tx_last_upper = upper;
1688 le->opcode = OP_ADDR64 | HW_OWNER;
1689 }
1690
1691 /* Check for TCP Segmentation Offload */
1692 mss = skb_shinfo(skb)->gso_size;
1693 if (mss != 0) {
1694
1695 if (!(hw->flags & SKY2_HW_NEW_LE))
1696 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1697
1698 if (mss != sky2->tx_last_mss) {
1699 le = get_tx_le(sky2, &slot);
1700 le->addr = cpu_to_le32(mss);
1701
1702 if (hw->flags & SKY2_HW_NEW_LE)
1703 le->opcode = OP_MSS | HW_OWNER;
1704 else
1705 le->opcode = OP_LRGLEN | HW_OWNER;
1706 sky2->tx_last_mss = mss;
1707 }
1708 }
1709
1710 ctrl = 0;
1711 #ifdef SKY2_VLAN_TAG_USED
1712 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1713 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1714 if (!le) {
1715 le = get_tx_le(sky2, &slot);
1716 le->addr = 0;
1717 le->opcode = OP_VLAN|HW_OWNER;
1718 } else
1719 le->opcode |= OP_VLAN;
1720 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1721 ctrl |= INS_VLAN;
1722 }
1723 #endif
1724
1725 /* Handle TCP checksum offload */
1726 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1727 /* On Yukon EX (some versions) encoding change. */
1728 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1729 ctrl |= CALSUM; /* auto checksum */
1730 else {
1731 const unsigned offset = skb_transport_offset(skb);
1732 u32 tcpsum;
1733
1734 tcpsum = offset << 16; /* sum start */
1735 tcpsum |= offset + skb->csum_offset; /* sum write */
1736
1737 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1738 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1739 ctrl |= UDPTCP;
1740
1741 if (tcpsum != sky2->tx_tcpsum) {
1742 sky2->tx_tcpsum = tcpsum;
1743
1744 le = get_tx_le(sky2, &slot);
1745 le->addr = cpu_to_le32(tcpsum);
1746 le->length = 0; /* initial checksum value */
1747 le->ctrl = 1; /* one packet */
1748 le->opcode = OP_TCPLISW | HW_OWNER;
1749 }
1750 }
1751 }
1752
1753 re = sky2->tx_ring + slot;
1754 re->flags = TX_MAP_SINGLE;
1755 pci_unmap_addr_set(re, mapaddr, mapping);
1756 pci_unmap_len_set(re, maplen, len);
1757
1758 le = get_tx_le(sky2, &slot);
1759 le->addr = cpu_to_le32(lower_32_bits(mapping));
1760 le->length = cpu_to_le16(len);
1761 le->ctrl = ctrl;
1762 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1763
1764
1765 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1766 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1767
1768 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1769 frag->size, PCI_DMA_TODEVICE);
1770
1771 if (pci_dma_mapping_error(hw->pdev, mapping))
1772 goto mapping_unwind;
1773
1774 upper = upper_32_bits(mapping);
1775 if (upper != sky2->tx_last_upper) {
1776 le = get_tx_le(sky2, &slot);
1777 le->addr = cpu_to_le32(upper);
1778 sky2->tx_last_upper = upper;
1779 le->opcode = OP_ADDR64 | HW_OWNER;
1780 }
1781
1782 re = sky2->tx_ring + slot;
1783 re->flags = TX_MAP_PAGE;
1784 pci_unmap_addr_set(re, mapaddr, mapping);
1785 pci_unmap_len_set(re, maplen, frag->size);
1786
1787 le = get_tx_le(sky2, &slot);
1788 le->addr = cpu_to_le32(lower_32_bits(mapping));
1789 le->length = cpu_to_le16(frag->size);
1790 le->ctrl = ctrl;
1791 le->opcode = OP_BUFFER | HW_OWNER;
1792 }
1793
1794 re->skb = skb;
1795 le->ctrl |= EOP;
1796
1797 sky2->tx_prod = slot;
1798
1799 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1800 netif_stop_queue(dev);
1801
1802 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1803
1804 return NETDEV_TX_OK;
1805
1806 mapping_unwind:
1807 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1808 re = sky2->tx_ring + i;
1809
1810 sky2_tx_unmap(hw->pdev, re);
1811 }
1812
1813 mapping_error:
1814 if (net_ratelimit())
1815 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1816 dev_kfree_skb(skb);
1817 return NETDEV_TX_OK;
1818 }
1819
1820 /*
1821 * Free ring elements from starting at tx_cons until "done"
1822 *
1823 * NB:
1824 * 1. The hardware will tell us about partial completion of multi-part
1825 * buffers so make sure not to free skb to early.
1826 * 2. This may run in parallel start_xmit because the it only
1827 * looks at the tail of the queue of FIFO (tx_cons), not
1828 * the head (tx_prod)
1829 */
1830 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1831 {
1832 struct net_device *dev = sky2->netdev;
1833 unsigned idx;
1834
1835 BUG_ON(done >= sky2->tx_ring_size);
1836
1837 for (idx = sky2->tx_cons; idx != done;
1838 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
1839 struct tx_ring_info *re = sky2->tx_ring + idx;
1840 struct sk_buff *skb = re->skb;
1841
1842 sky2_tx_unmap(sky2->hw->pdev, re);
1843
1844 if (skb) {
1845 if (unlikely(netif_msg_tx_done(sky2)))
1846 printk(KERN_DEBUG "%s: tx done %u\n",
1847 dev->name, idx);
1848
1849 dev->stats.tx_packets++;
1850 dev->stats.tx_bytes += skb->len;
1851
1852 re->skb = NULL;
1853 dev_kfree_skb_any(skb);
1854
1855 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
1856 }
1857 }
1858
1859 sky2->tx_cons = idx;
1860 smp_mb();
1861
1862 /* Wake unless it's detached, and called e.g. from sky2_down() */
1863 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4 && netif_device_present(dev))
1864 netif_wake_queue(dev);
1865 }
1866
1867 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
1868 {
1869 /* Disable Force Sync bit and Enable Alloc bit */
1870 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1871 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1872
1873 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1874 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1875 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1876
1877 /* Reset the PCI FIFO of the async Tx queue */
1878 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1879 BMU_RST_SET | BMU_FIFO_RST);
1880
1881 /* Reset the Tx prefetch units */
1882 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1883 PREF_UNIT_RST_SET);
1884
1885 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1886 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1887 }
1888
1889 /* Network shutdown */
1890 static int sky2_down(struct net_device *dev)
1891 {
1892 struct sky2_port *sky2 = netdev_priv(dev);
1893 struct sky2_hw *hw = sky2->hw;
1894 unsigned port = sky2->port;
1895 u16 ctrl;
1896 u32 imask;
1897
1898 /* Never really got started! */
1899 if (!sky2->tx_le)
1900 return 0;
1901
1902 if (netif_msg_ifdown(sky2))
1903 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1904
1905 /* Force flow control off */
1906 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1907
1908 /* Stop transmitter */
1909 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1910 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1911
1912 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1913 RB_RST_SET | RB_DIS_OP_MD);
1914
1915 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1916 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1917 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1918
1919 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1920
1921 /* Workaround shared GMAC reset */
1922 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1923 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1924 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1925
1926 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1927
1928 /* Force any delayed status interrrupt and NAPI */
1929 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1930 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1931 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1932 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1933
1934 sky2_rx_stop(sky2);
1935
1936 /* Disable port IRQ */
1937 imask = sky2_read32(hw, B0_IMSK);
1938 imask &= ~portirq_msk[port];
1939 sky2_write32(hw, B0_IMSK, imask);
1940 sky2_read32(hw, B0_IMSK);
1941
1942 synchronize_irq(hw->pdev->irq);
1943 napi_synchronize(&hw->napi);
1944
1945 spin_lock_bh(&sky2->phy_lock);
1946 sky2_phy_power_down(hw, port);
1947 spin_unlock_bh(&sky2->phy_lock);
1948
1949 sky2_tx_reset(hw, port);
1950
1951 /* Free any pending frames stuck in HW queue */
1952 sky2_tx_complete(sky2, sky2->tx_prod);
1953
1954 sky2_rx_clean(sky2);
1955
1956 sky2_free_buffers(sky2);
1957
1958 return 0;
1959 }
1960
1961 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1962 {
1963 if (hw->flags & SKY2_HW_FIBRE_PHY)
1964 return SPEED_1000;
1965
1966 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1967 if (aux & PHY_M_PS_SPEED_100)
1968 return SPEED_100;
1969 else
1970 return SPEED_10;
1971 }
1972
1973 switch (aux & PHY_M_PS_SPEED_MSK) {
1974 case PHY_M_PS_SPEED_1000:
1975 return SPEED_1000;
1976 case PHY_M_PS_SPEED_100:
1977 return SPEED_100;
1978 default:
1979 return SPEED_10;
1980 }
1981 }
1982
1983 static void sky2_link_up(struct sky2_port *sky2)
1984 {
1985 struct sky2_hw *hw = sky2->hw;
1986 unsigned port = sky2->port;
1987 static const char *fc_name[] = {
1988 [FC_NONE] = "none",
1989 [FC_TX] = "tx",
1990 [FC_RX] = "rx",
1991 [FC_BOTH] = "both",
1992 };
1993
1994 sky2_enable_rx_tx(sky2);
1995
1996 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1997
1998 netif_carrier_on(sky2->netdev);
1999
2000 mod_timer(&hw->watchdog_timer, jiffies + 1);
2001
2002 /* Turn on link LED */
2003 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2004 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2005
2006 if (netif_msg_link(sky2))
2007 printk(KERN_INFO PFX
2008 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
2009 sky2->netdev->name, sky2->speed,
2010 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2011 fc_name[sky2->flow_status]);
2012 }
2013
2014 static void sky2_link_down(struct sky2_port *sky2)
2015 {
2016 struct sky2_hw *hw = sky2->hw;
2017 unsigned port = sky2->port;
2018 u16 reg;
2019
2020 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2021
2022 reg = gma_read16(hw, port, GM_GP_CTRL);
2023 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2024 gma_write16(hw, port, GM_GP_CTRL, reg);
2025
2026 netif_carrier_off(sky2->netdev);
2027
2028 /* Turn off link LED */
2029 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2030
2031 if (netif_msg_link(sky2))
2032 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2033
2034 sky2_phy_init(hw, port);
2035 }
2036
2037 static enum flow_control sky2_flow(int rx, int tx)
2038 {
2039 if (rx)
2040 return tx ? FC_BOTH : FC_RX;
2041 else
2042 return tx ? FC_TX : FC_NONE;
2043 }
2044
2045 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2046 {
2047 struct sky2_hw *hw = sky2->hw;
2048 unsigned port = sky2->port;
2049 u16 advert, lpa;
2050
2051 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2052 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2053 if (lpa & PHY_M_AN_RF) {
2054 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2055 return -1;
2056 }
2057
2058 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2059 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2060 sky2->netdev->name);
2061 return -1;
2062 }
2063
2064 sky2->speed = sky2_phy_speed(hw, aux);
2065 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2066
2067 /* Since the pause result bits seem to in different positions on
2068 * different chips. look at registers.
2069 */
2070 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2071 /* Shift for bits in fiber PHY */
2072 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2073 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2074
2075 if (advert & ADVERTISE_1000XPAUSE)
2076 advert |= ADVERTISE_PAUSE_CAP;
2077 if (advert & ADVERTISE_1000XPSE_ASYM)
2078 advert |= ADVERTISE_PAUSE_ASYM;
2079 if (lpa & LPA_1000XPAUSE)
2080 lpa |= LPA_PAUSE_CAP;
2081 if (lpa & LPA_1000XPAUSE_ASYM)
2082 lpa |= LPA_PAUSE_ASYM;
2083 }
2084
2085 sky2->flow_status = FC_NONE;
2086 if (advert & ADVERTISE_PAUSE_CAP) {
2087 if (lpa & LPA_PAUSE_CAP)
2088 sky2->flow_status = FC_BOTH;
2089 else if (advert & ADVERTISE_PAUSE_ASYM)
2090 sky2->flow_status = FC_RX;
2091 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2092 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2093 sky2->flow_status = FC_TX;
2094 }
2095
2096 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2097 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2098 sky2->flow_status = FC_NONE;
2099
2100 if (sky2->flow_status & FC_TX)
2101 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2102 else
2103 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2104
2105 return 0;
2106 }
2107
2108 /* Interrupt from PHY */
2109 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2110 {
2111 struct net_device *dev = hw->dev[port];
2112 struct sky2_port *sky2 = netdev_priv(dev);
2113 u16 istatus, phystat;
2114
2115 if (!netif_running(dev))
2116 return;
2117
2118 spin_lock(&sky2->phy_lock);
2119 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2120 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2121
2122 if (netif_msg_intr(sky2))
2123 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2124 sky2->netdev->name, istatus, phystat);
2125
2126 if (istatus & PHY_M_IS_AN_COMPL) {
2127 if (sky2_autoneg_done(sky2, phystat) == 0)
2128 sky2_link_up(sky2);
2129 goto out;
2130 }
2131
2132 if (istatus & PHY_M_IS_LSP_CHANGE)
2133 sky2->speed = sky2_phy_speed(hw, phystat);
2134
2135 if (istatus & PHY_M_IS_DUP_CHANGE)
2136 sky2->duplex =
2137 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2138
2139 if (istatus & PHY_M_IS_LST_CHANGE) {
2140 if (phystat & PHY_M_PS_LINK_UP)
2141 sky2_link_up(sky2);
2142 else
2143 sky2_link_down(sky2);
2144 }
2145 out:
2146 spin_unlock(&sky2->phy_lock);
2147 }
2148
2149 /* Special quick link interrupt (Yukon-2 Optima only) */
2150 static void sky2_qlink_intr(struct sky2_hw *hw)
2151 {
2152 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2153 u32 imask;
2154 u16 phy;
2155
2156 /* disable irq */
2157 imask = sky2_read32(hw, B0_IMSK);
2158 imask &= ~Y2_IS_PHY_QLNK;
2159 sky2_write32(hw, B0_IMSK, imask);
2160
2161 /* reset PHY Link Detect */
2162 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2163 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2164 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2165 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2166
2167 sky2_link_up(sky2);
2168 }
2169
2170 /* Transmit timeout is only called if we are running, carrier is up
2171 * and tx queue is full (stopped).
2172 */
2173 static void sky2_tx_timeout(struct net_device *dev)
2174 {
2175 struct sky2_port *sky2 = netdev_priv(dev);
2176 struct sky2_hw *hw = sky2->hw;
2177
2178 if (netif_msg_timer(sky2))
2179 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2180
2181 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2182 dev->name, sky2->tx_cons, sky2->tx_prod,
2183 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2184 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2185
2186 /* can't restart safely under softirq */
2187 schedule_work(&hw->restart_work);
2188 }
2189
2190 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2191 {
2192 struct sky2_port *sky2 = netdev_priv(dev);
2193 struct sky2_hw *hw = sky2->hw;
2194 unsigned port = sky2->port;
2195 int err;
2196 u16 ctl, mode;
2197 u32 imask;
2198
2199 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2200 return -EINVAL;
2201
2202 if (new_mtu > ETH_DATA_LEN &&
2203 (hw->chip_id == CHIP_ID_YUKON_FE ||
2204 hw->chip_id == CHIP_ID_YUKON_FE_P))
2205 return -EINVAL;
2206
2207 if (!netif_running(dev)) {
2208 dev->mtu = new_mtu;
2209 return 0;
2210 }
2211
2212 imask = sky2_read32(hw, B0_IMSK);
2213 sky2_write32(hw, B0_IMSK, 0);
2214
2215 dev->trans_start = jiffies; /* prevent tx timeout */
2216 netif_stop_queue(dev);
2217 napi_disable(&hw->napi);
2218
2219 synchronize_irq(hw->pdev->irq);
2220
2221 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2222 sky2_set_tx_stfwd(hw, port);
2223
2224 ctl = gma_read16(hw, port, GM_GP_CTRL);
2225 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2226 sky2_rx_stop(sky2);
2227 sky2_rx_clean(sky2);
2228
2229 dev->mtu = new_mtu;
2230
2231 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2232 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2233
2234 if (dev->mtu > ETH_DATA_LEN)
2235 mode |= GM_SMOD_JUMBO_ENA;
2236
2237 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2238
2239 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2240
2241 err = sky2_rx_start(sky2);
2242 sky2_write32(hw, B0_IMSK, imask);
2243
2244 sky2_read32(hw, B0_Y2_SP_LISR);
2245 napi_enable(&hw->napi);
2246
2247 if (err)
2248 dev_close(dev);
2249 else {
2250 gma_write16(hw, port, GM_GP_CTRL, ctl);
2251
2252 netif_wake_queue(dev);
2253 }
2254
2255 return err;
2256 }
2257
2258 /* For small just reuse existing skb for next receive */
2259 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2260 const struct rx_ring_info *re,
2261 unsigned length)
2262 {
2263 struct sk_buff *skb;
2264
2265 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2266 if (likely(skb)) {
2267 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2268 length, PCI_DMA_FROMDEVICE);
2269 skb_copy_from_linear_data(re->skb, skb->data, length);
2270 skb->ip_summed = re->skb->ip_summed;
2271 skb->csum = re->skb->csum;
2272 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2273 length, PCI_DMA_FROMDEVICE);
2274 re->skb->ip_summed = CHECKSUM_NONE;
2275 skb_put(skb, length);
2276 }
2277 return skb;
2278 }
2279
2280 /* Adjust length of skb with fragments to match received data */
2281 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2282 unsigned int length)
2283 {
2284 int i, num_frags;
2285 unsigned int size;
2286
2287 /* put header into skb */
2288 size = min(length, hdr_space);
2289 skb->tail += size;
2290 skb->len += size;
2291 length -= size;
2292
2293 num_frags = skb_shinfo(skb)->nr_frags;
2294 for (i = 0; i < num_frags; i++) {
2295 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2296
2297 if (length == 0) {
2298 /* don't need this page */
2299 __free_page(frag->page);
2300 --skb_shinfo(skb)->nr_frags;
2301 } else {
2302 size = min(length, (unsigned) PAGE_SIZE);
2303
2304 frag->size = size;
2305 skb->data_len += size;
2306 skb->truesize += size;
2307 skb->len += size;
2308 length -= size;
2309 }
2310 }
2311 }
2312
2313 /* Normal packet - take skb from ring element and put in a new one */
2314 static struct sk_buff *receive_new(struct sky2_port *sky2,
2315 struct rx_ring_info *re,
2316 unsigned int length)
2317 {
2318 struct sk_buff *skb, *nskb;
2319 unsigned hdr_space = sky2->rx_data_size;
2320
2321 /* Don't be tricky about reusing pages (yet) */
2322 nskb = sky2_rx_alloc(sky2);
2323 if (unlikely(!nskb))
2324 return NULL;
2325
2326 skb = re->skb;
2327 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2328
2329 prefetch(skb->data);
2330 re->skb = nskb;
2331 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2332 dev_kfree_skb(nskb);
2333 re->skb = skb;
2334 return NULL;
2335 }
2336
2337 if (skb_shinfo(skb)->nr_frags)
2338 skb_put_frags(skb, hdr_space, length);
2339 else
2340 skb_put(skb, length);
2341 return skb;
2342 }
2343
2344 /*
2345 * Receive one packet.
2346 * For larger packets, get new buffer.
2347 */
2348 static struct sk_buff *sky2_receive(struct net_device *dev,
2349 u16 length, u32 status)
2350 {
2351 struct sky2_port *sky2 = netdev_priv(dev);
2352 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2353 struct sk_buff *skb = NULL;
2354 u16 count = (status & GMR_FS_LEN) >> 16;
2355
2356 #ifdef SKY2_VLAN_TAG_USED
2357 /* Account for vlan tag */
2358 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2359 count -= VLAN_HLEN;
2360 #endif
2361
2362 if (unlikely(netif_msg_rx_status(sky2)))
2363 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2364 dev->name, sky2->rx_next, status, length);
2365
2366 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2367 prefetch(sky2->rx_ring + sky2->rx_next);
2368
2369 /* This chip has hardware problems that generates bogus status.
2370 * So do only marginal checking and expect higher level protocols
2371 * to handle crap frames.
2372 */
2373 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2374 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2375 length != count)
2376 goto okay;
2377
2378 if (status & GMR_FS_ANY_ERR)
2379 goto error;
2380
2381 if (!(status & GMR_FS_RX_OK))
2382 goto resubmit;
2383
2384 /* if length reported by DMA does not match PHY, packet was truncated */
2385 if (length != count)
2386 goto len_error;
2387
2388 okay:
2389 if (length < copybreak)
2390 skb = receive_copy(sky2, re, length);
2391 else
2392 skb = receive_new(sky2, re, length);
2393 resubmit:
2394 sky2_rx_submit(sky2, re);
2395
2396 return skb;
2397
2398 len_error:
2399 /* Truncation of overlength packets
2400 causes PHY length to not match MAC length */
2401 ++dev->stats.rx_length_errors;
2402 if (netif_msg_rx_err(sky2) && net_ratelimit())
2403 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2404 dev->name, status, length);
2405 goto resubmit;
2406
2407 error:
2408 ++dev->stats.rx_errors;
2409 if (status & GMR_FS_RX_FF_OV) {
2410 dev->stats.rx_over_errors++;
2411 goto resubmit;
2412 }
2413
2414 if (netif_msg_rx_err(sky2) && net_ratelimit())
2415 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2416 dev->name, status, length);
2417
2418 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2419 dev->stats.rx_length_errors++;
2420 if (status & GMR_FS_FRAGMENT)
2421 dev->stats.rx_frame_errors++;
2422 if (status & GMR_FS_CRC_ERR)
2423 dev->stats.rx_crc_errors++;
2424
2425 goto resubmit;
2426 }
2427
2428 /* Transmit complete */
2429 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2430 {
2431 struct sky2_port *sky2 = netdev_priv(dev);
2432
2433 if (netif_running(dev))
2434 sky2_tx_complete(sky2, last);
2435 }
2436
2437 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2438 u32 status, struct sk_buff *skb)
2439 {
2440 #ifdef SKY2_VLAN_TAG_USED
2441 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2442 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2443 if (skb->ip_summed == CHECKSUM_NONE)
2444 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2445 else
2446 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2447 vlan_tag, skb);
2448 return;
2449 }
2450 #endif
2451 if (skb->ip_summed == CHECKSUM_NONE)
2452 netif_receive_skb(skb);
2453 else
2454 napi_gro_receive(&sky2->hw->napi, skb);
2455 }
2456
2457 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2458 unsigned packets, unsigned bytes)
2459 {
2460 if (packets) {
2461 struct net_device *dev = hw->dev[port];
2462
2463 dev->stats.rx_packets += packets;
2464 dev->stats.rx_bytes += bytes;
2465 dev->last_rx = jiffies;
2466 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2467 }
2468 }
2469
2470 /* Process status response ring */
2471 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2472 {
2473 int work_done = 0;
2474 unsigned int total_bytes[2] = { 0 };
2475 unsigned int total_packets[2] = { 0 };
2476
2477 rmb();
2478 do {
2479 struct sky2_port *sky2;
2480 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2481 unsigned port;
2482 struct net_device *dev;
2483 struct sk_buff *skb;
2484 u32 status;
2485 u16 length;
2486 u8 opcode = le->opcode;
2487
2488 if (!(opcode & HW_OWNER))
2489 break;
2490
2491 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2492
2493 port = le->css & CSS_LINK_BIT;
2494 dev = hw->dev[port];
2495 sky2 = netdev_priv(dev);
2496 length = le16_to_cpu(le->length);
2497 status = le32_to_cpu(le->status);
2498
2499 le->opcode = 0;
2500 switch (opcode & ~HW_OWNER) {
2501 case OP_RXSTAT:
2502 total_packets[port]++;
2503 total_bytes[port] += length;
2504 skb = sky2_receive(dev, length, status);
2505 if (unlikely(!skb)) {
2506 dev->stats.rx_dropped++;
2507 break;
2508 }
2509
2510 /* This chip reports checksum status differently */
2511 if (hw->flags & SKY2_HW_NEW_LE) {
2512 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
2513 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2514 (le->css & CSS_TCPUDPCSOK))
2515 skb->ip_summed = CHECKSUM_UNNECESSARY;
2516 else
2517 skb->ip_summed = CHECKSUM_NONE;
2518 }
2519
2520 skb->protocol = eth_type_trans(skb, dev);
2521
2522 sky2_skb_rx(sky2, status, skb);
2523
2524 /* Stop after net poll weight */
2525 if (++work_done >= to_do)
2526 goto exit_loop;
2527 break;
2528
2529 #ifdef SKY2_VLAN_TAG_USED
2530 case OP_RXVLAN:
2531 sky2->rx_tag = length;
2532 break;
2533
2534 case OP_RXCHKSVLAN:
2535 sky2->rx_tag = length;
2536 /* fall through */
2537 #endif
2538 case OP_RXCHKS:
2539 if (!(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2540 break;
2541
2542 /* If this happens then driver assuming wrong format */
2543 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2544 if (net_ratelimit())
2545 printk(KERN_NOTICE "%s: unexpected"
2546 " checksum status\n",
2547 dev->name);
2548 break;
2549 }
2550
2551 /* Both checksum counters are programmed to start at
2552 * the same offset, so unless there is a problem they
2553 * should match. This failure is an early indication that
2554 * hardware receive checksumming won't work.
2555 */
2556 if (likely(status >> 16 == (status & 0xffff))) {
2557 skb = sky2->rx_ring[sky2->rx_next].skb;
2558 skb->ip_summed = CHECKSUM_COMPLETE;
2559 skb->csum = le16_to_cpu(status);
2560 } else {
2561 printk(KERN_NOTICE PFX "%s: hardware receive "
2562 "checksum problem (status = %#x)\n",
2563 dev->name, status);
2564 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2565
2566 sky2_write32(sky2->hw,
2567 Q_ADDR(rxqaddr[port], Q_CSR),
2568 BMU_DIS_RX_CHKSUM);
2569 }
2570 break;
2571
2572 case OP_TXINDEXLE:
2573 /* TX index reports status for both ports */
2574 sky2_tx_done(hw->dev[0], status & 0xfff);
2575 if (hw->dev[1])
2576 sky2_tx_done(hw->dev[1],
2577 ((status >> 24) & 0xff)
2578 | (u16)(length & 0xf) << 8);
2579 break;
2580
2581 default:
2582 if (net_ratelimit())
2583 printk(KERN_WARNING PFX
2584 "unknown status opcode 0x%x\n", opcode);
2585 }
2586 } while (hw->st_idx != idx);
2587
2588 /* Fully processed status ring so clear irq */
2589 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2590
2591 exit_loop:
2592 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2593 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2594
2595 return work_done;
2596 }
2597
2598 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2599 {
2600 struct net_device *dev = hw->dev[port];
2601
2602 if (net_ratelimit())
2603 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2604 dev->name, status);
2605
2606 if (status & Y2_IS_PAR_RD1) {
2607 if (net_ratelimit())
2608 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2609 dev->name);
2610 /* Clear IRQ */
2611 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2612 }
2613
2614 if (status & Y2_IS_PAR_WR1) {
2615 if (net_ratelimit())
2616 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2617 dev->name);
2618
2619 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2620 }
2621
2622 if (status & Y2_IS_PAR_MAC1) {
2623 if (net_ratelimit())
2624 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2625 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2626 }
2627
2628 if (status & Y2_IS_PAR_RX1) {
2629 if (net_ratelimit())
2630 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2631 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2632 }
2633
2634 if (status & Y2_IS_TCP_TXA1) {
2635 if (net_ratelimit())
2636 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2637 dev->name);
2638 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2639 }
2640 }
2641
2642 static void sky2_hw_intr(struct sky2_hw *hw)
2643 {
2644 struct pci_dev *pdev = hw->pdev;
2645 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2646 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2647
2648 status &= hwmsk;
2649
2650 if (status & Y2_IS_TIST_OV)
2651 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2652
2653 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2654 u16 pci_err;
2655
2656 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2657 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2658 if (net_ratelimit())
2659 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2660 pci_err);
2661
2662 sky2_pci_write16(hw, PCI_STATUS,
2663 pci_err | PCI_STATUS_ERROR_BITS);
2664 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2665 }
2666
2667 if (status & Y2_IS_PCI_EXP) {
2668 /* PCI-Express uncorrectable Error occurred */
2669 u32 err;
2670
2671 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2672 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2673 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2674 0xfffffffful);
2675 if (net_ratelimit())
2676 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2677
2678 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2679 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2680 }
2681
2682 if (status & Y2_HWE_L1_MASK)
2683 sky2_hw_error(hw, 0, status);
2684 status >>= 8;
2685 if (status & Y2_HWE_L1_MASK)
2686 sky2_hw_error(hw, 1, status);
2687 }
2688
2689 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2690 {
2691 struct net_device *dev = hw->dev[port];
2692 struct sky2_port *sky2 = netdev_priv(dev);
2693 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2694
2695 if (netif_msg_intr(sky2))
2696 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2697 dev->name, status);
2698
2699 if (status & GM_IS_RX_CO_OV)
2700 gma_read16(hw, port, GM_RX_IRQ_SRC);
2701
2702 if (status & GM_IS_TX_CO_OV)
2703 gma_read16(hw, port, GM_TX_IRQ_SRC);
2704
2705 if (status & GM_IS_RX_FF_OR) {
2706 ++dev->stats.rx_fifo_errors;
2707 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2708 }
2709
2710 if (status & GM_IS_TX_FF_UR) {
2711 ++dev->stats.tx_fifo_errors;
2712 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2713 }
2714 }
2715
2716 /* This should never happen it is a bug. */
2717 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2718 {
2719 struct net_device *dev = hw->dev[port];
2720 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2721
2722 dev_err(&hw->pdev->dev, PFX
2723 "%s: descriptor error q=%#x get=%u put=%u\n",
2724 dev->name, (unsigned) q, (unsigned) idx,
2725 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2726
2727 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2728 }
2729
2730 static int sky2_rx_hung(struct net_device *dev)
2731 {
2732 struct sky2_port *sky2 = netdev_priv(dev);
2733 struct sky2_hw *hw = sky2->hw;
2734 unsigned port = sky2->port;
2735 unsigned rxq = rxqaddr[port];
2736 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2737 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2738 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2739 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2740
2741 /* If idle and MAC or PCI is stuck */
2742 if (sky2->check.last == dev->last_rx &&
2743 ((mac_rp == sky2->check.mac_rp &&
2744 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2745 /* Check if the PCI RX hang */
2746 (fifo_rp == sky2->check.fifo_rp &&
2747 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2748 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2749 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2750 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2751 return 1;
2752 } else {
2753 sky2->check.last = dev->last_rx;
2754 sky2->check.mac_rp = mac_rp;
2755 sky2->check.mac_lev = mac_lev;
2756 sky2->check.fifo_rp = fifo_rp;
2757 sky2->check.fifo_lev = fifo_lev;
2758 return 0;
2759 }
2760 }
2761
2762 static void sky2_watchdog(unsigned long arg)
2763 {
2764 struct sky2_hw *hw = (struct sky2_hw *) arg;
2765
2766 /* Check for lost IRQ once a second */
2767 if (sky2_read32(hw, B0_ISRC)) {
2768 napi_schedule(&hw->napi);
2769 } else {
2770 int i, active = 0;
2771
2772 for (i = 0; i < hw->ports; i++) {
2773 struct net_device *dev = hw->dev[i];
2774 if (!netif_running(dev))
2775 continue;
2776 ++active;
2777
2778 /* For chips with Rx FIFO, check if stuck */
2779 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2780 sky2_rx_hung(dev)) {
2781 pr_info(PFX "%s: receiver hang detected\n",
2782 dev->name);
2783 schedule_work(&hw->restart_work);
2784 return;
2785 }
2786 }
2787
2788 if (active == 0)
2789 return;
2790 }
2791
2792 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2793 }
2794
2795 /* Hardware/software error handling */
2796 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2797 {
2798 if (net_ratelimit())
2799 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2800
2801 if (status & Y2_IS_HW_ERR)
2802 sky2_hw_intr(hw);
2803
2804 if (status & Y2_IS_IRQ_MAC1)
2805 sky2_mac_intr(hw, 0);
2806
2807 if (status & Y2_IS_IRQ_MAC2)
2808 sky2_mac_intr(hw, 1);
2809
2810 if (status & Y2_IS_CHK_RX1)
2811 sky2_le_error(hw, 0, Q_R1);
2812
2813 if (status & Y2_IS_CHK_RX2)
2814 sky2_le_error(hw, 1, Q_R2);
2815
2816 if (status & Y2_IS_CHK_TXA1)
2817 sky2_le_error(hw, 0, Q_XA1);
2818
2819 if (status & Y2_IS_CHK_TXA2)
2820 sky2_le_error(hw, 1, Q_XA2);
2821 }
2822
2823 static int sky2_poll(struct napi_struct *napi, int work_limit)
2824 {
2825 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2826 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2827 int work_done = 0;
2828 u16 idx;
2829
2830 if (unlikely(status & Y2_IS_ERROR))
2831 sky2_err_intr(hw, status);
2832
2833 if (status & Y2_IS_IRQ_PHY1)
2834 sky2_phy_intr(hw, 0);
2835
2836 if (status & Y2_IS_IRQ_PHY2)
2837 sky2_phy_intr(hw, 1);
2838
2839 if (status & Y2_IS_PHY_QLNK)
2840 sky2_qlink_intr(hw);
2841
2842 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2843 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2844
2845 if (work_done >= work_limit)
2846 goto done;
2847 }
2848
2849 napi_complete(napi);
2850 sky2_read32(hw, B0_Y2_SP_LISR);
2851 done:
2852
2853 return work_done;
2854 }
2855
2856 static irqreturn_t sky2_intr(int irq, void *dev_id)
2857 {
2858 struct sky2_hw *hw = dev_id;
2859 u32 status;
2860
2861 /* Reading this mask interrupts as side effect */
2862 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2863 if (status == 0 || status == ~0)
2864 return IRQ_NONE;
2865
2866 prefetch(&hw->st_le[hw->st_idx]);
2867
2868 napi_schedule(&hw->napi);
2869
2870 return IRQ_HANDLED;
2871 }
2872
2873 #ifdef CONFIG_NET_POLL_CONTROLLER
2874 static void sky2_netpoll(struct net_device *dev)
2875 {
2876 struct sky2_port *sky2 = netdev_priv(dev);
2877
2878 napi_schedule(&sky2->hw->napi);
2879 }
2880 #endif
2881
2882 /* Chip internal frequency for clock calculations */
2883 static u32 sky2_mhz(const struct sky2_hw *hw)
2884 {
2885 switch (hw->chip_id) {
2886 case CHIP_ID_YUKON_EC:
2887 case CHIP_ID_YUKON_EC_U:
2888 case CHIP_ID_YUKON_EX:
2889 case CHIP_ID_YUKON_SUPR:
2890 case CHIP_ID_YUKON_UL_2:
2891 case CHIP_ID_YUKON_OPT:
2892 return 125;
2893
2894 case CHIP_ID_YUKON_FE:
2895 return 100;
2896
2897 case CHIP_ID_YUKON_FE_P:
2898 return 50;
2899
2900 case CHIP_ID_YUKON_XL:
2901 return 156;
2902
2903 default:
2904 BUG();
2905 }
2906 }
2907
2908 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2909 {
2910 return sky2_mhz(hw) * us;
2911 }
2912
2913 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2914 {
2915 return clk / sky2_mhz(hw);
2916 }
2917
2918
2919 static int __devinit sky2_init(struct sky2_hw *hw)
2920 {
2921 u8 t8;
2922
2923 /* Enable all clocks and check for bad PCI access */
2924 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2925
2926 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2927
2928 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2929 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2930
2931 switch(hw->chip_id) {
2932 case CHIP_ID_YUKON_XL:
2933 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2934 break;
2935
2936 case CHIP_ID_YUKON_EC_U:
2937 hw->flags = SKY2_HW_GIGABIT
2938 | SKY2_HW_NEWER_PHY
2939 | SKY2_HW_ADV_POWER_CTL;
2940 break;
2941
2942 case CHIP_ID_YUKON_EX:
2943 hw->flags = SKY2_HW_GIGABIT
2944 | SKY2_HW_NEWER_PHY
2945 | SKY2_HW_NEW_LE
2946 | SKY2_HW_ADV_POWER_CTL;
2947
2948 /* New transmit checksum */
2949 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2950 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2951 break;
2952
2953 case CHIP_ID_YUKON_EC:
2954 /* This rev is really old, and requires untested workarounds */
2955 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2956 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2957 return -EOPNOTSUPP;
2958 }
2959 hw->flags = SKY2_HW_GIGABIT;
2960 break;
2961
2962 case CHIP_ID_YUKON_FE:
2963 break;
2964
2965 case CHIP_ID_YUKON_FE_P:
2966 hw->flags = SKY2_HW_NEWER_PHY
2967 | SKY2_HW_NEW_LE
2968 | SKY2_HW_AUTO_TX_SUM
2969 | SKY2_HW_ADV_POWER_CTL;
2970 break;
2971
2972 case CHIP_ID_YUKON_SUPR:
2973 hw->flags = SKY2_HW_GIGABIT
2974 | SKY2_HW_NEWER_PHY
2975 | SKY2_HW_NEW_LE
2976 | SKY2_HW_AUTO_TX_SUM
2977 | SKY2_HW_ADV_POWER_CTL;
2978 break;
2979
2980 case CHIP_ID_YUKON_UL_2:
2981 hw->flags = SKY2_HW_GIGABIT
2982 | SKY2_HW_ADV_POWER_CTL;
2983 break;
2984
2985 case CHIP_ID_YUKON_OPT:
2986 hw->flags = SKY2_HW_GIGABIT
2987 | SKY2_HW_NEW_LE
2988 | SKY2_HW_ADV_POWER_CTL;
2989 break;
2990
2991 default:
2992 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2993 hw->chip_id);
2994 return -EOPNOTSUPP;
2995 }
2996
2997 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2998 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2999 hw->flags |= SKY2_HW_FIBRE_PHY;
3000
3001 hw->ports = 1;
3002 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3003 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3004 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3005 ++hw->ports;
3006 }
3007
3008 if (sky2_read8(hw, B2_E_0))
3009 hw->flags |= SKY2_HW_RAM_BUFFER;
3010
3011 return 0;
3012 }
3013
3014 static void sky2_reset(struct sky2_hw *hw)
3015 {
3016 struct pci_dev *pdev = hw->pdev;
3017 u16 status;
3018 int i, cap;
3019 u32 hwe_mask = Y2_HWE_ALL_MASK;
3020
3021 /* disable ASF */
3022 if (hw->chip_id == CHIP_ID_YUKON_EX) {
3023 status = sky2_read16(hw, HCU_CCSR);
3024 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3025 HCU_CCSR_UC_STATE_MSK);
3026 sky2_write16(hw, HCU_CCSR, status);
3027 } else
3028 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3029 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3030
3031 /* do a SW reset */
3032 sky2_write8(hw, B0_CTST, CS_RST_SET);
3033 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3034
3035 /* allow writes to PCI config */
3036 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3037
3038 /* clear PCI errors, if any */
3039 status = sky2_pci_read16(hw, PCI_STATUS);
3040 status |= PCI_STATUS_ERROR_BITS;
3041 sky2_pci_write16(hw, PCI_STATUS, status);
3042
3043 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3044
3045 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3046 if (cap) {
3047 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3048 0xfffffffful);
3049
3050 /* If error bit is stuck on ignore it */
3051 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3052 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3053 else
3054 hwe_mask |= Y2_IS_PCI_EXP;
3055 }
3056
3057 sky2_power_on(hw);
3058 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3059
3060 for (i = 0; i < hw->ports; i++) {
3061 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3062 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3063
3064 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3065 hw->chip_id == CHIP_ID_YUKON_SUPR)
3066 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3067 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3068 | GMC_BYP_RETR_ON);
3069
3070 }
3071
3072 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3073 /* enable MACSec clock gating */
3074 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3075 }
3076
3077 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3078 u16 reg;
3079 u32 msk;
3080
3081 if (hw->chip_rev == 0) {
3082 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3083 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3084
3085 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3086 reg = 10;
3087 } else {
3088 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3089 reg = 3;
3090 }
3091
3092 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3093
3094 /* reset PHY Link Detect */
3095 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3096 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3097 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3098 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3099
3100
3101 /* enable PHY Quick Link */
3102 msk = sky2_read32(hw, B0_IMSK);
3103 msk |= Y2_IS_PHY_QLNK;
3104 sky2_write32(hw, B0_IMSK, msk);
3105
3106 /* check if PSMv2 was running before */
3107 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3108 if (reg & PCI_EXP_LNKCTL_ASPMC) {
3109 int cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3110 /* restore the PCIe Link Control register */
3111 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3112 }
3113 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3114
3115 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3116 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3117 }
3118
3119 /* Clear I2C IRQ noise */
3120 sky2_write32(hw, B2_I2C_IRQ, 1);
3121
3122 /* turn off hardware timer (unused) */
3123 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3124 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3125
3126 /* Turn off descriptor polling */
3127 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3128
3129 /* Turn off receive timestamp */
3130 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3131 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3132
3133 /* enable the Tx Arbiters */
3134 for (i = 0; i < hw->ports; i++)
3135 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3136
3137 /* Initialize ram interface */
3138 for (i = 0; i < hw->ports; i++) {
3139 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3140
3141 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3142 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3143 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3144 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3145 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3146 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3147 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3148 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3149 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3150 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3151 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3152 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3153 }
3154
3155 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3156
3157 for (i = 0; i < hw->ports; i++)
3158 sky2_gmac_reset(hw, i);
3159
3160 memset(hw->st_le, 0, STATUS_LE_BYTES);
3161 hw->st_idx = 0;
3162
3163 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3164 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3165
3166 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3167 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3168
3169 /* Set the list last index */
3170 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3171
3172 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3173 sky2_write8(hw, STAT_FIFO_WM, 16);
3174
3175 /* set Status-FIFO ISR watermark */
3176 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3177 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3178 else
3179 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3180
3181 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3182 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3183 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3184
3185 /* enable status unit */
3186 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3187
3188 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3189 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3190 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3191 }
3192
3193 /* Take device down (offline).
3194 * Equivalent to doing dev_stop() but this does not
3195 * inform upper layers of the transistion.
3196 */
3197 static void sky2_detach(struct net_device *dev)
3198 {
3199 if (netif_running(dev)) {
3200 netif_device_detach(dev); /* stop txq */
3201 sky2_down(dev);
3202 }
3203 }
3204
3205 /* Bring device back after doing sky2_detach */
3206 static int sky2_reattach(struct net_device *dev)
3207 {
3208 int err = 0;
3209
3210 if (netif_running(dev)) {
3211 err = sky2_up(dev);
3212 if (err) {
3213 printk(KERN_INFO PFX "%s: could not restart %d\n",
3214 dev->name, err);
3215 dev_close(dev);
3216 } else {
3217 netif_device_attach(dev);
3218 sky2_set_multicast(dev);
3219 }
3220 }
3221
3222 return err;
3223 }
3224
3225 static void sky2_restart(struct work_struct *work)
3226 {
3227 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3228 int i;
3229
3230 rtnl_lock();
3231 for (i = 0; i < hw->ports; i++)
3232 sky2_detach(hw->dev[i]);
3233
3234 napi_disable(&hw->napi);
3235 sky2_write32(hw, B0_IMSK, 0);
3236 sky2_reset(hw);
3237 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3238 napi_enable(&hw->napi);
3239
3240 for (i = 0; i < hw->ports; i++)
3241 sky2_reattach(hw->dev[i]);
3242
3243 rtnl_unlock();
3244 }
3245
3246 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3247 {
3248 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3249 }
3250
3251 static void sky2_hw_set_wol(struct sky2_hw *hw)
3252 {
3253 int wol = 0;
3254 int i;
3255
3256 for (i = 0; i < hw->ports; i++) {
3257 struct net_device *dev = hw->dev[i];
3258 struct sky2_port *sky2 = netdev_priv(dev);
3259
3260 if (sky2->wol)
3261 wol = 1;
3262 }
3263
3264 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3265 hw->chip_id == CHIP_ID_YUKON_EX ||
3266 hw->chip_id == CHIP_ID_YUKON_FE_P)
3267 sky2_write32(hw, B0_CTST, wol ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3268
3269 device_set_wakeup_enable(&hw->pdev->dev, wol);
3270 }
3271
3272 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3273 {
3274 const struct sky2_port *sky2 = netdev_priv(dev);
3275
3276 wol->supported = sky2_wol_supported(sky2->hw);
3277 wol->wolopts = sky2->wol;
3278 }
3279
3280 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3281 {
3282 struct sky2_port *sky2 = netdev_priv(dev);
3283 struct sky2_hw *hw = sky2->hw;
3284
3285 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3286 !device_can_wakeup(&hw->pdev->dev))
3287 return -EOPNOTSUPP;
3288
3289 sky2->wol = wol->wolopts;
3290
3291 sky2_hw_set_wol(hw);
3292
3293 if (!netif_running(dev))
3294 sky2_wol_init(sky2);
3295 return 0;
3296 }
3297
3298 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3299 {
3300 if (sky2_is_copper(hw)) {
3301 u32 modes = SUPPORTED_10baseT_Half
3302 | SUPPORTED_10baseT_Full
3303 | SUPPORTED_100baseT_Half
3304 | SUPPORTED_100baseT_Full
3305 | SUPPORTED_Autoneg | SUPPORTED_TP;
3306
3307 if (hw->flags & SKY2_HW_GIGABIT)
3308 modes |= SUPPORTED_1000baseT_Half
3309 | SUPPORTED_1000baseT_Full;
3310 return modes;
3311 } else
3312 return SUPPORTED_1000baseT_Half
3313 | SUPPORTED_1000baseT_Full
3314 | SUPPORTED_Autoneg
3315 | SUPPORTED_FIBRE;
3316 }
3317
3318 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3319 {
3320 struct sky2_port *sky2 = netdev_priv(dev);
3321 struct sky2_hw *hw = sky2->hw;
3322
3323 ecmd->transceiver = XCVR_INTERNAL;
3324 ecmd->supported = sky2_supported_modes(hw);
3325 ecmd->phy_address = PHY_ADDR_MARV;
3326 if (sky2_is_copper(hw)) {
3327 ecmd->port = PORT_TP;
3328 ecmd->speed = sky2->speed;
3329 } else {
3330 ecmd->speed = SPEED_1000;
3331 ecmd->port = PORT_FIBRE;
3332 }
3333
3334 ecmd->advertising = sky2->advertising;
3335 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3336 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3337 ecmd->duplex = sky2->duplex;
3338 return 0;
3339 }
3340
3341 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3342 {
3343 struct sky2_port *sky2 = netdev_priv(dev);
3344 const struct sky2_hw *hw = sky2->hw;
3345 u32 supported = sky2_supported_modes(hw);
3346
3347 if (ecmd->autoneg == AUTONEG_ENABLE) {
3348 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3349 ecmd->advertising = supported;
3350 sky2->duplex = -1;
3351 sky2->speed = -1;
3352 } else {
3353 u32 setting;
3354
3355 switch (ecmd->speed) {
3356 case SPEED_1000:
3357 if (ecmd->duplex == DUPLEX_FULL)
3358 setting = SUPPORTED_1000baseT_Full;
3359 else if (ecmd->duplex == DUPLEX_HALF)
3360 setting = SUPPORTED_1000baseT_Half;
3361 else
3362 return -EINVAL;
3363 break;
3364 case SPEED_100:
3365 if (ecmd->duplex == DUPLEX_FULL)
3366 setting = SUPPORTED_100baseT_Full;
3367 else if (ecmd->duplex == DUPLEX_HALF)
3368 setting = SUPPORTED_100baseT_Half;
3369 else
3370 return -EINVAL;
3371 break;
3372
3373 case SPEED_10:
3374 if (ecmd->duplex == DUPLEX_FULL)
3375 setting = SUPPORTED_10baseT_Full;
3376 else if (ecmd->duplex == DUPLEX_HALF)
3377 setting = SUPPORTED_10baseT_Half;
3378 else
3379 return -EINVAL;
3380 break;
3381 default:
3382 return -EINVAL;
3383 }
3384
3385 if ((setting & supported) == 0)
3386 return -EINVAL;
3387
3388 sky2->speed = ecmd->speed;
3389 sky2->duplex = ecmd->duplex;
3390 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3391 }
3392
3393 sky2->advertising = ecmd->advertising;
3394
3395 if (netif_running(dev)) {
3396 sky2_phy_reinit(sky2);
3397 sky2_set_multicast(dev);
3398 }
3399
3400 return 0;
3401 }
3402
3403 static void sky2_get_drvinfo(struct net_device *dev,
3404 struct ethtool_drvinfo *info)
3405 {
3406 struct sky2_port *sky2 = netdev_priv(dev);
3407
3408 strcpy(info->driver, DRV_NAME);
3409 strcpy(info->version, DRV_VERSION);
3410 strcpy(info->fw_version, "N/A");
3411 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3412 }
3413
3414 static const struct sky2_stat {
3415 char name[ETH_GSTRING_LEN];
3416 u16 offset;
3417 } sky2_stats[] = {
3418 { "tx_bytes", GM_TXO_OK_HI },
3419 { "rx_bytes", GM_RXO_OK_HI },
3420 { "tx_broadcast", GM_TXF_BC_OK },
3421 { "rx_broadcast", GM_RXF_BC_OK },
3422 { "tx_multicast", GM_TXF_MC_OK },
3423 { "rx_multicast", GM_RXF_MC_OK },
3424 { "tx_unicast", GM_TXF_UC_OK },
3425 { "rx_unicast", GM_RXF_UC_OK },
3426 { "tx_mac_pause", GM_TXF_MPAUSE },
3427 { "rx_mac_pause", GM_RXF_MPAUSE },
3428 { "collisions", GM_TXF_COL },
3429 { "late_collision",GM_TXF_LAT_COL },
3430 { "aborted", GM_TXF_ABO_COL },
3431 { "single_collisions", GM_TXF_SNG_COL },
3432 { "multi_collisions", GM_TXF_MUL_COL },
3433
3434 { "rx_short", GM_RXF_SHT },
3435 { "rx_runt", GM_RXE_FRAG },
3436 { "rx_64_byte_packets", GM_RXF_64B },
3437 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3438 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3439 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3440 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3441 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3442 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3443 { "rx_too_long", GM_RXF_LNG_ERR },
3444 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3445 { "rx_jabber", GM_RXF_JAB_PKT },
3446 { "rx_fcs_error", GM_RXF_FCS_ERR },
3447
3448 { "tx_64_byte_packets", GM_TXF_64B },
3449 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3450 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3451 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3452 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3453 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3454 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3455 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3456 };
3457
3458 static u32 sky2_get_rx_csum(struct net_device *dev)
3459 {
3460 struct sky2_port *sky2 = netdev_priv(dev);
3461
3462 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
3463 }
3464
3465 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3466 {
3467 struct sky2_port *sky2 = netdev_priv(dev);
3468
3469 if (data)
3470 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3471 else
3472 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
3473
3474 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3475 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3476
3477 return 0;
3478 }
3479
3480 static u32 sky2_get_msglevel(struct net_device *netdev)
3481 {
3482 struct sky2_port *sky2 = netdev_priv(netdev);
3483 return sky2->msg_enable;
3484 }
3485
3486 static int sky2_nway_reset(struct net_device *dev)
3487 {
3488 struct sky2_port *sky2 = netdev_priv(dev);
3489
3490 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3491 return -EINVAL;
3492
3493 sky2_phy_reinit(sky2);
3494 sky2_set_multicast(dev);
3495
3496 return 0;
3497 }
3498
3499 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3500 {
3501 struct sky2_hw *hw = sky2->hw;
3502 unsigned port = sky2->port;
3503 int i;
3504
3505 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3506 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3507 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3508 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3509
3510 for (i = 2; i < count; i++)
3511 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3512 }
3513
3514 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3515 {
3516 struct sky2_port *sky2 = netdev_priv(netdev);
3517 sky2->msg_enable = value;
3518 }
3519
3520 static int sky2_get_sset_count(struct net_device *dev, int sset)
3521 {
3522 switch (sset) {
3523 case ETH_SS_STATS:
3524 return ARRAY_SIZE(sky2_stats);
3525 default:
3526 return -EOPNOTSUPP;
3527 }
3528 }
3529
3530 static void sky2_get_ethtool_stats(struct net_device *dev,
3531 struct ethtool_stats *stats, u64 * data)
3532 {
3533 struct sky2_port *sky2 = netdev_priv(dev);
3534
3535 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3536 }
3537
3538 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3539 {
3540 int i;
3541
3542 switch (stringset) {
3543 case ETH_SS_STATS:
3544 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3545 memcpy(data + i * ETH_GSTRING_LEN,
3546 sky2_stats[i].name, ETH_GSTRING_LEN);
3547 break;
3548 }
3549 }
3550
3551 static int sky2_set_mac_address(struct net_device *dev, void *p)
3552 {
3553 struct sky2_port *sky2 = netdev_priv(dev);
3554 struct sky2_hw *hw = sky2->hw;
3555 unsigned port = sky2->port;
3556 const struct sockaddr *addr = p;
3557
3558 if (!is_valid_ether_addr(addr->sa_data))
3559 return -EADDRNOTAVAIL;
3560
3561 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3562 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3563 dev->dev_addr, ETH_ALEN);
3564 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3565 dev->dev_addr, ETH_ALEN);
3566
3567 /* virtual address for data */
3568 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3569
3570 /* physical address: used for pause frames */
3571 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3572
3573 return 0;
3574 }
3575
3576 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3577 {
3578 u32 bit;
3579
3580 bit = ether_crc(ETH_ALEN, addr) & 63;
3581 filter[bit >> 3] |= 1 << (bit & 7);
3582 }
3583
3584 static void sky2_set_multicast(struct net_device *dev)
3585 {
3586 struct sky2_port *sky2 = netdev_priv(dev);
3587 struct sky2_hw *hw = sky2->hw;
3588 unsigned port = sky2->port;
3589 struct dev_mc_list *list = dev->mc_list;
3590 u16 reg;
3591 u8 filter[8];
3592 int rx_pause;
3593 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3594
3595 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3596 memset(filter, 0, sizeof(filter));
3597
3598 reg = gma_read16(hw, port, GM_RX_CTRL);
3599 reg |= GM_RXCR_UCF_ENA;
3600
3601 if (dev->flags & IFF_PROMISC) /* promiscuous */
3602 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3603 else if (dev->flags & IFF_ALLMULTI)
3604 memset(filter, 0xff, sizeof(filter));
3605 else if (dev->mc_count == 0 && !rx_pause)
3606 reg &= ~GM_RXCR_MCF_ENA;
3607 else {
3608 int i;
3609 reg |= GM_RXCR_MCF_ENA;
3610
3611 if (rx_pause)
3612 sky2_add_filter(filter, pause_mc_addr);
3613
3614 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3615 sky2_add_filter(filter, list->dmi_addr);
3616 }
3617
3618 gma_write16(hw, port, GM_MC_ADDR_H1,
3619 (u16) filter[0] | ((u16) filter[1] << 8));
3620 gma_write16(hw, port, GM_MC_ADDR_H2,
3621 (u16) filter[2] | ((u16) filter[3] << 8));
3622 gma_write16(hw, port, GM_MC_ADDR_H3,
3623 (u16) filter[4] | ((u16) filter[5] << 8));
3624 gma_write16(hw, port, GM_MC_ADDR_H4,
3625 (u16) filter[6] | ((u16) filter[7] << 8));
3626
3627 gma_write16(hw, port, GM_RX_CTRL, reg);
3628 }
3629
3630 /* Can have one global because blinking is controlled by
3631 * ethtool and that is always under RTNL mutex
3632 */
3633 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3634 {
3635 struct sky2_hw *hw = sky2->hw;
3636 unsigned port = sky2->port;
3637
3638 spin_lock_bh(&sky2->phy_lock);
3639 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3640 hw->chip_id == CHIP_ID_YUKON_EX ||
3641 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3642 u16 pg;
3643 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3644 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3645
3646 switch (mode) {
3647 case MO_LED_OFF:
3648 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3649 PHY_M_LEDC_LOS_CTRL(8) |
3650 PHY_M_LEDC_INIT_CTRL(8) |
3651 PHY_M_LEDC_STA1_CTRL(8) |
3652 PHY_M_LEDC_STA0_CTRL(8));
3653 break;
3654 case MO_LED_ON:
3655 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3656 PHY_M_LEDC_LOS_CTRL(9) |
3657 PHY_M_LEDC_INIT_CTRL(9) |
3658 PHY_M_LEDC_STA1_CTRL(9) |
3659 PHY_M_LEDC_STA0_CTRL(9));
3660 break;
3661 case MO_LED_BLINK:
3662 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3663 PHY_M_LEDC_LOS_CTRL(0xa) |
3664 PHY_M_LEDC_INIT_CTRL(0xa) |
3665 PHY_M_LEDC_STA1_CTRL(0xa) |
3666 PHY_M_LEDC_STA0_CTRL(0xa));
3667 break;
3668 case MO_LED_NORM:
3669 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3670 PHY_M_LEDC_LOS_CTRL(1) |
3671 PHY_M_LEDC_INIT_CTRL(8) |
3672 PHY_M_LEDC_STA1_CTRL(7) |
3673 PHY_M_LEDC_STA0_CTRL(7));
3674 }
3675
3676 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3677 } else
3678 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3679 PHY_M_LED_MO_DUP(mode) |
3680 PHY_M_LED_MO_10(mode) |
3681 PHY_M_LED_MO_100(mode) |
3682 PHY_M_LED_MO_1000(mode) |
3683 PHY_M_LED_MO_RX(mode) |
3684 PHY_M_LED_MO_TX(mode));
3685
3686 spin_unlock_bh(&sky2->phy_lock);
3687 }
3688
3689 /* blink LED's for finding board */
3690 static int sky2_phys_id(struct net_device *dev, u32 data)
3691 {
3692 struct sky2_port *sky2 = netdev_priv(dev);
3693 unsigned int i;
3694
3695 if (data == 0)
3696 data = UINT_MAX;
3697
3698 for (i = 0; i < data; i++) {
3699 sky2_led(sky2, MO_LED_ON);
3700 if (msleep_interruptible(500))
3701 break;
3702 sky2_led(sky2, MO_LED_OFF);
3703 if (msleep_interruptible(500))
3704 break;
3705 }
3706 sky2_led(sky2, MO_LED_NORM);
3707
3708 return 0;
3709 }
3710
3711 static void sky2_get_pauseparam(struct net_device *dev,
3712 struct ethtool_pauseparam *ecmd)
3713 {
3714 struct sky2_port *sky2 = netdev_priv(dev);
3715
3716 switch (sky2->flow_mode) {
3717 case FC_NONE:
3718 ecmd->tx_pause = ecmd->rx_pause = 0;
3719 break;
3720 case FC_TX:
3721 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3722 break;
3723 case FC_RX:
3724 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3725 break;
3726 case FC_BOTH:
3727 ecmd->tx_pause = ecmd->rx_pause = 1;
3728 }
3729
3730 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3731 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3732 }
3733
3734 static int sky2_set_pauseparam(struct net_device *dev,
3735 struct ethtool_pauseparam *ecmd)
3736 {
3737 struct sky2_port *sky2 = netdev_priv(dev);
3738
3739 if (ecmd->autoneg == AUTONEG_ENABLE)
3740 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3741 else
3742 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3743
3744 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3745
3746 if (netif_running(dev))
3747 sky2_phy_reinit(sky2);
3748
3749 return 0;
3750 }
3751
3752 static int sky2_get_coalesce(struct net_device *dev,
3753 struct ethtool_coalesce *ecmd)
3754 {
3755 struct sky2_port *sky2 = netdev_priv(dev);
3756 struct sky2_hw *hw = sky2->hw;
3757
3758 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3759 ecmd->tx_coalesce_usecs = 0;
3760 else {
3761 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3762 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3763 }
3764 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3765
3766 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3767 ecmd->rx_coalesce_usecs = 0;
3768 else {
3769 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3770 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3771 }
3772 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3773
3774 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3775 ecmd->rx_coalesce_usecs_irq = 0;
3776 else {
3777 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3778 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3779 }
3780
3781 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3782
3783 return 0;
3784 }
3785
3786 /* Note: this affect both ports */
3787 static int sky2_set_coalesce(struct net_device *dev,
3788 struct ethtool_coalesce *ecmd)
3789 {
3790 struct sky2_port *sky2 = netdev_priv(dev);
3791 struct sky2_hw *hw = sky2->hw;
3792 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3793
3794 if (ecmd->tx_coalesce_usecs > tmax ||
3795 ecmd->rx_coalesce_usecs > tmax ||
3796 ecmd->rx_coalesce_usecs_irq > tmax)
3797 return -EINVAL;
3798
3799 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
3800 return -EINVAL;
3801 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3802 return -EINVAL;
3803 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3804 return -EINVAL;
3805
3806 if (ecmd->tx_coalesce_usecs == 0)
3807 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3808 else {
3809 sky2_write32(hw, STAT_TX_TIMER_INI,
3810 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3811 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3812 }
3813 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3814
3815 if (ecmd->rx_coalesce_usecs == 0)
3816 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3817 else {
3818 sky2_write32(hw, STAT_LEV_TIMER_INI,
3819 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3820 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3821 }
3822 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3823
3824 if (ecmd->rx_coalesce_usecs_irq == 0)
3825 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3826 else {
3827 sky2_write32(hw, STAT_ISR_TIMER_INI,
3828 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3829 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3830 }
3831 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3832 return 0;
3833 }
3834
3835 static void sky2_get_ringparam(struct net_device *dev,
3836 struct ethtool_ringparam *ering)
3837 {
3838 struct sky2_port *sky2 = netdev_priv(dev);
3839
3840 ering->rx_max_pending = RX_MAX_PENDING;
3841 ering->rx_mini_max_pending = 0;
3842 ering->rx_jumbo_max_pending = 0;
3843 ering->tx_max_pending = TX_MAX_PENDING;
3844
3845 ering->rx_pending = sky2->rx_pending;
3846 ering->rx_mini_pending = 0;
3847 ering->rx_jumbo_pending = 0;
3848 ering->tx_pending = sky2->tx_pending;
3849 }
3850
3851 static int sky2_set_ringparam(struct net_device *dev,
3852 struct ethtool_ringparam *ering)
3853 {
3854 struct sky2_port *sky2 = netdev_priv(dev);
3855
3856 if (ering->rx_pending > RX_MAX_PENDING ||
3857 ering->rx_pending < 8 ||
3858 ering->tx_pending < TX_MIN_PENDING ||
3859 ering->tx_pending > TX_MAX_PENDING)
3860 return -EINVAL;
3861
3862 sky2_detach(dev);
3863
3864 sky2->rx_pending = ering->rx_pending;
3865 sky2->tx_pending = ering->tx_pending;
3866 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
3867
3868 return sky2_reattach(dev);
3869 }
3870
3871 static int sky2_get_regs_len(struct net_device *dev)
3872 {
3873 return 0x4000;
3874 }
3875
3876 /*
3877 * Returns copy of control register region
3878 * Note: ethtool_get_regs always provides full size (16k) buffer
3879 */
3880 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3881 void *p)
3882 {
3883 const struct sky2_port *sky2 = netdev_priv(dev);
3884 const void __iomem *io = sky2->hw->regs;
3885 unsigned int b;
3886
3887 regs->version = 1;
3888
3889 for (b = 0; b < 128; b++) {
3890 /* This complicated switch statement is to make sure and
3891 * only access regions that are unreserved.
3892 * Some blocks are only valid on dual port cards.
3893 * and block 3 has some special diagnostic registers that
3894 * are poison.
3895 */
3896 switch (b) {
3897 case 3:
3898 /* skip diagnostic ram region */
3899 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3900 break;
3901
3902 /* dual port cards only */
3903 case 5: /* Tx Arbiter 2 */
3904 case 9: /* RX2 */
3905 case 14 ... 15: /* TX2 */
3906 case 17: case 19: /* Ram Buffer 2 */
3907 case 22 ... 23: /* Tx Ram Buffer 2 */
3908 case 25: /* Rx MAC Fifo 1 */
3909 case 27: /* Tx MAC Fifo 2 */
3910 case 31: /* GPHY 2 */
3911 case 40 ... 47: /* Pattern Ram 2 */
3912 case 52: case 54: /* TCP Segmentation 2 */
3913 case 112 ... 116: /* GMAC 2 */
3914 if (sky2->hw->ports == 1)
3915 goto reserved;
3916 /* fall through */
3917 case 0: /* Control */
3918 case 2: /* Mac address */
3919 case 4: /* Tx Arbiter 1 */
3920 case 7: /* PCI express reg */
3921 case 8: /* RX1 */
3922 case 12 ... 13: /* TX1 */
3923 case 16: case 18:/* Rx Ram Buffer 1 */
3924 case 20 ... 21: /* Tx Ram Buffer 1 */
3925 case 24: /* Rx MAC Fifo 1 */
3926 case 26: /* Tx MAC Fifo 1 */
3927 case 28 ... 29: /* Descriptor and status unit */
3928 case 30: /* GPHY 1*/
3929 case 32 ... 39: /* Pattern Ram 1 */
3930 case 48: case 50: /* TCP Segmentation 1 */
3931 case 56 ... 60: /* PCI space */
3932 case 80 ... 84: /* GMAC 1 */
3933 memcpy_fromio(p, io, 128);
3934 break;
3935 default:
3936 reserved:
3937 memset(p, 0, 128);
3938 }
3939
3940 p += 128;
3941 io += 128;
3942 }
3943 }
3944
3945 /* In order to do Jumbo packets on these chips, need to turn off the
3946 * transmit store/forward. Therefore checksum offload won't work.
3947 */
3948 static int no_tx_offload(struct net_device *dev)
3949 {
3950 const struct sky2_port *sky2 = netdev_priv(dev);
3951 const struct sky2_hw *hw = sky2->hw;
3952
3953 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3954 }
3955
3956 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3957 {
3958 if (data && no_tx_offload(dev))
3959 return -EINVAL;
3960
3961 return ethtool_op_set_tx_csum(dev, data);
3962 }
3963
3964
3965 static int sky2_set_tso(struct net_device *dev, u32 data)
3966 {
3967 if (data && no_tx_offload(dev))
3968 return -EINVAL;
3969
3970 return ethtool_op_set_tso(dev, data);
3971 }
3972
3973 static int sky2_get_eeprom_len(struct net_device *dev)
3974 {
3975 struct sky2_port *sky2 = netdev_priv(dev);
3976 struct sky2_hw *hw = sky2->hw;
3977 u16 reg2;
3978
3979 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3980 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3981 }
3982
3983 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
3984 {
3985 unsigned long start = jiffies;
3986
3987 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3988 /* Can take up to 10.6 ms for write */
3989 if (time_after(jiffies, start + HZ/4)) {
3990 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3991 return -ETIMEDOUT;
3992 }
3993 mdelay(1);
3994 }
3995
3996 return 0;
3997 }
3998
3999 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4000 u16 offset, size_t length)
4001 {
4002 int rc = 0;
4003
4004 while (length > 0) {
4005 u32 val;
4006
4007 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4008 rc = sky2_vpd_wait(hw, cap, 0);
4009 if (rc)
4010 break;
4011
4012 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4013
4014 memcpy(data, &val, min(sizeof(val), length));
4015 offset += sizeof(u32);
4016 data += sizeof(u32);
4017 length -= sizeof(u32);
4018 }
4019
4020 return rc;
4021 }
4022
4023 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4024 u16 offset, unsigned int length)
4025 {
4026 unsigned int i;
4027 int rc = 0;
4028
4029 for (i = 0; i < length; i += sizeof(u32)) {
4030 u32 val = *(u32 *)(data + i);
4031
4032 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4033 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4034
4035 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4036 if (rc)
4037 break;
4038 }
4039 return rc;
4040 }
4041
4042 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4043 u8 *data)
4044 {
4045 struct sky2_port *sky2 = netdev_priv(dev);
4046 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4047
4048 if (!cap)
4049 return -EINVAL;
4050
4051 eeprom->magic = SKY2_EEPROM_MAGIC;
4052
4053 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4054 }
4055
4056 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4057 u8 *data)
4058 {
4059 struct sky2_port *sky2 = netdev_priv(dev);
4060 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4061
4062 if (!cap)
4063 return -EINVAL;
4064
4065 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4066 return -EINVAL;
4067
4068 /* Partial writes not supported */
4069 if ((eeprom->offset & 3) || (eeprom->len & 3))
4070 return -EINVAL;
4071
4072 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4073 }
4074
4075
4076 static const struct ethtool_ops sky2_ethtool_ops = {
4077 .get_settings = sky2_get_settings,
4078 .set_settings = sky2_set_settings,
4079 .get_drvinfo = sky2_get_drvinfo,
4080 .get_wol = sky2_get_wol,
4081 .set_wol = sky2_set_wol,
4082 .get_msglevel = sky2_get_msglevel,
4083 .set_msglevel = sky2_set_msglevel,
4084 .nway_reset = sky2_nway_reset,
4085 .get_regs_len = sky2_get_regs_len,
4086 .get_regs = sky2_get_regs,
4087 .get_link = ethtool_op_get_link,
4088 .get_eeprom_len = sky2_get_eeprom_len,
4089 .get_eeprom = sky2_get_eeprom,
4090 .set_eeprom = sky2_set_eeprom,
4091 .set_sg = ethtool_op_set_sg,
4092 .set_tx_csum = sky2_set_tx_csum,
4093 .set_tso = sky2_set_tso,
4094 .get_rx_csum = sky2_get_rx_csum,
4095 .set_rx_csum = sky2_set_rx_csum,
4096 .get_strings = sky2_get_strings,
4097 .get_coalesce = sky2_get_coalesce,
4098 .set_coalesce = sky2_set_coalesce,
4099 .get_ringparam = sky2_get_ringparam,
4100 .set_ringparam = sky2_set_ringparam,
4101 .get_pauseparam = sky2_get_pauseparam,
4102 .set_pauseparam = sky2_set_pauseparam,
4103 .phys_id = sky2_phys_id,
4104 .get_sset_count = sky2_get_sset_count,
4105 .get_ethtool_stats = sky2_get_ethtool_stats,
4106 };
4107
4108 #ifdef CONFIG_SKY2_DEBUG
4109
4110 static struct dentry *sky2_debug;
4111
4112
4113 /*
4114 * Read and parse the first part of Vital Product Data
4115 */
4116 #define VPD_SIZE 128
4117 #define VPD_MAGIC 0x82
4118
4119 static const struct vpd_tag {
4120 char tag[2];
4121 char *label;
4122 } vpd_tags[] = {
4123 { "PN", "Part Number" },
4124 { "EC", "Engineering Level" },
4125 { "MN", "Manufacturer" },
4126 { "SN", "Serial Number" },
4127 { "YA", "Asset Tag" },
4128 { "VL", "First Error Log Message" },
4129 { "VF", "Second Error Log Message" },
4130 { "VB", "Boot Agent ROM Configuration" },
4131 { "VE", "EFI UNDI Configuration" },
4132 };
4133
4134 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4135 {
4136 size_t vpd_size;
4137 loff_t offs;
4138 u8 len;
4139 unsigned char *buf;
4140 u16 reg2;
4141
4142 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4143 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4144
4145 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4146 buf = kmalloc(vpd_size, GFP_KERNEL);
4147 if (!buf) {
4148 seq_puts(seq, "no memory!\n");
4149 return;
4150 }
4151
4152 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4153 seq_puts(seq, "VPD read failed\n");
4154 goto out;
4155 }
4156
4157 if (buf[0] != VPD_MAGIC) {
4158 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4159 goto out;
4160 }
4161 len = buf[1];
4162 if (len == 0 || len > vpd_size - 4) {
4163 seq_printf(seq, "Invalid id length: %d\n", len);
4164 goto out;
4165 }
4166
4167 seq_printf(seq, "%.*s\n", len, buf + 3);
4168 offs = len + 3;
4169
4170 while (offs < vpd_size - 4) {
4171 int i;
4172
4173 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4174 break;
4175 len = buf[offs + 2];
4176 if (offs + len + 3 >= vpd_size)
4177 break;
4178
4179 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4180 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4181 seq_printf(seq, " %s: %.*s\n",
4182 vpd_tags[i].label, len, buf + offs + 3);
4183 break;
4184 }
4185 }
4186 offs += len + 3;
4187 }
4188 out:
4189 kfree(buf);
4190 }
4191
4192 static int sky2_debug_show(struct seq_file *seq, void *v)
4193 {
4194 struct net_device *dev = seq->private;
4195 const struct sky2_port *sky2 = netdev_priv(dev);
4196 struct sky2_hw *hw = sky2->hw;
4197 unsigned port = sky2->port;
4198 unsigned idx, last;
4199 int sop;
4200
4201 sky2_show_vpd(seq, hw);
4202
4203 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4204 sky2_read32(hw, B0_ISRC),
4205 sky2_read32(hw, B0_IMSK),
4206 sky2_read32(hw, B0_Y2_SP_ICR));
4207
4208 if (!netif_running(dev)) {
4209 seq_printf(seq, "network not running\n");
4210 return 0;
4211 }
4212
4213 napi_disable(&hw->napi);
4214 last = sky2_read16(hw, STAT_PUT_IDX);
4215
4216 if (hw->st_idx == last)
4217 seq_puts(seq, "Status ring (empty)\n");
4218 else {
4219 seq_puts(seq, "Status ring\n");
4220 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4221 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4222 const struct sky2_status_le *le = hw->st_le + idx;
4223 seq_printf(seq, "[%d] %#x %d %#x\n",
4224 idx, le->opcode, le->length, le->status);
4225 }
4226 seq_puts(seq, "\n");
4227 }
4228
4229 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4230 sky2->tx_cons, sky2->tx_prod,
4231 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4232 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4233
4234 /* Dump contents of tx ring */
4235 sop = 1;
4236 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4237 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4238 const struct sky2_tx_le *le = sky2->tx_le + idx;
4239 u32 a = le32_to_cpu(le->addr);
4240
4241 if (sop)
4242 seq_printf(seq, "%u:", idx);
4243 sop = 0;
4244
4245 switch(le->opcode & ~HW_OWNER) {
4246 case OP_ADDR64:
4247 seq_printf(seq, " %#x:", a);
4248 break;
4249 case OP_LRGLEN:
4250 seq_printf(seq, " mtu=%d", a);
4251 break;
4252 case OP_VLAN:
4253 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4254 break;
4255 case OP_TCPLISW:
4256 seq_printf(seq, " csum=%#x", a);
4257 break;
4258 case OP_LARGESEND:
4259 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4260 break;
4261 case OP_PACKET:
4262 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4263 break;
4264 case OP_BUFFER:
4265 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4266 break;
4267 default:
4268 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4269 a, le16_to_cpu(le->length));
4270 }
4271
4272 if (le->ctrl & EOP) {
4273 seq_putc(seq, '\n');
4274 sop = 1;
4275 }
4276 }
4277
4278 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4279 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4280 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4281 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4282
4283 sky2_read32(hw, B0_Y2_SP_LISR);
4284 napi_enable(&hw->napi);
4285 return 0;
4286 }
4287
4288 static int sky2_debug_open(struct inode *inode, struct file *file)
4289 {
4290 return single_open(file, sky2_debug_show, inode->i_private);
4291 }
4292
4293 static const struct file_operations sky2_debug_fops = {
4294 .owner = THIS_MODULE,
4295 .open = sky2_debug_open,
4296 .read = seq_read,
4297 .llseek = seq_lseek,
4298 .release = single_release,
4299 };
4300
4301 /*
4302 * Use network device events to create/remove/rename
4303 * debugfs file entries
4304 */
4305 static int sky2_device_event(struct notifier_block *unused,
4306 unsigned long event, void *ptr)
4307 {
4308 struct net_device *dev = ptr;
4309 struct sky2_port *sky2 = netdev_priv(dev);
4310
4311 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4312 return NOTIFY_DONE;
4313
4314 switch(event) {
4315 case NETDEV_CHANGENAME:
4316 if (sky2->debugfs) {
4317 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4318 sky2_debug, dev->name);
4319 }
4320 break;
4321
4322 case NETDEV_GOING_DOWN:
4323 if (sky2->debugfs) {
4324 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4325 dev->name);
4326 debugfs_remove(sky2->debugfs);
4327 sky2->debugfs = NULL;
4328 }
4329 break;
4330
4331 case NETDEV_UP:
4332 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4333 sky2_debug, dev,
4334 &sky2_debug_fops);
4335 if (IS_ERR(sky2->debugfs))
4336 sky2->debugfs = NULL;
4337 }
4338
4339 return NOTIFY_DONE;
4340 }
4341
4342 static struct notifier_block sky2_notifier = {
4343 .notifier_call = sky2_device_event,
4344 };
4345
4346
4347 static __init void sky2_debug_init(void)
4348 {
4349 struct dentry *ent;
4350
4351 ent = debugfs_create_dir("sky2", NULL);
4352 if (!ent || IS_ERR(ent))
4353 return;
4354
4355 sky2_debug = ent;
4356 register_netdevice_notifier(&sky2_notifier);
4357 }
4358
4359 static __exit void sky2_debug_cleanup(void)
4360 {
4361 if (sky2_debug) {
4362 unregister_netdevice_notifier(&sky2_notifier);
4363 debugfs_remove(sky2_debug);
4364 sky2_debug = NULL;
4365 }
4366 }
4367
4368 #else
4369 #define sky2_debug_init()
4370 #define sky2_debug_cleanup()
4371 #endif
4372
4373 /* Two copies of network device operations to handle special case of
4374 not allowing netpoll on second port */
4375 static const struct net_device_ops sky2_netdev_ops[2] = {
4376 {
4377 .ndo_open = sky2_up,
4378 .ndo_stop = sky2_down,
4379 .ndo_start_xmit = sky2_xmit_frame,
4380 .ndo_do_ioctl = sky2_ioctl,
4381 .ndo_validate_addr = eth_validate_addr,
4382 .ndo_set_mac_address = sky2_set_mac_address,
4383 .ndo_set_multicast_list = sky2_set_multicast,
4384 .ndo_change_mtu = sky2_change_mtu,
4385 .ndo_tx_timeout = sky2_tx_timeout,
4386 #ifdef SKY2_VLAN_TAG_USED
4387 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4388 #endif
4389 #ifdef CONFIG_NET_POLL_CONTROLLER
4390 .ndo_poll_controller = sky2_netpoll,
4391 #endif
4392 },
4393 {
4394 .ndo_open = sky2_up,
4395 .ndo_stop = sky2_down,
4396 .ndo_start_xmit = sky2_xmit_frame,
4397 .ndo_do_ioctl = sky2_ioctl,
4398 .ndo_validate_addr = eth_validate_addr,
4399 .ndo_set_mac_address = sky2_set_mac_address,
4400 .ndo_set_multicast_list = sky2_set_multicast,
4401 .ndo_change_mtu = sky2_change_mtu,
4402 .ndo_tx_timeout = sky2_tx_timeout,
4403 #ifdef SKY2_VLAN_TAG_USED
4404 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4405 #endif
4406 },
4407 };
4408
4409 /* Initialize network device */
4410 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4411 unsigned port,
4412 int highmem, int wol)
4413 {
4414 struct sky2_port *sky2;
4415 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4416
4417 if (!dev) {
4418 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4419 return NULL;
4420 }
4421
4422 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4423 dev->irq = hw->pdev->irq;
4424 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4425 dev->watchdog_timeo = TX_WATCHDOG;
4426 dev->netdev_ops = &sky2_netdev_ops[port];
4427
4428 sky2 = netdev_priv(dev);
4429 sky2->netdev = dev;
4430 sky2->hw = hw;
4431 sky2->msg_enable = netif_msg_init(debug, default_msg);
4432
4433 /* Auto speed and flow control */
4434 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4435 if (hw->chip_id != CHIP_ID_YUKON_XL)
4436 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4437
4438 sky2->flow_mode = FC_BOTH;
4439
4440 sky2->duplex = -1;
4441 sky2->speed = -1;
4442 sky2->advertising = sky2_supported_modes(hw);
4443 sky2->wol = wol;
4444
4445 spin_lock_init(&sky2->phy_lock);
4446
4447 sky2->tx_pending = TX_DEF_PENDING;
4448 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4449 sky2->rx_pending = RX_DEF_PENDING;
4450
4451 hw->dev[port] = dev;
4452
4453 sky2->port = port;
4454
4455 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4456 if (highmem)
4457 dev->features |= NETIF_F_HIGHDMA;
4458
4459 #ifdef SKY2_VLAN_TAG_USED
4460 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4461 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4462 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4463 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4464 }
4465 #endif
4466
4467 /* read the mac address */
4468 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4469 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4470
4471 return dev;
4472 }
4473
4474 static void __devinit sky2_show_addr(struct net_device *dev)
4475 {
4476 const struct sky2_port *sky2 = netdev_priv(dev);
4477
4478 if (netif_msg_probe(sky2))
4479 printk(KERN_INFO PFX "%s: addr %pM\n",
4480 dev->name, dev->dev_addr);
4481 }
4482
4483 /* Handle software interrupt used during MSI test */
4484 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4485 {
4486 struct sky2_hw *hw = dev_id;
4487 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4488
4489 if (status == 0)
4490 return IRQ_NONE;
4491
4492 if (status & Y2_IS_IRQ_SW) {
4493 hw->flags |= SKY2_HW_USE_MSI;
4494 wake_up(&hw->msi_wait);
4495 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4496 }
4497 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4498
4499 return IRQ_HANDLED;
4500 }
4501
4502 /* Test interrupt path by forcing a a software IRQ */
4503 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4504 {
4505 struct pci_dev *pdev = hw->pdev;
4506 int err;
4507
4508 init_waitqueue_head (&hw->msi_wait);
4509
4510 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4511
4512 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4513 if (err) {
4514 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4515 return err;
4516 }
4517
4518 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4519 sky2_read8(hw, B0_CTST);
4520
4521 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4522
4523 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4524 /* MSI test failed, go back to INTx mode */
4525 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4526 "switching to INTx mode.\n");
4527
4528 err = -EOPNOTSUPP;
4529 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4530 }
4531
4532 sky2_write32(hw, B0_IMSK, 0);
4533 sky2_read32(hw, B0_IMSK);
4534
4535 free_irq(pdev->irq, hw);
4536
4537 return err;
4538 }
4539
4540 /* This driver supports yukon2 chipset only */
4541 static const char *sky2_name(u8 chipid, char *buf, int sz)
4542 {
4543 const char *name[] = {
4544 "XL", /* 0xb3 */
4545 "EC Ultra", /* 0xb4 */
4546 "Extreme", /* 0xb5 */
4547 "EC", /* 0xb6 */
4548 "FE", /* 0xb7 */
4549 "FE+", /* 0xb8 */
4550 "Supreme", /* 0xb9 */
4551 "UL 2", /* 0xba */
4552 "Unknown", /* 0xbb */
4553 "Optima", /* 0xbc */
4554 };
4555
4556 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
4557 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4558 else
4559 snprintf(buf, sz, "(chip %#x)", chipid);
4560 return buf;
4561 }
4562
4563 static int __devinit sky2_probe(struct pci_dev *pdev,
4564 const struct pci_device_id *ent)
4565 {
4566 struct net_device *dev;
4567 struct sky2_hw *hw;
4568 int err, using_dac = 0, wol_default;
4569 u32 reg;
4570 char buf1[16];
4571
4572 err = pci_enable_device(pdev);
4573 if (err) {
4574 dev_err(&pdev->dev, "cannot enable PCI device\n");
4575 goto err_out;
4576 }
4577
4578 /* Get configuration information
4579 * Note: only regular PCI config access once to test for HW issues
4580 * other PCI access through shared memory for speed and to
4581 * avoid MMCONFIG problems.
4582 */
4583 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4584 if (err) {
4585 dev_err(&pdev->dev, "PCI read config failed\n");
4586 goto err_out;
4587 }
4588
4589 if (~reg == 0) {
4590 dev_err(&pdev->dev, "PCI configuration read error\n");
4591 goto err_out;
4592 }
4593
4594 err = pci_request_regions(pdev, DRV_NAME);
4595 if (err) {
4596 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4597 goto err_out_disable;
4598 }
4599
4600 pci_set_master(pdev);
4601
4602 if (sizeof(dma_addr_t) > sizeof(u32) &&
4603 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4604 using_dac = 1;
4605 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4606 if (err < 0) {
4607 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4608 "for consistent allocations\n");
4609 goto err_out_free_regions;
4610 }
4611 } else {
4612 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4613 if (err) {
4614 dev_err(&pdev->dev, "no usable DMA configuration\n");
4615 goto err_out_free_regions;
4616 }
4617 }
4618
4619
4620 #ifdef __BIG_ENDIAN
4621 /* The sk98lin vendor driver uses hardware byte swapping but
4622 * this driver uses software swapping.
4623 */
4624 reg &= ~PCI_REV_DESC;
4625 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4626 if (err) {
4627 dev_err(&pdev->dev, "PCI write config failed\n");
4628 goto err_out_free_regions;
4629 }
4630 #endif
4631
4632 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4633
4634 err = -ENOMEM;
4635
4636 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4637 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4638 if (!hw) {
4639 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4640 goto err_out_free_regions;
4641 }
4642
4643 hw->pdev = pdev;
4644 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4645
4646 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4647 if (!hw->regs) {
4648 dev_err(&pdev->dev, "cannot map device registers\n");
4649 goto err_out_free_hw;
4650 }
4651
4652 /* ring for status responses */
4653 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4654 if (!hw->st_le)
4655 goto err_out_iounmap;
4656
4657 err = sky2_init(hw);
4658 if (err)
4659 goto err_out_iounmap;
4660
4661 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4662 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4663
4664 sky2_reset(hw);
4665
4666 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4667 if (!dev) {
4668 err = -ENOMEM;
4669 goto err_out_free_pci;
4670 }
4671
4672 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4673 err = sky2_test_msi(hw);
4674 if (err == -EOPNOTSUPP)
4675 pci_disable_msi(pdev);
4676 else if (err)
4677 goto err_out_free_netdev;
4678 }
4679
4680 err = register_netdev(dev);
4681 if (err) {
4682 dev_err(&pdev->dev, "cannot register net device\n");
4683 goto err_out_free_netdev;
4684 }
4685
4686 netif_carrier_off(dev);
4687
4688 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4689
4690 err = request_irq(pdev->irq, sky2_intr,
4691 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4692 hw->irq_name, hw);
4693 if (err) {
4694 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4695 goto err_out_unregister;
4696 }
4697 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4698 napi_enable(&hw->napi);
4699
4700 sky2_show_addr(dev);
4701
4702 if (hw->ports > 1) {
4703 struct net_device *dev1;
4704
4705 err = -ENOMEM;
4706 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4707 if (dev1 && (err = register_netdev(dev1)) == 0)
4708 sky2_show_addr(dev1);
4709 else {
4710 dev_warn(&pdev->dev,
4711 "register of second port failed (%d)\n", err);
4712 hw->dev[1] = NULL;
4713 hw->ports = 1;
4714 if (dev1)
4715 free_netdev(dev1);
4716 }
4717 }
4718
4719 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4720 INIT_WORK(&hw->restart_work, sky2_restart);
4721
4722 pci_set_drvdata(pdev, hw);
4723 pdev->d3_delay = 150;
4724
4725 return 0;
4726
4727 err_out_unregister:
4728 if (hw->flags & SKY2_HW_USE_MSI)
4729 pci_disable_msi(pdev);
4730 unregister_netdev(dev);
4731 err_out_free_netdev:
4732 free_netdev(dev);
4733 err_out_free_pci:
4734 sky2_write8(hw, B0_CTST, CS_RST_SET);
4735 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4736 err_out_iounmap:
4737 iounmap(hw->regs);
4738 err_out_free_hw:
4739 kfree(hw);
4740 err_out_free_regions:
4741 pci_release_regions(pdev);
4742 err_out_disable:
4743 pci_disable_device(pdev);
4744 err_out:
4745 pci_set_drvdata(pdev, NULL);
4746 return err;
4747 }
4748
4749 static void __devexit sky2_remove(struct pci_dev *pdev)
4750 {
4751 struct sky2_hw *hw = pci_get_drvdata(pdev);
4752 int i;
4753
4754 if (!hw)
4755 return;
4756
4757 del_timer_sync(&hw->watchdog_timer);
4758 cancel_work_sync(&hw->restart_work);
4759
4760 for (i = hw->ports-1; i >= 0; --i)
4761 unregister_netdev(hw->dev[i]);
4762
4763 sky2_write32(hw, B0_IMSK, 0);
4764
4765 sky2_power_aux(hw);
4766
4767 sky2_write8(hw, B0_CTST, CS_RST_SET);
4768 sky2_read8(hw, B0_CTST);
4769
4770 free_irq(pdev->irq, hw);
4771 if (hw->flags & SKY2_HW_USE_MSI)
4772 pci_disable_msi(pdev);
4773 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4774 pci_release_regions(pdev);
4775 pci_disable_device(pdev);
4776
4777 for (i = hw->ports-1; i >= 0; --i)
4778 free_netdev(hw->dev[i]);
4779
4780 iounmap(hw->regs);
4781 kfree(hw);
4782
4783 pci_set_drvdata(pdev, NULL);
4784 }
4785
4786 #ifdef CONFIG_PM
4787 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4788 {
4789 struct sky2_hw *hw = pci_get_drvdata(pdev);
4790 int i, wol = 0;
4791
4792 if (!hw)
4793 return 0;
4794
4795 del_timer_sync(&hw->watchdog_timer);
4796 cancel_work_sync(&hw->restart_work);
4797
4798 rtnl_lock();
4799 for (i = 0; i < hw->ports; i++) {
4800 struct net_device *dev = hw->dev[i];
4801 struct sky2_port *sky2 = netdev_priv(dev);
4802
4803 sky2_detach(dev);
4804
4805 if (sky2->wol)
4806 sky2_wol_init(sky2);
4807
4808 wol |= sky2->wol;
4809 }
4810
4811 sky2_write32(hw, B0_IMSK, 0);
4812 napi_disable(&hw->napi);
4813 sky2_power_aux(hw);
4814 rtnl_unlock();
4815
4816 pci_save_state(pdev);
4817 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4818 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4819
4820 return 0;
4821 }
4822
4823 static int sky2_resume(struct pci_dev *pdev)
4824 {
4825 struct sky2_hw *hw = pci_get_drvdata(pdev);
4826 int i, err;
4827
4828 if (!hw)
4829 return 0;
4830
4831 err = pci_set_power_state(pdev, PCI_D0);
4832 if (err)
4833 goto out;
4834
4835 err = pci_restore_state(pdev);
4836 if (err)
4837 goto out;
4838
4839 pci_enable_wake(pdev, PCI_D0, 0);
4840
4841 /* Re-enable all clocks */
4842 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4843 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4844 hw->chip_id == CHIP_ID_YUKON_FE_P)
4845 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4846
4847 sky2_reset(hw);
4848 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4849 napi_enable(&hw->napi);
4850
4851 rtnl_lock();
4852 for (i = 0; i < hw->ports; i++) {
4853 err = sky2_reattach(hw->dev[i]);
4854 if (err)
4855 goto out;
4856 }
4857 rtnl_unlock();
4858
4859 return 0;
4860 out:
4861 rtnl_unlock();
4862
4863 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4864 pci_disable_device(pdev);
4865 return err;
4866 }
4867 #endif
4868
4869 static void sky2_shutdown(struct pci_dev *pdev)
4870 {
4871 struct sky2_hw *hw = pci_get_drvdata(pdev);
4872 int i, wol = 0;
4873
4874 if (!hw)
4875 return;
4876
4877 rtnl_lock();
4878 del_timer_sync(&hw->watchdog_timer);
4879
4880 for (i = 0; i < hw->ports; i++) {
4881 struct net_device *dev = hw->dev[i];
4882 struct sky2_port *sky2 = netdev_priv(dev);
4883
4884 if (sky2->wol) {
4885 wol = 1;
4886 sky2_wol_init(sky2);
4887 }
4888 }
4889
4890 if (wol)
4891 sky2_power_aux(hw);
4892 rtnl_unlock();
4893
4894 pci_enable_wake(pdev, PCI_D3hot, wol);
4895 pci_enable_wake(pdev, PCI_D3cold, wol);
4896
4897 pci_disable_device(pdev);
4898 pci_set_power_state(pdev, PCI_D3hot);
4899 }
4900
4901 static struct pci_driver sky2_driver = {
4902 .name = DRV_NAME,
4903 .id_table = sky2_id_table,
4904 .probe = sky2_probe,
4905 .remove = __devexit_p(sky2_remove),
4906 #ifdef CONFIG_PM
4907 .suspend = sky2_suspend,
4908 .resume = sky2_resume,
4909 #endif
4910 .shutdown = sky2_shutdown,
4911 };
4912
4913 static int __init sky2_init_module(void)
4914 {
4915 pr_info(PFX "driver version " DRV_VERSION "\n");
4916
4917 sky2_debug_init();
4918 return pci_register_driver(&sky2_driver);
4919 }
4920
4921 static void __exit sky2_cleanup_module(void)
4922 {
4923 pci_unregister_driver(&sky2_driver);
4924 sky2_debug_cleanup();
4925 }
4926
4927 module_init(sky2_init_module);
4928 module_exit(sky2_cleanup_module);
4929
4930 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4931 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4932 MODULE_LICENSE("GPL");
4933 MODULE_VERSION(DRV_VERSION);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree