2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/firewire.h>
26 #include <linux/firewire-constants.h>
27 #include <linux/gfp.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/pci.h>
37 #include <linux/pci_ids.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
41 #include <asm/atomic.h>
42 #include <asm/byteorder.h>
44 #include <asm/system.h>
46 #ifdef CONFIG_PPC_PMAC
47 #include <asm/pmac_feature.h>
53 #define DESCRIPTOR_OUTPUT_MORE 0
54 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
55 #define DESCRIPTOR_INPUT_MORE (2 << 12)
56 #define DESCRIPTOR_INPUT_LAST (3 << 12)
57 #define DESCRIPTOR_STATUS (1 << 11)
58 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
59 #define DESCRIPTOR_PING (1 << 7)
60 #define DESCRIPTOR_YY (1 << 6)
61 #define DESCRIPTOR_NO_IRQ (0 << 4)
62 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
63 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
64 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
65 #define DESCRIPTOR_WAIT (3 << 0)
71 __le32 branch_address
;
73 __le16 transfer_status
;
74 } __attribute__((aligned(16)));
76 struct db_descriptor
{
79 __le16 second_req_count
;
80 __le16 first_req_count
;
81 __le32 branch_address
;
82 __le16 second_res_count
;
83 __le16 first_res_count
;
88 } __attribute__((aligned(16)));
90 #define CONTROL_SET(regs) (regs)
91 #define CONTROL_CLEAR(regs) ((regs) + 4)
92 #define COMMAND_PTR(regs) ((regs) + 12)
93 #define CONTEXT_MATCH(regs) ((regs) + 16)
96 struct descriptor descriptor
;
97 struct ar_buffer
*next
;
102 struct fw_ohci
*ohci
;
103 struct ar_buffer
*current_buffer
;
104 struct ar_buffer
*last_buffer
;
107 struct tasklet_struct tasklet
;
112 typedef int (*descriptor_callback_t
)(struct context
*ctx
,
113 struct descriptor
*d
,
114 struct descriptor
*last
);
117 * A buffer that contains a block of DMA-able coherent memory used for
118 * storing a portion of a DMA descriptor program.
120 struct descriptor_buffer
{
121 struct list_head list
;
122 dma_addr_t buffer_bus
;
125 struct descriptor buffer
[0];
129 struct fw_ohci
*ohci
;
131 int total_allocation
;
134 * List of page-sized buffers for storing DMA descriptors.
135 * Head of list contains buffers in use and tail of list contains
138 struct list_head buffer_list
;
141 * Pointer to a buffer inside buffer_list that contains the tail
142 * end of the current DMA program.
144 struct descriptor_buffer
*buffer_tail
;
147 * The descriptor containing the branch address of the first
148 * descriptor that has not yet been filled by the device.
150 struct descriptor
*last
;
153 * The last descriptor in the DMA program. It contains the branch
154 * address that must be updated upon appending a new descriptor.
156 struct descriptor
*prev
;
158 descriptor_callback_t callback
;
160 struct tasklet_struct tasklet
;
163 #define IT_HEADER_SY(v) ((v) << 0)
164 #define IT_HEADER_TCODE(v) ((v) << 4)
165 #define IT_HEADER_CHANNEL(v) ((v) << 8)
166 #define IT_HEADER_TAG(v) ((v) << 14)
167 #define IT_HEADER_SPEED(v) ((v) << 16)
168 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
171 struct fw_iso_context base
;
172 struct context context
;
175 size_t header_length
;
178 #define CONFIG_ROM_SIZE 1024
183 __iomem
char *registers
;
184 dma_addr_t self_id_bus
;
186 struct tasklet_struct bus_reset_tasklet
;
189 int request_generation
; /* for timestamping incoming requests */
190 atomic_t bus_seconds
;
194 bool bus_reset_packet_quirk
;
197 * Spinlock for accessing fw_ohci data. Never call out of
198 * this driver with this lock held.
201 u32 self_id_buffer
[512];
203 /* Config rom buffers */
205 dma_addr_t config_rom_bus
;
206 __be32
*next_config_rom
;
207 dma_addr_t next_config_rom_bus
;
210 struct ar_context ar_request_ctx
;
211 struct ar_context ar_response_ctx
;
212 struct context at_request_ctx
;
213 struct context at_response_ctx
;
216 struct iso_context
*it_context_list
;
217 u64 ir_context_channels
;
219 struct iso_context
*ir_context_list
;
222 static inline struct fw_ohci
*fw_ohci(struct fw_card
*card
)
224 return container_of(card
, struct fw_ohci
, card
);
227 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
228 #define IR_CONTEXT_BUFFER_FILL 0x80000000
229 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
230 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
231 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
232 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
234 #define CONTEXT_RUN 0x8000
235 #define CONTEXT_WAKE 0x1000
236 #define CONTEXT_DEAD 0x0800
237 #define CONTEXT_ACTIVE 0x0400
239 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
240 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
241 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
243 #define OHCI1394_REGISTER_SIZE 0x800
244 #define OHCI_LOOP_COUNT 500
245 #define OHCI1394_PCI_HCI_Control 0x40
246 #define SELF_ID_BUF_SIZE 0x800
247 #define OHCI_TCODE_PHY_PACKET 0x0e
248 #define OHCI_VERSION_1_1 0x010010
250 static char ohci_driver_name
[] = KBUILD_MODNAME
;
252 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
254 #define OHCI_PARAM_DEBUG_AT_AR 1
255 #define OHCI_PARAM_DEBUG_SELFIDS 2
256 #define OHCI_PARAM_DEBUG_IRQS 4
257 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
259 static int param_debug
;
260 module_param_named(debug
, param_debug
, int, 0644);
261 MODULE_PARM_DESC(debug
, "Verbose logging (default = 0"
262 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR
)
263 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS
)
264 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS
)
265 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS
)
266 ", or a combination, or all = -1)");
268 static void log_irqs(u32 evt
)
270 if (likely(!(param_debug
&
271 (OHCI_PARAM_DEBUG_IRQS
| OHCI_PARAM_DEBUG_BUSRESETS
))))
274 if (!(param_debug
& OHCI_PARAM_DEBUG_IRQS
) &&
275 !(evt
& OHCI1394_busReset
))
278 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt
,
279 evt
& OHCI1394_selfIDComplete
? " selfID" : "",
280 evt
& OHCI1394_RQPkt
? " AR_req" : "",
281 evt
& OHCI1394_RSPkt
? " AR_resp" : "",
282 evt
& OHCI1394_reqTxComplete
? " AT_req" : "",
283 evt
& OHCI1394_respTxComplete
? " AT_resp" : "",
284 evt
& OHCI1394_isochRx
? " IR" : "",
285 evt
& OHCI1394_isochTx
? " IT" : "",
286 evt
& OHCI1394_postedWriteErr
? " postedWriteErr" : "",
287 evt
& OHCI1394_cycleTooLong
? " cycleTooLong" : "",
288 evt
& OHCI1394_cycle64Seconds
? " cycle64Seconds" : "",
289 evt
& OHCI1394_cycleInconsistent
? " cycleInconsistent" : "",
290 evt
& OHCI1394_regAccessFail
? " regAccessFail" : "",
291 evt
& OHCI1394_busReset
? " busReset" : "",
292 evt
& ~(OHCI1394_selfIDComplete
| OHCI1394_RQPkt
|
293 OHCI1394_RSPkt
| OHCI1394_reqTxComplete
|
294 OHCI1394_respTxComplete
| OHCI1394_isochRx
|
295 OHCI1394_isochTx
| OHCI1394_postedWriteErr
|
296 OHCI1394_cycleTooLong
| OHCI1394_cycle64Seconds
|
297 OHCI1394_cycleInconsistent
|
298 OHCI1394_regAccessFail
| OHCI1394_busReset
)
302 static const char *speed
[] = {
303 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
305 static const char *power
[] = {
306 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
307 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
309 static const char port
[] = { '.', '-', 'p', 'c', };
311 static char _p(u32
*s
, int shift
)
313 return port
[*s
>> shift
& 3];
316 static void log_selfids(int node_id
, int generation
, int self_id_count
, u32
*s
)
318 if (likely(!(param_debug
& OHCI_PARAM_DEBUG_SELFIDS
)))
321 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
322 self_id_count
, generation
, node_id
);
324 for (; self_id_count
--; ++s
)
325 if ((*s
& 1 << 23) == 0)
326 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
327 "%s gc=%d %s %s%s%s\n",
328 *s
, *s
>> 24 & 63, _p(s
, 6), _p(s
, 4), _p(s
, 2),
329 speed
[*s
>> 14 & 3], *s
>> 16 & 63,
330 power
[*s
>> 8 & 7], *s
>> 22 & 1 ? "L" : "",
331 *s
>> 11 & 1 ? "c" : "", *s
& 2 ? "i" : "");
333 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
335 _p(s
, 16), _p(s
, 14), _p(s
, 12), _p(s
, 10),
336 _p(s
, 8), _p(s
, 6), _p(s
, 4), _p(s
, 2));
339 static const char *evts
[] = {
340 [0x00] = "evt_no_status", [0x01] = "-reserved-",
341 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
342 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
343 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
344 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
345 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
346 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
347 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
348 [0x10] = "-reserved-", [0x11] = "ack_complete",
349 [0x12] = "ack_pending ", [0x13] = "-reserved-",
350 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
351 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
352 [0x18] = "-reserved-", [0x19] = "-reserved-",
353 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
354 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
355 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
356 [0x20] = "pending/cancelled",
358 static const char *tcodes
[] = {
359 [0x0] = "QW req", [0x1] = "BW req",
360 [0x2] = "W resp", [0x3] = "-reserved-",
361 [0x4] = "QR req", [0x5] = "BR req",
362 [0x6] = "QR resp", [0x7] = "BR resp",
363 [0x8] = "cycle start", [0x9] = "Lk req",
364 [0xa] = "async stream packet", [0xb] = "Lk resp",
365 [0xc] = "-reserved-", [0xd] = "-reserved-",
366 [0xe] = "link internal", [0xf] = "-reserved-",
368 static const char *phys
[] = {
369 [0x0] = "phy config packet", [0x1] = "link-on packet",
370 [0x2] = "self-id packet", [0x3] = "-reserved-",
373 static void log_ar_at_event(char dir
, int speed
, u32
*header
, int evt
)
375 int tcode
= header
[0] >> 4 & 0xf;
378 if (likely(!(param_debug
& OHCI_PARAM_DEBUG_AT_AR
)))
381 if (unlikely(evt
>= ARRAY_SIZE(evts
)))
384 if (evt
== OHCI1394_evt_bus_reset
) {
385 fw_notify("A%c evt_bus_reset, generation %d\n",
386 dir
, (header
[2] >> 16) & 0xff);
390 if (header
[0] == ~header
[1]) {
391 fw_notify("A%c %s, %s, %08x\n",
392 dir
, evts
[evt
], phys
[header
[0] >> 30 & 0x3], header
[0]);
397 case 0x0: case 0x6: case 0x8:
398 snprintf(specific
, sizeof(specific
), " = %08x",
399 be32_to_cpu((__force __be32
)header
[3]));
401 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
402 snprintf(specific
, sizeof(specific
), " %x,%x",
403 header
[3] >> 16, header
[3] & 0xffff);
411 fw_notify("A%c %s, %s\n", dir
, evts
[evt
], tcodes
[tcode
]);
413 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
414 fw_notify("A%c spd %x tl %02x, "
417 dir
, speed
, header
[0] >> 10 & 0x3f,
418 header
[1] >> 16, header
[0] >> 16, evts
[evt
],
419 tcodes
[tcode
], header
[1] & 0xffff, header
[2], specific
);
422 fw_notify("A%c spd %x tl %02x, "
425 dir
, speed
, header
[0] >> 10 & 0x3f,
426 header
[1] >> 16, header
[0] >> 16, evts
[evt
],
427 tcodes
[tcode
], specific
);
433 #define log_irqs(evt)
434 #define log_selfids(node_id, generation, self_id_count, sid)
435 #define log_ar_at_event(dir, speed, header, evt)
437 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
439 static inline void reg_write(const struct fw_ohci
*ohci
, int offset
, u32 data
)
441 writel(data
, ohci
->registers
+ offset
);
444 static inline u32
reg_read(const struct fw_ohci
*ohci
, int offset
)
446 return readl(ohci
->registers
+ offset
);
449 static inline void flush_writes(const struct fw_ohci
*ohci
)
451 /* Do a dummy read to flush writes. */
452 reg_read(ohci
, OHCI1394_Version
);
455 static int ohci_update_phy_reg(struct fw_card
*card
, int addr
,
456 int clear_bits
, int set_bits
)
458 struct fw_ohci
*ohci
= fw_ohci(card
);
461 reg_write(ohci
, OHCI1394_PhyControl
, OHCI1394_PhyControl_Read(addr
));
464 val
= reg_read(ohci
, OHCI1394_PhyControl
);
465 if ((val
& OHCI1394_PhyControl_ReadDone
) == 0) {
466 fw_error("failed to set phy reg bits.\n");
470 old
= OHCI1394_PhyControl_ReadData(val
);
471 old
= (old
& ~clear_bits
) | set_bits
;
472 reg_write(ohci
, OHCI1394_PhyControl
,
473 OHCI1394_PhyControl_Write(addr
, old
));
478 static int ar_context_add_page(struct ar_context
*ctx
)
480 struct device
*dev
= ctx
->ohci
->card
.device
;
481 struct ar_buffer
*ab
;
482 dma_addr_t
uninitialized_var(ab_bus
);
485 ab
= dma_alloc_coherent(dev
, PAGE_SIZE
, &ab_bus
, GFP_ATOMIC
);
490 memset(&ab
->descriptor
, 0, sizeof(ab
->descriptor
));
491 ab
->descriptor
.control
= cpu_to_le16(DESCRIPTOR_INPUT_MORE
|
493 DESCRIPTOR_BRANCH_ALWAYS
);
494 offset
= offsetof(struct ar_buffer
, data
);
495 ab
->descriptor
.req_count
= cpu_to_le16(PAGE_SIZE
- offset
);
496 ab
->descriptor
.data_address
= cpu_to_le32(ab_bus
+ offset
);
497 ab
->descriptor
.res_count
= cpu_to_le16(PAGE_SIZE
- offset
);
498 ab
->descriptor
.branch_address
= 0;
500 ctx
->last_buffer
->descriptor
.branch_address
= cpu_to_le32(ab_bus
| 1);
501 ctx
->last_buffer
->next
= ab
;
502 ctx
->last_buffer
= ab
;
504 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_WAKE
);
505 flush_writes(ctx
->ohci
);
510 static void ar_context_release(struct ar_context
*ctx
)
512 struct ar_buffer
*ab
, *ab_next
;
516 for (ab
= ctx
->current_buffer
; ab
; ab
= ab_next
) {
518 offset
= offsetof(struct ar_buffer
, data
);
519 ab_bus
= le32_to_cpu(ab
->descriptor
.data_address
) - offset
;
520 dma_free_coherent(ctx
->ohci
->card
.device
, PAGE_SIZE
,
525 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
526 #define cond_le32_to_cpu(v) \
527 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
529 #define cond_le32_to_cpu(v) le32_to_cpu(v)
532 static __le32
*handle_ar_packet(struct ar_context
*ctx
, __le32
*buffer
)
534 struct fw_ohci
*ohci
= ctx
->ohci
;
536 u32 status
, length
, tcode
;
539 p
.header
[0] = cond_le32_to_cpu(buffer
[0]);
540 p
.header
[1] = cond_le32_to_cpu(buffer
[1]);
541 p
.header
[2] = cond_le32_to_cpu(buffer
[2]);
543 tcode
= (p
.header
[0] >> 4) & 0x0f;
545 case TCODE_WRITE_QUADLET_REQUEST
:
546 case TCODE_READ_QUADLET_RESPONSE
:
547 p
.header
[3] = (__force __u32
) buffer
[3];
548 p
.header_length
= 16;
549 p
.payload_length
= 0;
552 case TCODE_READ_BLOCK_REQUEST
:
553 p
.header
[3] = cond_le32_to_cpu(buffer
[3]);
554 p
.header_length
= 16;
555 p
.payload_length
= 0;
558 case TCODE_WRITE_BLOCK_REQUEST
:
559 case TCODE_READ_BLOCK_RESPONSE
:
560 case TCODE_LOCK_REQUEST
:
561 case TCODE_LOCK_RESPONSE
:
562 p
.header
[3] = cond_le32_to_cpu(buffer
[3]);
563 p
.header_length
= 16;
564 p
.payload_length
= p
.header
[3] >> 16;
567 case TCODE_WRITE_RESPONSE
:
568 case TCODE_READ_QUADLET_REQUEST
:
569 case OHCI_TCODE_PHY_PACKET
:
570 p
.header_length
= 12;
571 p
.payload_length
= 0;
575 /* FIXME: Stop context, discard everything, and restart? */
577 p
.payload_length
= 0;
580 p
.payload
= (void *) buffer
+ p
.header_length
;
582 /* FIXME: What to do about evt_* errors? */
583 length
= (p
.header_length
+ p
.payload_length
+ 3) / 4;
584 status
= cond_le32_to_cpu(buffer
[length
]);
585 evt
= (status
>> 16) & 0x1f;
588 p
.speed
= (status
>> 21) & 0x7;
589 p
.timestamp
= status
& 0xffff;
590 p
.generation
= ohci
->request_generation
;
592 log_ar_at_event('R', p
.speed
, p
.header
, evt
);
595 * The OHCI bus reset handler synthesizes a phy packet with
596 * the new generation number when a bus reset happens (see
597 * section 8.4.2.3). This helps us determine when a request
598 * was received and make sure we send the response in the same
599 * generation. We only need this for requests; for responses
600 * we use the unique tlabel for finding the matching
603 * Alas some chips sometimes emit bus reset packets with a
604 * wrong generation. We set the correct generation for these
605 * at a slightly incorrect time (in bus_reset_tasklet).
607 if (evt
== OHCI1394_evt_bus_reset
) {
608 if (!ohci
->bus_reset_packet_quirk
)
609 ohci
->request_generation
= (p
.header
[2] >> 16) & 0xff;
610 } else if (ctx
== &ohci
->ar_request_ctx
) {
611 fw_core_handle_request(&ohci
->card
, &p
);
613 fw_core_handle_response(&ohci
->card
, &p
);
616 return buffer
+ length
+ 1;
619 static void ar_context_tasklet(unsigned long data
)
621 struct ar_context
*ctx
= (struct ar_context
*)data
;
622 struct fw_ohci
*ohci
= ctx
->ohci
;
623 struct ar_buffer
*ab
;
624 struct descriptor
*d
;
627 ab
= ctx
->current_buffer
;
630 if (d
->res_count
== 0) {
631 size_t size
, size2
, rest
, pktsize
, size3
, offset
;
632 dma_addr_t start_bus
;
636 * This descriptor is finished and we may have a
637 * packet split across this and the next buffer. We
638 * reuse the page for reassembling the split packet.
641 offset
= offsetof(struct ar_buffer
, data
);
643 start_bus
= le32_to_cpu(ab
->descriptor
.data_address
) - offset
;
648 size
= start
+ PAGE_SIZE
- ctx
->pointer
;
649 /* valid buffer data in the next page */
650 rest
= le16_to_cpu(d
->req_count
) - le16_to_cpu(d
->res_count
);
651 /* what actually fits in this page */
652 size2
= min(rest
, (size_t)PAGE_SIZE
- offset
- size
);
653 memmove(buffer
, ctx
->pointer
, size
);
654 memcpy(buffer
+ size
, ab
->data
, size2
);
657 void *next
= handle_ar_packet(ctx
, buffer
);
658 pktsize
= next
- buffer
;
659 if (pktsize
>= size
) {
661 * We have handled all the data that was
662 * originally in this page, so we can now
663 * continue in the next page.
668 /* move the next packet to the start of the buffer */
669 memmove(buffer
, next
, size
+ size2
- pktsize
);
671 /* fill up this page again */
672 size3
= min(rest
- size2
,
673 (size_t)PAGE_SIZE
- offset
- size
- size2
);
674 memcpy(buffer
+ size
+ size2
,
675 (void *) ab
->data
+ size2
, size3
);
680 /* handle the packets that are fully in the next page */
681 buffer
= (void *) ab
->data
+
682 (buffer
- (start
+ offset
+ size
));
683 end
= (void *) ab
->data
+ rest
;
686 buffer
= handle_ar_packet(ctx
, buffer
);
688 ctx
->current_buffer
= ab
;
691 dma_free_coherent(ohci
->card
.device
, PAGE_SIZE
,
693 ar_context_add_page(ctx
);
695 ctx
->pointer
= start
+ PAGE_SIZE
;
698 buffer
= ctx
->pointer
;
700 (void *) ab
+ PAGE_SIZE
- le16_to_cpu(d
->res_count
);
703 buffer
= handle_ar_packet(ctx
, buffer
);
707 static int ar_context_init(struct ar_context
*ctx
,
708 struct fw_ohci
*ohci
, u32 regs
)
714 ctx
->last_buffer
= &ab
;
715 tasklet_init(&ctx
->tasklet
, ar_context_tasklet
, (unsigned long)ctx
);
717 ar_context_add_page(ctx
);
718 ar_context_add_page(ctx
);
719 ctx
->current_buffer
= ab
.next
;
720 ctx
->pointer
= ctx
->current_buffer
->data
;
725 static void ar_context_run(struct ar_context
*ctx
)
727 struct ar_buffer
*ab
= ctx
->current_buffer
;
731 offset
= offsetof(struct ar_buffer
, data
);
732 ab_bus
= le32_to_cpu(ab
->descriptor
.data_address
) - offset
;
734 reg_write(ctx
->ohci
, COMMAND_PTR(ctx
->regs
), ab_bus
| 1);
735 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_RUN
);
736 flush_writes(ctx
->ohci
);
739 static struct descriptor
*find_branch_descriptor(struct descriptor
*d
, int z
)
743 b
= (le16_to_cpu(d
->control
) & DESCRIPTOR_BRANCH_ALWAYS
) >> 2;
744 key
= (le16_to_cpu(d
->control
) & DESCRIPTOR_KEY_IMMEDIATE
) >> 8;
746 /* figure out which descriptor the branch address goes in */
747 if (z
== 2 && (b
== 3 || key
== 2))
753 static void context_tasklet(unsigned long data
)
755 struct context
*ctx
= (struct context
*) data
;
756 struct descriptor
*d
, *last
;
759 struct descriptor_buffer
*desc
;
761 desc
= list_entry(ctx
->buffer_list
.next
,
762 struct descriptor_buffer
, list
);
764 while (last
->branch_address
!= 0) {
765 struct descriptor_buffer
*old_desc
= desc
;
766 address
= le32_to_cpu(last
->branch_address
);
770 /* If the branch address points to a buffer outside of the
771 * current buffer, advance to the next buffer. */
772 if (address
< desc
->buffer_bus
||
773 address
>= desc
->buffer_bus
+ desc
->used
)
774 desc
= list_entry(desc
->list
.next
,
775 struct descriptor_buffer
, list
);
776 d
= desc
->buffer
+ (address
- desc
->buffer_bus
) / sizeof(*d
);
777 last
= find_branch_descriptor(d
, z
);
779 if (!ctx
->callback(ctx
, d
, last
))
782 if (old_desc
!= desc
) {
783 /* If we've advanced to the next buffer, move the
784 * previous buffer to the free list. */
787 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
788 list_move_tail(&old_desc
->list
, &ctx
->buffer_list
);
789 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
796 * Allocate a new buffer and add it to the list of free buffers for this
797 * context. Must be called with ohci->lock held.
799 static int context_add_buffer(struct context
*ctx
)
801 struct descriptor_buffer
*desc
;
802 dma_addr_t
uninitialized_var(bus_addr
);
806 * 16MB of descriptors should be far more than enough for any DMA
807 * program. This will catch run-away userspace or DoS attacks.
809 if (ctx
->total_allocation
>= 16*1024*1024)
812 desc
= dma_alloc_coherent(ctx
->ohci
->card
.device
, PAGE_SIZE
,
813 &bus_addr
, GFP_ATOMIC
);
817 offset
= (void *)&desc
->buffer
- (void *)desc
;
818 desc
->buffer_size
= PAGE_SIZE
- offset
;
819 desc
->buffer_bus
= bus_addr
+ offset
;
822 list_add_tail(&desc
->list
, &ctx
->buffer_list
);
823 ctx
->total_allocation
+= PAGE_SIZE
;
828 static int context_init(struct context
*ctx
, struct fw_ohci
*ohci
,
829 u32 regs
, descriptor_callback_t callback
)
833 ctx
->total_allocation
= 0;
835 INIT_LIST_HEAD(&ctx
->buffer_list
);
836 if (context_add_buffer(ctx
) < 0)
839 ctx
->buffer_tail
= list_entry(ctx
->buffer_list
.next
,
840 struct descriptor_buffer
, list
);
842 tasklet_init(&ctx
->tasklet
, context_tasklet
, (unsigned long)ctx
);
843 ctx
->callback
= callback
;
846 * We put a dummy descriptor in the buffer that has a NULL
847 * branch address and looks like it's been sent. That way we
848 * have a descriptor to append DMA programs to.
850 memset(ctx
->buffer_tail
->buffer
, 0, sizeof(*ctx
->buffer_tail
->buffer
));
851 ctx
->buffer_tail
->buffer
->control
= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
);
852 ctx
->buffer_tail
->buffer
->transfer_status
= cpu_to_le16(0x8011);
853 ctx
->buffer_tail
->used
+= sizeof(*ctx
->buffer_tail
->buffer
);
854 ctx
->last
= ctx
->buffer_tail
->buffer
;
855 ctx
->prev
= ctx
->buffer_tail
->buffer
;
860 static void context_release(struct context
*ctx
)
862 struct fw_card
*card
= &ctx
->ohci
->card
;
863 struct descriptor_buffer
*desc
, *tmp
;
865 list_for_each_entry_safe(desc
, tmp
, &ctx
->buffer_list
, list
)
866 dma_free_coherent(card
->device
, PAGE_SIZE
, desc
,
868 ((void *)&desc
->buffer
- (void *)desc
));
871 /* Must be called with ohci->lock held */
872 static struct descriptor
*context_get_descriptors(struct context
*ctx
,
873 int z
, dma_addr_t
*d_bus
)
875 struct descriptor
*d
= NULL
;
876 struct descriptor_buffer
*desc
= ctx
->buffer_tail
;
878 if (z
* sizeof(*d
) > desc
->buffer_size
)
881 if (z
* sizeof(*d
) > desc
->buffer_size
- desc
->used
) {
882 /* No room for the descriptor in this buffer, so advance to the
885 if (desc
->list
.next
== &ctx
->buffer_list
) {
886 /* If there is no free buffer next in the list,
888 if (context_add_buffer(ctx
) < 0)
891 desc
= list_entry(desc
->list
.next
,
892 struct descriptor_buffer
, list
);
893 ctx
->buffer_tail
= desc
;
896 d
= desc
->buffer
+ desc
->used
/ sizeof(*d
);
897 memset(d
, 0, z
* sizeof(*d
));
898 *d_bus
= desc
->buffer_bus
+ desc
->used
;
903 static void context_run(struct context
*ctx
, u32 extra
)
905 struct fw_ohci
*ohci
= ctx
->ohci
;
907 reg_write(ohci
, COMMAND_PTR(ctx
->regs
),
908 le32_to_cpu(ctx
->last
->branch_address
));
909 reg_write(ohci
, CONTROL_CLEAR(ctx
->regs
), ~0);
910 reg_write(ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_RUN
| extra
);
914 static void context_append(struct context
*ctx
,
915 struct descriptor
*d
, int z
, int extra
)
918 struct descriptor_buffer
*desc
= ctx
->buffer_tail
;
920 d_bus
= desc
->buffer_bus
+ (d
- desc
->buffer
) * sizeof(*d
);
922 desc
->used
+= (z
+ extra
) * sizeof(*d
);
923 ctx
->prev
->branch_address
= cpu_to_le32(d_bus
| z
);
924 ctx
->prev
= find_branch_descriptor(d
, z
);
926 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_WAKE
);
927 flush_writes(ctx
->ohci
);
930 static void context_stop(struct context
*ctx
)
935 reg_write(ctx
->ohci
, CONTROL_CLEAR(ctx
->regs
), CONTEXT_RUN
);
936 flush_writes(ctx
->ohci
);
938 for (i
= 0; i
< 10; i
++) {
939 reg
= reg_read(ctx
->ohci
, CONTROL_SET(ctx
->regs
));
940 if ((reg
& CONTEXT_ACTIVE
) == 0)
945 fw_error("Error: DMA context still active (0x%08x)\n", reg
);
949 struct fw_packet
*packet
;
953 * This function apppends a packet to the DMA queue for transmission.
954 * Must always be called with the ochi->lock held to ensure proper
955 * generation handling and locking around packet queue manipulation.
957 static int at_context_queue_packet(struct context
*ctx
,
958 struct fw_packet
*packet
)
960 struct fw_ohci
*ohci
= ctx
->ohci
;
961 dma_addr_t d_bus
, uninitialized_var(payload_bus
);
962 struct driver_data
*driver_data
;
963 struct descriptor
*d
, *last
;
968 d
= context_get_descriptors(ctx
, 4, &d_bus
);
970 packet
->ack
= RCODE_SEND_ERROR
;
974 d
[0].control
= cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE
);
975 d
[0].res_count
= cpu_to_le16(packet
->timestamp
);
978 * The DMA format for asyncronous link packets is different
979 * from the IEEE1394 layout, so shift the fields around
980 * accordingly. If header_length is 8, it's a PHY packet, to
981 * which we need to prepend an extra quadlet.
984 header
= (__le32
*) &d
[1];
985 switch (packet
->header_length
) {
988 header
[0] = cpu_to_le32((packet
->header
[0] & 0xffff) |
989 (packet
->speed
<< 16));
990 header
[1] = cpu_to_le32((packet
->header
[1] & 0xffff) |
991 (packet
->header
[0] & 0xffff0000));
992 header
[2] = cpu_to_le32(packet
->header
[2]);
994 tcode
= (packet
->header
[0] >> 4) & 0x0f;
995 if (TCODE_IS_BLOCK_PACKET(tcode
))
996 header
[3] = cpu_to_le32(packet
->header
[3]);
998 header
[3] = (__force __le32
) packet
->header
[3];
1000 d
[0].req_count
= cpu_to_le16(packet
->header_length
);
1004 header
[0] = cpu_to_le32((OHCI1394_phy_tcode
<< 4) |
1005 (packet
->speed
<< 16));
1006 header
[1] = cpu_to_le32(packet
->header
[0]);
1007 header
[2] = cpu_to_le32(packet
->header
[1]);
1008 d
[0].req_count
= cpu_to_le16(12);
1012 header
[0] = cpu_to_le32((packet
->header
[0] & 0xffff) |
1013 (packet
->speed
<< 16));
1014 header
[1] = cpu_to_le32(packet
->header
[0] & 0xffff0000);
1015 d
[0].req_count
= cpu_to_le16(8);
1020 packet
->ack
= RCODE_SEND_ERROR
;
1024 driver_data
= (struct driver_data
*) &d
[3];
1025 driver_data
->packet
= packet
;
1026 packet
->driver_data
= driver_data
;
1028 if (packet
->payload_length
> 0) {
1030 dma_map_single(ohci
->card
.device
, packet
->payload
,
1031 packet
->payload_length
, DMA_TO_DEVICE
);
1032 if (dma_mapping_error(ohci
->card
.device
, payload_bus
)) {
1033 packet
->ack
= RCODE_SEND_ERROR
;
1036 packet
->payload_bus
= payload_bus
;
1037 packet
->payload_mapped
= true;
1039 d
[2].req_count
= cpu_to_le16(packet
->payload_length
);
1040 d
[2].data_address
= cpu_to_le32(payload_bus
);
1048 last
->control
|= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
|
1049 DESCRIPTOR_IRQ_ALWAYS
|
1050 DESCRIPTOR_BRANCH_ALWAYS
);
1053 * If the controller and packet generations don't match, we need to
1054 * bail out and try again. If IntEvent.busReset is set, the AT context
1055 * is halted, so appending to the context and trying to run it is
1056 * futile. Most controllers do the right thing and just flush the AT
1057 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1058 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1059 * up stalling out. So we just bail out in software and try again
1060 * later, and everyone is happy.
1061 * FIXME: Document how the locking works.
1063 if (ohci
->generation
!= packet
->generation
||
1064 reg_read(ohci
, OHCI1394_IntEventSet
) & OHCI1394_busReset
) {
1065 if (packet
->payload_mapped
)
1066 dma_unmap_single(ohci
->card
.device
, payload_bus
,
1067 packet
->payload_length
, DMA_TO_DEVICE
);
1068 packet
->ack
= RCODE_GENERATION
;
1072 context_append(ctx
, d
, z
, 4 - z
);
1074 /* If the context isn't already running, start it up. */
1075 reg
= reg_read(ctx
->ohci
, CONTROL_SET(ctx
->regs
));
1076 if ((reg
& CONTEXT_RUN
) == 0)
1077 context_run(ctx
, 0);
1082 static int handle_at_packet(struct context
*context
,
1083 struct descriptor
*d
,
1084 struct descriptor
*last
)
1086 struct driver_data
*driver_data
;
1087 struct fw_packet
*packet
;
1088 struct fw_ohci
*ohci
= context
->ohci
;
1091 if (last
->transfer_status
== 0)
1092 /* This descriptor isn't done yet, stop iteration. */
1095 driver_data
= (struct driver_data
*) &d
[3];
1096 packet
= driver_data
->packet
;
1098 /* This packet was cancelled, just continue. */
1101 if (packet
->payload_mapped
)
1102 dma_unmap_single(ohci
->card
.device
, packet
->payload_bus
,
1103 packet
->payload_length
, DMA_TO_DEVICE
);
1105 evt
= le16_to_cpu(last
->transfer_status
) & 0x1f;
1106 packet
->timestamp
= le16_to_cpu(last
->res_count
);
1108 log_ar_at_event('T', packet
->speed
, packet
->header
, evt
);
1111 case OHCI1394_evt_timeout
:
1112 /* Async response transmit timed out. */
1113 packet
->ack
= RCODE_CANCELLED
;
1116 case OHCI1394_evt_flushed
:
1118 * The packet was flushed should give same error as
1119 * when we try to use a stale generation count.
1121 packet
->ack
= RCODE_GENERATION
;
1124 case OHCI1394_evt_missing_ack
:
1126 * Using a valid (current) generation count, but the
1127 * node is not on the bus or not sending acks.
1129 packet
->ack
= RCODE_NO_ACK
;
1132 case ACK_COMPLETE
+ 0x10:
1133 case ACK_PENDING
+ 0x10:
1134 case ACK_BUSY_X
+ 0x10:
1135 case ACK_BUSY_A
+ 0x10:
1136 case ACK_BUSY_B
+ 0x10:
1137 case ACK_DATA_ERROR
+ 0x10:
1138 case ACK_TYPE_ERROR
+ 0x10:
1139 packet
->ack
= evt
- 0x10;
1143 packet
->ack
= RCODE_SEND_ERROR
;
1147 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
1152 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1153 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1154 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1155 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1156 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1158 static void handle_local_rom(struct fw_ohci
*ohci
,
1159 struct fw_packet
*packet
, u32 csr
)
1161 struct fw_packet response
;
1162 int tcode
, length
, i
;
1164 tcode
= HEADER_GET_TCODE(packet
->header
[0]);
1165 if (TCODE_IS_BLOCK_PACKET(tcode
))
1166 length
= HEADER_GET_DATA_LENGTH(packet
->header
[3]);
1170 i
= csr
- CSR_CONFIG_ROM
;
1171 if (i
+ length
> CONFIG_ROM_SIZE
) {
1172 fw_fill_response(&response
, packet
->header
,
1173 RCODE_ADDRESS_ERROR
, NULL
, 0);
1174 } else if (!TCODE_IS_READ_REQUEST(tcode
)) {
1175 fw_fill_response(&response
, packet
->header
,
1176 RCODE_TYPE_ERROR
, NULL
, 0);
1178 fw_fill_response(&response
, packet
->header
, RCODE_COMPLETE
,
1179 (void *) ohci
->config_rom
+ i
, length
);
1182 fw_core_handle_response(&ohci
->card
, &response
);
1185 static void handle_local_lock(struct fw_ohci
*ohci
,
1186 struct fw_packet
*packet
, u32 csr
)
1188 struct fw_packet response
;
1189 int tcode
, length
, ext_tcode
, sel
;
1190 __be32
*payload
, lock_old
;
1191 u32 lock_arg
, lock_data
;
1193 tcode
= HEADER_GET_TCODE(packet
->header
[0]);
1194 length
= HEADER_GET_DATA_LENGTH(packet
->header
[3]);
1195 payload
= packet
->payload
;
1196 ext_tcode
= HEADER_GET_EXTENDED_TCODE(packet
->header
[3]);
1198 if (tcode
== TCODE_LOCK_REQUEST
&&
1199 ext_tcode
== EXTCODE_COMPARE_SWAP
&& length
== 8) {
1200 lock_arg
= be32_to_cpu(payload
[0]);
1201 lock_data
= be32_to_cpu(payload
[1]);
1202 } else if (tcode
== TCODE_READ_QUADLET_REQUEST
) {
1206 fw_fill_response(&response
, packet
->header
,
1207 RCODE_TYPE_ERROR
, NULL
, 0);
1211 sel
= (csr
- CSR_BUS_MANAGER_ID
) / 4;
1212 reg_write(ohci
, OHCI1394_CSRData
, lock_data
);
1213 reg_write(ohci
, OHCI1394_CSRCompareData
, lock_arg
);
1214 reg_write(ohci
, OHCI1394_CSRControl
, sel
);
1216 if (reg_read(ohci
, OHCI1394_CSRControl
) & 0x80000000)
1217 lock_old
= cpu_to_be32(reg_read(ohci
, OHCI1394_CSRData
));
1219 fw_notify("swap not done yet\n");
1221 fw_fill_response(&response
, packet
->header
,
1222 RCODE_COMPLETE
, &lock_old
, sizeof(lock_old
));
1224 fw_core_handle_response(&ohci
->card
, &response
);
1227 static void handle_local_request(struct context
*ctx
, struct fw_packet
*packet
)
1232 if (ctx
== &ctx
->ohci
->at_request_ctx
) {
1233 packet
->ack
= ACK_PENDING
;
1234 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
1238 ((unsigned long long)
1239 HEADER_GET_OFFSET_HIGH(packet
->header
[1]) << 32) |
1241 csr
= offset
- CSR_REGISTER_BASE
;
1243 /* Handle config rom reads. */
1244 if (csr
>= CSR_CONFIG_ROM
&& csr
< CSR_CONFIG_ROM_END
)
1245 handle_local_rom(ctx
->ohci
, packet
, csr
);
1247 case CSR_BUS_MANAGER_ID
:
1248 case CSR_BANDWIDTH_AVAILABLE
:
1249 case CSR_CHANNELS_AVAILABLE_HI
:
1250 case CSR_CHANNELS_AVAILABLE_LO
:
1251 handle_local_lock(ctx
->ohci
, packet
, csr
);
1254 if (ctx
== &ctx
->ohci
->at_request_ctx
)
1255 fw_core_handle_request(&ctx
->ohci
->card
, packet
);
1257 fw_core_handle_response(&ctx
->ohci
->card
, packet
);
1261 if (ctx
== &ctx
->ohci
->at_response_ctx
) {
1262 packet
->ack
= ACK_COMPLETE
;
1263 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
1267 static void at_context_transmit(struct context
*ctx
, struct fw_packet
*packet
)
1269 unsigned long flags
;
1272 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
1274 if (HEADER_GET_DESTINATION(packet
->header
[0]) == ctx
->ohci
->node_id
&&
1275 ctx
->ohci
->generation
== packet
->generation
) {
1276 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
1277 handle_local_request(ctx
, packet
);
1281 ret
= at_context_queue_packet(ctx
, packet
);
1282 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
1285 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
1289 static void bus_reset_tasklet(unsigned long data
)
1291 struct fw_ohci
*ohci
= (struct fw_ohci
*)data
;
1292 int self_id_count
, i
, j
, reg
;
1293 int generation
, new_generation
;
1294 unsigned long flags
;
1295 void *free_rom
= NULL
;
1296 dma_addr_t free_rom_bus
= 0;
1298 reg
= reg_read(ohci
, OHCI1394_NodeID
);
1299 if (!(reg
& OHCI1394_NodeID_idValid
)) {
1300 fw_notify("node ID not valid, new bus reset in progress\n");
1303 if ((reg
& OHCI1394_NodeID_nodeNumber
) == 63) {
1304 fw_notify("malconfigured bus\n");
1307 ohci
->node_id
= reg
& (OHCI1394_NodeID_busNumber
|
1308 OHCI1394_NodeID_nodeNumber
);
1310 reg
= reg_read(ohci
, OHCI1394_SelfIDCount
);
1311 if (reg
& OHCI1394_SelfIDCount_selfIDError
) {
1312 fw_notify("inconsistent self IDs\n");
1316 * The count in the SelfIDCount register is the number of
1317 * bytes in the self ID receive buffer. Since we also receive
1318 * the inverted quadlets and a header quadlet, we shift one
1319 * bit extra to get the actual number of self IDs.
1321 self_id_count
= (reg
>> 3) & 0xff;
1322 if (self_id_count
== 0 || self_id_count
> 252) {
1323 fw_notify("inconsistent self IDs\n");
1326 generation
= (cond_le32_to_cpu(ohci
->self_id_cpu
[0]) >> 16) & 0xff;
1329 for (i
= 1, j
= 0; j
< self_id_count
; i
+= 2, j
++) {
1330 if (ohci
->self_id_cpu
[i
] != ~ohci
->self_id_cpu
[i
+ 1]) {
1331 fw_notify("inconsistent self IDs\n");
1334 ohci
->self_id_buffer
[j
] =
1335 cond_le32_to_cpu(ohci
->self_id_cpu
[i
]);
1340 * Check the consistency of the self IDs we just read. The
1341 * problem we face is that a new bus reset can start while we
1342 * read out the self IDs from the DMA buffer. If this happens,
1343 * the DMA buffer will be overwritten with new self IDs and we
1344 * will read out inconsistent data. The OHCI specification
1345 * (section 11.2) recommends a technique similar to
1346 * linux/seqlock.h, where we remember the generation of the
1347 * self IDs in the buffer before reading them out and compare
1348 * it to the current generation after reading them out. If
1349 * the two generations match we know we have a consistent set
1353 new_generation
= (reg_read(ohci
, OHCI1394_SelfIDCount
) >> 16) & 0xff;
1354 if (new_generation
!= generation
) {
1355 fw_notify("recursive bus reset detected, "
1356 "discarding self ids\n");
1360 /* FIXME: Document how the locking works. */
1361 spin_lock_irqsave(&ohci
->lock
, flags
);
1363 ohci
->generation
= generation
;
1364 context_stop(&ohci
->at_request_ctx
);
1365 context_stop(&ohci
->at_response_ctx
);
1366 reg_write(ohci
, OHCI1394_IntEventClear
, OHCI1394_busReset
);
1368 if (ohci
->bus_reset_packet_quirk
)
1369 ohci
->request_generation
= generation
;
1372 * This next bit is unrelated to the AT context stuff but we
1373 * have to do it under the spinlock also. If a new config rom
1374 * was set up before this reset, the old one is now no longer
1375 * in use and we can free it. Update the config rom pointers
1376 * to point to the current config rom and clear the
1377 * next_config_rom pointer so a new udpate can take place.
1380 if (ohci
->next_config_rom
!= NULL
) {
1381 if (ohci
->next_config_rom
!= ohci
->config_rom
) {
1382 free_rom
= ohci
->config_rom
;
1383 free_rom_bus
= ohci
->config_rom_bus
;
1385 ohci
->config_rom
= ohci
->next_config_rom
;
1386 ohci
->config_rom_bus
= ohci
->next_config_rom_bus
;
1387 ohci
->next_config_rom
= NULL
;
1390 * Restore config_rom image and manually update
1391 * config_rom registers. Writing the header quadlet
1392 * will indicate that the config rom is ready, so we
1395 reg_write(ohci
, OHCI1394_BusOptions
,
1396 be32_to_cpu(ohci
->config_rom
[2]));
1397 ohci
->config_rom
[0] = ohci
->next_header
;
1398 reg_write(ohci
, OHCI1394_ConfigROMhdr
,
1399 be32_to_cpu(ohci
->next_header
));
1402 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1403 reg_write(ohci
, OHCI1394_PhyReqFilterHiSet
, ~0);
1404 reg_write(ohci
, OHCI1394_PhyReqFilterLoSet
, ~0);
1407 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1410 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1411 free_rom
, free_rom_bus
);
1413 log_selfids(ohci
->node_id
, generation
,
1414 self_id_count
, ohci
->self_id_buffer
);
1416 fw_core_handle_bus_reset(&ohci
->card
, ohci
->node_id
, generation
,
1417 self_id_count
, ohci
->self_id_buffer
);
1420 static irqreturn_t
irq_handler(int irq
, void *data
)
1422 struct fw_ohci
*ohci
= data
;
1423 u32 event
, iso_event
, cycle_time
;
1426 event
= reg_read(ohci
, OHCI1394_IntEventClear
);
1428 if (!event
|| !~event
)
1431 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1432 reg_write(ohci
, OHCI1394_IntEventClear
, event
& ~OHCI1394_busReset
);
1435 if (event
& OHCI1394_selfIDComplete
)
1436 tasklet_schedule(&ohci
->bus_reset_tasklet
);
1438 if (event
& OHCI1394_RQPkt
)
1439 tasklet_schedule(&ohci
->ar_request_ctx
.tasklet
);
1441 if (event
& OHCI1394_RSPkt
)
1442 tasklet_schedule(&ohci
->ar_response_ctx
.tasklet
);
1444 if (event
& OHCI1394_reqTxComplete
)
1445 tasklet_schedule(&ohci
->at_request_ctx
.tasklet
);
1447 if (event
& OHCI1394_respTxComplete
)
1448 tasklet_schedule(&ohci
->at_response_ctx
.tasklet
);
1450 iso_event
= reg_read(ohci
, OHCI1394_IsoRecvIntEventClear
);
1451 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, iso_event
);
1454 i
= ffs(iso_event
) - 1;
1455 tasklet_schedule(&ohci
->ir_context_list
[i
].context
.tasklet
);
1456 iso_event
&= ~(1 << i
);
1459 iso_event
= reg_read(ohci
, OHCI1394_IsoXmitIntEventClear
);
1460 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, iso_event
);
1463 i
= ffs(iso_event
) - 1;
1464 tasklet_schedule(&ohci
->it_context_list
[i
].context
.tasklet
);
1465 iso_event
&= ~(1 << i
);
1468 if (unlikely(event
& OHCI1394_regAccessFail
))
1469 fw_error("Register access failure - "
1470 "please notify linux1394-devel@lists.sf.net\n");
1472 if (unlikely(event
& OHCI1394_postedWriteErr
))
1473 fw_error("PCI posted write error\n");
1475 if (unlikely(event
& OHCI1394_cycleTooLong
)) {
1476 if (printk_ratelimit())
1477 fw_notify("isochronous cycle too long\n");
1478 reg_write(ohci
, OHCI1394_LinkControlSet
,
1479 OHCI1394_LinkControl_cycleMaster
);
1482 if (unlikely(event
& OHCI1394_cycleInconsistent
)) {
1484 * We need to clear this event bit in order to make
1485 * cycleMatch isochronous I/O work. In theory we should
1486 * stop active cycleMatch iso contexts now and restart
1487 * them at least two cycles later. (FIXME?)
1489 if (printk_ratelimit())
1490 fw_notify("isochronous cycle inconsistent\n");
1493 if (event
& OHCI1394_cycle64Seconds
) {
1494 cycle_time
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1495 if ((cycle_time
& 0x80000000) == 0)
1496 atomic_inc(&ohci
->bus_seconds
);
1502 static int software_reset(struct fw_ohci
*ohci
)
1506 reg_write(ohci
, OHCI1394_HCControlSet
, OHCI1394_HCControl_softReset
);
1508 for (i
= 0; i
< OHCI_LOOP_COUNT
; i
++) {
1509 if ((reg_read(ohci
, OHCI1394_HCControlSet
) &
1510 OHCI1394_HCControl_softReset
) == 0)
1518 static void copy_config_rom(__be32
*dest
, const __be32
*src
, size_t length
)
1520 size_t size
= length
* 4;
1522 memcpy(dest
, src
, size
);
1523 if (size
< CONFIG_ROM_SIZE
)
1524 memset(&dest
[length
], 0, CONFIG_ROM_SIZE
- size
);
1527 static int ohci_enable(struct fw_card
*card
,
1528 const __be32
*config_rom
, size_t length
)
1530 struct fw_ohci
*ohci
= fw_ohci(card
);
1531 struct pci_dev
*dev
= to_pci_dev(card
->device
);
1535 if (software_reset(ohci
)) {
1536 fw_error("Failed to reset ohci card.\n");
1541 * Now enable LPS, which we need in order to start accessing
1542 * most of the registers. In fact, on some cards (ALI M5251),
1543 * accessing registers in the SClk domain without LPS enabled
1544 * will lock up the machine. Wait 50msec to make sure we have
1545 * full link enabled. However, with some cards (well, at least
1546 * a JMicron PCIe card), we have to try again sometimes.
1548 reg_write(ohci
, OHCI1394_HCControlSet
,
1549 OHCI1394_HCControl_LPS
|
1550 OHCI1394_HCControl_postedWriteEnable
);
1553 for (lps
= 0, i
= 0; !lps
&& i
< 3; i
++) {
1555 lps
= reg_read(ohci
, OHCI1394_HCControlSet
) &
1556 OHCI1394_HCControl_LPS
;
1560 fw_error("Failed to set Link Power Status\n");
1564 reg_write(ohci
, OHCI1394_HCControlClear
,
1565 OHCI1394_HCControl_noByteSwapData
);
1567 reg_write(ohci
, OHCI1394_SelfIDBuffer
, ohci
->self_id_bus
);
1568 reg_write(ohci
, OHCI1394_LinkControlClear
,
1569 OHCI1394_LinkControl_rcvPhyPkt
);
1570 reg_write(ohci
, OHCI1394_LinkControlSet
,
1571 OHCI1394_LinkControl_rcvSelfID
|
1572 OHCI1394_LinkControl_cycleTimerEnable
|
1573 OHCI1394_LinkControl_cycleMaster
);
1575 reg_write(ohci
, OHCI1394_ATRetries
,
1576 OHCI1394_MAX_AT_REQ_RETRIES
|
1577 (OHCI1394_MAX_AT_RESP_RETRIES
<< 4) |
1578 (OHCI1394_MAX_PHYS_RESP_RETRIES
<< 8));
1580 ar_context_run(&ohci
->ar_request_ctx
);
1581 ar_context_run(&ohci
->ar_response_ctx
);
1583 reg_write(ohci
, OHCI1394_PhyUpperBound
, 0x00010000);
1584 reg_write(ohci
, OHCI1394_IntEventClear
, ~0);
1585 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
1586 reg_write(ohci
, OHCI1394_IntMaskSet
,
1587 OHCI1394_selfIDComplete
|
1588 OHCI1394_RQPkt
| OHCI1394_RSPkt
|
1589 OHCI1394_reqTxComplete
| OHCI1394_respTxComplete
|
1590 OHCI1394_isochRx
| OHCI1394_isochTx
|
1591 OHCI1394_postedWriteErr
| OHCI1394_cycleTooLong
|
1592 OHCI1394_cycleInconsistent
|
1593 OHCI1394_cycle64Seconds
| OHCI1394_regAccessFail
|
1594 OHCI1394_masterIntEnable
);
1595 if (param_debug
& OHCI_PARAM_DEBUG_BUSRESETS
)
1596 reg_write(ohci
, OHCI1394_IntMaskSet
, OHCI1394_busReset
);
1598 /* Activate link_on bit and contender bit in our self ID packets.*/
1599 if (ohci_update_phy_reg(card
, 4, 0,
1600 PHY_LINK_ACTIVE
| PHY_CONTENDER
) < 0)
1604 * When the link is not yet enabled, the atomic config rom
1605 * update mechanism described below in ohci_set_config_rom()
1606 * is not active. We have to update ConfigRomHeader and
1607 * BusOptions manually, and the write to ConfigROMmap takes
1608 * effect immediately. We tie this to the enabling of the
1609 * link, so we have a valid config rom before enabling - the
1610 * OHCI requires that ConfigROMhdr and BusOptions have valid
1611 * values before enabling.
1613 * However, when the ConfigROMmap is written, some controllers
1614 * always read back quadlets 0 and 2 from the config rom to
1615 * the ConfigRomHeader and BusOptions registers on bus reset.
1616 * They shouldn't do that in this initial case where the link
1617 * isn't enabled. This means we have to use the same
1618 * workaround here, setting the bus header to 0 and then write
1619 * the right values in the bus reset tasklet.
1623 ohci
->next_config_rom
=
1624 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1625 &ohci
->next_config_rom_bus
,
1627 if (ohci
->next_config_rom
== NULL
)
1630 copy_config_rom(ohci
->next_config_rom
, config_rom
, length
);
1633 * In the suspend case, config_rom is NULL, which
1634 * means that we just reuse the old config rom.
1636 ohci
->next_config_rom
= ohci
->config_rom
;
1637 ohci
->next_config_rom_bus
= ohci
->config_rom_bus
;
1640 ohci
->next_header
= ohci
->next_config_rom
[0];
1641 ohci
->next_config_rom
[0] = 0;
1642 reg_write(ohci
, OHCI1394_ConfigROMhdr
, 0);
1643 reg_write(ohci
, OHCI1394_BusOptions
,
1644 be32_to_cpu(ohci
->next_config_rom
[2]));
1645 reg_write(ohci
, OHCI1394_ConfigROMmap
, ohci
->next_config_rom_bus
);
1647 reg_write(ohci
, OHCI1394_AsReqFilterHiSet
, 0x80000000);
1649 if (request_irq(dev
->irq
, irq_handler
,
1650 IRQF_SHARED
, ohci_driver_name
, ohci
)) {
1651 fw_error("Failed to allocate shared interrupt %d.\n",
1653 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1654 ohci
->config_rom
, ohci
->config_rom_bus
);
1658 reg_write(ohci
, OHCI1394_HCControlSet
,
1659 OHCI1394_HCControl_linkEnable
|
1660 OHCI1394_HCControl_BIBimageValid
);
1664 * We are ready to go, initiate bus reset to finish the
1668 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1673 static int ohci_set_config_rom(struct fw_card
*card
,
1674 const __be32
*config_rom
, size_t length
)
1676 struct fw_ohci
*ohci
;
1677 unsigned long flags
;
1679 __be32
*next_config_rom
;
1680 dma_addr_t
uninitialized_var(next_config_rom_bus
);
1682 ohci
= fw_ohci(card
);
1685 * When the OHCI controller is enabled, the config rom update
1686 * mechanism is a bit tricky, but easy enough to use. See
1687 * section 5.5.6 in the OHCI specification.
1689 * The OHCI controller caches the new config rom address in a
1690 * shadow register (ConfigROMmapNext) and needs a bus reset
1691 * for the changes to take place. When the bus reset is
1692 * detected, the controller loads the new values for the
1693 * ConfigRomHeader and BusOptions registers from the specified
1694 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1695 * shadow register. All automatically and atomically.
1697 * Now, there's a twist to this story. The automatic load of
1698 * ConfigRomHeader and BusOptions doesn't honor the
1699 * noByteSwapData bit, so with a be32 config rom, the
1700 * controller will load be32 values in to these registers
1701 * during the atomic update, even on litte endian
1702 * architectures. The workaround we use is to put a 0 in the
1703 * header quadlet; 0 is endian agnostic and means that the
1704 * config rom isn't ready yet. In the bus reset tasklet we
1705 * then set up the real values for the two registers.
1707 * We use ohci->lock to avoid racing with the code that sets
1708 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1712 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1713 &next_config_rom_bus
, GFP_KERNEL
);
1714 if (next_config_rom
== NULL
)
1717 spin_lock_irqsave(&ohci
->lock
, flags
);
1719 if (ohci
->next_config_rom
== NULL
) {
1720 ohci
->next_config_rom
= next_config_rom
;
1721 ohci
->next_config_rom_bus
= next_config_rom_bus
;
1723 copy_config_rom(ohci
->next_config_rom
, config_rom
, length
);
1725 ohci
->next_header
= config_rom
[0];
1726 ohci
->next_config_rom
[0] = 0;
1728 reg_write(ohci
, OHCI1394_ConfigROMmap
,
1729 ohci
->next_config_rom_bus
);
1733 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1736 * Now initiate a bus reset to have the changes take
1737 * effect. We clean up the old config rom memory and DMA
1738 * mappings in the bus reset tasklet, since the OHCI
1739 * controller could need to access it before the bus reset
1743 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1745 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1746 next_config_rom
, next_config_rom_bus
);
1751 static void ohci_send_request(struct fw_card
*card
, struct fw_packet
*packet
)
1753 struct fw_ohci
*ohci
= fw_ohci(card
);
1755 at_context_transmit(&ohci
->at_request_ctx
, packet
);
1758 static void ohci_send_response(struct fw_card
*card
, struct fw_packet
*packet
)
1760 struct fw_ohci
*ohci
= fw_ohci(card
);
1762 at_context_transmit(&ohci
->at_response_ctx
, packet
);
1765 static int ohci_cancel_packet(struct fw_card
*card
, struct fw_packet
*packet
)
1767 struct fw_ohci
*ohci
= fw_ohci(card
);
1768 struct context
*ctx
= &ohci
->at_request_ctx
;
1769 struct driver_data
*driver_data
= packet
->driver_data
;
1772 tasklet_disable(&ctx
->tasklet
);
1774 if (packet
->ack
!= 0)
1777 if (packet
->payload_mapped
)
1778 dma_unmap_single(ohci
->card
.device
, packet
->payload_bus
,
1779 packet
->payload_length
, DMA_TO_DEVICE
);
1781 log_ar_at_event('T', packet
->speed
, packet
->header
, 0x20);
1782 driver_data
->packet
= NULL
;
1783 packet
->ack
= RCODE_CANCELLED
;
1784 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
1787 tasklet_enable(&ctx
->tasklet
);
1792 static int ohci_enable_phys_dma(struct fw_card
*card
,
1793 int node_id
, int generation
)
1795 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1798 struct fw_ohci
*ohci
= fw_ohci(card
);
1799 unsigned long flags
;
1803 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1804 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1807 spin_lock_irqsave(&ohci
->lock
, flags
);
1809 if (ohci
->generation
!= generation
) {
1815 * Note, if the node ID contains a non-local bus ID, physical DMA is
1816 * enabled for _all_ nodes on remote buses.
1819 n
= (node_id
& 0xffc0) == LOCAL_BUS
? node_id
& 0x3f : 63;
1821 reg_write(ohci
, OHCI1394_PhyReqFilterLoSet
, 1 << n
);
1823 reg_write(ohci
, OHCI1394_PhyReqFilterHiSet
, 1 << (n
- 32));
1827 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1830 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1833 static u64
ohci_get_bus_time(struct fw_card
*card
)
1835 struct fw_ohci
*ohci
= fw_ohci(card
);
1839 cycle_time
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1840 bus_time
= ((u64
)atomic_read(&ohci
->bus_seconds
) << 32) | cycle_time
;
1845 static void copy_iso_headers(struct iso_context
*ctx
, void *p
)
1847 int i
= ctx
->header_length
;
1849 if (i
+ ctx
->base
.header_size
> PAGE_SIZE
)
1853 * The iso header is byteswapped to little endian by
1854 * the controller, but the remaining header quadlets
1855 * are big endian. We want to present all the headers
1856 * as big endian, so we have to swap the first quadlet.
1858 if (ctx
->base
.header_size
> 0)
1859 *(u32
*) (ctx
->header
+ i
) = __swab32(*(u32
*) (p
+ 4));
1860 if (ctx
->base
.header_size
> 4)
1861 *(u32
*) (ctx
->header
+ i
+ 4) = __swab32(*(u32
*) p
);
1862 if (ctx
->base
.header_size
> 8)
1863 memcpy(ctx
->header
+ i
+ 8, p
+ 8, ctx
->base
.header_size
- 8);
1864 ctx
->header_length
+= ctx
->base
.header_size
;
1867 static int handle_ir_dualbuffer_packet(struct context
*context
,
1868 struct descriptor
*d
,
1869 struct descriptor
*last
)
1871 struct iso_context
*ctx
=
1872 container_of(context
, struct iso_context
, context
);
1873 struct db_descriptor
*db
= (struct db_descriptor
*) d
;
1875 size_t header_length
;
1878 if (db
->first_res_count
!= 0 && db
->second_res_count
!= 0) {
1879 if (ctx
->excess_bytes
<= le16_to_cpu(db
->second_req_count
)) {
1880 /* This descriptor isn't done yet, stop iteration. */
1883 ctx
->excess_bytes
-= le16_to_cpu(db
->second_req_count
);
1886 header_length
= le16_to_cpu(db
->first_req_count
) -
1887 le16_to_cpu(db
->first_res_count
);
1890 end
= p
+ header_length
;
1892 copy_iso_headers(ctx
, p
);
1893 ctx
->excess_bytes
+=
1894 (le32_to_cpu(*(__le32
*)(p
+ 4)) >> 16) & 0xffff;
1895 p
+= max(ctx
->base
.header_size
, (size_t)8);
1898 ctx
->excess_bytes
-= le16_to_cpu(db
->second_req_count
) -
1899 le16_to_cpu(db
->second_res_count
);
1901 if (le16_to_cpu(db
->control
) & DESCRIPTOR_IRQ_ALWAYS
) {
1902 ir_header
= (__le32
*) (db
+ 1);
1903 ctx
->base
.callback(&ctx
->base
,
1904 le32_to_cpu(ir_header
[0]) & 0xffff,
1905 ctx
->header_length
, ctx
->header
,
1906 ctx
->base
.callback_data
);
1907 ctx
->header_length
= 0;
1913 static int handle_ir_packet_per_buffer(struct context
*context
,
1914 struct descriptor
*d
,
1915 struct descriptor
*last
)
1917 struct iso_context
*ctx
=
1918 container_of(context
, struct iso_context
, context
);
1919 struct descriptor
*pd
;
1923 for (pd
= d
; pd
<= last
; pd
++) {
1924 if (pd
->transfer_status
)
1928 /* Descriptor(s) not done yet, stop iteration */
1932 copy_iso_headers(ctx
, p
);
1934 if (le16_to_cpu(last
->control
) & DESCRIPTOR_IRQ_ALWAYS
) {
1935 ir_header
= (__le32
*) p
;
1936 ctx
->base
.callback(&ctx
->base
,
1937 le32_to_cpu(ir_header
[0]) & 0xffff,
1938 ctx
->header_length
, ctx
->header
,
1939 ctx
->base
.callback_data
);
1940 ctx
->header_length
= 0;
1946 static int handle_it_packet(struct context
*context
,
1947 struct descriptor
*d
,
1948 struct descriptor
*last
)
1950 struct iso_context
*ctx
=
1951 container_of(context
, struct iso_context
, context
);
1953 struct descriptor
*pd
;
1955 for (pd
= d
; pd
<= last
; pd
++)
1956 if (pd
->transfer_status
)
1959 /* Descriptor(s) not done yet, stop iteration */
1962 i
= ctx
->header_length
;
1963 if (i
+ 4 < PAGE_SIZE
) {
1964 /* Present this value as big-endian to match the receive code */
1965 *(__be32
*)(ctx
->header
+ i
) = cpu_to_be32(
1966 ((u32
)le16_to_cpu(pd
->transfer_status
) << 16) |
1967 le16_to_cpu(pd
->res_count
));
1968 ctx
->header_length
+= 4;
1970 if (le16_to_cpu(last
->control
) & DESCRIPTOR_IRQ_ALWAYS
) {
1971 ctx
->base
.callback(&ctx
->base
, le16_to_cpu(last
->res_count
),
1972 ctx
->header_length
, ctx
->header
,
1973 ctx
->base
.callback_data
);
1974 ctx
->header_length
= 0;
1979 static struct fw_iso_context
*ohci_allocate_iso_context(struct fw_card
*card
,
1980 int type
, int channel
, size_t header_size
)
1982 struct fw_ohci
*ohci
= fw_ohci(card
);
1983 struct iso_context
*ctx
, *list
;
1984 descriptor_callback_t callback
;
1985 u64
*channels
, dont_care
= ~0ULL;
1987 unsigned long flags
;
1988 int index
, ret
= -ENOMEM
;
1990 if (type
== FW_ISO_CONTEXT_TRANSMIT
) {
1991 channels
= &dont_care
;
1992 mask
= &ohci
->it_context_mask
;
1993 list
= ohci
->it_context_list
;
1994 callback
= handle_it_packet
;
1996 channels
= &ohci
->ir_context_channels
;
1997 mask
= &ohci
->ir_context_mask
;
1998 list
= ohci
->ir_context_list
;
1999 if (ohci
->use_dualbuffer
)
2000 callback
= handle_ir_dualbuffer_packet
;
2002 callback
= handle_ir_packet_per_buffer
;
2005 spin_lock_irqsave(&ohci
->lock
, flags
);
2006 index
= *channels
& 1ULL << channel
? ffs(*mask
) - 1 : -1;
2008 *channels
&= ~(1ULL << channel
);
2009 *mask
&= ~(1 << index
);
2011 spin_unlock_irqrestore(&ohci
->lock
, flags
);
2014 return ERR_PTR(-EBUSY
);
2016 if (type
== FW_ISO_CONTEXT_TRANSMIT
)
2017 regs
= OHCI1394_IsoXmitContextBase(index
);
2019 regs
= OHCI1394_IsoRcvContextBase(index
);
2022 memset(ctx
, 0, sizeof(*ctx
));
2023 ctx
->header_length
= 0;
2024 ctx
->header
= (void *) __get_free_page(GFP_KERNEL
);
2025 if (ctx
->header
== NULL
)
2028 ret
= context_init(&ctx
->context
, ohci
, regs
, callback
);
2030 goto out_with_header
;
2035 free_page((unsigned long)ctx
->header
);
2037 spin_lock_irqsave(&ohci
->lock
, flags
);
2038 *mask
|= 1 << index
;
2039 spin_unlock_irqrestore(&ohci
->lock
, flags
);
2041 return ERR_PTR(ret
);
2044 static int ohci_start_iso(struct fw_iso_context
*base
,
2045 s32 cycle
, u32 sync
, u32 tags
)
2047 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2048 struct fw_ohci
*ohci
= ctx
->context
.ohci
;
2052 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
2053 index
= ctx
- ohci
->it_context_list
;
2056 match
= IT_CONTEXT_CYCLE_MATCH_ENABLE
|
2057 (cycle
& 0x7fff) << 16;
2059 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, 1 << index
);
2060 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, 1 << index
);
2061 context_run(&ctx
->context
, match
);
2063 index
= ctx
- ohci
->ir_context_list
;
2064 control
= IR_CONTEXT_ISOCH_HEADER
;
2065 if (ohci
->use_dualbuffer
)
2066 control
|= IR_CONTEXT_DUAL_BUFFER_MODE
;
2067 match
= (tags
<< 28) | (sync
<< 8) | ctx
->base
.channel
;
2069 match
|= (cycle
& 0x07fff) << 12;
2070 control
|= IR_CONTEXT_CYCLE_MATCH_ENABLE
;
2073 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, 1 << index
);
2074 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, 1 << index
);
2075 reg_write(ohci
, CONTEXT_MATCH(ctx
->context
.regs
), match
);
2076 context_run(&ctx
->context
, control
);
2082 static int ohci_stop_iso(struct fw_iso_context
*base
)
2084 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
2085 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2088 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
2089 index
= ctx
- ohci
->it_context_list
;
2090 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, 1 << index
);
2092 index
= ctx
- ohci
->ir_context_list
;
2093 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, 1 << index
);
2096 context_stop(&ctx
->context
);
2101 static void ohci_free_iso_context(struct fw_iso_context
*base
)
2103 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
2104 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2105 unsigned long flags
;
2108 ohci_stop_iso(base
);
2109 context_release(&ctx
->context
);
2110 free_page((unsigned long)ctx
->header
);
2112 spin_lock_irqsave(&ohci
->lock
, flags
);
2114 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
2115 index
= ctx
- ohci
->it_context_list
;
2116 ohci
->it_context_mask
|= 1 << index
;
2118 index
= ctx
- ohci
->ir_context_list
;
2119 ohci
->ir_context_mask
|= 1 << index
;
2120 ohci
->ir_context_channels
|= 1ULL << base
->channel
;
2123 spin_unlock_irqrestore(&ohci
->lock
, flags
);
2126 static int ohci_queue_iso_transmit(struct fw_iso_context
*base
,
2127 struct fw_iso_packet
*packet
,
2128 struct fw_iso_buffer
*buffer
,
2129 unsigned long payload
)
2131 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2132 struct descriptor
*d
, *last
, *pd
;
2133 struct fw_iso_packet
*p
;
2135 dma_addr_t d_bus
, page_bus
;
2136 u32 z
, header_z
, payload_z
, irq
;
2137 u32 payload_index
, payload_end_index
, next_page_index
;
2138 int page
, end_page
, i
, length
, offset
;
2141 payload_index
= payload
;
2147 if (p
->header_length
> 0)
2150 /* Determine the first page the payload isn't contained in. */
2151 end_page
= PAGE_ALIGN(payload_index
+ p
->payload_length
) >> PAGE_SHIFT
;
2152 if (p
->payload_length
> 0)
2153 payload_z
= end_page
- (payload_index
>> PAGE_SHIFT
);
2159 /* Get header size in number of descriptors. */
2160 header_z
= DIV_ROUND_UP(p
->header_length
, sizeof(*d
));
2162 d
= context_get_descriptors(&ctx
->context
, z
+ header_z
, &d_bus
);
2167 d
[0].control
= cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE
);
2168 d
[0].req_count
= cpu_to_le16(8);
2170 * Link the skip address to this descriptor itself. This causes
2171 * a context to skip a cycle whenever lost cycles or FIFO
2172 * overruns occur, without dropping the data. The application
2173 * should then decide whether this is an error condition or not.
2174 * FIXME: Make the context's cycle-lost behaviour configurable?
2176 d
[0].branch_address
= cpu_to_le32(d_bus
| z
);
2178 header
= (__le32
*) &d
[1];
2179 header
[0] = cpu_to_le32(IT_HEADER_SY(p
->sy
) |
2180 IT_HEADER_TAG(p
->tag
) |
2181 IT_HEADER_TCODE(TCODE_STREAM_DATA
) |
2182 IT_HEADER_CHANNEL(ctx
->base
.channel
) |
2183 IT_HEADER_SPEED(ctx
->base
.speed
));
2185 cpu_to_le32(IT_HEADER_DATA_LENGTH(p
->header_length
+
2186 p
->payload_length
));
2189 if (p
->header_length
> 0) {
2190 d
[2].req_count
= cpu_to_le16(p
->header_length
);
2191 d
[2].data_address
= cpu_to_le32(d_bus
+ z
* sizeof(*d
));
2192 memcpy(&d
[z
], p
->header
, p
->header_length
);
2195 pd
= d
+ z
- payload_z
;
2196 payload_end_index
= payload_index
+ p
->payload_length
;
2197 for (i
= 0; i
< payload_z
; i
++) {
2198 page
= payload_index
>> PAGE_SHIFT
;
2199 offset
= payload_index
& ~PAGE_MASK
;
2200 next_page_index
= (page
+ 1) << PAGE_SHIFT
;
2202 min(next_page_index
, payload_end_index
) - payload_index
;
2203 pd
[i
].req_count
= cpu_to_le16(length
);
2205 page_bus
= page_private(buffer
->pages
[page
]);
2206 pd
[i
].data_address
= cpu_to_le32(page_bus
+ offset
);
2208 payload_index
+= length
;
2212 irq
= DESCRIPTOR_IRQ_ALWAYS
;
2214 irq
= DESCRIPTOR_NO_IRQ
;
2216 last
= z
== 2 ? d
: d
+ z
- 1;
2217 last
->control
|= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
|
2219 DESCRIPTOR_BRANCH_ALWAYS
|
2222 context_append(&ctx
->context
, d
, z
, header_z
);
2227 static int ohci_queue_iso_receive_dualbuffer(struct fw_iso_context
*base
,
2228 struct fw_iso_packet
*packet
,
2229 struct fw_iso_buffer
*buffer
,
2230 unsigned long payload
)
2232 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2233 struct db_descriptor
*db
= NULL
;
2234 struct descriptor
*d
;
2235 struct fw_iso_packet
*p
;
2236 dma_addr_t d_bus
, page_bus
;
2237 u32 z
, header_z
, length
, rest
;
2238 int page
, offset
, packet_count
, header_size
;
2241 * FIXME: Cycle lost behavior should be configurable: lose
2242 * packet, retransmit or terminate..
2249 * The OHCI controller puts the isochronous header and trailer in the
2250 * buffer, so we need at least 8 bytes.
2252 packet_count
= p
->header_length
/ ctx
->base
.header_size
;
2253 header_size
= packet_count
* max(ctx
->base
.header_size
, (size_t)8);
2255 /* Get header size in number of descriptors. */
2256 header_z
= DIV_ROUND_UP(header_size
, sizeof(*d
));
2257 page
= payload
>> PAGE_SHIFT
;
2258 offset
= payload
& ~PAGE_MASK
;
2259 rest
= p
->payload_length
;
2261 * The controllers I've tested have not worked correctly when
2262 * second_req_count is zero. Rather than do something we know won't
2263 * work, return an error
2269 d
= context_get_descriptors(&ctx
->context
,
2270 z
+ header_z
, &d_bus
);
2274 db
= (struct db_descriptor
*) d
;
2275 db
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2276 DESCRIPTOR_BRANCH_ALWAYS
);
2278 cpu_to_le16(max(ctx
->base
.header_size
, (size_t)8));
2279 if (p
->skip
&& rest
== p
->payload_length
) {
2280 db
->control
|= cpu_to_le16(DESCRIPTOR_WAIT
);
2281 db
->first_req_count
= db
->first_size
;
2283 db
->first_req_count
= cpu_to_le16(header_size
);
2285 db
->first_res_count
= db
->first_req_count
;
2286 db
->first_buffer
= cpu_to_le32(d_bus
+ sizeof(*db
));
2288 if (p
->skip
&& rest
== p
->payload_length
)
2290 else if (offset
+ rest
< PAGE_SIZE
)
2293 length
= PAGE_SIZE
- offset
;
2295 db
->second_req_count
= cpu_to_le16(length
);
2296 db
->second_res_count
= db
->second_req_count
;
2297 page_bus
= page_private(buffer
->pages
[page
]);
2298 db
->second_buffer
= cpu_to_le32(page_bus
+ offset
);
2300 if (p
->interrupt
&& length
== rest
)
2301 db
->control
|= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS
);
2303 context_append(&ctx
->context
, d
, z
, header_z
);
2304 offset
= (offset
+ length
) & ~PAGE_MASK
;
2313 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context
*base
,
2314 struct fw_iso_packet
*packet
,
2315 struct fw_iso_buffer
*buffer
,
2316 unsigned long payload
)
2318 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2319 struct descriptor
*d
, *pd
;
2320 struct fw_iso_packet
*p
= packet
;
2321 dma_addr_t d_bus
, page_bus
;
2322 u32 z
, header_z
, rest
;
2324 int page
, offset
, packet_count
, header_size
, payload_per_buffer
;
2327 * The OHCI controller puts the isochronous header and trailer in the
2328 * buffer, so we need at least 8 bytes.
2330 packet_count
= p
->header_length
/ ctx
->base
.header_size
;
2331 header_size
= max(ctx
->base
.header_size
, (size_t)8);
2333 /* Get header size in number of descriptors. */
2334 header_z
= DIV_ROUND_UP(header_size
, sizeof(*d
));
2335 page
= payload
>> PAGE_SHIFT
;
2336 offset
= payload
& ~PAGE_MASK
;
2337 payload_per_buffer
= p
->payload_length
/ packet_count
;
2339 for (i
= 0; i
< packet_count
; i
++) {
2340 /* d points to the header descriptor */
2341 z
= DIV_ROUND_UP(payload_per_buffer
+ offset
, PAGE_SIZE
) + 1;
2342 d
= context_get_descriptors(&ctx
->context
,
2343 z
+ header_z
, &d_bus
);
2347 d
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2348 DESCRIPTOR_INPUT_MORE
);
2349 if (p
->skip
&& i
== 0)
2350 d
->control
|= cpu_to_le16(DESCRIPTOR_WAIT
);
2351 d
->req_count
= cpu_to_le16(header_size
);
2352 d
->res_count
= d
->req_count
;
2353 d
->transfer_status
= 0;
2354 d
->data_address
= cpu_to_le32(d_bus
+ (z
* sizeof(*d
)));
2356 rest
= payload_per_buffer
;
2358 for (j
= 1; j
< z
; j
++) {
2360 pd
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2361 DESCRIPTOR_INPUT_MORE
);
2363 if (offset
+ rest
< PAGE_SIZE
)
2366 length
= PAGE_SIZE
- offset
;
2367 pd
->req_count
= cpu_to_le16(length
);
2368 pd
->res_count
= pd
->req_count
;
2369 pd
->transfer_status
= 0;
2371 page_bus
= page_private(buffer
->pages
[page
]);
2372 pd
->data_address
= cpu_to_le32(page_bus
+ offset
);
2374 offset
= (offset
+ length
) & ~PAGE_MASK
;
2379 pd
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2380 DESCRIPTOR_INPUT_LAST
|
2381 DESCRIPTOR_BRANCH_ALWAYS
);
2382 if (p
->interrupt
&& i
== packet_count
- 1)
2383 pd
->control
|= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS
);
2385 context_append(&ctx
->context
, d
, z
, header_z
);
2391 static int ohci_queue_iso(struct fw_iso_context
*base
,
2392 struct fw_iso_packet
*packet
,
2393 struct fw_iso_buffer
*buffer
,
2394 unsigned long payload
)
2396 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2397 unsigned long flags
;
2400 spin_lock_irqsave(&ctx
->context
.ohci
->lock
, flags
);
2401 if (base
->type
== FW_ISO_CONTEXT_TRANSMIT
)
2402 ret
= ohci_queue_iso_transmit(base
, packet
, buffer
, payload
);
2403 else if (ctx
->context
.ohci
->use_dualbuffer
)
2404 ret
= ohci_queue_iso_receive_dualbuffer(base
, packet
,
2407 ret
= ohci_queue_iso_receive_packet_per_buffer(base
, packet
,
2409 spin_unlock_irqrestore(&ctx
->context
.ohci
->lock
, flags
);
2414 static const struct fw_card_driver ohci_driver
= {
2415 .enable
= ohci_enable
,
2416 .update_phy_reg
= ohci_update_phy_reg
,
2417 .set_config_rom
= ohci_set_config_rom
,
2418 .send_request
= ohci_send_request
,
2419 .send_response
= ohci_send_response
,
2420 .cancel_packet
= ohci_cancel_packet
,
2421 .enable_phys_dma
= ohci_enable_phys_dma
,
2422 .get_bus_time
= ohci_get_bus_time
,
2424 .allocate_iso_context
= ohci_allocate_iso_context
,
2425 .free_iso_context
= ohci_free_iso_context
,
2426 .queue_iso
= ohci_queue_iso
,
2427 .start_iso
= ohci_start_iso
,
2428 .stop_iso
= ohci_stop_iso
,
2431 #ifdef CONFIG_PPC_PMAC
2432 static void ohci_pmac_on(struct pci_dev
*dev
)
2434 if (machine_is(powermac
)) {
2435 struct device_node
*ofn
= pci_device_to_OF_node(dev
);
2438 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, ofn
, 0, 1);
2439 pmac_call_feature(PMAC_FTR_1394_ENABLE
, ofn
, 0, 1);
2444 static void ohci_pmac_off(struct pci_dev
*dev
)
2446 if (machine_is(powermac
)) {
2447 struct device_node
*ofn
= pci_device_to_OF_node(dev
);
2450 pmac_call_feature(PMAC_FTR_1394_ENABLE
, ofn
, 0, 0);
2451 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, ofn
, 0, 0);
2456 #define ohci_pmac_on(dev)
2457 #define ohci_pmac_off(dev)
2458 #endif /* CONFIG_PPC_PMAC */
2460 #define PCI_VENDOR_ID_AGERE PCI_VENDOR_ID_ATT
2461 #define PCI_DEVICE_ID_AGERE_FW643 0x5901
2462 #define PCI_DEVICE_ID_TI_TSB43AB23 0x8024
2464 static int __devinit
pci_probe(struct pci_dev
*dev
,
2465 const struct pci_device_id
*ent
)
2467 struct fw_ohci
*ohci
;
2468 u32 bus_options
, max_receive
, link_speed
, version
;
2473 ohci
= kzalloc(sizeof(*ohci
), GFP_KERNEL
);
2479 fw_card_initialize(&ohci
->card
, &ohci_driver
, &dev
->dev
);
2483 err
= pci_enable_device(dev
);
2485 fw_error("Failed to enable OHCI hardware\n");
2489 pci_set_master(dev
);
2490 pci_write_config_dword(dev
, OHCI1394_PCI_HCI_Control
, 0);
2491 pci_set_drvdata(dev
, ohci
);
2493 spin_lock_init(&ohci
->lock
);
2495 tasklet_init(&ohci
->bus_reset_tasklet
,
2496 bus_reset_tasklet
, (unsigned long)ohci
);
2498 err
= pci_request_region(dev
, 0, ohci_driver_name
);
2500 fw_error("MMIO resource unavailable\n");
2504 ohci
->registers
= pci_iomap(dev
, 0, OHCI1394_REGISTER_SIZE
);
2505 if (ohci
->registers
== NULL
) {
2506 fw_error("Failed to remap registers\n");
2511 version
= reg_read(ohci
, OHCI1394_Version
) & 0x00ff00ff;
2513 /* FIXME: make it a context option or remove dual-buffer mode */
2514 ohci
->use_dualbuffer
= version
>= OHCI_VERSION_1_1
;
2517 /* dual-buffer mode is broken if more than one IR context is active */
2518 if (dev
->vendor
== PCI_VENDOR_ID_AGERE
&&
2519 dev
->device
== PCI_DEVICE_ID_AGERE_FW643
)
2520 ohci
->use_dualbuffer
= false;
2522 /* dual-buffer mode is broken */
2523 if (dev
->vendor
== PCI_VENDOR_ID_RICOH
&&
2524 dev
->device
== PCI_DEVICE_ID_RICOH_R5C832
)
2525 ohci
->use_dualbuffer
= false;
2527 /* x86-32 currently doesn't use highmem for dma_alloc_coherent */
2528 #if !defined(CONFIG_X86_32)
2529 /* dual-buffer mode is broken with descriptor addresses above 2G */
2530 if (dev
->vendor
== PCI_VENDOR_ID_TI
&&
2531 (dev
->device
== PCI_DEVICE_ID_TI_TSB43AB22
||
2532 dev
->device
== PCI_DEVICE_ID_TI_TSB43AB23
))
2533 ohci
->use_dualbuffer
= false;
2536 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2537 ohci
->old_uninorth
= dev
->vendor
== PCI_VENDOR_ID_APPLE
&&
2538 dev
->device
== PCI_DEVICE_ID_APPLE_UNI_N_FW
;
2540 ohci
->bus_reset_packet_quirk
= dev
->vendor
== PCI_VENDOR_ID_TI
;
2542 ar_context_init(&ohci
->ar_request_ctx
, ohci
,
2543 OHCI1394_AsReqRcvContextControlSet
);
2545 ar_context_init(&ohci
->ar_response_ctx
, ohci
,
2546 OHCI1394_AsRspRcvContextControlSet
);
2548 context_init(&ohci
->at_request_ctx
, ohci
,
2549 OHCI1394_AsReqTrContextControlSet
, handle_at_packet
);
2551 context_init(&ohci
->at_response_ctx
, ohci
,
2552 OHCI1394_AsRspTrContextControlSet
, handle_at_packet
);
2554 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, ~0);
2555 ohci
->it_context_mask
= reg_read(ohci
, OHCI1394_IsoRecvIntMaskSet
);
2556 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, ~0);
2557 size
= sizeof(struct iso_context
) * hweight32(ohci
->it_context_mask
);
2558 ohci
->it_context_list
= kzalloc(size
, GFP_KERNEL
);
2560 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, ~0);
2561 ohci
->ir_context_channels
= ~0ULL;
2562 ohci
->ir_context_mask
= reg_read(ohci
, OHCI1394_IsoXmitIntMaskSet
);
2563 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, ~0);
2564 size
= sizeof(struct iso_context
) * hweight32(ohci
->ir_context_mask
);
2565 ohci
->ir_context_list
= kzalloc(size
, GFP_KERNEL
);
2567 if (ohci
->it_context_list
== NULL
|| ohci
->ir_context_list
== NULL
) {
2572 /* self-id dma buffer allocation */
2573 ohci
->self_id_cpu
= dma_alloc_coherent(ohci
->card
.device
,
2577 if (ohci
->self_id_cpu
== NULL
) {
2582 bus_options
= reg_read(ohci
, OHCI1394_BusOptions
);
2583 max_receive
= (bus_options
>> 12) & 0xf;
2584 link_speed
= bus_options
& 0x7;
2585 guid
= ((u64
) reg_read(ohci
, OHCI1394_GUIDHi
) << 32) |
2586 reg_read(ohci
, OHCI1394_GUIDLo
);
2588 err
= fw_card_add(&ohci
->card
, max_receive
, link_speed
, guid
);
2592 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2593 dev_name(&dev
->dev
), version
>> 16, version
& 0xff);
2598 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
2599 ohci
->self_id_cpu
, ohci
->self_id_bus
);
2601 kfree(ohci
->ir_context_list
);
2602 kfree(ohci
->it_context_list
);
2603 context_release(&ohci
->at_response_ctx
);
2604 context_release(&ohci
->at_request_ctx
);
2605 ar_context_release(&ohci
->ar_response_ctx
);
2606 ar_context_release(&ohci
->ar_request_ctx
);
2607 pci_iounmap(dev
, ohci
->registers
);
2609 pci_release_region(dev
, 0);
2611 pci_disable_device(dev
);
2617 fw_error("Out of memory\n");
2622 static void pci_remove(struct pci_dev
*dev
)
2624 struct fw_ohci
*ohci
;
2626 ohci
= pci_get_drvdata(dev
);
2627 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
2629 fw_core_remove_card(&ohci
->card
);
2632 * FIXME: Fail all pending packets here, now that the upper
2633 * layers can't queue any more.
2636 software_reset(ohci
);
2637 free_irq(dev
->irq
, ohci
);
2639 if (ohci
->next_config_rom
&& ohci
->next_config_rom
!= ohci
->config_rom
)
2640 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
2641 ohci
->next_config_rom
, ohci
->next_config_rom_bus
);
2642 if (ohci
->config_rom
)
2643 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
2644 ohci
->config_rom
, ohci
->config_rom_bus
);
2645 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
2646 ohci
->self_id_cpu
, ohci
->self_id_bus
);
2647 ar_context_release(&ohci
->ar_request_ctx
);
2648 ar_context_release(&ohci
->ar_response_ctx
);
2649 context_release(&ohci
->at_request_ctx
);
2650 context_release(&ohci
->at_response_ctx
);
2651 kfree(ohci
->it_context_list
);
2652 kfree(ohci
->ir_context_list
);
2653 pci_iounmap(dev
, ohci
->registers
);
2654 pci_release_region(dev
, 0);
2655 pci_disable_device(dev
);
2659 fw_notify("Removed fw-ohci device.\n");
2663 static int pci_suspend(struct pci_dev
*dev
, pm_message_t state
)
2665 struct fw_ohci
*ohci
= pci_get_drvdata(dev
);
2668 software_reset(ohci
);
2669 free_irq(dev
->irq
, ohci
);
2670 err
= pci_save_state(dev
);
2672 fw_error("pci_save_state failed\n");
2675 err
= pci_set_power_state(dev
, pci_choose_state(dev
, state
));
2677 fw_error("pci_set_power_state failed with %d\n", err
);
2683 static int pci_resume(struct pci_dev
*dev
)
2685 struct fw_ohci
*ohci
= pci_get_drvdata(dev
);
2689 pci_set_power_state(dev
, PCI_D0
);
2690 pci_restore_state(dev
);
2691 err
= pci_enable_device(dev
);
2693 fw_error("pci_enable_device failed\n");
2697 return ohci_enable(&ohci
->card
, NULL
, 0);
2701 static struct pci_device_id pci_table
[] = {
2702 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI
, ~0) },
2706 MODULE_DEVICE_TABLE(pci
, pci_table
);
2708 static struct pci_driver fw_ohci_pci_driver
= {
2709 .name
= ohci_driver_name
,
2710 .id_table
= pci_table
,
2712 .remove
= pci_remove
,
2714 .resume
= pci_resume
,
2715 .suspend
= pci_suspend
,
2719 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2720 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2721 MODULE_LICENSE("GPL");
2723 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2724 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2725 MODULE_ALIAS("ohci1394");
2728 static int __init
fw_ohci_init(void)
2730 return pci_register_driver(&fw_ohci_pci_driver
);
2733 static void __exit
fw_ohci_cleanup(void)
2735 pci_unregister_driver(&fw_ohci_pci_driver
);
2738 module_init(fw_ohci_init
);
2739 module_exit(fw_ohci_cleanup
);