arch/mips/mm/uasm.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * A small micro-assembler. It is intentionally kept simple, does only
   7  * support a subset of instructions, and does not try to hide pipeline
   8  * effects like branch delay slots.
   9  *
  10  * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
  11  * Copyright (C) 2005, 2007  Maciej W. Rozycki
  12  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/types.h>
  17 #include <linux/init.h>
  18
  19 #include <asm/inst.h>
  20 #include <asm/elf.h>
  21 #include <asm/bugs.h>
  22
  23 #include "uasm.h"
  24
  25 enum fields {
  26         RS = 0x001,
  27         RT = 0x002,
  28         RD = 0x004,
  29         RE = 0x008,
  30         SIMM = 0x010,
  31         UIMM = 0x020,
  32         BIMM = 0x040,
  33         JIMM = 0x080,
  34         FUNC = 0x100,
  35         SET = 0x200
  36 };
  37
  38 #define OP_MASK         0x3f
  39 #define OP_SH           26
  40 #define RS_MASK         0x1f
  41 #define RS_SH           21
  42 #define RT_MASK         0x1f
  43 #define RT_SH           16
  44 #define RD_MASK         0x1f
  45 #define RD_SH           11
  46 #define RE_MASK         0x1f
  47 #define RE_SH           6
  48 #define IMM_MASK        0xffff
  49 #define IMM_SH          0
  50 #define JIMM_MASK       0x3ffffff
  51 #define JIMM_SH         0
  52 #define FUNC_MASK       0x3f
  53 #define FUNC_SH         0
  54 #define SET_MASK        0x7
  55 #define SET_SH          0
  56
  57 enum opcode {
  58         insn_invalid,
  59         insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
  60         insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
  61         insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
  62         insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
  63         insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,
  64         insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
  65         insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
  66         insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
  67         insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins
  68 };
  69
  70 struct insn {
  71         enum opcode opcode;
  72         u32 match;
  73         enum fields fields;
  74 };
  75
  76 /* This macro sets the non-variable bits of an instruction. */
  77 #define M(a, b, c, d, e, f)                                     \
  78         ((a) << OP_SH                                           \
  79          | (b) << RS_SH                                         \
  80          | (c) << RT_SH                                         \
  81          | (d) << RD_SH                                         \
  82          | (e) << RE_SH                                         \
  83          | (f) << FUNC_SH)
  84
  85 static struct insn insn_table[] __cpuinitdata = {
  86         { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
  87         { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
  88         { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
  89         { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
  90         { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
  91         { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
  92         { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
  93         { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
  94         { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
  95         { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
  96         { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
  97         { insn_cache,  M(cache_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
  98         { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
  99         { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
 100         { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
 101         { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
 102         { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
 103         { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
 104         { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
 105         { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
 106         { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
 107         { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
 108         { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
 109         { insn_eret,  M(cop0_op, cop_op, 0, 0, 0, eret_op),  0 },
 110         { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
 111         { insn_jal,  M(jal_op, 0, 0, 0, 0, 0),  JIMM },
 112         { insn_jr,  M(spec_op, 0, 0, 0, 0, jr_op),  RS },
 113         { insn_ld,  M(ld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 114         { insn_ll,  M(ll_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 115         { insn_lld,  M(lld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 116         { insn_lui,  M(lui_op, 0, 0, 0, 0, 0),  RT | SIMM },
 117         { insn_lw,  M(lw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 118         { insn_mfc0,  M(cop0_op, mfc_op, 0, 0, 0, 0),  RT | RD | SET},
 119         { insn_mtc0,  M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},
 120         { insn_ori,  M(ori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
 121         { insn_pref,  M(pref_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 122         { insn_rfe,  M(cop0_op, cop_op, 0, 0, 0, rfe_op),  0 },
 123         { insn_sc,  M(sc_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 124         { insn_scd,  M(scd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 125         { insn_sd,  M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 126         { insn_sll,  M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE },
 127         { insn_sra,  M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE },
 128         { insn_srl,  M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE },
 129         { insn_subu,  M(spec_op, 0, 0, 0, 0, subu_op),  RS | RT | RD },
 130         { insn_sw,  M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 131         { insn_tlbp,  M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0 },
 132         { insn_tlbwi,  M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0 },
 133         { insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },
 134         { insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
 135         { insn_xori,  M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
 136         { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
 137         { insn_invalid, 0, 0 }
 138 };
 139
 140 #undef M
 141
 142 static inline __cpuinit u32 build_rs(u32 arg)
 143 {
 144         if (arg & ~RS_MASK)
 145                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 146
 147         return (arg & RS_MASK) << RS_SH;
 148 }
 149
 150 static inline __cpuinit u32 build_rt(u32 arg)
 151 {
 152         if (arg & ~RT_MASK)
 153                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 154
 155         return (arg & RT_MASK) << RT_SH;
 156 }
 157
 158 static inline __cpuinit u32 build_rd(u32 arg)
 159 {
 160         if (arg & ~RD_MASK)
 161                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 162
 163         return (arg & RD_MASK) << RD_SH;
 164 }
 165
 166 static inline __cpuinit u32 build_re(u32 arg)
 167 {
 168         if (arg & ~RE_MASK)
 169                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 170
 171         return (arg & RE_MASK) << RE_SH;
 172 }
 173
 174 static inline __cpuinit u32 build_simm(s32 arg)
 175 {
 176         if (arg > 0x7fff || arg < -0x8000)
 177                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 178
 179         return arg & 0xffff;
 180 }
 181
 182 static inline __cpuinit u32 build_uimm(u32 arg)
 183 {
 184         if (arg & ~IMM_MASK)
 185                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 186
 187         return arg & IMM_MASK;
 188 }
 189
 190 static inline __cpuinit u32 build_bimm(s32 arg)
 191 {
 192         if (arg > 0x1ffff || arg < -0x20000)
 193                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 194
 195         if (arg & 0x3)
 196                 printk(KERN_WARNING "Invalid micro-assembler branch target\n");
 197
 198         return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
 199 }
 200
 201 static inline __cpuinit u32 build_jimm(u32 arg)
 202 {
 203         if (arg & ~((JIMM_MASK) << 2))
 204                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 205
 206         return (arg >> 2) & JIMM_MASK;
 207 }
 208
 209 static inline __cpuinit u32 build_func(u32 arg)
 210 {
 211         if (arg & ~FUNC_MASK)
 212                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 213
 214         return arg & FUNC_MASK;
 215 }
 216
 217 static inline __cpuinit u32 build_set(u32 arg)
 218 {
 219         if (arg & ~SET_MASK)
 220                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 221
 222         return arg & SET_MASK;
 223 }
 224
 225 /*
 226  * The order of opcode arguments is implicitly left to right,
 227  * starting with RS and ending with FUNC or IMM.
 228  */
 229 static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...)
 230 {
 231         struct insn *ip = NULL;
 232         unsigned int i;
 233         va_list ap;
 234         u32 op;
 235
 236         for (i = 0; insn_table[i].opcode != insn_invalid; i++)
 237                 if (insn_table[i].opcode == opc) {
 238                         ip = &insn_table[i];
 239                         break;
 240                 }
 241
 242         if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
 243                 panic("Unsupported Micro-assembler instruction %d", opc);
 244
 245         op = ip->match;
 246         va_start(ap, opc);
 247         if (ip->fields & RS)
 248                 op |= build_rs(va_arg(ap, u32));
 249         if (ip->fields & RT)
 250                 op |= build_rt(va_arg(ap, u32));
 251         if (ip->fields & RD)
 252                 op |= build_rd(va_arg(ap, u32));
 253         if (ip->fields & RE)
 254                 op |= build_re(va_arg(ap, u32));
 255         if (ip->fields & SIMM)
 256                 op |= build_simm(va_arg(ap, s32));
 257         if (ip->fields & UIMM)
 258                 op |= build_uimm(va_arg(ap, u32));
 259         if (ip->fields & BIMM)
 260                 op |= build_bimm(va_arg(ap, s32));
 261         if (ip->fields & JIMM)
 262                 op |= build_jimm(va_arg(ap, u32));
 263         if (ip->fields & FUNC)
 264                 op |= build_func(va_arg(ap, u32));
 265         if (ip->fields & SET)
 266                 op |= build_set(va_arg(ap, u32));
 267         va_end(ap);
 268
 269         **buf = op;
 270         (*buf)++;
 271 }
 272
 273 #define I_u1u2u3(op)                                    \
 274 Ip_u1u2u3(op)                                           \
 275 {                                                       \
 276         build_insn(buf, insn##op, a, b, c);             \
 277 }
 278
 279 #define I_u2u1u3(op)                                    \
 280 Ip_u2u1u3(op)                                           \
 281 {                                                       \
 282         build_insn(buf, insn##op, b, a, c);             \
 283 }
 284
 285 #define I_u3u1u2(op)                                    \
 286 Ip_u3u1u2(op)                                           \
 287 {                                                       \
 288         build_insn(buf, insn##op, b, c, a);             \
 289 }
 290
 291 #define I_u1u2s3(op)                                    \
 292 Ip_u1u2s3(op)                                           \
 293 {                                                       \
 294         build_insn(buf, insn##op, a, b, c);             \
 295 }
 296
 297 #define I_u2s3u1(op)                                    \
 298 Ip_u2s3u1(op)                                           \
 299 {                                                       \
 300         build_insn(buf, insn##op, c, a, b);             \
 301 }
 302
 303 #define I_u2u1s3(op)                                    \
 304 Ip_u2u1s3(op)                                           \
 305 {                                                       \
 306         build_insn(buf, insn##op, b, a, c);             \
 307 }
 308
 309 #define I_u2u1msbu3(op)                                 \
 310 Ip_u2u1msbu3(op)                                        \
 311 {                                                       \
 312         build_insn(buf, insn##op, b, a, c+d-1, c);      \
 313 }
 314
 315 #define I_u1u2(op)                                      \
 316 Ip_u1u2(op)                                             \
 317 {                                                       \
 318         build_insn(buf, insn##op, a, b);                \
 319 }
 320
 321 #define I_u1s2(op)                                      \
 322 Ip_u1s2(op)                                             \
 323 {                                                       \
 324         build_insn(buf, insn##op, a, b);                \
 325 }
 326
 327 #define I_u1(op)                                        \
 328 Ip_u1(op)                                               \
 329 {                                                       \
 330         build_insn(buf, insn##op, a);                   \
 331 }
 332
 333 #define I_0(op)                                         \
 334 Ip_0(op)                                                \
 335 {                                                       \
 336         build_insn(buf, insn##op);                      \
 337 }
 338
 339 I_u2u1s3(_addiu)
 340 I_u3u1u2(_addu)
 341 I_u2u1u3(_andi)
 342 I_u3u1u2(_and)
 343 I_u1u2s3(_beq)
 344 I_u1u2s3(_beql)
 345 I_u1s2(_bgez)
 346 I_u1s2(_bgezl)
 347 I_u1s2(_bltz)
 348 I_u1s2(_bltzl)
 349 I_u1u2s3(_bne)
 350 I_u2s3u1(_cache)
 351 I_u1u2u3(_dmfc0)
 352 I_u1u2u3(_dmtc0)
 353 I_u2u1s3(_daddiu)
 354 I_u3u1u2(_daddu)
 355 I_u2u1u3(_dsll)
 356 I_u2u1u3(_dsll32)
 357 I_u2u1u3(_dsra)
 358 I_u2u1u3(_dsrl)
 359 I_u2u1u3(_dsrl32)
 360 I_u2u1u3(_drotr)
 361 I_u3u1u2(_dsubu)
 362 I_0(_eret)
 363 I_u1(_j)
 364 I_u1(_jal)
 365 I_u1(_jr)
 366 I_u2s3u1(_ld)
 367 I_u2s3u1(_ll)
 368 I_u2s3u1(_lld)
 369 I_u1s2(_lui)
 370 I_u2s3u1(_lw)
 371 I_u1u2u3(_mfc0)
 372 I_u1u2u3(_mtc0)
 373 I_u2u1u3(_ori)
 374 I_u2s3u1(_pref)
 375 I_0(_rfe)
 376 I_u2s3u1(_sc)
 377 I_u2s3u1(_scd)
 378 I_u2s3u1(_sd)
 379 I_u2u1u3(_sll)
 380 I_u2u1u3(_sra)
 381 I_u2u1u3(_srl)
 382 I_u3u1u2(_subu)
 383 I_u2s3u1(_sw)
 384 I_0(_tlbp)
 385 I_0(_tlbwi)
 386 I_0(_tlbwr)
 387 I_u3u1u2(_xor)
 388 I_u2u1u3(_xori)
 389 I_u2u1msbu3(_dins);
 390
 391 /* Handle labels. */
 392 void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
 393 {
 394         (*lab)->addr = addr;
 395         (*lab)->lab = lid;
 396         (*lab)++;
 397 }
 398
 399 int __cpuinit uasm_in_compat_space_p(long addr)
 400 {
 401         /* Is this address in 32bit compat space? */
 402 #ifdef CONFIG_64BIT
 403         return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
 404 #else
 405         return 1;
 406 #endif
 407 }
 408
 409 static int __cpuinit uasm_rel_highest(long val)
 410 {
 411 #ifdef CONFIG_64BIT
 412         return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
 413 #else
 414         return 0;
 415 #endif
 416 }
 417
 418 static int __cpuinit uasm_rel_higher(long val)
 419 {
 420 #ifdef CONFIG_64BIT
 421         return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
 422 #else
 423         return 0;
 424 #endif
 425 }
 426
 427 int __cpuinit uasm_rel_hi(long val)
 428 {
 429         return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
 430 }
 431
 432 int __cpuinit uasm_rel_lo(long val)
 433 {
 434         return ((val & 0xffff) ^ 0x8000) - 0x8000;
 435 }
 436
 437 void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
 438 {
 439         if (!uasm_in_compat_space_p(addr)) {
 440                 uasm_i_lui(buf, rs, uasm_rel_highest(addr));
 441                 if (uasm_rel_higher(addr))
 442                         uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
 443                 if (uasm_rel_hi(addr)) {
 444                         uasm_i_dsll(buf, rs, rs, 16);
 445                         uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr));
 446                         uasm_i_dsll(buf, rs, rs, 16);
 447                 } else
 448                         uasm_i_dsll32(buf, rs, rs, 0);
 449         } else
 450                 uasm_i_lui(buf, rs, uasm_rel_hi(addr));
 451 }
 452
 453 void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
 454 {
 455         UASM_i_LA_mostly(buf, rs, addr);
 456         if (uasm_rel_lo(addr)) {
 457                 if (!uasm_in_compat_space_p(addr))
 458                         uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr));
 459                 else
 460                         uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr));
 461         }
 462 }
 463
 464 /* Handle relocations. */
 465 void __cpuinit
 466 uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
 467 {
 468         (*rel)->addr = addr;
 469         (*rel)->type = R_MIPS_PC16;
 470         (*rel)->lab = lid;
 471         (*rel)++;
 472 }
 473
 474 static inline void __cpuinit
 475 __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
 476 {
 477         long laddr = (long)lab->addr;
 478         long raddr = (long)rel->addr;
 479
 480         switch (rel->type) {
 481         case R_MIPS_PC16:
 482                 *rel->addr |= build_bimm(laddr - (raddr + 4));
 483                 break;
 484
 485         default:
 486                 panic("Unsupported Micro-assembler relocation %d",
 487                       rel->type);
 488         }
 489 }
 490
 491 void __cpuinit
 492 uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
 493 {
 494         struct uasm_label *l;
 495
 496         for (; rel->lab != UASM_LABEL_INVALID; rel++)
 497                 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
 498                         if (rel->lab == l->lab)
 499                                 __resolve_relocs(rel, l);
 500 }
 501
 502 void __cpuinit
 503 uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off)
 504 {
 505         for (; rel->lab != UASM_LABEL_INVALID; rel++)
 506                 if (rel->addr >= first && rel->addr < end)
 507                         rel->addr += off;
 508 }
 509
 510 void __cpuinit
 511 uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off)
 512 {
 513         for (; lab->lab != UASM_LABEL_INVALID; lab++)
 514                 if (lab->addr >= first && lab->addr < end)
 515                         lab->addr += off;
 516 }
 517
 518 void __cpuinit
 519 uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
 520                   u32 *end, u32 *target)
 521 {
 522         long off = (long)(target - first);
 523
 524         memcpy(target, first, (end - first) * sizeof(u32));
 525
 526         uasm_move_relocs(rel, first, end, off);
 527         uasm_move_labels(lab, first, end, off);
 528 }
 529
 530 int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
 531 {
 532         for (; rel->lab != UASM_LABEL_INVALID; rel++) {
 533                 if (rel->addr == addr
 534                     && (rel->type == R_MIPS_PC16
 535                         || rel->type == R_MIPS_26))
 536                         return 1;
 537         }
 538
 539         return 0;
 540 }
 541
 542 /* Convenience functions for labeled branches. */
 543 void __cpuinit
 544 uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 545 {
 546         uasm_r_mips_pc16(r, *p, lid);
 547         uasm_i_bltz(p, reg, 0);
 548 }
 549
 550 void __cpuinit
 551 uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
 552 {
 553         uasm_r_mips_pc16(r, *p, lid);
 554         uasm_i_b(p, 0);
 555 }
 556
 557 void __cpuinit
 558 uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 559 {
 560         uasm_r_mips_pc16(r, *p, lid);
 561         uasm_i_beqz(p, reg, 0);
 562 }
 563
 564 void __cpuinit
 565 uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 566 {
 567         uasm_r_mips_pc16(r, *p, lid);
 568         uasm_i_beqzl(p, reg, 0);
 569 }
 570
 571 void __cpuinit
 572 uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
 573         unsigned int reg2, int lid)
 574 {
 575         uasm_r_mips_pc16(r, *p, lid);
 576         uasm_i_bne(p, reg1, reg2, 0);
 577 }
 578
 579 void __cpuinit
 580 uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 581 {
 582         uasm_r_mips_pc16(r, *p, lid);
 583         uasm_i_bnez(p, reg, 0);
 584 }
 585
 586 void __cpuinit
 587 uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 588 {
 589         uasm_r_mips_pc16(r, *p, lid);
 590         uasm_i_bgezl(p, reg, 0);
 591 }
 592
 593 void __cpuinit
 594 uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 595 {
 596         uasm_r_mips_pc16(r, *p, lid);
 597         uasm_i_bgez(p, reg, 0);
 598 }