3 Broadcom BCM43xx wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Stefano Brivio <st3@riseup.net>
7 Michael Buesch <mbuesch@freenet.de>
8 Danny van Dyk <kugelfang@gentoo.org>
9 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
34 #include "bcm43xx_main.h"
35 #include "bcm43xx_phy.h"
36 #include "bcm43xx_radio.h"
37 #include "bcm43xx_ilt.h"
40 /* Table for bcm43xx_radio_calibrationvalue() */
41 static const u16 rcc_table
[16] = {
42 0x0002, 0x0003, 0x0001, 0x000F,
43 0x0006, 0x0007, 0x0005, 0x000F,
44 0x000A, 0x000B, 0x0009, 0x000F,
45 0x000E, 0x000F, 0x000D, 0x000F,
48 /* Reverse the bits of a 4bit value.
49 * Example: 1101 is flipped 1011
51 static u16
flip_4bit(u16 value
)
55 assert((value
& ~0x000F) == 0x0000);
57 flipped
|= (value
& 0x0001) << 3;
58 flipped
|= (value
& 0x0002) << 1;
59 flipped
|= (value
& 0x0004) >> 1;
60 flipped
|= (value
& 0x0008) >> 3;
65 /* Get the freq, as it has to be written to the device. */
67 u16
channel2freq_bg(u8 channel
)
69 /* Frequencies are given as frequencies_bg[index] + 2.4GHz
70 * Starting with channel 1
72 static const u16 frequencies_bg
[14] = {
79 assert(channel
>= 1 && channel
<= 14);
81 return frequencies_bg
[channel
- 1];
84 /* Get the freq, as it has to be written to the device. */
86 u16
channel2freq_a(u8 channel
)
88 assert(channel
<= 200);
90 return (5000 + 5 * channel
);
93 void bcm43xx_radio_lock(struct bcm43xx_private
*bcm
)
97 status
= bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
);
98 status
|= BCM43xx_SBF_RADIOREG_LOCK
;
99 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
, status
);
103 void bcm43xx_radio_unlock(struct bcm43xx_private
*bcm
)
107 bcm43xx_read16(bcm
, BCM43xx_MMIO_PHY_VER
); /* dummy read */
108 status
= bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
);
109 status
&= ~BCM43xx_SBF_RADIOREG_LOCK
;
110 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
, status
);
113 u16
bcm43xx_radio_read16(struct bcm43xx_private
*bcm
, u16 offset
)
115 struct bcm43xx_phyinfo
*phy
= bcm
->current_core
->phy
;
116 struct bcm43xx_radioinfo
*radio
= bcm
->current_core
->radio
;
119 case BCM43xx_PHYTYPE_A
:
122 case BCM43xx_PHYTYPE_B
:
123 if (radio
->version
== 0x2053) {
126 else if (offset
< 0x80)
128 } else if (radio
->version
== 0x2050) {
133 case BCM43xx_PHYTYPE_G
:
138 bcm43xx_write16(bcm
, BCM43xx_MMIO_RADIO_CONTROL
, offset
);
139 return bcm43xx_read16(bcm
, BCM43xx_MMIO_RADIO_DATA_LOW
);
142 void bcm43xx_radio_write16(struct bcm43xx_private
*bcm
, u16 offset
, u16 val
)
144 bcm43xx_write16(bcm
, BCM43xx_MMIO_RADIO_CONTROL
, offset
);
145 bcm43xx_write16(bcm
, BCM43xx_MMIO_RADIO_DATA_LOW
, val
);
148 static void bcm43xx_set_all_gains(struct bcm43xx_private
*bcm
,
149 s16 first
, s16 second
, s16 third
)
151 struct bcm43xx_phyinfo
*phy
= bcm
->current_core
->phy
;
153 u16 start
= 0x08, end
= 0x18;
163 for (i
= 0; i
< 4; i
++)
164 bcm43xx_ilt_write16(bcm
, offset
+ i
, first
);
166 for (i
= start
; i
< end
; i
++)
167 bcm43xx_ilt_write16(bcm
, offset
+ i
, second
);
170 tmp
= ((u16
)third
<< 14) | ((u16
)third
<< 6);
171 bcm43xx_phy_write(bcm
, 0x04A0,
172 (bcm43xx_phy_read(bcm
, 0x04A0) & 0xBFBF) | tmp
);
173 bcm43xx_phy_write(bcm
, 0x04A1,
174 (bcm43xx_phy_read(bcm
, 0x04A1) & 0xBFBF) | tmp
);
175 bcm43xx_phy_write(bcm
, 0x04A2,
176 (bcm43xx_phy_read(bcm
, 0x04A2) & 0xBFBF) | tmp
);
178 bcm43xx_dummy_transmission(bcm
);
181 static void bcm43xx_set_original_gains(struct bcm43xx_private
*bcm
)
183 struct bcm43xx_phyinfo
*phy
= bcm
->current_core
->phy
;
186 u16 start
= 0x0008, end
= 0x0018;
194 for (i
= 0; i
< 4; i
++) {
196 tmp
|= (i
& 0x0001) << 1;
197 tmp
|= (i
& 0x0002) >> 1;
199 bcm43xx_ilt_write16(bcm
, offset
+ i
, tmp
);
202 for (i
= start
; i
< end
; i
++)
203 bcm43xx_ilt_write16(bcm
, offset
+ i
, i
- start
);
205 bcm43xx_phy_write(bcm
, 0x04A0,
206 (bcm43xx_phy_read(bcm
, 0x04A0) & 0xBFBF) | 0x4040);
207 bcm43xx_phy_write(bcm
, 0x04A1,
208 (bcm43xx_phy_read(bcm
, 0x04A1) & 0xBFBF) | 0x4040);
209 bcm43xx_phy_write(bcm
, 0x04A2,
210 (bcm43xx_phy_read(bcm
, 0x04A2) & 0xBFBF) | 0x4000);
211 bcm43xx_dummy_transmission(bcm
);
214 /* Synthetic PU workaround */
215 static void bcm43xx_synth_pu_workaround(struct bcm43xx_private
*bcm
, u8 channel
)
217 struct bcm43xx_radioinfo
*radio
= bcm
->current_core
->radio
;
219 if (radio
->version
!= 0x2050 || radio
->revision
>= 6) {
220 /* We do not need the workaround. */
225 bcm43xx_write16(bcm
, BCM43xx_MMIO_CHANNEL
,
226 channel2freq_bg(channel
+ 4));
228 bcm43xx_write16(bcm
, BCM43xx_MMIO_CHANNEL
,
232 bcm43xx_write16(bcm
, BCM43xx_MMIO_CHANNEL
,
233 channel2freq_bg(channel
));
236 u8
bcm43xx_radio_aci_detect(struct bcm43xx_private
*bcm
, u8 channel
)
238 struct bcm43xx_radioinfo
*radio
= bcm
->current_core
->radio
;
240 u16 saved
, rssi
, temp
;
243 saved
= bcm43xx_phy_read(bcm
, 0x0403);
244 bcm43xx_radio_selectchannel(bcm
, channel
, 0);
245 bcm43xx_phy_write(bcm
, 0x0403, (saved
& 0xFFF8) | 5);
246 if (radio
->aci_hw_rssi
)
247 rssi
= bcm43xx_phy_read(bcm
, 0x048A) & 0x3F;
250 /* clamp temp to signed 5bit */
253 for (i
= 0;i
< 100; i
++) {
254 temp
= (bcm43xx_phy_read(bcm
, 0x047F) >> 8) & 0x3F;
262 bcm43xx_phy_write(bcm
, 0x0403, saved
);
267 u8
bcm43xx_radio_aci_scan(struct bcm43xx_private
*bcm
)
269 struct bcm43xx_phyinfo
*phy
= bcm
->current_core
->phy
;
270 struct bcm43xx_radioinfo
*radio
= bcm
->current_core
->radio
;
272 unsigned int channel
= radio
->channel
;
273 unsigned int i
, j
, start
, end
;
274 unsigned long phylock_flags
;
276 if (!((phy
->type
== BCM43xx_PHYTYPE_G
) && (phy
->rev
> 0)))
279 bcm43xx_phy_lock(bcm
, phylock_flags
);
280 bcm43xx_radio_lock(bcm
);
281 bcm43xx_phy_write(bcm
, 0x0802,
282 bcm43xx_phy_read(bcm
, 0x0802) & 0xFFFC);
283 bcm43xx_phy_write(bcm
, BCM43xx_PHY_G_CRS
,
284 bcm43xx_phy_read(bcm
, BCM43xx_PHY_G_CRS
) & 0x7FFF);
285 bcm43xx_set_all_gains(bcm
, 3, 8, 1);
287 start
= (channel
- 5 > 0) ? channel
- 5 : 1;
288 end
= (channel
+ 5 < 14) ? channel
+ 5 : 13;
290 for (i
= start
; i
<= end
; i
++) {
291 if (abs(channel
- i
) > 2)
292 ret
[i
-1] = bcm43xx_radio_aci_detect(bcm
, i
);
294 bcm43xx_radio_selectchannel(bcm
, channel
, 0);
295 bcm43xx_phy_write(bcm
, 0x0802,
296 (bcm43xx_phy_read(bcm
, 0x0802) & 0xFFFC) | 0x0003);
297 bcm43xx_phy_write(bcm
, 0x0403,
298 bcm43xx_phy_read(bcm
, 0x0403) & 0xFFF8);
299 bcm43xx_phy_write(bcm
, BCM43xx_PHY_G_CRS
,
300 bcm43xx_phy_read(bcm
, BCM43xx_PHY_G_CRS
) | 0x8000);
301 bcm43xx_set_original_gains(bcm
);
302 for (i
= 0; i
< 13; i
++) {
305 end
= (i
+ 5 < 13) ? i
+ 5 : 13;
306 for (j
= i
; j
< end
; j
++)
309 bcm43xx_radio_unlock(bcm
);
310 bcm43xx_phy_unlock(bcm
, phylock_flags
);
312 return ret
[channel
- 1];
315 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
316 void bcm43xx_nrssi_hw_write(struct bcm43xx_private
*bcm
, u16 offset
, s16 val
)
318 bcm43xx_phy_write(bcm
, BCM43xx_PHY_NRSSILT_CTRL
, offset
);
319 bcm43xx_phy_write(bcm
, BCM43xx_PHY_NRSSILT_DATA
, (u16
)val
);
322 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
323 s16
bcm43xx_nrssi_hw_read(struct bcm43xx_private
*bcm
, u16 offset
)
327 bcm43xx_phy_write(bcm
, BCM43xx_PHY_NRSSILT_CTRL
, offset
);
328 val
= bcm43xx_phy_read(bcm
, BCM43xx_PHY_NRSSILT_DATA
);
333 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
334 void bcm43xx_nrssi_hw_update(struct bcm43xx_private
*bcm
, u16 val
)
339 for (i
= 0; i
< 64; i
++) {
340 tmp
= bcm43xx_nrssi_hw_read(bcm
, i
);
342 tmp
= limit_value(tmp
, -32, 31);
343 bcm43xx_nrssi_hw_write(bcm
, i
, tmp
);
347 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
348 void bcm43xx_nrssi_mem_update(struct bcm43xx_private
*bcm
)
353 delta
= 0x1F - bcm
->current_core
->radio
->nrssi
[0];
354 for (i
= 0; i
< 64; i
++) {
355 tmp
= (i
- delta
) * bcm
->current_core
->radio
->nrssislope
;
358 tmp
= limit_value(tmp
, 0, 0x3F);
359 bcm
->current_core
->radio
->nrssi_lt
[i
] = tmp
;
363 static void bcm43xx_calc_nrssi_offset(struct bcm43xx_private
*bcm
)
365 struct bcm43xx_phyinfo
*phy
= bcm
->current_core
->phy
;
366 u16 backup
[20] = { 0 };
371 backup
[0] = bcm43xx_phy_read(bcm
, 0x0001);
372 backup
[1] = bcm43xx_phy_read(bcm
, 0x0811);
373 backup
[2] = bcm43xx_phy_read(bcm
, 0x0812);
374 backup
[3] = bcm43xx_phy_read(bcm
, 0x0814);
375 backup
[4] = bcm43xx_phy_read(bcm
, 0x0815);
376 backup
[5] = bcm43xx_phy_read(bcm
, 0x005A);
377 backup
[6] = bcm43xx_phy_read(bcm
, 0x0059);
378 backup
[7] = bcm43xx_phy_read(bcm
, 0x0058);
379 backup
[8] = bcm43xx_phy_read(bcm
, 0x000A);
380 backup
[9] = bcm43xx_phy_read(bcm
, 0x0003);
381 backup
[10] = bcm43xx_radio_read16(bcm
, 0x007A);
382 backup
[11] = bcm43xx_radio_read16(bcm
, 0x0043);
384 bcm43xx_phy_write(bcm
, 0x0429,
385 bcm43xx_phy_read(bcm
, 0x0429) & 0x7FFF);
386 bcm43xx_phy_write(bcm
, 0x0001,
387 (bcm43xx_phy_read(bcm
, 0x0001) & 0x3FFF) | 0x4000);
388 bcm43xx_phy_write(bcm
, 0x0811,
389 bcm43xx_phy_read(bcm
, 0x0811) | 0x000C);
390 bcm43xx_phy_write(bcm
, 0x0812,
391 (bcm43xx_phy_read(bcm
, 0x0812) & 0xFFF3) | 0x0004);
392 bcm43xx_phy_write(bcm
, 0x0802,
393 bcm43xx_phy_read(bcm
, 0x0802) & ~(0x1 | 0x2));
395 backup
[12] = bcm43xx_phy_read(bcm
, 0x002E);
396 backup
[13] = bcm43xx_phy_read(bcm
, 0x002F);
397 backup
[14] = bcm43xx_phy_read(bcm
, 0x080F);
398 backup
[15] = bcm43xx_phy_read(bcm
, 0x0810);
399 backup
[16] = bcm43xx_phy_read(bcm
, 0x0801);
400 backup
[17] = bcm43xx_phy_read(bcm
, 0x0060);
401 backup
[18] = bcm43xx_phy_read(bcm
, 0x0014);
402 backup
[19] = bcm43xx_phy_read(bcm
, 0x0478);
404 bcm43xx_phy_write(bcm
, 0x002E, 0);
405 bcm43xx_phy_write(bcm
, 0x002F, 0);
406 bcm43xx_phy_write(bcm
, 0x080F, 0);
407 bcm43xx_phy_write(bcm
, 0x0810, 0);
408 bcm43xx_phy_write(bcm
, 0x0478,
409 bcm43xx_phy_read(bcm
, 0x0478) | 0x0100);
410 bcm43xx_phy_write(bcm
, 0x0801,
411 bcm43xx_phy_read(bcm
, 0x0801) | 0x0040);
412 bcm43xx_phy_write(bcm
, 0x0060,
413 bcm43xx_phy_read(bcm
, 0x0060) | 0x0040);
414 bcm43xx_phy_write(bcm
, 0x0014,
415 bcm43xx_phy_read(bcm
, 0x0014) | 0x0200);
417 bcm43xx_radio_write16(bcm
, 0x007A,
418 bcm43xx_radio_read16(bcm
, 0x007A) | 0x0070);
419 bcm43xx_radio_write16(bcm
, 0x007A,
420 bcm43xx_radio_read16(bcm
, 0x007A) | 0x0080);
423 v47F
= (s16
)((bcm43xx_phy_read(bcm
, 0x047F) >> 8) & 0x003F);
427 for (i
= 7; i
>= 4; i
--) {
428 bcm43xx_radio_write16(bcm
, 0x007B, i
);
430 v47F
= (s16
)((bcm43xx_phy_read(bcm
, 0x047F) >> 8) & 0x003F);
433 if (v47F
< 31 && saved
== 0xFFFF)
439 bcm43xx_radio_write16(bcm
, 0x007A,
440 bcm43xx_radio_read16(bcm
, 0x007A) & 0x007F);
441 bcm43xx_phy_write(bcm
, 0x0814,
442 bcm43xx_phy_read(bcm
, 0x0814) | 0x0001);
443 bcm43xx_phy_write(bcm
, 0x0815,
444 bcm43xx_phy_read(bcm
, 0x0815) & 0xFFFE);
445 bcm43xx_phy_write(bcm
, 0x0811,
446 bcm43xx_phy_read(bcm
, 0x0811) | 0x000C);
447 bcm43xx_phy_write(bcm
, 0x0812,
448 bcm43xx_phy_read(bcm
, 0x0812) | 0x000C);
449 bcm43xx_phy_write(bcm
, 0x0811,
450 bcm43xx_phy_read(bcm
, 0x0811) | 0x0030);
451 bcm43xx_phy_write(bcm
, 0x0812,
452 bcm43xx_phy_read(bcm
, 0x0812) | 0x0030);
453 bcm43xx_phy_write(bcm
, 0x005A, 0x0480);
454 bcm43xx_phy_write(bcm
, 0x0059, 0x0810);
455 bcm43xx_phy_write(bcm
, 0x0058, 0x000D);
457 bcm43xx_phy_write(bcm
, 0x0003, 0x0122);
459 bcm43xx_phy_write(bcm
, 0x000A,
460 bcm43xx_phy_read(bcm
, 0x000A)
463 bcm43xx_phy_write(bcm
, 0x0814,
464 bcm43xx_phy_read(bcm
, 0x0814) | 0x0004);
465 bcm43xx_phy_write(bcm
, 0x0815,
466 bcm43xx_phy_read(bcm
, 0x0815) & 0xFFFB);
467 bcm43xx_phy_write(bcm
, 0x0003,
468 (bcm43xx_phy_read(bcm
, 0x0003) & 0xFF9F)
470 bcm43xx_radio_write16(bcm
, 0x007A,
471 bcm43xx_radio_read16(bcm
, 0x007A) | 0x000F);
472 bcm43xx_set_all_gains(bcm
, 3, 0, 1);
473 bcm43xx_radio_write16(bcm
, 0x0043,
474 (bcm43xx_radio_read16(bcm
, 0x0043)
477 v47F
= (s16
)((bcm43xx_phy_read(bcm
, 0x047F) >> 8) & 0x003F);
481 for (i
= 0; i
< 4; i
++) {
482 bcm43xx_radio_write16(bcm
, 0x007B, i
);
484 v47F
= (s16
)((bcm43xx_phy_read(bcm
, 0x047F) >> 8) & 0x003F);
487 if (v47F
> -31 && saved
== 0xFFFF)
495 bcm43xx_radio_write16(bcm
, 0x007B, saved
);
498 bcm43xx_phy_write(bcm
, 0x002E, backup
[12]);
499 bcm43xx_phy_write(bcm
, 0x002F, backup
[13]);
500 bcm43xx_phy_write(bcm
, 0x080F, backup
[14]);
501 bcm43xx_phy_write(bcm
, 0x0810, backup
[15]);
503 bcm43xx_phy_write(bcm
, 0x0814, backup
[3]);
504 bcm43xx_phy_write(bcm
, 0x0815, backup
[4]);
505 bcm43xx_phy_write(bcm
, 0x005A, backup
[5]);
506 bcm43xx_phy_write(bcm
, 0x0059, backup
[6]);
507 bcm43xx_phy_write(bcm
, 0x0058, backup
[7]);
508 bcm43xx_phy_write(bcm
, 0x000A, backup
[8]);
509 bcm43xx_phy_write(bcm
, 0x0003, backup
[9]);
510 bcm43xx_radio_write16(bcm
, 0x0043, backup
[11]);
511 bcm43xx_radio_write16(bcm
, 0x007A, backup
[10]);
512 bcm43xx_phy_write(bcm
, 0x0802,
513 bcm43xx_phy_read(bcm
, 0x0802) | 0x1 | 0x2);
514 bcm43xx_phy_write(bcm
, 0x0429,
515 bcm43xx_phy_read(bcm
, 0x0429) | 0x8000);
516 bcm43xx_set_original_gains(bcm
);
518 bcm43xx_phy_write(bcm
, 0x0801, backup
[16]);
519 bcm43xx_phy_write(bcm
, 0x0060, backup
[17]);
520 bcm43xx_phy_write(bcm
, 0x0014, backup
[18]);
521 bcm43xx_phy_write(bcm
, 0x0478, backup
[19]);
523 bcm43xx_phy_write(bcm
, 0x0001, backup
[0]);
524 bcm43xx_phy_write(bcm
, 0x0812, backup
[2]);
525 bcm43xx_phy_write(bcm
, 0x0811, backup
[1]);
528 void bcm43xx_calc_nrssi_slope(struct bcm43xx_private
*bcm
)
530 struct bcm43xx_phyinfo
*phy
= bcm
->current_core
->phy
;
531 struct bcm43xx_radioinfo
*radio
= bcm
->current_core
->radio
;
532 u16 backup
[18] = { 0 };
537 case BCM43xx_PHYTYPE_B
:
538 backup
[0] = bcm43xx_radio_read16(bcm
, 0x007A);
539 backup
[1] = bcm43xx_radio_read16(bcm
, 0x0052);
540 backup
[2] = bcm43xx_radio_read16(bcm
, 0x0043);
541 backup
[3] = bcm43xx_phy_read(bcm
, 0x0030);
542 backup
[4] = bcm43xx_phy_read(bcm
, 0x0026);
543 backup
[5] = bcm43xx_phy_read(bcm
, 0x0015);
544 backup
[6] = bcm43xx_phy_read(bcm
, 0x002A);
545 backup
[7] = bcm43xx_phy_read(bcm
, 0x0020);
546 backup
[8] = bcm43xx_phy_read(bcm
, 0x005A);
547 backup
[9] = bcm43xx_phy_read(bcm
, 0x0059);
548 backup
[10] = bcm43xx_phy_read(bcm
, 0x0058);
549 backup
[11] = bcm43xx_read16(bcm
, 0x03E2);
550 backup
[12] = bcm43xx_read16(bcm
, 0x03E6);
551 backup
[13] = bcm43xx_read16(bcm
, BCM43xx_MMIO_CHANNEL_EXT
);
553 tmp
= bcm43xx_radio_read16(bcm
, 0x007A);
554 tmp
&= (phy
->rev
>= 5) ? 0x007F : 0x000F;
555 bcm43xx_radio_write16(bcm
, 0x007A, tmp
);
556 bcm43xx_phy_write(bcm
, 0x0030, 0x00FF);
557 bcm43xx_write16(bcm
, 0x03EC, 0x7F7F);
558 bcm43xx_phy_write(bcm
, 0x0026, 0x0000);
559 bcm43xx_phy_write(bcm
, 0x0015,
560 bcm43xx_phy_read(bcm
, 0x0015) | 0x0020);
561 bcm43xx_phy_write(bcm
, 0x002A, 0x08A3);
562 bcm43xx_radio_write16(bcm
, 0x007A,
563 bcm43xx_radio_read16(bcm
, 0x007A) | 0x0080);
565 nrssi0
= (s16
)bcm43xx_phy_read(bcm
, 0x0027);
566 bcm43xx_radio_write16(bcm
, 0x007A,
567 bcm43xx_radio_read16(bcm
, 0x007A) & 0x007F);
569 bcm43xx_write16(bcm
, 0x03E6, 0x0040);
570 } else if (phy
->rev
== 0) {
571 bcm43xx_write16(bcm
, 0x03E6, 0x0122);
573 bcm43xx_write16(bcm
, BCM43xx_MMIO_CHANNEL_EXT
,
574 bcm43xx_read16(bcm
, BCM43xx_MMIO_CHANNEL_EXT
) & 0x2000);
576 bcm43xx_phy_write(bcm
, 0x0020, 0x3F3F);
577 bcm43xx_phy_write(bcm
, 0x0015, 0xF330);
578 bcm43xx_radio_write16(bcm
, 0x005A, 0x0060);
579 bcm43xx_radio_write16(bcm
, 0x0043,
580 bcm43xx_radio_read16(bcm
, 0x0043) & 0x00F0);
581 bcm43xx_phy_write(bcm
, 0x005A, 0x0480);
582 bcm43xx_phy_write(bcm
, 0x0059, 0x0810);
583 bcm43xx_phy_write(bcm
, 0x0058, 0x000D);
586 nrssi1
= (s16
)bcm43xx_phy_read(bcm
, 0x0027);
587 bcm43xx_phy_write(bcm
, 0x0030, backup
[3]);
588 bcm43xx_radio_write16(bcm
, 0x007A, backup
[0]);
589 bcm43xx_write16(bcm
, 0x03E2, backup
[11]);
590 bcm43xx_phy_write(bcm
, 0x0026, backup
[4]);
591 bcm43xx_phy_write(bcm
, 0x0015, backup
[5]);
592 bcm43xx_phy_write(bcm
, 0x002A, backup
[6]);
593 bcm43xx_synth_pu_workaround(bcm
, radio
->channel
);
595 bcm43xx_write16(bcm
, 0x03F4, backup
[13]);
597 bcm43xx_phy_write(bcm
, 0x0020, backup
[7]);
598 bcm43xx_phy_write(bcm
, 0x005A, backup
[8]);
599 bcm43xx_phy_write(bcm
, 0x0059, backup
[9]);
600 bcm43xx_phy_write(bcm
, 0x0058, backup
[10]);
601 bcm43xx_radio_write16(bcm
, 0x0052, backup
[1]);
602 bcm43xx_radio_write16(bcm
, 0x0043, backup
[2]);
604 if (nrssi0
== nrssi1
)
605 radio
->nrssislope
= 0x00010000;
607 radio
->nrssislope
= 0x00400000 / (nrssi0
- nrssi1
);
610 radio
->nrssi
[0] = nrssi0
;
611 radio
->nrssi
[1] = nrssi1
;
614 case BCM43xx_PHYTYPE_G
:
615 //FIXME: Something is broken here. This is called when enabling WLAN interfmode.
616 // If this is done at runtime, I get an XMIT ERROR and transmission is
617 // broken. I guess some important register is overwritten by accident.
618 // The XMIT ERROR comes from the dummy_transmissions in set_gains.
619 if (radio
->revision
>= 9)
621 if (radio
->revision
== 8)
622 bcm43xx_calc_nrssi_offset(bcm
);
624 bcm43xx_phy_write(bcm
, BCM43xx_PHY_G_CRS
,
625 bcm43xx_phy_read(bcm
, BCM43xx_PHY_G_CRS
) & 0x7FFF);
626 bcm43xx_phy_write(bcm
, 0x0802,
627 bcm43xx_phy_read(bcm
, 0x0802) & 0xFFFC);
628 backup
[7] = bcm43xx_read16(bcm
, 0x03E2);
629 bcm43xx_write16(bcm
, 0x03E2,
630 bcm43xx_read16(bcm
, 0x03E2) | 0x8000);
631 backup
[0] = bcm43xx_radio_read16(bcm
, 0x007A);
632 backup
[1] = bcm43xx_radio_read16(bcm
, 0x0052);
633 backup
[2] = bcm43xx_radio_read16(bcm
, 0x0043);
634 backup
[3] = bcm43xx_phy_read(bcm
, 0x0015);
635 backup
[4] = bcm43xx_phy_read(bcm
, 0x005A);
636 backup
[5] = bcm43xx_phy_read(bcm
, 0x0059);
637 backup
[6] = bcm43xx_phy_read(bcm
, 0x0058);
638 backup
[8] = bcm43xx_read16(bcm
, 0x03E6);
639 backup
[9] = bcm43xx_read16(bcm
, BCM43xx_MMIO_CHANNEL_EXT
);
641 backup
[10] = bcm43xx_phy_read(bcm
, 0x002E);
642 backup
[11] = bcm43xx_phy_read(bcm
, 0x002F);
643 backup
[12] = bcm43xx_phy_read(bcm
, 0x080F);
644 backup
[13] = bcm43xx_phy_read(bcm
, BCM43xx_PHY_G_LO_CONTROL
);
645 backup
[14] = bcm43xx_phy_read(bcm
, 0x0801);
646 backup
[15] = bcm43xx_phy_read(bcm
, 0x0060);
647 backup
[16] = bcm43xx_phy_read(bcm
, 0x0014);
648 backup
[17] = bcm43xx_phy_read(bcm
, 0x0478);
649 bcm43xx_phy_write(bcm
, 0x002E, 0);
650 bcm43xx_phy_write(bcm
, BCM43xx_PHY_G_LO_CONTROL
, 0);
652 case 4: case 6: case 7:
653 bcm43xx_phy_write(bcm
, 0x0478,
654 bcm43xx_phy_read(bcm
, 0x0478)
656 bcm43xx_phy_write(bcm
, 0x0801,
657 bcm43xx_phy_read(bcm
, 0x0801)
661 bcm43xx_phy_write(bcm
, 0x0801,
662 bcm43xx_phy_read(bcm
, 0x0801)
666 bcm43xx_phy_write(bcm
, 0x0060,
667 bcm43xx_phy_read(bcm
, 0x0060)
669 bcm43xx_phy_write(bcm
, 0x0014,
670 bcm43xx_phy_read(bcm
, 0x0014)
673 bcm43xx_radio_write16(bcm
, 0x007A,
674 bcm43xx_radio_read16(bcm
, 0x007A) | 0x0070);
675 bcm43xx_set_all_gains(bcm
, 0, 8, 0);
676 bcm43xx_radio_write16(bcm
, 0x007A,
677 bcm43xx_radio_read16(bcm
, 0x007A) & 0x00F7);
679 bcm43xx_phy_write(bcm
, 0x0811,
680 (bcm43xx_phy_read(bcm
, 0x0811) & 0xFFCF) | 0x0030);
681 bcm43xx_phy_write(bcm
, 0x0812,
682 (bcm43xx_phy_read(bcm
, 0x0812) & 0xFFCF) | 0x0010);
684 bcm43xx_radio_write16(bcm
, 0x007A,
685 bcm43xx_radio_read16(bcm
, 0x007A) | 0x0080);
688 nrssi0
= (s16
)((bcm43xx_phy_read(bcm
, 0x047F) >> 8) & 0x003F);
689 if (nrssi0
>= 0x0020)
692 bcm43xx_radio_write16(bcm
, 0x007A,
693 bcm43xx_radio_read16(bcm
, 0x007A) & 0x007F);
695 bcm43xx_phy_write(bcm
, 0x0003,
696 (bcm43xx_phy_read(bcm
, 0x0003)
700 bcm43xx_write16(bcm
, BCM43xx_MMIO_CHANNEL_EXT
,
701 bcm43xx_read16(bcm
, BCM43xx_MMIO_CHANNEL_EXT
)
703 bcm43xx_radio_write16(bcm
, 0x007A,
704 bcm43xx_radio_read16(bcm
, 0x007A) | 0x000F);
705 bcm43xx_phy_write(bcm
, 0x0015, 0xF330);
707 bcm43xx_phy_write(bcm
, 0x0812,
708 (bcm43xx_phy_read(bcm
, 0x0812) & 0xFFCF) | 0x0020);
709 bcm43xx_phy_write(bcm
, 0x0811,
710 (bcm43xx_phy_read(bcm
, 0x0811) & 0xFFCF) | 0x0020);
713 bcm43xx_set_all_gains(bcm
, 3, 0, 1);
714 if (radio
->revision
== 8) {
715 bcm43xx_radio_write16(bcm
, 0x0043, 0x001F);
717 tmp
= bcm43xx_radio_read16(bcm
, 0x0052) & 0xFF0F;
718 bcm43xx_radio_write16(bcm
, 0x0052, tmp
| 0x0060);
719 tmp
= bcm43xx_radio_read16(bcm
, 0x0043) & 0xFFF0;
720 bcm43xx_radio_write16(bcm
, 0x0043, tmp
| 0x0009);
722 bcm43xx_phy_write(bcm
, 0x005A, 0x0480);
723 bcm43xx_phy_write(bcm
, 0x0059, 0x0810);
724 bcm43xx_phy_write(bcm
, 0x0058, 0x000D);
726 nrssi1
= (s16
)((bcm43xx_phy_read(bcm
, 0x047F) >> 8) & 0x003F);
727 if (nrssi1
>= 0x0020)
729 if (nrssi0
== nrssi1
)
730 radio
->nrssislope
= 0x00010000;
732 radio
->nrssislope
= 0x00400000 / (nrssi0
- nrssi1
);
734 radio
->nrssi
[0] = nrssi1
;
735 radio
->nrssi
[1] = nrssi0
;
738 bcm43xx_phy_write(bcm
, 0x002E, backup
[10]);
739 bcm43xx_phy_write(bcm
, 0x002F, backup
[11]);
740 bcm43xx_phy_write(bcm
, 0x080F, backup
[12]);
741 bcm43xx_phy_write(bcm
, BCM43xx_PHY_G_LO_CONTROL
, backup
[13]);
744 bcm43xx_phy_write(bcm
, 0x0812,
745 bcm43xx_phy_read(bcm
, 0x0812) & 0xFFCF);
746 bcm43xx_phy_write(bcm
, 0x0811,
747 bcm43xx_phy_read(bcm
, 0x0811) & 0xFFCF);
750 bcm43xx_radio_write16(bcm
, 0x007A, backup
[0]);
751 bcm43xx_radio_write16(bcm
, 0x0052, backup
[1]);
752 bcm43xx_radio_write16(bcm
, 0x0043, backup
[2]);
753 bcm43xx_write16(bcm
, 0x03E2, backup
[7]);
754 bcm43xx_write16(bcm
, 0x03E6, backup
[8]);
755 bcm43xx_write16(bcm
, BCM43xx_MMIO_CHANNEL_EXT
, backup
[9]);
756 bcm43xx_phy_write(bcm
, 0x0015, backup
[3]);
757 bcm43xx_phy_write(bcm
, 0x005A, backup
[4]);
758 bcm43xx_phy_write(bcm
, 0x0059, backup
[5]);
759 bcm43xx_phy_write(bcm
, 0x0058, backup
[6]);
760 bcm43xx_synth_pu_workaround(bcm
, radio
->channel
);
761 bcm43xx_phy_write(bcm
, 0x0802,
762 bcm43xx_phy_read(bcm
, 0x0802) | (0x0001 | 0x0002));
763 bcm43xx_set_original_gains(bcm
);
764 bcm43xx_phy_write(bcm
, BCM43xx_PHY_G_CRS
,
765 bcm43xx_phy_read(bcm
, BCM43xx_PHY_G_CRS
) | 0x8000);
767 bcm43xx_phy_write(bcm
, 0x0801, backup
[14]);
768 bcm43xx_phy_write(bcm
, 0x0060, backup
[15]);
769 bcm43xx_phy_write(bcm
, 0x0014, backup
[16]);
770 bcm43xx_phy_write(bcm
, 0x0478, backup
[17]);
772 bcm43xx_nrssi_mem_update(bcm
);
773 bcm43xx_calc_nrssi_threshold(bcm
);
780 void bcm43xx_calc_nrssi_threshold(struct bcm43xx_private
*bcm
)
782 struct bcm43xx_phyinfo
*phy
= bcm
->current_core
->phy
;
783 struct bcm43xx_radioinfo
*radio
= bcm
->current_core
->radio
;
791 case BCM43xx_PHYTYPE_B
: {
796 if (radio
->version
!= 0x2050)
798 if (!(bcm
->sprom
.boardflags
& BCM43xx_BFL_RSSI
))
801 tmp
= radio
->revision
;
802 if ((radio
->manufact
== 0x175 && tmp
== 5) ||
803 (radio
->manufact
== 0x17F && (tmp
== 3 || tmp
== 4)))
806 if (radiotype
== 1) {
807 threshold
= bcm
->current_core
->radio
->nrssi
[1] - 5;
809 threshold
= 40 * radio
->nrssi
[0];
810 threshold
+= 33 * (radio
->nrssi
[1] - radio
->nrssi
[0]);
814 threshold
= limit_value(threshold
, 0, 0x3E);
815 bcm43xx_phy_read(bcm
, 0x0020); /* dummy read */
816 bcm43xx_phy_write(bcm
, 0x0020, (((u16
)threshold
) << 8) | 0x001C);
818 if (radiotype
== 1) {
819 bcm43xx_phy_write(bcm
, 0x0087, 0x0E0D);
820 bcm43xx_phy_write(bcm
, 0x0086, 0x0C0B);
821 bcm43xx_phy_write(bcm
, 0x0085, 0x0A09);
822 bcm43xx_phy_write(bcm
, 0x0084, 0x0808);
823 bcm43xx_phy_write(bcm
, 0x0083, 0x0808);
824 bcm43xx_phy_write(bcm
, 0x0082, 0x0604);
825 bcm43xx_phy_write(bcm
, 0x0081, 0x0302);
826 bcm43xx_phy_write(bcm
, 0x0080, 0x0100);
830 case BCM43xx_PHYTYPE_G
:
831 if (!phy
->connected
||
832 !(bcm
->sprom
.boardflags
& BCM43xx_BFL_RSSI
)) {
833 tmp16
= bcm43xx_nrssi_hw_read(bcm
, 0x20);
837 bcm43xx_phy_write(bcm
, 0x048A,
838 (bcm43xx_phy_read(bcm
, 0x048A)
841 bcm43xx_phy_write(bcm
, 0x048A,
842 (bcm43xx_phy_read(bcm
, 0x048A)
846 tmp
= radio
->interfmode
;
847 if (tmp
== BCM43xx_RADIO_INTERFMODE_NONWLAN
) {
850 } else if (tmp
== BCM43xx_RADIO_INTERFMODE_NONE
&&
851 !radio
->aci_enable
) {
859 a
*= radio
->nrssi
[1] - radio
->nrssi
[0];
860 a
+= radio
->nrssi
[0] * 0x40;
863 b
*= radio
->nrssi
[1] - radio
->nrssi
[0];
864 b
+= radio
->nrssi
[0] * 0x40;
867 a
= limit_value(a
, -31, 31);
868 b
= limit_value(b
, -31, 31);
870 tmp_u16
= bcm43xx_phy_read(bcm
, 0x048A) & 0xF000;
871 tmp_u16
|= ((u32
)a
& 0x003F);
872 tmp_u16
|= (((u32
)b
& 0x003F) << 6);
873 bcm43xx_phy_write(bcm
, 0x048A, tmp_u16
);
881 /* Helper macros to save on and restore values from the radio->interfstack */
886 # undef stack_restore
888 #define stack_save(value) \
890 assert(i < ARRAY_SIZE(radio->interfstack)); \
891 stack[i++] = (value); \
894 #define stack_restore() \
896 assert(i < ARRAY_SIZE(radio->interfstack)); \
901 bcm43xx_radio_interference_mitigation_enable(struct bcm43xx_private
*bcm
,
904 struct bcm43xx_phyinfo
*phy
= bcm
->current_core
->phy
;
905 struct bcm43xx_radioinfo
*radio
= bcm
->current_core
->radio
;
907 u16
*stack
= radio
->interfstack
;
911 case BCM43xx_RADIO_INTERFMODE_NONWLAN
:
913 bcm43xx_phy_write(bcm
, 0x042B,
914 bcm43xx_phy_read(bcm
, 0x042B) & 0x0800);
915 bcm43xx_phy_write(bcm
, BCM43xx_PHY_G_CRS
,
916 bcm43xx_phy_read(bcm
, BCM43xx_PHY_G_CRS
) & ~0x4000);
919 tmp
= (bcm43xx_radio_read16(bcm
, 0x0078) & 0x001E);
920 flipped
= flip_4bit(tmp
);
921 if ((flipped
>> 1) >= 4)
923 tmp
= flip_4bit(tmp
);
924 bcm43xx_radio_write16(bcm
, 0x0078, tmp
<< 1);
926 bcm43xx_calc_nrssi_threshold(bcm
);
928 if (bcm
->current_core
->rev
< 5) {
929 stack_save(bcm43xx_phy_read(bcm
, 0x0406));
930 bcm43xx_phy_write(bcm
, 0x0406, 0x7E28);
932 stack_save(bcm43xx_phy_read(bcm
, 0x04C0));
933 stack_save(bcm43xx_phy_read(bcm
, 0x04C1));
934 bcm43xx_phy_write(bcm
, 0x04C0, 0x3E04);
935 bcm43xx_phy_write(bcm
, 0x04C1, 0x0640);
938 bcm43xx_phy_write(bcm
, 0x042B,
939 bcm43xx_phy_read(bcm
, 0x042B) | 0x0800);
940 bcm43xx_phy_write(bcm
, BCM43xx_PHY_RADIO_BITFIELD
,
941 bcm43xx_phy_read(bcm
, BCM43xx_PHY_RADIO_BITFIELD
) | 0x1000);
943 stack_save(bcm43xx_phy_read(bcm
, 0x04A0));
944 bcm43xx_phy_write(bcm
, 0x04A0,
945 (bcm43xx_phy_read(bcm
, 0x04A0) & 0xC0C0) | 0x0008);
946 stack_save(bcm43xx_phy_read(bcm
, 0x04A1));
947 bcm43xx_phy_write(bcm
, 0x04A1,
948 (bcm43xx_phy_read(bcm
, 0x04A1) & 0xC0C0) | 0x0605);
949 stack_save(bcm43xx_phy_read(bcm
, 0x04A2));
950 bcm43xx_phy_write(bcm
, 0x04A2,
951 (bcm43xx_phy_read(bcm
, 0x04A2) & 0xC0C0) | 0x0204);
952 stack_save(bcm43xx_phy_read(bcm
, 0x04A8));
953 bcm43xx_phy_write(bcm
, 0x04A8,
954 (bcm43xx_phy_read(bcm
, 0x04A8) & 0xC0C0) | 0x0403);
955 stack_save(bcm43xx_phy_read(bcm
, 0x04AB));
956 bcm43xx_phy_write(bcm
, 0x04AB,
957 (bcm43xx_phy_read(bcm
, 0x04AB) & 0xC0C0) | 0x0504);
959 stack_save(bcm43xx_phy_read(bcm
, 0x04A7));
960 bcm43xx_phy_write(bcm
, 0x04A7, 0x0002);
961 stack_save(bcm43xx_phy_read(bcm
, 0x04A3));
962 bcm43xx_phy_write(bcm
, 0x04A3, 0x287A);
963 stack_save(bcm43xx_phy_read(bcm
, 0x04A9));
964 bcm43xx_phy_write(bcm
, 0x04A9, 0x2027);
965 stack_save(bcm43xx_phy_read(bcm
, 0x0493));
966 bcm43xx_phy_write(bcm
, 0x0493, 0x32F5);
967 stack_save(bcm43xx_phy_read(bcm
, 0x04AA));
968 bcm43xx_phy_write(bcm
, 0x04AA, 0x2027);
969 stack_save(bcm43xx_phy_read(bcm
, 0x04AC));
970 bcm43xx_phy_write(bcm
, 0x04AC, 0x32F5);
972 case BCM43xx_RADIO_INTERFMODE_MANUALWLAN
:
973 if (bcm43xx_phy_read(bcm
, 0x0033) == 0x0800)
976 radio
->aci_enable
= 1;
978 stack_save(bcm43xx_phy_read(bcm
, BCM43xx_PHY_RADIO_BITFIELD
));
979 stack_save(bcm43xx_phy_read(bcm
, BCM43xx_PHY_G_CRS
));
980 if (bcm
->current_core
->rev
< 5) {
981 stack_save(bcm43xx_phy_read(bcm
, 0x0406));
983 stack_save(bcm43xx_phy_read(bcm
, 0x04C0));
984 stack_save(bcm43xx_phy_read(bcm
, 0x04C1));
986 stack_save(bcm43xx_phy_read(bcm
, 0x0033));
987 stack_save(bcm43xx_phy_read(bcm
, 0x04A7));
988 stack_save(bcm43xx_phy_read(bcm
, 0x04A3));
989 stack_save(bcm43xx_phy_read(bcm
, 0x04A9));
990 stack_save(bcm43xx_phy_read(bcm
, 0x04AA));
991 stack_save(bcm43xx_phy_read(bcm
, 0x04AC));
992 stack_save(bcm43xx_phy_read(bcm
, 0x0493));
993 stack_save(bcm43xx_phy_read(bcm
, 0x04A1));
994 stack_save(bcm43xx_phy_read(bcm
, 0x04A0));
995 stack_save(bcm43xx_phy_read(bcm
, 0x04A2));
996 stack_save(bcm43xx_phy_read(bcm
, 0x048A));
997 stack_save(bcm43xx_phy_read(bcm
, 0x04A8));
998 stack_save(bcm43xx_phy_read(bcm
, 0x04AB));
1000 bcm43xx_phy_write(bcm
, BCM43xx_PHY_RADIO_BITFIELD
,
1001 bcm43xx_phy_read(bcm
, BCM43xx_PHY_RADIO_BITFIELD
) & 0xEFFF);
1002 bcm43xx_phy_write(bcm
, BCM43xx_PHY_G_CRS
,
1003 (bcm43xx_phy_read(bcm
, BCM43xx_PHY_G_CRS
) & 0xEFFF) | 0x0002);
1005 bcm43xx_phy_write(bcm
, 0x04A7, 0x0800);
1006 bcm43xx_phy_write(bcm
, 0x04A3, 0x287A);
1007 bcm43xx_phy_write(bcm
, 0x04A9, 0x2027);
1008 bcm43xx_phy_write(bcm
, 0x0493, 0x32F5);
1009 bcm43xx_phy_write(bcm
, 0x04AA, 0x2027);
1010 bcm43xx_phy_write(bcm
, 0x04AC, 0x32F5);
1012 bcm43xx_phy_write(bcm
, 0x04A0,
1013 (bcm43xx_phy_read(bcm
, 0x04A0) & 0xFFC0) | 0x001A);
1014 if (bcm
->current_core
->rev
< 5) {
1015 bcm43xx_phy_write(bcm
, 0x0406, 0x280D);
1017 bcm43xx_phy_write(bcm
, 0x04C0, 0x0640);
1018 bcm43xx_phy_write(bcm
, 0x04C1, 0x00A9);
1021 bcm43xx_phy_write(bcm
, 0x04A1,
1022 (bcm43xx_phy_read(bcm
, 0x04A1) & 0xC0FF) | 0x1800);
1023 bcm43xx_phy_write(bcm
, 0x04A1,
1024 (bcm43xx_phy_read(bcm
, 0x04A1) & 0xFFC0) | 0x0016);
1025 bcm43xx_phy_write(bcm
, 0x04A2,
1026 (bcm43xx_phy_read(bcm
, 0x04A2) & 0xF0FF) | 0x0900);
1027 bcm43xx_phy_write(bcm
, 0x04A0,
1028 (bcm43xx_phy_read(bcm
, 0x04A0) & 0xF0FF) | 0x0700);
1029 bcm43xx_phy_write(bcm
, 0x04A2,
1030 (bcm43xx_phy_read(bcm
, 0x04A2) & 0xFFF0) | 0x000D);
1031 bcm43xx_phy_write(bcm
, 0x04A8,
1032 (bcm43xx_phy_read(bcm
, 0x04A8) & 0xCFFF) | 0x1000);
1033 bcm43xx_phy_write(bcm
, 0x04A8,
1034 (bcm43xx_phy_read(bcm
, 0x04A8) & 0xF0FF) | 0x0A00);
1035 bcm43xx_phy_write(bcm
, 0x04AB,
1036 (bcm43xx_phy_read(bcm
, 0x04AB) & 0xCFFF) | 0x1000);
1037 bcm43xx_phy_write(bcm
, 0x04AB,
1038 (bcm43xx_phy_read(bcm
, 0x04AB) & 0xF0FF) | 0x0800);
1039 bcm43xx_phy_write(bcm
, 0x04AB,
1040 (bcm43xx_phy_read(bcm
, 0x04AB) & 0xFFCF) | 0x0010);
1041 bcm43xx_phy_write(bcm
, 0x04AB,
1042 (bcm43xx_phy_read(bcm
, 0x04AB) & 0xFFF0) | 0x0006);
1044 bcm43xx_calc_nrssi_slope(bcm
);
1052 bcm43xx_radio_interference_mitigation_disable(struct bcm43xx_private
*bcm
,
1055 struct bcm43xx_phyinfo
*phy
= bcm
->current_core
->phy
;
1056 struct bcm43xx_radioinfo
*radio
= bcm
->current_core
->radio
;
1058 u16
*stack
= radio
->interfstack
;
1062 case BCM43xx_RADIO_INTERFMODE_NONWLAN
:
1063 if (phy
->rev
!= 1) {
1064 bcm43xx_phy_write(bcm
, 0x042B,
1065 bcm43xx_phy_read(bcm
, 0x042B) & ~0x0800);
1066 bcm43xx_phy_write(bcm
, BCM43xx_PHY_G_CRS
,
1067 bcm43xx_phy_read(bcm
, BCM43xx_PHY_G_CRS
) & 0x4000);
1070 tmp
= (bcm43xx_radio_read16(bcm
, 0x0078) & 0x001E);
1071 flipped
= flip_4bit(tmp
);
1072 if ((flipped
>> 1) >= 0x000C)
1074 tmp
= flip_4bit(tmp
);
1075 bcm43xx_radio_write16(bcm
, 0x0078, tmp
<< 1);
1077 bcm43xx_calc_nrssi_threshold(bcm
);
1079 if (bcm
->current_core
->rev
< 5) {
1080 bcm43xx_phy_write(bcm
, 0x0406, stack_restore());
1082 bcm43xx_phy_write(bcm
, 0x04C0, stack_restore());
1083 bcm43xx_phy_write(bcm
, 0x04C1, stack_restore());
1085 bcm43xx_phy_write(bcm
, 0x042B,
1086 bcm43xx_phy_read(bcm
, 0x042B) & ~0x0800);
1088 if (!bcm
->bad_frames_preempt
)
1089 bcm43xx_phy_write(bcm
, BCM43xx_PHY_RADIO_BITFIELD
,
1090 bcm43xx_phy_read(bcm
, BCM43xx_PHY_RADIO_BITFIELD
) & ~(1 << 11));
1091 bcm43xx_phy_write(bcm
, BCM43xx_PHY_G_CRS
,
1092 bcm43xx_phy_read(bcm
, BCM43xx_PHY_G_CRS
) & 0x4000);
1093 bcm43xx_phy_write(bcm
, 0x04A0, stack_restore());
1094 bcm43xx_phy_write(bcm
, 0x04A1, stack_restore());
1095 bcm43xx_phy_write(bcm
, 0x04A2, stack_restore());
1096 bcm43xx_phy_write(bcm
, 0x04A8, stack_restore());
1097 bcm43xx_phy_write(bcm
, 0x04AB, stack_restore());
1098 bcm43xx_phy_write(bcm
, 0x04A7, stack_restore());
1099 bcm43xx_phy_write(bcm
, 0x04A3, stack_restore());
1100 bcm43xx_phy_write(bcm
, 0x04A9, stack_restore());
1101 bcm43xx_phy_write(bcm
, 0x0493, stack_restore());
1102 bcm43xx_phy_write(bcm
, 0x04AA, stack_restore());
1103 bcm43xx_phy_write(bcm
, 0x04AC, stack_restore());
1105 case BCM43xx_RADIO_INTERFMODE_MANUALWLAN
:
1106 if (bcm43xx_phy_read(bcm
, 0x0033) != 0x0800)
1109 radio
->aci_enable
= 0;
1111 bcm43xx_phy_write(bcm
, BCM43xx_PHY_RADIO_BITFIELD
, stack_restore());
1112 bcm43xx_phy_write(bcm
, BCM43xx_PHY_G_CRS
, stack_restore());
1113 if (bcm
->current_core
->rev
< 5) {
1114 bcm43xx_phy_write(bcm
, 0x0406, stack_restore());
1116 bcm43xx_phy_write(bcm
, 0x04C0, stack_restore());
1117 bcm43xx_phy_write(bcm
, 0x04C1, stack_restore());
1119 bcm43xx_phy_write(bcm
, 0x0033, stack_restore());
1120 bcm43xx_phy_write(bcm
, 0x04A7, stack_restore());
1121 bcm43xx_phy_write(bcm
, 0x04A3, stack_restore());
1122 bcm43xx_phy_write(bcm
, 0x04A9, stack_restore());
1123 bcm43xx_phy_write(bcm
, 0x04AA, stack_restore());
1124 bcm43xx_phy_write(bcm
, 0x04AC, stack_restore());
1125 bcm43xx_phy_write(bcm
, 0x0493, stack_restore());
1126 bcm43xx_phy_write(bcm
, 0x04A1, stack_restore());
1127 bcm43xx_phy_write(bcm
, 0x04A0, stack_restore());
1128 bcm43xx_phy_write(bcm
, 0x04A2, stack_restore());
1129 bcm43xx_phy_write(bcm
, 0x04A8, stack_restore());
1130 bcm43xx_phy_write(bcm
, 0x04AB, stack_restore());
1132 bcm43xx_calc_nrssi_slope(bcm
);
1140 #undef stack_restore
1142 int bcm43xx_radio_set_interference_mitigation(struct bcm43xx_private
*bcm
,
1145 struct bcm43xx_phyinfo
*phy
= bcm
->current_core
->phy
;
1146 struct bcm43xx_radioinfo
*radio
= bcm
->current_core
->radio
;
1149 if ((phy
->type
!= BCM43xx_PHYTYPE_G
) ||
1154 radio
->aci_wlan_automatic
= 0;
1156 case BCM43xx_RADIO_INTERFMODE_AUTOWLAN
:
1157 radio
->aci_wlan_automatic
= 1;
1158 if (radio
->aci_enable
)
1159 mode
= BCM43xx_RADIO_INTERFMODE_MANUALWLAN
;
1161 mode
= BCM43xx_RADIO_INTERFMODE_NONE
;
1163 case BCM43xx_RADIO_INTERFMODE_NONE
:
1164 case BCM43xx_RADIO_INTERFMODE_NONWLAN
:
1165 case BCM43xx_RADIO_INTERFMODE_MANUALWLAN
:
1171 currentmode
= radio
->interfmode
;
1172 if (currentmode
== mode
)
1174 if (currentmode
!= BCM43xx_RADIO_INTERFMODE_NONE
)
1175 bcm43xx_radio_interference_mitigation_disable(bcm
, currentmode
);
1177 if (mode
== BCM43xx_RADIO_INTERFMODE_NONE
) {
1178 radio
->aci_enable
= 0;
1179 radio
->aci_hw_rssi
= 0;
1181 bcm43xx_radio_interference_mitigation_enable(bcm
, mode
);
1182 radio
->interfmode
= mode
;
1187 static u16
bcm43xx_radio_calibrationvalue(struct bcm43xx_private
*bcm
)
1189 u16 reg
, index
, ret
;
1191 reg
= bcm43xx_radio_read16(bcm
, 0x0060);
1192 index
= (reg
& 0x001E) >> 1;
1193 ret
= rcc_table
[index
] << 1;
1194 ret
|= (reg
& 0x0001);
1200 u16
bcm43xx_radio_init2050(struct bcm43xx_private
*bcm
)
1202 struct bcm43xx_phyinfo
*phy
= bcm
->current_core
->phy
;
1203 struct bcm43xx_radioinfo
*radio
= bcm
->current_core
->radio
;
1204 u16 backup
[19] = { 0 };
1207 u32 tmp1
= 0, tmp2
= 0;
1209 backup
[0] = bcm43xx_radio_read16(bcm
, 0x0043);
1210 backup
[14] = bcm43xx_radio_read16(bcm
, 0x0051);
1211 backup
[15] = bcm43xx_radio_read16(bcm
, 0x0052);
1212 backup
[1] = bcm43xx_phy_read(bcm
, 0x0015);
1213 backup
[16] = bcm43xx_phy_read(bcm
, 0x005A);
1214 backup
[17] = bcm43xx_phy_read(bcm
, 0x0059);
1215 backup
[18] = bcm43xx_phy_read(bcm
, 0x0058);
1216 if (phy
->type
== BCM43xx_PHYTYPE_B
) {
1217 backup
[2] = bcm43xx_phy_read(bcm
, 0x0030);
1218 backup
[3] = bcm43xx_read16(bcm
, 0x03EC);
1219 bcm43xx_phy_write(bcm
, 0x0030, 0x00FF);
1220 bcm43xx_write16(bcm
, 0x03EC, 0x3F3F);
1222 if (phy
->connected
) {
1223 backup
[4] = bcm43xx_phy_read(bcm
, 0x0811);
1224 backup
[5] = bcm43xx_phy_read(bcm
, 0x0812);
1225 backup
[6] = bcm43xx_phy_read(bcm
, 0x0814);
1226 backup
[7] = bcm43xx_phy_read(bcm
, 0x0815);
1227 backup
[8] = bcm43xx_phy_read(bcm
, BCM43xx_PHY_G_CRS
);
1228 backup
[9] = bcm43xx_phy_read(bcm
, 0x0802);
1229 bcm43xx_phy_write(bcm
, 0x0814,
1230 (bcm43xx_phy_read(bcm
, 0x0814) | 0x0003));
1231 bcm43xx_phy_write(bcm
, 0x0815,
1232 (bcm43xx_phy_read(bcm
, 0x0815) & 0xFFFC));
1233 bcm43xx_phy_write(bcm
, BCM43xx_PHY_G_CRS
,
1234 (bcm43xx_phy_read(bcm
, BCM43xx_PHY_G_CRS
) & 0x7FFF));
1235 bcm43xx_phy_write(bcm
, 0x0802,
1236 (bcm43xx_phy_read(bcm
, 0x0802) & 0xFFFC));
1237 bcm43xx_phy_write(bcm
, 0x0811, 0x01B3);
1238 bcm43xx_phy_write(bcm
, 0x0812, 0x0FB2);
1240 bcm43xx_write16(bcm
, BCM43xx_MMIO_PHY_RADIO
,
1241 (bcm43xx_read16(bcm
, BCM43xx_MMIO_PHY_RADIO
) | 0x8000));
1243 backup
[10] = bcm43xx_phy_read(bcm
, 0x0035);
1244 bcm43xx_phy_write(bcm
, 0x0035,
1245 (bcm43xx_phy_read(bcm
, 0x0035) & 0xFF7F));
1246 backup
[11] = bcm43xx_read16(bcm
, 0x03E6);
1247 backup
[12] = bcm43xx_read16(bcm
, BCM43xx_MMIO_CHANNEL_EXT
);
1250 if (phy
->version
== 0) {
1251 bcm43xx_write16(bcm
, 0x03E6, 0x0122);
1253 if (phy
->version
>= 2)
1254 bcm43xx_write16(bcm
, 0x03E6, 0x0040);
1255 bcm43xx_write16(bcm
, BCM43xx_MMIO_CHANNEL_EXT
,
1256 (bcm43xx_read16(bcm
, BCM43xx_MMIO_CHANNEL_EXT
) | 0x2000));
1259 ret
= bcm43xx_radio_calibrationvalue(bcm
);
1261 if (phy
->type
== BCM43xx_PHYTYPE_B
)
1262 bcm43xx_radio_write16(bcm
, 0x0078, 0x0003);
1264 bcm43xx_phy_write(bcm
, 0x0015, 0xBFAF);
1265 bcm43xx_phy_write(bcm
, 0x002B, 0x1403);
1267 bcm43xx_phy_write(bcm
, 0x0812, 0x00B2);
1268 bcm43xx_phy_write(bcm
, 0x0015, 0xBFA0);
1269 bcm43xx_radio_write16(bcm
, 0x0051,
1270 (bcm43xx_radio_read16(bcm
, 0x0051) | 0x0004));
1271 bcm43xx_radio_write16(bcm
, 0x0052, 0x0000);
1272 bcm43xx_radio_write16(bcm
, 0x0043,
1273 bcm43xx_radio_read16(bcm
, 0x0043) | 0x0009);
1274 bcm43xx_phy_write(bcm
, 0x0058, 0x0000);
1276 for (i
= 0; i
< 16; i
++) {
1277 bcm43xx_phy_write(bcm
, 0x005A, 0x0480);
1278 bcm43xx_phy_write(bcm
, 0x0059, 0xC810);
1279 bcm43xx_phy_write(bcm
, 0x0058, 0x000D);
1281 bcm43xx_phy_write(bcm
, 0x0812, 0x30B2);
1282 bcm43xx_phy_write(bcm
, 0x0015, 0xAFB0);
1285 bcm43xx_phy_write(bcm
, 0x0812, 0x30B2);
1286 bcm43xx_phy_write(bcm
, 0x0015, 0xEFB0);
1289 bcm43xx_phy_write(bcm
, 0x0812, 0x30B2);
1290 bcm43xx_phy_write(bcm
, 0x0015, 0xFFF0);
1292 tmp1
+= bcm43xx_phy_read(bcm
, 0x002D);
1293 bcm43xx_phy_write(bcm
, 0x0058, 0x0000);
1295 bcm43xx_phy_write(bcm
, 0x0812, 0x30B2);
1296 bcm43xx_phy_write(bcm
, 0x0015, 0xAFB0);
1302 bcm43xx_phy_write(bcm
, 0x0058, 0x0000);
1304 for (i
= 0; i
< 16; i
++) {
1305 bcm43xx_radio_write16(bcm
, 0x0078, (flip_4bit(i
) << 1) | 0x0020);
1306 backup
[13] = bcm43xx_radio_read16(bcm
, 0x0078);
1308 for (j
= 0; j
< 16; j
++) {
1309 bcm43xx_phy_write(bcm
, 0x005A, 0x0D80);
1310 bcm43xx_phy_write(bcm
, 0x0059, 0xC810);
1311 bcm43xx_phy_write(bcm
, 0x0058, 0x000D);
1313 bcm43xx_phy_write(bcm
, 0x0812, 0x30B2);
1314 bcm43xx_phy_write(bcm
, 0x0015, 0xAFB0);
1317 bcm43xx_phy_write(bcm
, 0x0812, 0x30B2);
1318 bcm43xx_phy_write(bcm
, 0x0015, 0xEFB0);
1321 bcm43xx_phy_write(bcm
, 0x0812, 0x30B3); /* 0x30B3 is not a typo */
1322 bcm43xx_phy_write(bcm
, 0x0015, 0xFFF0);
1324 tmp2
+= bcm43xx_phy_read(bcm
, 0x002D);
1325 bcm43xx_phy_write(bcm
, 0x0058, 0x0000);
1327 bcm43xx_phy_write(bcm
, 0x0812, 0x30B2);
1328 bcm43xx_phy_write(bcm
, 0x0015, 0xAFB0);
1336 /* Restore the registers */
1337 bcm43xx_phy_write(bcm
, 0x0015, backup
[1]);
1338 bcm43xx_radio_write16(bcm
, 0x0051, backup
[14]);
1339 bcm43xx_radio_write16(bcm
, 0x0052, backup
[15]);
1340 bcm43xx_radio_write16(bcm
, 0x0043, backup
[0]);
1341 bcm43xx_phy_write(bcm
, 0x005A, backup
[16]);
1342 bcm43xx_phy_write(bcm
, 0x0059, backup
[17]);
1343 bcm43xx_phy_write(bcm
, 0x0058, backup
[18]);
1344 bcm43xx_write16(bcm
, 0x03E6, backup
[11]);
1345 if (phy
->version
!= 0)
1346 bcm43xx_write16(bcm
, BCM43xx_MMIO_CHANNEL_EXT
, backup
[12]);
1347 bcm43xx_phy_write(bcm
, 0x0035, backup
[10]);
1348 bcm43xx_radio_selectchannel(bcm
, radio
->channel
, 1);
1349 if (phy
->type
== BCM43xx_PHYTYPE_B
) {
1350 bcm43xx_phy_write(bcm
, 0x0030, backup
[2]);
1351 bcm43xx_write16(bcm
, 0x03EC, backup
[3]);
1353 bcm43xx_write16(bcm
, BCM43xx_MMIO_PHY_RADIO
,
1354 (bcm43xx_read16(bcm
, BCM43xx_MMIO_PHY_RADIO
) & 0x7FFF));
1355 if (phy
->connected
) {
1356 bcm43xx_phy_write(bcm
, 0x0811, backup
[4]);
1357 bcm43xx_phy_write(bcm
, 0x0812, backup
[5]);
1358 bcm43xx_phy_write(bcm
, 0x0814, backup
[6]);
1359 bcm43xx_phy_write(bcm
, 0x0815, backup
[7]);
1360 bcm43xx_phy_write(bcm
, BCM43xx_PHY_G_CRS
, backup
[8]);
1361 bcm43xx_phy_write(bcm
, 0x0802, backup
[9]);
1370 void bcm43xx_radio_init2060(struct bcm43xx_private
*bcm
)
1374 bcm43xx_radio_write16(bcm
, 0x0004, 0x00C0);
1375 bcm43xx_radio_write16(bcm
, 0x0005, 0x0008);
1376 bcm43xx_radio_write16(bcm
, 0x0009, 0x0040);
1377 bcm43xx_radio_write16(bcm
, 0x0005, 0x00AA);
1378 bcm43xx_radio_write16(bcm
, 0x0032, 0x008F);
1379 bcm43xx_radio_write16(bcm
, 0x0006, 0x008F);
1380 bcm43xx_radio_write16(bcm
, 0x0034, 0x008F);
1381 bcm43xx_radio_write16(bcm
, 0x002C, 0x0007);
1382 bcm43xx_radio_write16(bcm
, 0x0082, 0x0080);
1383 bcm43xx_radio_write16(bcm
, 0x0080, 0x0000);
1384 bcm43xx_radio_write16(bcm
, 0x003F, 0x00DA);
1385 bcm43xx_radio_write16(bcm
, 0x0005, bcm43xx_radio_read16(bcm
, 0x0005) & ~0x0008);
1386 bcm43xx_radio_write16(bcm
, 0x0081, bcm43xx_radio_read16(bcm
, 0x0081) & ~0x0010);
1387 bcm43xx_radio_write16(bcm
, 0x0081, bcm43xx_radio_read16(bcm
, 0x0081) & ~0x0020);
1388 bcm43xx_radio_write16(bcm
, 0x0081, bcm43xx_radio_read16(bcm
, 0x0081) & ~0x0020);
1391 bcm43xx_radio_write16(bcm
, 0x0081, (bcm43xx_radio_read16(bcm
, 0x0081) & ~0x0020) | 0x0010);
1394 bcm43xx_radio_write16(bcm
, 0x0005, (bcm43xx_radio_read16(bcm
, 0x0005) & ~0x0008) | 0x0008);
1395 bcm43xx_radio_write16(bcm
, 0x0085, bcm43xx_radio_read16(bcm
, 0x0085) & ~0x0010);
1396 bcm43xx_radio_write16(bcm
, 0x0005, bcm43xx_radio_read16(bcm
, 0x0005) & ~0x0008);
1397 bcm43xx_radio_write16(bcm
, 0x0081, bcm43xx_radio_read16(bcm
, 0x0081) & ~0x0040);
1398 bcm43xx_radio_write16(bcm
, 0x0081, (bcm43xx_radio_read16(bcm
, 0x0081) & ~0x0040) | 0x0040);
1399 bcm43xx_radio_write16(bcm
, 0x0005, (bcm43xx_radio_read16(bcm
, 0x0081) & ~0x0008) | 0x0008);
1400 bcm43xx_phy_write(bcm
, 0x0063, 0xDDC6);
1401 bcm43xx_phy_write(bcm
, 0x0069, 0x07BE);
1402 bcm43xx_phy_write(bcm
, 0x006A, 0x0000);
1404 err
= bcm43xx_radio_selectchannel(bcm
, BCM43xx_RADIO_DEFAULT_CHANNEL_A
, 0);
1410 u16
freq_r3A_value(u16 frequency
)
1414 if (frequency
< 5091)
1416 else if (frequency
< 5321)
1418 else if (frequency
< 5806)
1426 void bcm43xx_radio_set_tx_iq(struct bcm43xx_private
*bcm
)
1428 static const u8 data_high
[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
1429 static const u8 data_low
[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
1430 u16 tmp
= bcm43xx_radio_read16(bcm
, 0x001E);
1433 for (i
= 0; i
< 5; i
++) {
1434 for (j
= 0; j
< 5; j
++) {
1435 if (tmp
== (data_high
[i
] << 4 | data_low
[j
])) {
1436 bcm43xx_phy_write(bcm
, 0x0069, (i
- j
) << 8 | 0x00C0);
1443 int bcm43xx_radio_selectchannel(struct bcm43xx_private
*bcm
,
1445 int synthetic_pu_workaround
)
1447 struct bcm43xx_radioinfo
*radio
= bcm
->current_core
->radio
;
1451 if ((radio
->manufact
== 0x17F) &&
1452 (radio
->version
== 0x2060) &&
1453 (radio
->revision
== 1)) {
1456 freq
= channel2freq_a(channel
);
1458 r8
= bcm43xx_radio_read16(bcm
, 0x0008);
1459 bcm43xx_write16(bcm
, 0x03F0, freq
);
1460 bcm43xx_radio_write16(bcm
, 0x0008, r8
);
1462 TODO();//TODO: write max channel TX power? to Radio 0x2D
1463 tmp
= bcm43xx_radio_read16(bcm
, 0x002E);
1465 TODO();//TODO: OR tmp with the Power out estimation for this channel?
1466 bcm43xx_radio_write16(bcm
, 0x002E, tmp
);
1468 if (freq
>= 4920 && freq
<= 5500) {
1470 * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
1471 * = (freq * 0.025862069
1473 r8
= 3 * freq
/ 116; /* is equal to r8 = freq * 0.025862 */
1475 bcm43xx_radio_write16(bcm
, 0x0007, (r8
<< 4) | r8
);
1476 bcm43xx_radio_write16(bcm
, 0x0020, (r8
<< 4) | r8
);
1477 bcm43xx_radio_write16(bcm
, 0x0021, (r8
<< 4) | r8
);
1478 bcm43xx_radio_write16(bcm
, 0x0022,
1479 (bcm43xx_radio_read16(bcm
, 0x0022)
1480 & 0x000F) | (r8
<< 4));
1481 bcm43xx_radio_write16(bcm
, 0x002A, (r8
<< 4));
1482 bcm43xx_radio_write16(bcm
, 0x002B, (r8
<< 4));
1483 bcm43xx_radio_write16(bcm
, 0x0008,
1484 (bcm43xx_radio_read16(bcm
, 0x0008)
1485 & 0x00F0) | (r8
<< 4));
1486 bcm43xx_radio_write16(bcm
, 0x0029,
1487 (bcm43xx_radio_read16(bcm
, 0x0029)
1488 & 0xFF0F) | 0x00B0);
1489 bcm43xx_radio_write16(bcm
, 0x0035, 0x00AA);
1490 bcm43xx_radio_write16(bcm
, 0x0036, 0x0085);
1491 bcm43xx_radio_write16(bcm
, 0x003A,
1492 (bcm43xx_radio_read16(bcm
, 0x003A)
1493 & 0xFF20) | freq_r3A_value(freq
));
1494 bcm43xx_radio_write16(bcm
, 0x003D,
1495 bcm43xx_radio_read16(bcm
, 0x003D) & 0x00FF);
1496 bcm43xx_radio_write16(bcm
, 0x0081,
1497 (bcm43xx_radio_read16(bcm
, 0x0081)
1498 & 0xFF7F) | 0x0080);
1499 bcm43xx_radio_write16(bcm
, 0x0035,
1500 bcm43xx_radio_read16(bcm
, 0x0035) & 0xFFEF);
1501 bcm43xx_radio_write16(bcm
, 0x0035,
1502 (bcm43xx_radio_read16(bcm
, 0x0035)
1503 & 0xFFEF) | 0x0010);
1504 bcm43xx_radio_set_tx_iq(bcm
);
1505 TODO(); //TODO: TSSI2dbm workaround
1506 bcm43xx_phy_xmitpower(bcm
);//FIXME correct?
1508 if ((channel
< 1) || (channel
> 14))
1511 if (synthetic_pu_workaround
)
1512 bcm43xx_synth_pu_workaround(bcm
, channel
);
1514 bcm43xx_write16(bcm
, BCM43xx_MMIO_CHANNEL
,
1515 channel2freq_bg(channel
));
1517 if (channel
== 14) {
1518 if (bcm
->sprom
.locale
== BCM43xx_LOCALE_JAPAN
) {
1519 bcm43xx_shm_write32(bcm
, BCM43xx_SHM_SHARED
,
1520 BCM43xx_UCODEFLAGS_OFFSET
,
1521 bcm43xx_shm_read32(bcm
, BCM43xx_SHM_SHARED
,
1522 BCM43xx_UCODEFLAGS_OFFSET
)
1525 bcm43xx_shm_write32(bcm
, BCM43xx_SHM_SHARED
,
1526 BCM43xx_UCODEFLAGS_OFFSET
,
1527 bcm43xx_shm_read32(bcm
, BCM43xx_SHM_SHARED
,
1528 BCM43xx_UCODEFLAGS_OFFSET
)
1531 bcm43xx_write16(bcm
, BCM43xx_MMIO_CHANNEL_EXT
,
1532 bcm43xx_read16(bcm
, BCM43xx_MMIO_CHANNEL_EXT
)
1535 bcm43xx_write16(bcm
, BCM43xx_MMIO_CHANNEL_EXT
,
1536 bcm43xx_read16(bcm
, BCM43xx_MMIO_CHANNEL_EXT
)
1541 radio
->channel
= channel
;
1542 //XXX: Using the longer of 2 timeouts (8000 vs 2000 usecs). Specs states
1543 // that 2000 usecs might suffice.
1549 void bcm43xx_radio_set_txantenna(struct bcm43xx_private
*bcm
, u32 val
)
1554 tmp
= bcm43xx_shm_read16(bcm
, BCM43xx_SHM_SHARED
, 0x0022) & 0xFCFF;
1555 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x0022, tmp
| val
);
1556 tmp
= bcm43xx_shm_read16(bcm
, BCM43xx_SHM_SHARED
, 0x03A8) & 0xFCFF;
1557 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x03A8, tmp
| val
);
1558 tmp
= bcm43xx_shm_read16(bcm
, BCM43xx_SHM_SHARED
, 0x0054) & 0xFCFF;
1559 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x0054, tmp
| val
);
1562 /* http://bcm-specs.sipsolutions.net/TX_Gain_Base_Band */
1563 static u16
bcm43xx_get_txgain_base_band(u16 txpower
)
1567 assert(txpower
<= 63);
1571 else if (txpower
>= 49)
1573 else if (txpower
>= 44)
1581 /* http://bcm-specs.sipsolutions.net/TX_Gain_Radio_Frequency_Power_Amplifier */
1582 static u16
bcm43xx_get_txgain_freq_power_amp(u16 txpower
)
1586 assert(txpower
<= 63);
1590 else if (txpower
>= 25)
1592 else if (txpower
>= 20)
1594 else if (txpower
>= 12)
1602 /* http://bcm-specs.sipsolutions.net/TX_Gain_Digital_Analog_Converter */
1603 static u16
bcm43xx_get_txgain_dac(u16 txpower
)
1607 assert(txpower
<= 63);
1611 else if (txpower
>= 49)
1613 else if (txpower
>= 44)
1615 else if (txpower
>= 32)
1617 else if (txpower
>= 25)
1619 else if (txpower
>= 20)
1621 else if (txpower
>= 12)
1629 void bcm43xx_radio_set_txpower_a(struct bcm43xx_private
*bcm
, u16 txpower
)
1631 u16 pamp
, base
, dac
, ilt
;
1633 txpower
= limit_value(txpower
, 0, 63);
1635 pamp
= bcm43xx_get_txgain_freq_power_amp(txpower
);
1638 bcm43xx_phy_write(bcm
, 0x0019, pamp
);
1640 base
= bcm43xx_get_txgain_base_band(txpower
);
1642 bcm43xx_phy_write(bcm
, 0x0017, base
| 0x0020);
1644 ilt
= bcm43xx_ilt_read16(bcm
, 0x3001);
1647 dac
= bcm43xx_get_txgain_dac(txpower
);
1651 bcm43xx_ilt_write16(bcm
, 0x3001, dac
);
1653 bcm
->current_core
->radio
->txpower
[0] = txpower
;
1656 //TODO: FuncPlaceholder (Adjust BB loft cancel)
1659 void bcm43xx_radio_set_txpower_bg(struct bcm43xx_private
*bcm
,
1660 u16 baseband_attenuation
, u16 radio_attenuation
,
1663 struct bcm43xx_radioinfo
*radio
= bcm
->current_core
->radio
;
1664 struct bcm43xx_phyinfo
*phy
= bcm
->current_core
->phy
;
1666 if (baseband_attenuation
== 0xFFFF)
1667 baseband_attenuation
= radio
->txpower
[0];
1669 radio
->txpower
[0] = baseband_attenuation
;
1670 if (radio_attenuation
== 0xFFFF)
1671 radio_attenuation
= radio
->txpower
[1];
1673 radio
->txpower
[1] = radio_attenuation
;
1674 if (txpower
== 0xFFFF)
1675 txpower
= radio
->txpower
[2];
1677 radio
->txpower
[2] = txpower
;
1679 assert(/*baseband_attenuation >= 0 &&*/ baseband_attenuation
<= 11);
1680 if (radio
->revision
< 6)
1681 assert(/*radio_attenuation >= 0 &&*/ radio_attenuation
<= 9);
1683 assert(/* radio_attenuation >= 0 &&*/ radio_attenuation
<= 31);
1684 assert(/*txpower >= 0 &&*/ txpower
<= 7);
1686 bcm43xx_phy_set_baseband_attenuation(bcm
, baseband_attenuation
);
1687 bcm43xx_radio_write16(bcm
, 0x0043, radio_attenuation
);
1688 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x0064, radio_attenuation
);
1689 if (radio
->version
== 0x2050) {
1690 bcm43xx_radio_write16(bcm
, 0x0052,
1691 (bcm43xx_radio_read16(bcm
, 0x0052) & 0xFF8F)
1694 if (phy
->type
== BCM43xx_PHYTYPE_G
)
1695 bcm43xx_phy_lo_adjust(bcm
, 0);
1699 void bcm43xx_radio_turn_on(struct bcm43xx_private
*bcm
)
1701 struct bcm43xx_phyinfo
*phy
= bcm
->current_core
->phy
;
1702 struct bcm43xx_radioinfo
*radio
= bcm
->current_core
->radio
;
1708 switch (phy
->type
) {
1709 case BCM43xx_PHYTYPE_A
:
1710 bcm43xx_radio_write16(bcm
, 0x0004, 0x00C0);
1711 bcm43xx_radio_write16(bcm
, 0x0005, 0x0008);
1712 bcm43xx_phy_write(bcm
, 0x0010, bcm43xx_phy_read(bcm
, 0x0010) & 0xFFF7);
1713 bcm43xx_phy_write(bcm
, 0x0011, bcm43xx_phy_read(bcm
, 0x0011) & 0xFFF7);
1714 bcm43xx_radio_init2060(bcm
);
1716 case BCM43xx_PHYTYPE_B
:
1717 case BCM43xx_PHYTYPE_G
:
1718 bcm43xx_phy_write(bcm
, 0x0015, 0x8000);
1719 bcm43xx_phy_write(bcm
, 0x0015, 0xCC00);
1720 bcm43xx_phy_write(bcm
, 0x0015, (phy
->connected
? 0x00C0 : 0x0000));
1721 err
= bcm43xx_radio_selectchannel(bcm
, BCM43xx_RADIO_DEFAULT_CHANNEL_BG
, 1);
1728 dprintk(KERN_INFO PFX
"Radio turned on\n");
1731 void bcm43xx_radio_turn_off(struct bcm43xx_private
*bcm
)
1733 struct bcm43xx_phyinfo
*phy
= bcm
->current_core
->phy
;
1734 struct bcm43xx_radioinfo
*radio
= bcm
->current_core
->radio
;
1736 if (phy
->type
== BCM43xx_PHYTYPE_A
) {
1737 bcm43xx_radio_write16(bcm
, 0x0004, 0x00FF);
1738 bcm43xx_radio_write16(bcm
, 0x0005, 0x00FB);
1739 bcm43xx_phy_write(bcm
, 0x0010, bcm43xx_phy_read(bcm
, 0x0010) | 0x0008);
1740 bcm43xx_phy_write(bcm
, 0x0011, bcm43xx_phy_read(bcm
, 0x0011) | 0x0008);
1742 if (phy
->type
== BCM43xx_PHYTYPE_G
&& bcm
->current_core
->rev
>= 5) {
1743 bcm43xx_phy_write(bcm
, 0x0811, bcm43xx_phy_read(bcm
, 0x0811) | 0x008C);
1744 bcm43xx_phy_write(bcm
, 0x0812, bcm43xx_phy_read(bcm
, 0x0812) & 0xFF73);
1746 bcm43xx_phy_write(bcm
, 0x0015, 0xAA00);
1748 dprintk(KERN_INFO PFX
"Radio turned off\n");
1751 void bcm43xx_radio_clear_tssi(struct bcm43xx_private
*bcm
)
1753 switch (bcm
->current_core
->phy
->type
) {
1754 case BCM43xx_PHYTYPE_A
:
1755 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x0068, 0x7F7F);
1756 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x006a, 0x7F7F);
1758 case BCM43xx_PHYTYPE_B
:
1759 case BCM43xx_PHYTYPE_G
:
1760 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x0058, 0x7F7F);
1761 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x005a, 0x7F7F);
1762 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x0070, 0x7F7F);
1763 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x0072, 0x7F7F);