arch/arm/mach-s3c2410/mach-bast.c

   1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
   2  *
   3  * Copyright 2003-2008 Simtec Electronics
   4  *   Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * http://www.simtec.co.uk/products/EB2410ITX/
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/list.h>
  17 #include <linux/timer.h>
  18 #include <linux/init.h>
  19 #include <linux/gpio.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dm9000.h>
  24 #include <linux/ata_platform.h>
  25 #include <linux/i2c.h>
  26 #include <linux/io.h>
  27
  28 #include <net/ax88796.h>
  29
  30 #include <asm/mach/arch.h>
  31 #include <asm/mach/map.h>
  32 #include <asm/mach/irq.h>
  33
  34 #include <mach/bast-map.h>
  35 #include <mach/bast-irq.h>
  36 #include <mach/bast-cpld.h>
  37
  38 #include <mach/hardware.h>
  39 #include <asm/irq.h>
  40 #include <asm/mach-types.h>
  41
  42 //#include <asm/debug-ll.h>
  43 #include <plat/regs-serial.h>
  44 #include <mach/regs-gpio.h>
  45 #include <mach/regs-mem.h>
  46 #include <mach/regs-lcd.h>
  47
  48 #include <plat/hwmon.h>
  49 #include <plat/nand.h>
  50 #include <plat/iic.h>
  51 #include <mach/fb.h>
  52
  53 #include <linux/mtd/mtd.h>
  54 #include <linux/mtd/nand.h>
  55 #include <linux/mtd/nand_ecc.h>
  56 #include <linux/mtd/partitions.h>
  57
  58 #include <linux/serial_8250.h>
  59
  60 #include <plat/clock.h>
  61 #include <plat/devs.h>
  62 #include <plat/cpu.h>
  63 #include <plat/cpu-freq.h>
  64 #include <plat/gpio-cfg.h>
  65 #include <plat/audio-simtec.h>
  66
  67 #include "usb-simtec.h"
  68 #include "nor-simtec.h"
  69
  70 #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
  71
  72 /* macros for virtual address mods for the io space entries */
  73 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
  74 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
  75 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
  76 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
  77
  78 /* macros to modify the physical addresses for io space */
  79
  80 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
  81 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
  82 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
  83 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
  84
  85 static struct map_desc bast_iodesc[] __initdata = {
  86   /* ISA IO areas */
  87   {
  88           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  89           .pfn          = PA_CS2(BAST_PA_ISAIO),
  90           .length       = SZ_16M,
  91           .type         = MT_DEVICE,
  92   }, {
  93           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
  94           .pfn          = PA_CS3(BAST_PA_ISAIO),
  95           .length       = SZ_16M,
  96           .type         = MT_DEVICE,
  97   },
  98   /* bast CPLD control registers, and external interrupt controls */
  99   {
 100           .virtual      = (u32)BAST_VA_CTRL1,
 101           .pfn          = __phys_to_pfn(BAST_PA_CTRL1),
 102           .length       = SZ_1M,
 103           .type         = MT_DEVICE,
 104   }, {
 105           .virtual      = (u32)BAST_VA_CTRL2,
 106           .pfn          = __phys_to_pfn(BAST_PA_CTRL2),
 107           .length       = SZ_1M,
 108           .type         = MT_DEVICE,
 109   }, {
 110           .virtual      = (u32)BAST_VA_CTRL3,
 111           .pfn          = __phys_to_pfn(BAST_PA_CTRL3),
 112           .length       = SZ_1M,
 113           .type         = MT_DEVICE,
 114   }, {
 115           .virtual      = (u32)BAST_VA_CTRL4,
 116           .pfn          = __phys_to_pfn(BAST_PA_CTRL4),
 117           .length       = SZ_1M,
 118           .type         = MT_DEVICE,
 119   },
 120   /* PC104 IRQ mux */
 121   {
 122           .virtual      = (u32)BAST_VA_PC104_IRQREQ,
 123           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
 124           .length       = SZ_1M,
 125           .type         = MT_DEVICE,
 126   }, {
 127           .virtual      = (u32)BAST_VA_PC104_IRQRAW,
 128           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
 129           .length       = SZ_1M,
 130           .type         = MT_DEVICE,
 131   }, {
 132           .virtual      = (u32)BAST_VA_PC104_IRQMASK,
 133           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
 134           .length       = SZ_1M,
 135           .type         = MT_DEVICE,
 136   },
 137
 138   /* peripheral space... one for each of fast/slow/byte/16bit */
 139   /* note, ide is only decoded in word space, even though some registers
 140    * are only 8bit */
 141
 142   /* slow, byte */
 143   { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 144   { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 145   { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 146
 147   /* slow, word */
 148   { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 149   { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 150   { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 151
 152   /* fast, byte */
 153   { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 154   { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 155   { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 156
 157   /* fast, word */
 158   { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 159   { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 160   { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 161 };
 162
 163 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
 164 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 165 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 166
 167 static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
 168         [0] = {
 169                 .name           = "uclk",
 170                 .divisor        = 1,
 171                 .min_baud       = 0,
 172                 .max_baud       = 0,
 173         },
 174         [1] = {
 175                 .name           = "pclk",
 176                 .divisor        = 1,
 177                 .min_baud       = 0,
 178                 .max_baud       = 0,
 179         }
 180 };
 181
 182
 183 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
 184         [0] = {
 185                 .hwport      = 0,
 186                 .flags       = 0,
 187                 .ucon        = UCON,
 188                 .ulcon       = ULCON,
 189                 .ufcon       = UFCON,
 190                 .clocks      = bast_serial_clocks,
 191                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
 192         },
 193         [1] = {
 194                 .hwport      = 1,
 195                 .flags       = 0,
 196                 .ucon        = UCON,
 197                 .ulcon       = ULCON,
 198                 .ufcon       = UFCON,
 199                 .clocks      = bast_serial_clocks,
 200                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
 201         },
 202         /* port 2 is not actually used */
 203         [2] = {
 204                 .hwport      = 2,
 205                 .flags       = 0,
 206                 .ucon        = UCON,
 207                 .ulcon       = ULCON,
 208                 .ufcon       = UFCON,
 209                 .clocks      = bast_serial_clocks,
 210                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
 211         }
 212 };
 213
 214 /* NAND Flash on BAST board */
 215
 216 #ifdef CONFIG_PM
 217 static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
 218 {
 219         /* ensure that an nRESET is not generated on resume. */
 220         gpio_direction_output(S3C2410_GPA(21), 1);
 221         return 0;
 222 }
 223
 224 static int bast_pm_resume(struct sys_device *sd)
 225 {
 226         s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
 227         return 0;
 228 }
 229
 230 #else
 231 #define bast_pm_suspend NULL
 232 #define bast_pm_resume NULL
 233 #endif
 234
 235 static struct sysdev_class bast_pm_sysclass = {
 236         .name           = "mach-bast",
 237         .suspend        = bast_pm_suspend,
 238         .resume         = bast_pm_resume,
 239 };
 240
 241 static struct sys_device bast_pm_sysdev = {
 242         .cls            = &bast_pm_sysclass,
 243 };
 244
 245 static int smartmedia_map[] = { 0 };
 246 static int chip0_map[] = { 1 };
 247 static int chip1_map[] = { 2 };
 248 static int chip2_map[] = { 3 };
 249
 250 static struct mtd_partition __initdata bast_default_nand_part[] = {
 251         [0] = {
 252                 .name   = "Boot Agent",
 253                 .size   = SZ_16K,
 254                 .offset = 0,
 255         },
 256         [1] = {
 257                 .name   = "/boot",
 258                 .size   = SZ_4M - SZ_16K,
 259                 .offset = SZ_16K,
 260         },
 261         [2] = {
 262                 .name   = "user",
 263                 .offset = SZ_4M,
 264                 .size   = MTDPART_SIZ_FULL,
 265         }
 266 };
 267
 268 /* the bast has 4 selectable slots for nand-flash, the three
 269  * on-board chip areas, as well as the external SmartMedia
 270  * slot.
 271  *
 272  * Note, there is no current hot-plug support for the SmartMedia
 273  * socket.
 274 */
 275
 276 static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
 277         [0] = {
 278                 .name           = "SmartMedia",
 279                 .nr_chips       = 1,
 280                 .nr_map         = smartmedia_map,
 281                 .options        = NAND_SCAN_SILENT_NODEV,
 282                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 283                 .partitions     = bast_default_nand_part,
 284         },
 285         [1] = {
 286                 .name           = "chip0",
 287                 .nr_chips       = 1,
 288                 .nr_map         = chip0_map,
 289                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 290                 .partitions     = bast_default_nand_part,
 291         },
 292         [2] = {
 293                 .name           = "chip1",
 294                 .nr_chips       = 1,
 295                 .nr_map         = chip1_map,
 296                 .options        = NAND_SCAN_SILENT_NODEV,
 297                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 298                 .partitions     = bast_default_nand_part,
 299         },
 300         [3] = {
 301                 .name           = "chip2",
 302                 .nr_chips       = 1,
 303                 .nr_map         = chip2_map,
 304                 .options        = NAND_SCAN_SILENT_NODEV,
 305                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 306                 .partitions     = bast_default_nand_part,
 307         }
 308 };
 309
 310 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
 311 {
 312         unsigned int tmp;
 313
 314         slot = set->nr_map[slot] & 3;
 315
 316         pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
 317                  slot, set, set->nr_map);
 318
 319         tmp = __raw_readb(BAST_VA_CTRL2);
 320         tmp &= BAST_CPLD_CTLR2_IDERST;
 321         tmp |= slot;
 322         tmp |= BAST_CPLD_CTRL2_WNAND;
 323
 324         pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
 325
 326         __raw_writeb(tmp, BAST_VA_CTRL2);
 327 }
 328
 329 static struct s3c2410_platform_nand __initdata bast_nand_info = {
 330         .tacls          = 30,
 331         .twrph0         = 60,
 332         .twrph1         = 60,
 333         .nr_sets        = ARRAY_SIZE(bast_nand_sets),
 334         .sets           = bast_nand_sets,
 335         .select_chip    = bast_nand_select,
 336 };
 337
 338 /* DM9000 */
 339
 340 static struct resource bast_dm9k_resource[] = {
 341         [0] = {
 342                 .start = S3C2410_CS5 + BAST_PA_DM9000,
 343                 .end   = S3C2410_CS5 + BAST_PA_DM9000 + 3,
 344                 .flags = IORESOURCE_MEM,
 345         },
 346         [1] = {
 347                 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
 348                 .end   = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
 349                 .flags = IORESOURCE_MEM,
 350         },
 351         [2] = {
 352                 .start = IRQ_DM9000,
 353                 .end   = IRQ_DM9000,
 354                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 355         }
 356
 357 };
 358
 359 /* for the moment we limit ourselves to 16bit IO until some
 360  * better IO routines can be written and tested
 361 */
 362
 363 static struct dm9000_plat_data bast_dm9k_platdata = {
 364         .flags          = DM9000_PLATF_16BITONLY,
 365 };
 366
 367 static struct platform_device bast_device_dm9k = {
 368         .name           = "dm9000",
 369         .id             = 0,
 370         .num_resources  = ARRAY_SIZE(bast_dm9k_resource),
 371         .resource       = bast_dm9k_resource,
 372         .dev            = {
 373                 .platform_data = &bast_dm9k_platdata,
 374         }
 375 };
 376
 377 /* serial devices */
 378
 379 #define SERIAL_BASE  (S3C2410_CS2 + BAST_PA_SUPERIO)
 380 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
 381 #define SERIAL_CLK   (1843200)
 382
 383 static struct plat_serial8250_port bast_sio_data[] = {
 384         [0] = {
 385                 .mapbase        = SERIAL_BASE + 0x2f8,
 386                 .irq            = IRQ_PCSERIAL1,
 387                 .flags          = SERIAL_FLAGS,
 388                 .iotype         = UPIO_MEM,
 389                 .regshift       = 0,
 390                 .uartclk        = SERIAL_CLK,
 391         },
 392         [1] = {
 393                 .mapbase        = SERIAL_BASE + 0x3f8,
 394                 .irq            = IRQ_PCSERIAL2,
 395                 .flags          = SERIAL_FLAGS,
 396                 .iotype         = UPIO_MEM,
 397                 .regshift       = 0,
 398                 .uartclk        = SERIAL_CLK,
 399         },
 400         { }
 401 };
 402
 403 static struct platform_device bast_sio = {
 404         .name                   = "serial8250",
 405         .id                     = PLAT8250_DEV_PLATFORM,
 406         .dev                    = {
 407                 .platform_data  = &bast_sio_data,
 408         },
 409 };
 410
 411 /* we have devices on the bus which cannot work much over the
 412  * standard 100KHz i2c bus frequency
 413 */
 414
 415 static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
 416         .flags          = 0,
 417         .slave_addr     = 0x10,
 418         .frequency      = 100*1000,
 419 };
 420
 421 /* Asix AX88796 10/100 ethernet controller */
 422
 423 static struct ax_plat_data bast_asix_platdata = {
 424         .flags          = AXFLG_MAC_FROMDEV,
 425         .wordlength     = 2,
 426         .dcr_val        = 0x48,
 427         .rcr_val        = 0x40,
 428 };
 429
 430 static struct resource bast_asix_resource[] = {
 431         [0] = {
 432                 .start = S3C2410_CS5 + BAST_PA_ASIXNET,
 433                 .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
 434                 .flags = IORESOURCE_MEM,
 435         },
 436         [1] = {
 437                 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
 438                 .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
 439                 .flags = IORESOURCE_MEM,
 440         },
 441         [2] = {
 442                 .start = IRQ_ASIX,
 443                 .end   = IRQ_ASIX,
 444                 .flags = IORESOURCE_IRQ
 445         }
 446 };
 447
 448 static struct platform_device bast_device_asix = {
 449         .name           = "ax88796",
 450         .id             = 0,
 451         .num_resources  = ARRAY_SIZE(bast_asix_resource),
 452         .resource       = bast_asix_resource,
 453         .dev            = {
 454                 .platform_data = &bast_asix_platdata
 455         }
 456 };
 457
 458 /* Asix AX88796 10/100 ethernet controller parallel port */
 459
 460 static struct resource bast_asixpp_resource[] = {
 461         [0] = {
 462                 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
 463                 .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
 464                 .flags = IORESOURCE_MEM,
 465         }
 466 };
 467
 468 static struct platform_device bast_device_axpp = {
 469         .name           = "ax88796-pp",
 470         .id             = 0,
 471         .num_resources  = ARRAY_SIZE(bast_asixpp_resource),
 472         .resource       = bast_asixpp_resource,
 473 };
 474
 475 /* LCD/VGA controller */
 476
 477 static struct s3c2410fb_display __initdata bast_lcd_info[] = {
 478         {
 479                 .type           = S3C2410_LCDCON1_TFT,
 480                 .width          = 640,
 481                 .height         = 480,
 482
 483                 .pixclock       = 33333,
 484                 .xres           = 640,
 485                 .yres           = 480,
 486                 .bpp            = 4,
 487                 .left_margin    = 40,
 488                 .right_margin   = 20,
 489                 .hsync_len      = 88,
 490                 .upper_margin   = 30,
 491                 .lower_margin   = 32,
 492                 .vsync_len      = 3,
 493
 494                 .lcdcon5        = 0x00014b02,
 495         },
 496         {
 497                 .type           = S3C2410_LCDCON1_TFT,
 498                 .width          = 640,
 499                 .height         = 480,
 500
 501                 .pixclock       = 33333,
 502                 .xres           = 640,
 503                 .yres           = 480,
 504                 .bpp            = 8,
 505                 .left_margin    = 40,
 506                 .right_margin   = 20,
 507                 .hsync_len      = 88,
 508                 .upper_margin   = 30,
 509                 .lower_margin   = 32,
 510                 .vsync_len      = 3,
 511
 512                 .lcdcon5        = 0x00014b02,
 513         },
 514         {
 515                 .type           = S3C2410_LCDCON1_TFT,
 516                 .width          = 640,
 517                 .height         = 480,
 518
 519                 .pixclock       = 33333,
 520                 .xres           = 640,
 521                 .yres           = 480,
 522                 .bpp            = 16,
 523                 .left_margin    = 40,
 524                 .right_margin   = 20,
 525                 .hsync_len      = 88,
 526                 .upper_margin   = 30,
 527                 .lower_margin   = 32,
 528                 .vsync_len      = 3,
 529
 530                 .lcdcon5        = 0x00014b02,
 531         },
 532 };
 533
 534 /* LCD/VGA controller */
 535
 536 static struct s3c2410fb_mach_info __initdata bast_fb_info = {
 537
 538         .displays = bast_lcd_info,
 539         .num_displays = ARRAY_SIZE(bast_lcd_info),
 540         .default_display = 1,
 541 };
 542
 543 /* I2C devices fitted. */
 544
 545 static struct i2c_board_info bast_i2c_devs[] __initdata = {
 546         {
 547                 I2C_BOARD_INFO("tlv320aic23", 0x1a),
 548         }, {
 549                 I2C_BOARD_INFO("simtec-pmu", 0x6b),
 550         }, {
 551                 I2C_BOARD_INFO("ch7013", 0x75),
 552         },
 553 };
 554
 555 static struct s3c_hwmon_pdata bast_hwmon_info = {
 556         /* LCD contrast (0-6.6V) */
 557         .in[0] = &(struct s3c_hwmon_chcfg) {
 558                 .name           = "lcd-contrast",
 559                 .mult           = 3300,
 560                 .div            = 512,
 561         },
 562         /* LED current feedback */
 563         .in[1] = &(struct s3c_hwmon_chcfg) {
 564                 .name           = "led-feedback",
 565                 .mult           = 3300,
 566                 .div            = 1024,
 567         },
 568         /* LCD feedback (0-6.6V) */
 569         .in[2] = &(struct s3c_hwmon_chcfg) {
 570                 .name           = "lcd-feedback",
 571                 .mult           = 3300,
 572                 .div            = 512,
 573         },
 574         /* Vcore (1.8-2.0V), Vref 3.3V  */
 575         .in[3] = &(struct s3c_hwmon_chcfg) {
 576                 .name           = "vcore",
 577                 .mult           = 3300,
 578                 .div            = 1024,
 579         },
 580 };
 581
 582 /* Standard BAST devices */
 583 // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
 584
 585 static struct platform_device *bast_devices[] __initdata = {
 586         &s3c_device_ohci,
 587         &s3c_device_lcd,
 588         &s3c_device_wdt,
 589         &s3c_device_i2c0,
 590         &s3c_device_rtc,
 591         &s3c_device_nand,
 592         &s3c_device_adc,
 593         &s3c_device_hwmon,
 594         &bast_device_dm9k,
 595         &bast_device_asix,
 596         &bast_device_axpp,
 597         &bast_sio,
 598 };
 599
 600 static struct clk *bast_clocks[] __initdata = {
 601         &s3c24xx_dclk0,
 602         &s3c24xx_dclk1,
 603         &s3c24xx_clkout0,
 604         &s3c24xx_clkout1,
 605         &s3c24xx_uclk,
 606 };
 607
 608 static struct s3c_cpufreq_board __initdata bast_cpufreq = {
 609         .refresh        = 7800, /* 7.8usec */
 610         .auto_io        = 1,
 611         .need_io        = 1,
 612 };
 613
 614 static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
 615         .have_mic       = 1,
 616         .have_lout      = 1,
 617 };
 618
 619 static void __init bast_map_io(void)
 620 {
 621         /* initialise the clocks */
 622
 623         s3c24xx_dclk0.parent = &clk_upll;
 624         s3c24xx_dclk0.rate   = 12*1000*1000;
 625
 626         s3c24xx_dclk1.parent = &clk_upll;
 627         s3c24xx_dclk1.rate   = 24*1000*1000;
 628
 629         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 630         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 631
 632         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 633
 634         s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
 635
 636         s3c_hwmon_set_platdata(&bast_hwmon_info);
 637
 638         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
 639         s3c24xx_init_clocks(0);
 640         s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
 641 }
 642
 643 static void __init bast_init(void)
 644 {
 645         sysdev_class_register(&bast_pm_sysclass);
 646         sysdev_register(&bast_pm_sysdev);
 647
 648         s3c_i2c0_set_platdata(&bast_i2c_info);
 649         s3c_nand_set_platdata(&bast_nand_info);
 650         s3c24xx_fb_set_platdata(&bast_fb_info);
 651         platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
 652
 653         i2c_register_board_info(0, bast_i2c_devs,
 654                                 ARRAY_SIZE(bast_i2c_devs));
 655
 656         usb_simtec_init();
 657         nor_simtec_init();
 658         simtec_audio_add(NULL, true, &bast_audio);
 659
 660         WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
 661
 662         s3c_cpufreq_setboard(&bast_cpufreq);
 663 }
 664
 665 MACHINE_START(BAST, "Simtec-BAST")
 666         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 667         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 668         .map_io         = bast_map_io,
 669         .init_irq       = s3c24xx_init_irq,
 670         .init_machine   = bast_init,
 671         .timer          = &s3c24xx_timer,
 672 MACHINE_END