arch/arm/mach-mx5/board-mx51_babbage.c

   1 /*
   2  * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/init.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/i2c.h>
  16 #include <linux/gpio.h>
  17 #include <linux/delay.h>
  18 #include <linux/io.h>
  19 #include <linux/fsl_devices.h>
  20 #include <linux/fec.h>
  21
  22 #include <mach/common.h>
  23 #include <mach/hardware.h>
  24 #include <mach/iomux-mx51.h>
  25 #include <mach/mxc_ehci.h>
  26
  27 #include <asm/irq.h>
  28 #include <asm/setup.h>
  29 #include <asm/mach-types.h>
  30 #include <asm/mach/arch.h>
  31 #include <asm/mach/time.h>
  32
  33 #include "devices-imx51.h"
  34 #include "devices.h"
  35
  36 #define BABBAGE_USB_HUB_RESET   (0*32 + 7)      /* GPIO_1_7 */
  37 #define BABBAGE_USBH1_STP       (0*32 + 27)     /* GPIO_1_27 */
  38 #define BABBAGE_PHY_RESET       (1*32 + 5)      /* GPIO_2_5 */
  39 #define BABBAGE_FEC_PHY_RESET   (1*32 + 14)     /* GPIO_2_14 */
  40
  41 /* USB_CTRL_1 */
  42 #define MX51_USB_CTRL_1_OFFSET                  0x10
  43 #define MX51_USB_CTRL_UH1_EXT_CLK_EN            (1 << 25)
  44
  45 #define MX51_USB_PLLDIV_12_MHZ          0x00
  46 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
  47 #define MX51_USB_PLL_DIV_24_MHZ 0x02
  48
  49 static struct pad_desc mx51babbage_pads[] = {
  50         /* UART1 */
  51         MX51_PAD_UART1_RXD__UART1_RXD,
  52         MX51_PAD_UART1_TXD__UART1_TXD,
  53         MX51_PAD_UART1_RTS__UART1_RTS,
  54         MX51_PAD_UART1_CTS__UART1_CTS,
  55
  56         /* UART2 */
  57         MX51_PAD_UART2_RXD__UART2_RXD,
  58         MX51_PAD_UART2_TXD__UART2_TXD,
  59
  60         /* UART3 */
  61         MX51_PAD_EIM_D25__UART3_RXD,
  62         MX51_PAD_EIM_D26__UART3_TXD,
  63         MX51_PAD_EIM_D27__UART3_RTS,
  64         MX51_PAD_EIM_D24__UART3_CTS,
  65
  66         /* I2C1 */
  67         MX51_PAD_EIM_D16__I2C1_SDA,
  68         MX51_PAD_EIM_D19__I2C1_SCL,
  69
  70         /* I2C2 */
  71         MX51_PAD_KEY_COL4__I2C2_SCL,
  72         MX51_PAD_KEY_COL5__I2C2_SDA,
  73
  74         /* HSI2C */
  75         MX51_PAD_I2C1_CLK__HSI2C_CLK,
  76         MX51_PAD_I2C1_DAT__HSI2C_DAT,
  77
  78         /* USB HOST1 */
  79         MX51_PAD_USBH1_CLK__USBH1_CLK,
  80         MX51_PAD_USBH1_DIR__USBH1_DIR,
  81         MX51_PAD_USBH1_NXT__USBH1_NXT,
  82         MX51_PAD_USBH1_DATA0__USBH1_DATA0,
  83         MX51_PAD_USBH1_DATA1__USBH1_DATA1,
  84         MX51_PAD_USBH1_DATA2__USBH1_DATA2,
  85         MX51_PAD_USBH1_DATA3__USBH1_DATA3,
  86         MX51_PAD_USBH1_DATA4__USBH1_DATA4,
  87         MX51_PAD_USBH1_DATA5__USBH1_DATA5,
  88         MX51_PAD_USBH1_DATA6__USBH1_DATA6,
  89         MX51_PAD_USBH1_DATA7__USBH1_DATA7,
  90
  91         /* USB HUB reset line*/
  92         MX51_PAD_GPIO_1_7__GPIO_1_7,
  93
  94         /* FEC */
  95         MX51_PAD_EIM_EB2__FEC_MDIO,
  96         MX51_PAD_EIM_EB3__FEC_RDAT1,
  97         MX51_PAD_EIM_CS2__FEC_RDAT2,
  98         MX51_PAD_EIM_CS3__FEC_RDAT3,
  99         MX51_PAD_EIM_CS4__FEC_RX_ER,
 100         MX51_PAD_EIM_CS5__FEC_CRS,
 101         MX51_PAD_NANDF_RB2__FEC_COL,
 102         MX51_PAD_NANDF_RB3__FEC_RXCLK,
 103         MX51_PAD_NANDF_RB6__FEC_RDAT0,
 104         MX51_PAD_NANDF_RB7__FEC_TDAT0,
 105         MX51_PAD_NANDF_CS2__FEC_TX_ER,
 106         MX51_PAD_NANDF_CS3__FEC_MDC,
 107         MX51_PAD_NANDF_CS4__FEC_TDAT1,
 108         MX51_PAD_NANDF_CS5__FEC_TDAT2,
 109         MX51_PAD_NANDF_CS6__FEC_TDAT3,
 110         MX51_PAD_NANDF_CS7__FEC_TX_EN,
 111         MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
 112
 113         /* FEC PHY reset line */
 114         MX51_PAD_EIM_A20__GPIO_2_14,
 115 };
 116
 117 /* Serial ports */
 118 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
 119 static const struct imxuart_platform_data uart_pdata __initconst = {
 120         .flags = IMXUART_HAVE_RTSCTS,
 121 };
 122
 123 static inline void mxc_init_imx_uart(void)
 124 {
 125         imx51_add_imx_uart(0, &uart_pdata);
 126         imx51_add_imx_uart(1, &uart_pdata);
 127         imx51_add_imx_uart(2, &uart_pdata);
 128 }
 129 #else /* !SERIAL_IMX */
 130 static inline void mxc_init_imx_uart(void)
 131 {
 132 }
 133 #endif /* SERIAL_IMX */
 134
 135 static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
 136         .bitrate = 100000,
 137 };
 138
 139 static struct imxi2c_platform_data babbage_hsi2c_data = {
 140         .bitrate = 400000,
 141 };
 142
 143 static int gpio_usbh1_active(void)
 144 {
 145         struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
 146         struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5;
 147         int ret;
 148
 149         /* Set USBH1_STP to GPIO and toggle it */
 150         mxc_iomux_v3_setup_pad(&usbh1stp_gpio);
 151         ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp");
 152
 153         if (ret) {
 154                 pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret);
 155                 return ret;
 156         }
 157         gpio_direction_output(BABBAGE_USBH1_STP, 0);
 158         gpio_set_value(BABBAGE_USBH1_STP, 1);
 159         msleep(100);
 160         gpio_free(BABBAGE_USBH1_STP);
 161
 162         /* De-assert USB PHY RESETB */
 163         mxc_iomux_v3_setup_pad(&phyreset_gpio);
 164         ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset");
 165
 166         if (ret) {
 167                 pr_debug("failed to get MX51_PAD_EIM_D21__GPIO_2_5: %d\n", ret);
 168                 return ret;
 169         }
 170         gpio_direction_output(BABBAGE_PHY_RESET, 1);
 171         return 0;
 172 }
 173
 174 static inline void babbage_usbhub_reset(void)
 175 {
 176         int ret;
 177
 178         /* Bring USB hub out of reset */
 179         ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7");
 180         if (ret) {
 181                 printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
 182                 return;
 183         }
 184         gpio_direction_output(BABBAGE_USB_HUB_RESET, 0);
 185
 186         /* USB HUB RESET - De-assert USB HUB RESET_N */
 187         msleep(1);
 188         gpio_set_value(BABBAGE_USB_HUB_RESET, 0);
 189         msleep(1);
 190         gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
 191 }
 192
 193 static inline void babbage_fec_reset(void)
 194 {
 195         int ret;
 196
 197         /* reset FEC PHY */
 198         ret = gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset");
 199         if (ret) {
 200                 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
 201                 return;
 202         }
 203         gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0);
 204         gpio_set_value(BABBAGE_FEC_PHY_RESET, 0);
 205         msleep(1);
 206         gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
 207 }
 208
 209 /* This function is board specific as the bit mask for the plldiv will also
 210 be different for other Freescale SoCs, thus a common bitmask is not
 211 possible and cannot get place in /plat-mxc/ehci.c.*/
 212 static int initialize_otg_port(struct platform_device *pdev)
 213 {
 214         u32 v;
 215         void __iomem *usb_base;
 216         void __iomem *usbother_base;
 217
 218         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
 219         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 220
 221         /* Set the PHY clock to 19.2MHz */
 222         v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 223         v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
 224         v |= MX51_USB_PLL_DIV_19_2_MHZ;
 225         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 226         iounmap(usb_base);
 227         return 0;
 228 }
 229
 230 static int initialize_usbh1_port(struct platform_device *pdev)
 231 {
 232         u32 v;
 233         void __iomem *usb_base;
 234         void __iomem *usbother_base;
 235
 236         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
 237         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 238
 239         /* The clock for the USBH1 ULPI port will come externally from the PHY. */
 240         v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
 241         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
 242         iounmap(usb_base);
 243         return 0;
 244 }
 245
 246 static struct mxc_usbh_platform_data dr_utmi_config = {
 247         .init           = initialize_otg_port,
 248         .portsc = MXC_EHCI_UTMI_16BIT,
 249         .flags  = MXC_EHCI_INTERNAL_PHY,
 250 };
 251
 252 static struct fsl_usb2_platform_data usb_pdata = {
 253         .operating_mode = FSL_USB2_DR_DEVICE,
 254         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 255 };
 256
 257 static struct mxc_usbh_platform_data usbh1_config = {
 258         .init           = initialize_usbh1_port,
 259         .portsc = MXC_EHCI_MODE_ULPI,
 260         .flags  = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
 261 };
 262
 263 static int otg_mode_host;
 264
 265 static int __init babbage_otg_mode(char *options)
 266 {
 267         if (!strcmp(options, "host"))
 268                 otg_mode_host = 1;
 269         else if (!strcmp(options, "device"))
 270                 otg_mode_host = 0;
 271         else
 272                 pr_info("otg_mode neither \"host\" nor \"device\". "
 273                         "Defaulting to device\n");
 274         return 0;
 275 }
 276 __setup("otg_mode=", babbage_otg_mode);
 277
 278 /*
 279  * Board specific initialization.
 280  */
 281 static void __init mxc_board_init(void)
 282 {
 283         struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
 284
 285         mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
 286                                         ARRAY_SIZE(mx51babbage_pads));
 287         mxc_init_imx_uart();
 288         babbage_fec_reset();
 289         imx51_add_fec(NULL);
 290
 291         imx51_add_imx_i2c(0, &babbage_i2c_data);
 292         imx51_add_imx_i2c(1, &babbage_i2c_data);
 293         mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
 294
 295         if (otg_mode_host)
 296                 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
 297         else {
 298                 initialize_otg_port(NULL);
 299                 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
 300         }
 301
 302         gpio_usbh1_active();
 303         mxc_register_device(&mxc_usbh1_device, &usbh1_config);
 304         /* setback USBH1_STP to be function */
 305         mxc_iomux_v3_setup_pad(&usbh1stp);
 306         babbage_usbhub_reset();
 307 }
 308
 309 static void __init mx51_babbage_timer_init(void)
 310 {
 311         mx51_clocks_init(32768, 24000000, 22579200, 0);
 312 }
 313
 314 static struct sys_timer mxc_timer = {
 315         .init   = mx51_babbage_timer_init,
 316 };
 317
 318 MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
 319         /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
 320         .boot_params = MX51_PHYS_OFFSET + 0x100,
 321         .map_io = mx51_map_io,
 322         .init_irq = mx51_init_irq,
 323         .init_machine = mxc_board_init,
 324         .timer = &mxc_timer,
 325 MACHINE_END