1 /* Copyright 2008-2009 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
13 * Written by Yaniv Rosner
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/pci.h>
20 #include <linux/netdevice.h>
21 #include <linux/delay.h>
22 #include <linux/ethtool.h>
23 #include <linux/mutex.h>
27 /********************************************************/
29 #define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
30 #define ETH_MIN_PACKET_SIZE 60
31 #define ETH_MAX_PACKET_SIZE 1500
32 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
33 #define MDIO_ACCESS_TIMEOUT 1000
34 #define BMAC_CONTROL_RX_ENABLE 2
36 /***********************************************************/
37 /* Shortcut definitions */
38 /***********************************************************/
40 #define NIG_LATCH_BC_ENABLE_MI_INT 0
42 #define NIG_STATUS_EMAC0_MI_INT \
43 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
44 #define NIG_STATUS_XGXS0_LINK10G \
45 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
46 #define NIG_STATUS_XGXS0_LINK_STATUS \
47 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
48 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
49 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
50 #define NIG_STATUS_SERDES0_LINK_STATUS \
51 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
52 #define NIG_MASK_MI_INT \
53 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
54 #define NIG_MASK_XGXS0_LINK10G \
55 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
56 #define NIG_MASK_XGXS0_LINK_STATUS \
57 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
58 #define NIG_MASK_SERDES0_LINK_STATUS \
59 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
61 #define MDIO_AN_CL73_OR_37_COMPLETE \
62 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
63 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
65 #define XGXS_RESET_BITS \
66 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
67 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
68 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
69 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
70 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
72 #define SERDES_RESET_BITS \
73 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
74 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
75 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
76 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
78 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
79 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
80 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
81 #define AUTONEG_PARALLEL \
82 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
83 #define AUTONEG_SGMII_FIBER_AUTODET \
84 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
85 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
87 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
88 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
89 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
90 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
91 #define GP_STATUS_SPEED_MASK \
92 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
93 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
94 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
95 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
96 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
97 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
98 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
99 #define GP_STATUS_10G_HIG \
100 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
101 #define GP_STATUS_10G_CX4 \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
103 #define GP_STATUS_12G_HIG \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
105 #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
106 #define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
107 #define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
108 #define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
109 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
110 #define GP_STATUS_10G_KX4 \
111 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
113 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
114 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
115 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
116 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
117 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
118 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
119 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
120 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
121 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
122 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
123 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
124 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
125 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
126 #define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
127 #define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
128 #define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
129 #define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
130 #define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
131 #define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
132 #define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
133 #define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
134 #define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
135 #define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
137 #define PHY_XGXS_FLAG 0x1
138 #define PHY_SGMII_FLAG 0x2
139 #define PHY_SERDES_FLAG 0x4
142 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
143 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
144 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
147 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
148 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
149 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
150 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
152 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
154 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
156 #define SFP_EEPROM_OPTIONS_ADDR 0x40
157 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
158 #define SFP_EEPROM_OPTIONS_SIZE 2
160 #define EDC_MODE_LINEAR 0x0022
161 #define EDC_MODE_LIMITING 0x0044
162 #define EDC_MODE_PASSIVE_DAC 0x0055
166 /**********************************************************/
168 /**********************************************************/
169 #define CL45_WR_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
170 bnx2x_cl45_write(_bp, _port, 0, _phy_addr, \
171 DEFAULT_PHY_DEV_ADDR, \
172 (_bank + (_addr & 0xf)), \
175 #define CL45_RD_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
176 bnx2x_cl45_read(_bp, _port, 0, _phy_addr, \
177 DEFAULT_PHY_DEV_ADDR, \
178 (_bank + (_addr & 0xf)), \
181 static void bnx2x_set_serdes_access(struct link_params
*params
)
183 struct bnx2x
*bp
= params
->bp
;
184 u32 emac_base
= (params
->port
) ? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
187 REG_WR(bp
, NIG_REG_SERDES0_CTRL_MD_ST
+ params
->port
*0x10, 1);
188 REG_WR(bp
, emac_base
+ EMAC_REG_EMAC_MDIO_COMM
, 0x245f8000);
190 REG_WR(bp
, emac_base
+ EMAC_REG_EMAC_MDIO_COMM
, 0x245d000f);
193 REG_WR(bp
, NIG_REG_SERDES0_CTRL_MD_ST
+ params
->port
*0x10, 0);
195 static void bnx2x_set_phy_mdio(struct link_params
*params
, u8 phy_flags
)
197 struct bnx2x
*bp
= params
->bp
;
199 if (phy_flags
& PHY_XGXS_FLAG
) {
200 REG_WR(bp
, NIG_REG_XGXS0_CTRL_MD_ST
+
201 params
->port
*0x18, 0);
202 REG_WR(bp
, NIG_REG_XGXS0_CTRL_MD_DEVAD
+ params
->port
*0x18,
203 DEFAULT_PHY_DEV_ADDR
);
205 bnx2x_set_serdes_access(params
);
207 REG_WR(bp
, NIG_REG_SERDES0_CTRL_MD_DEVAD
+
209 DEFAULT_PHY_DEV_ADDR
);
213 static u32
bnx2x_bits_en(struct bnx2x
*bp
, u32 reg
, u32 bits
)
215 u32 val
= REG_RD(bp
, reg
);
218 REG_WR(bp
, reg
, val
);
222 static u32
bnx2x_bits_dis(struct bnx2x
*bp
, u32 reg
, u32 bits
)
224 u32 val
= REG_RD(bp
, reg
);
227 REG_WR(bp
, reg
, val
);
231 static void bnx2x_emac_init(struct link_params
*params
,
232 struct link_vars
*vars
)
234 /* reset and unreset the emac core */
235 struct bnx2x
*bp
= params
->bp
;
236 u8 port
= params
->port
;
237 u32 emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
241 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
242 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
<< port
));
244 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
245 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
<< port
));
247 /* init emac - use read-modify-write */
248 /* self clear reset */
249 val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_MODE
);
250 EMAC_WR(bp
, EMAC_REG_EMAC_MODE
, (val
| EMAC_MODE_RESET
));
254 val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_MODE
);
255 DP(NETIF_MSG_LINK
, "EMAC reset reg is %u\n", val
);
257 DP(NETIF_MSG_LINK
, "EMAC timeout!\n");
261 } while (val
& EMAC_MODE_RESET
);
263 /* Set mac address */
264 val
= ((params
->mac_addr
[0] << 8) |
265 params
->mac_addr
[1]);
266 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
, val
);
268 val
= ((params
->mac_addr
[2] << 24) |
269 (params
->mac_addr
[3] << 16) |
270 (params
->mac_addr
[4] << 8) |
271 params
->mac_addr
[5]);
272 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ 4, val
);
275 static u8
bnx2x_emac_enable(struct link_params
*params
,
276 struct link_vars
*vars
, u8 lb
)
278 struct bnx2x
*bp
= params
->bp
;
279 u8 port
= params
->port
;
280 u32 emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
283 DP(NETIF_MSG_LINK
, "enabling EMAC\n");
285 /* enable emac and not bmac */
286 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_PORT
+ port
*4, 1);
289 if (CHIP_REV_IS_EMUL(bp
)) {
290 /* Use lane 1 (of lanes 0-3) */
291 REG_WR(bp
, NIG_REG_XGXS_LANE_SEL_P0
+ port
*4, 1);
292 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+
298 if (CHIP_REV_IS_FPGA(bp
)) {
299 /* Use lane 1 (of lanes 0-3) */
300 DP(NETIF_MSG_LINK
, "bnx2x_emac_enable: Setting FPGA\n");
302 REG_WR(bp
, NIG_REG_XGXS_LANE_SEL_P0
+ port
*4, 1);
303 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
*4,
307 if (vars
->phy_flags
& PHY_XGXS_FLAG
) {
308 u32 ser_lane
= ((params
->lane_config
&
309 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
310 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
312 DP(NETIF_MSG_LINK
, "XGXS\n");
313 /* select the master lanes (out of 0-3) */
314 REG_WR(bp
, NIG_REG_XGXS_LANE_SEL_P0
+
317 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+
320 } else { /* SerDes */
321 DP(NETIF_MSG_LINK
, "SerDes\n");
323 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+
327 bnx2x_bits_en(bp
, emac_base
+ EMAC_REG_EMAC_RX_MODE
,
329 bnx2x_bits_en(bp
, emac_base
+ EMAC_REG_EMAC_TX_MODE
,
332 if (CHIP_REV_IS_SLOW(bp
)) {
333 /* config GMII mode */
334 val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_MODE
);
335 EMAC_WR(bp
, EMAC_REG_EMAC_MODE
,
336 (val
| EMAC_MODE_PORT_GMII
));
338 /* pause enable/disable */
339 bnx2x_bits_dis(bp
, emac_base
+ EMAC_REG_EMAC_RX_MODE
,
340 EMAC_RX_MODE_FLOW_EN
);
341 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_RX
)
342 bnx2x_bits_en(bp
, emac_base
+
343 EMAC_REG_EMAC_RX_MODE
,
344 EMAC_RX_MODE_FLOW_EN
);
346 bnx2x_bits_dis(bp
, emac_base
+ EMAC_REG_EMAC_TX_MODE
,
347 (EMAC_TX_MODE_EXT_PAUSE_EN
|
348 EMAC_TX_MODE_FLOW_EN
));
349 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
350 bnx2x_bits_en(bp
, emac_base
+
351 EMAC_REG_EMAC_TX_MODE
,
352 (EMAC_TX_MODE_EXT_PAUSE_EN
|
353 EMAC_TX_MODE_FLOW_EN
));
356 /* KEEP_VLAN_TAG, promiscuous */
357 val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_RX_MODE
);
358 val
|= EMAC_RX_MODE_KEEP_VLAN_TAG
| EMAC_RX_MODE_PROMISCUOUS
;
359 EMAC_WR(bp
, EMAC_REG_EMAC_RX_MODE
, val
);
362 val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_MODE
);
367 EMAC_WR(bp
, EMAC_REG_EMAC_MODE
, val
);
370 REG_WR(bp
, NIG_REG_NIG_EMAC0_EN
+ port
*4, 1);
372 /* enable emac for jumbo packets */
373 EMAC_WR(bp
, EMAC_REG_EMAC_RX_MTU_SIZE
,
374 (EMAC_RX_MTU_SIZE_JUMBO_ENA
|
375 (ETH_MAX_JUMBO_PACKET_SIZE
+ ETH_OVREHEAD
)));
378 REG_WR(bp
, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC
+ port
*4, 0x1);
380 /* disable the NIG in/out to the bmac */
381 REG_WR(bp
, NIG_REG_BMAC0_IN_EN
+ port
*4, 0x0);
382 REG_WR(bp
, NIG_REG_BMAC0_PAUSE_OUT_EN
+ port
*4, 0x0);
383 REG_WR(bp
, NIG_REG_BMAC0_OUT_EN
+ port
*4, 0x0);
385 /* enable the NIG in/out to the emac */
386 REG_WR(bp
, NIG_REG_EMAC0_IN_EN
+ port
*4, 0x1);
388 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
391 REG_WR(bp
, NIG_REG_EMAC0_PAUSE_OUT_EN
+ port
*4, val
);
392 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_OUT_EN
+ port
*4, 0x1);
394 if (CHIP_REV_IS_EMUL(bp
)) {
395 /* take the BigMac out of reset */
397 GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
398 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
400 /* enable access for bmac registers */
401 REG_WR(bp
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
*4, 0x1);
403 REG_WR(bp
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
*4, 0x0);
405 vars
->mac_type
= MAC_TYPE_EMAC
;
411 static u8
bnx2x_bmac_enable(struct link_params
*params
, struct link_vars
*vars
,
414 struct bnx2x
*bp
= params
->bp
;
415 u8 port
= params
->port
;
416 u32 bmac_addr
= port
? NIG_REG_INGRESS_BMAC1_MEM
:
417 NIG_REG_INGRESS_BMAC0_MEM
;
421 DP(NETIF_MSG_LINK
, "Enabling BigMAC\n");
422 /* reset and unreset the BigMac */
423 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
424 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
427 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
428 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
430 /* enable access for bmac registers */
431 REG_WR(bp
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
*4, 0x1);
436 REG_WR_DMAE(bp
, bmac_addr
+
437 BIGMAC_REGISTER_BMAC_XGXS_CONTROL
,
441 wb_data
[0] = ((params
->mac_addr
[2] << 24) |
442 (params
->mac_addr
[3] << 16) |
443 (params
->mac_addr
[4] << 8) |
444 params
->mac_addr
[5]);
445 wb_data
[1] = ((params
->mac_addr
[0] << 8) |
446 params
->mac_addr
[1]);
447 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_TX_SOURCE_ADDR
,
452 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
456 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_TX_CONTROL
,
463 DP(NETIF_MSG_LINK
, "enable bmac loopback\n");
467 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_BMAC_CONTROL
,
471 wb_data
[0] = ETH_MAX_JUMBO_PACKET_SIZE
+ ETH_OVREHEAD
;
473 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_RX_MAX_SIZE
,
476 /* rx control set to don't strip crc */
478 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_RX
)
482 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_RX_CONTROL
,
486 wb_data
[0] = ETH_MAX_JUMBO_PACKET_SIZE
+ ETH_OVREHEAD
;
488 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_TX_MAX_SIZE
,
491 /* set cnt max size */
492 wb_data
[0] = ETH_MAX_JUMBO_PACKET_SIZE
+ ETH_OVREHEAD
;
494 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_CNT_MAX_SIZE
,
498 wb_data
[0] = 0x1000200;
500 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_RX_LLFC_MSG_FLDS
,
502 /* fix for emulation */
503 if (CHIP_REV_IS_EMUL(bp
)) {
507 bmac_addr
+ BIGMAC_REGISTER_TX_PAUSE_THRESHOLD
,
511 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
*4, 0x1);
512 REG_WR(bp
, NIG_REG_XGXS_LANE_SEL_P0
+ port
*4, 0x0);
513 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_PORT
+ port
*4, 0x0);
515 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
517 REG_WR(bp
, NIG_REG_BMAC0_PAUSE_OUT_EN
+ port
*4, val
);
518 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_OUT_EN
+ port
*4, 0x0);
519 REG_WR(bp
, NIG_REG_EMAC0_IN_EN
+ port
*4, 0x0);
520 REG_WR(bp
, NIG_REG_EMAC0_PAUSE_OUT_EN
+ port
*4, 0x0);
521 REG_WR(bp
, NIG_REG_BMAC0_IN_EN
+ port
*4, 0x1);
522 REG_WR(bp
, NIG_REG_BMAC0_OUT_EN
+ port
*4, 0x1);
524 vars
->mac_type
= MAC_TYPE_BMAC
;
528 static void bnx2x_phy_deassert(struct link_params
*params
, u8 phy_flags
)
530 struct bnx2x
*bp
= params
->bp
;
533 if (phy_flags
& PHY_XGXS_FLAG
) {
534 DP(NETIF_MSG_LINK
, "bnx2x_phy_deassert:XGXS\n");
535 val
= XGXS_RESET_BITS
;
537 } else { /* SerDes */
538 DP(NETIF_MSG_LINK
, "bnx2x_phy_deassert:SerDes\n");
539 val
= SERDES_RESET_BITS
;
542 val
= val
<< (params
->port
*16);
544 /* reset and unreset the SerDes/XGXS */
545 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_CLEAR
,
548 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_SET
,
550 bnx2x_set_phy_mdio(params
, phy_flags
);
553 void bnx2x_link_status_update(struct link_params
*params
,
554 struct link_vars
*vars
)
556 struct bnx2x
*bp
= params
->bp
;
558 u8 port
= params
->port
;
560 if (params
->switch_cfg
== SWITCH_CFG_1G
)
561 vars
->phy_flags
= PHY_SERDES_FLAG
;
563 vars
->phy_flags
= PHY_XGXS_FLAG
;
564 vars
->link_status
= REG_RD(bp
, params
->shmem_base
+
565 offsetof(struct shmem_region
,
566 port_mb
[port
].link_status
));
568 vars
->link_up
= (vars
->link_status
& LINK_STATUS_LINK_UP
);
571 DP(NETIF_MSG_LINK
, "phy link up\n");
573 vars
->phy_link_up
= 1;
574 vars
->duplex
= DUPLEX_FULL
;
575 switch (vars
->link_status
&
576 LINK_STATUS_SPEED_AND_DUPLEX_MASK
) {
578 vars
->duplex
= DUPLEX_HALF
;
581 vars
->line_speed
= SPEED_10
;
585 vars
->duplex
= DUPLEX_HALF
;
589 vars
->line_speed
= SPEED_100
;
593 vars
->duplex
= DUPLEX_HALF
;
596 vars
->line_speed
= SPEED_1000
;
600 vars
->duplex
= DUPLEX_HALF
;
603 vars
->line_speed
= SPEED_2500
;
607 vars
->line_speed
= SPEED_10000
;
611 vars
->line_speed
= SPEED_12000
;
615 vars
->line_speed
= SPEED_12500
;
619 vars
->line_speed
= SPEED_13000
;
623 vars
->line_speed
= SPEED_15000
;
627 vars
->line_speed
= SPEED_16000
;
634 if (vars
->link_status
& LINK_STATUS_TX_FLOW_CONTROL_ENABLED
)
635 vars
->flow_ctrl
|= BNX2X_FLOW_CTRL_TX
;
637 vars
->flow_ctrl
&= ~BNX2X_FLOW_CTRL_TX
;
639 if (vars
->link_status
& LINK_STATUS_RX_FLOW_CONTROL_ENABLED
)
640 vars
->flow_ctrl
|= BNX2X_FLOW_CTRL_RX
;
642 vars
->flow_ctrl
&= ~BNX2X_FLOW_CTRL_RX
;
644 if (vars
->phy_flags
& PHY_XGXS_FLAG
) {
645 if (vars
->line_speed
&&
646 ((vars
->line_speed
== SPEED_10
) ||
647 (vars
->line_speed
== SPEED_100
))) {
648 vars
->phy_flags
|= PHY_SGMII_FLAG
;
650 vars
->phy_flags
&= ~PHY_SGMII_FLAG
;
654 /* anything 10 and over uses the bmac */
655 link_10g
= ((vars
->line_speed
== SPEED_10000
) ||
656 (vars
->line_speed
== SPEED_12000
) ||
657 (vars
->line_speed
== SPEED_12500
) ||
658 (vars
->line_speed
== SPEED_13000
) ||
659 (vars
->line_speed
== SPEED_15000
) ||
660 (vars
->line_speed
== SPEED_16000
));
662 vars
->mac_type
= MAC_TYPE_BMAC
;
664 vars
->mac_type
= MAC_TYPE_EMAC
;
666 } else { /* link down */
667 DP(NETIF_MSG_LINK
, "phy link down\n");
669 vars
->phy_link_up
= 0;
671 vars
->line_speed
= 0;
672 vars
->duplex
= DUPLEX_FULL
;
673 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
675 /* indicate no mac active */
676 vars
->mac_type
= MAC_TYPE_NONE
;
679 DP(NETIF_MSG_LINK
, "link_status 0x%x phy_link_up %x\n",
680 vars
->link_status
, vars
->phy_link_up
);
681 DP(NETIF_MSG_LINK
, "line_speed %x duplex %x flow_ctrl 0x%x\n",
682 vars
->line_speed
, vars
->duplex
, vars
->flow_ctrl
);
685 static void bnx2x_update_mng(struct link_params
*params
, u32 link_status
)
687 struct bnx2x
*bp
= params
->bp
;
689 REG_WR(bp
, params
->shmem_base
+
690 offsetof(struct shmem_region
,
691 port_mb
[params
->port
].link_status
),
695 static void bnx2x_bmac_rx_disable(struct bnx2x
*bp
, u8 port
)
697 u32 bmac_addr
= port
? NIG_REG_INGRESS_BMAC1_MEM
:
698 NIG_REG_INGRESS_BMAC0_MEM
;
700 u32 nig_bmac_enable
= REG_RD(bp
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
*4);
702 /* Only if the bmac is out of reset */
703 if (REG_RD(bp
, MISC_REG_RESET_REG_2
) &
704 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
) &&
707 /* Clear Rx Enable bit in BMAC_CONTROL register */
708 REG_RD_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_BMAC_CONTROL
,
710 wb_data
[0] &= ~BMAC_CONTROL_RX_ENABLE
;
711 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_BMAC_CONTROL
,
718 static u8
bnx2x_pbf_update(struct link_params
*params
, u32 flow_ctrl
,
721 struct bnx2x
*bp
= params
->bp
;
722 u8 port
= params
->port
;
727 REG_WR(bp
, PBF_REG_DISABLE_NEW_TASK_PROC_P0
+ port
*4, 0x1);
729 /* wait for init credit */
730 init_crd
= REG_RD(bp
, PBF_REG_P0_INIT_CRD
+ port
*4);
731 crd
= REG_RD(bp
, PBF_REG_P0_CREDIT
+ port
*8);
732 DP(NETIF_MSG_LINK
, "init_crd 0x%x crd 0x%x\n", init_crd
, crd
);
734 while ((init_crd
!= crd
) && count
) {
737 crd
= REG_RD(bp
, PBF_REG_P0_CREDIT
+ port
*8);
740 crd
= REG_RD(bp
, PBF_REG_P0_CREDIT
+ port
*8);
741 if (init_crd
!= crd
) {
742 DP(NETIF_MSG_LINK
, "BUG! init_crd 0x%x != crd 0x%x\n",
747 if (flow_ctrl
& BNX2X_FLOW_CTRL_RX
||
748 line_speed
== SPEED_10
||
749 line_speed
== SPEED_100
||
750 line_speed
== SPEED_1000
||
751 line_speed
== SPEED_2500
) {
752 REG_WR(bp
, PBF_REG_P0_PAUSE_ENABLE
+ port
*4, 1);
753 /* update threshold */
754 REG_WR(bp
, PBF_REG_P0_ARB_THRSH
+ port
*4, 0);
755 /* update init credit */
756 init_crd
= 778; /* (800-18-4) */
759 u32 thresh
= (ETH_MAX_JUMBO_PACKET_SIZE
+
761 REG_WR(bp
, PBF_REG_P0_PAUSE_ENABLE
+ port
*4, 0);
762 /* update threshold */
763 REG_WR(bp
, PBF_REG_P0_ARB_THRSH
+ port
*4, thresh
);
764 /* update init credit */
765 switch (line_speed
) {
767 init_crd
= thresh
+ 553 - 22;
771 init_crd
= thresh
+ 664 - 22;
775 init_crd
= thresh
+ 742 - 22;
779 init_crd
= thresh
+ 778 - 22;
782 DP(NETIF_MSG_LINK
, "Invalid line_speed 0x%x\n",
787 REG_WR(bp
, PBF_REG_P0_INIT_CRD
+ port
*4, init_crd
);
788 DP(NETIF_MSG_LINK
, "PBF updated to speed %d credit %d\n",
789 line_speed
, init_crd
);
791 /* probe the credit changes */
792 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 0x1);
794 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 0x0);
797 REG_WR(bp
, PBF_REG_DISABLE_NEW_TASK_PROC_P0
+ port
*4, 0x0);
801 static u32
bnx2x_get_emac_base(struct bnx2x
*bp
, u32 ext_phy_type
, u8 port
)
805 switch (ext_phy_type
) {
806 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
:
807 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
808 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
809 /* All MDC/MDIO is directed through single EMAC */
810 if (REG_RD(bp
, NIG_REG_PORT_SWAP
))
811 emac_base
= GRCBASE_EMAC0
;
813 emac_base
= GRCBASE_EMAC1
;
815 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
:
816 emac_base
= (port
) ? GRCBASE_EMAC0
: GRCBASE_EMAC1
;
819 emac_base
= (port
) ? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
826 u8
bnx2x_cl45_write(struct bnx2x
*bp
, u8 port
, u32 ext_phy_type
,
827 u8 phy_addr
, u8 devad
, u16 reg
, u16 val
)
831 u32 mdio_ctrl
= bnx2x_get_emac_base(bp
, ext_phy_type
, port
);
833 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
834 * (a value of 49==0x31) and make sure that the AUTO poll is off
837 saved_mode
= REG_RD(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
);
838 tmp
= saved_mode
& ~(EMAC_MDIO_MODE_AUTO_POLL
|
839 EMAC_MDIO_MODE_CLOCK_CNT
);
840 tmp
|= (EMAC_MDIO_MODE_CLAUSE_45
|
841 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT
));
842 REG_WR(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
, tmp
);
843 REG_RD(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
);
848 tmp
= ((phy_addr
<< 21) | (devad
<< 16) | reg
|
849 EMAC_MDIO_COMM_COMMAND_ADDRESS
|
850 EMAC_MDIO_COMM_START_BUSY
);
851 REG_WR(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, tmp
);
853 for (i
= 0; i
< 50; i
++) {
856 tmp
= REG_RD(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
);
857 if (!(tmp
& EMAC_MDIO_COMM_START_BUSY
)) {
862 if (tmp
& EMAC_MDIO_COMM_START_BUSY
) {
863 DP(NETIF_MSG_LINK
, "write phy register failed\n");
867 tmp
= ((phy_addr
<< 21) | (devad
<< 16) | val
|
868 EMAC_MDIO_COMM_COMMAND_WRITE_45
|
869 EMAC_MDIO_COMM_START_BUSY
);
870 REG_WR(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, tmp
);
872 for (i
= 0; i
< 50; i
++) {
875 tmp
= REG_RD(bp
, mdio_ctrl
+
876 EMAC_REG_EMAC_MDIO_COMM
);
877 if (!(tmp
& EMAC_MDIO_COMM_START_BUSY
)) {
882 if (tmp
& EMAC_MDIO_COMM_START_BUSY
) {
883 DP(NETIF_MSG_LINK
, "write phy register failed\n");
888 /* Restore the saved mode */
889 REG_WR(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
, saved_mode
);
894 u8
bnx2x_cl45_read(struct bnx2x
*bp
, u8 port
, u32 ext_phy_type
,
895 u8 phy_addr
, u8 devad
, u16 reg
, u16
*ret_val
)
901 u32 mdio_ctrl
= bnx2x_get_emac_base(bp
, ext_phy_type
, port
);
902 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
903 * (a value of 49==0x31) and make sure that the AUTO poll is off
906 saved_mode
= REG_RD(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
);
907 val
= saved_mode
& ((EMAC_MDIO_MODE_AUTO_POLL
|
908 EMAC_MDIO_MODE_CLOCK_CNT
));
909 val
|= (EMAC_MDIO_MODE_CLAUSE_45
|
910 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT
));
911 REG_WR(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
, val
);
912 REG_RD(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
);
916 val
= ((phy_addr
<< 21) | (devad
<< 16) | reg
|
917 EMAC_MDIO_COMM_COMMAND_ADDRESS
|
918 EMAC_MDIO_COMM_START_BUSY
);
919 REG_WR(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, val
);
921 for (i
= 0; i
< 50; i
++) {
924 val
= REG_RD(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
);
925 if (!(val
& EMAC_MDIO_COMM_START_BUSY
)) {
930 if (val
& EMAC_MDIO_COMM_START_BUSY
) {
931 DP(NETIF_MSG_LINK
, "read phy register failed\n");
938 val
= ((phy_addr
<< 21) | (devad
<< 16) |
939 EMAC_MDIO_COMM_COMMAND_READ_45
|
940 EMAC_MDIO_COMM_START_BUSY
);
941 REG_WR(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, val
);
943 for (i
= 0; i
< 50; i
++) {
946 val
= REG_RD(bp
, mdio_ctrl
+
947 EMAC_REG_EMAC_MDIO_COMM
);
948 if (!(val
& EMAC_MDIO_COMM_START_BUSY
)) {
949 *ret_val
= (u16
)(val
& EMAC_MDIO_COMM_DATA
);
953 if (val
& EMAC_MDIO_COMM_START_BUSY
) {
954 DP(NETIF_MSG_LINK
, "read phy register failed\n");
961 /* Restore the saved mode */
962 REG_WR(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
, saved_mode
);
967 static void bnx2x_set_aer_mmd(struct link_params
*params
,
968 struct link_vars
*vars
)
970 struct bnx2x
*bp
= params
->bp
;
974 ser_lane
= ((params
->lane_config
&
975 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
976 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
978 offset
= (vars
->phy_flags
& PHY_XGXS_FLAG
) ?
979 (params
->phy_addr
+ ser_lane
) : 0;
981 CL45_WR_OVER_CL22(bp
, params
->port
,
983 MDIO_REG_BANK_AER_BLOCK
,
984 MDIO_AER_BLOCK_AER_REG
, 0x3800 + offset
);
987 static void bnx2x_set_master_ln(struct link_params
*params
)
989 struct bnx2x
*bp
= params
->bp
;
990 u16 new_master_ln
, ser_lane
;
991 ser_lane
= ((params
->lane_config
&
992 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
993 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
995 /* set the master_ln for AN */
996 CL45_RD_OVER_CL22(bp
, params
->port
,
998 MDIO_REG_BANK_XGXS_BLOCK2
,
999 MDIO_XGXS_BLOCK2_TEST_MODE_LANE
,
1002 CL45_WR_OVER_CL22(bp
, params
->port
,
1004 MDIO_REG_BANK_XGXS_BLOCK2
,
1005 MDIO_XGXS_BLOCK2_TEST_MODE_LANE
,
1006 (new_master_ln
| ser_lane
));
1009 static u8
bnx2x_reset_unicore(struct link_params
*params
)
1011 struct bnx2x
*bp
= params
->bp
;
1015 CL45_RD_OVER_CL22(bp
, params
->port
,
1017 MDIO_REG_BANK_COMBO_IEEE0
,
1018 MDIO_COMBO_IEEE0_MII_CONTROL
, &mii_control
);
1020 /* reset the unicore */
1021 CL45_WR_OVER_CL22(bp
, params
->port
,
1023 MDIO_REG_BANK_COMBO_IEEE0
,
1024 MDIO_COMBO_IEEE0_MII_CONTROL
,
1026 MDIO_COMBO_IEEO_MII_CONTROL_RESET
));
1027 if (params
->switch_cfg
== SWITCH_CFG_1G
)
1028 bnx2x_set_serdes_access(params
);
1030 /* wait for the reset to self clear */
1031 for (i
= 0; i
< MDIO_ACCESS_TIMEOUT
; i
++) {
1034 /* the reset erased the previous bank value */
1035 CL45_RD_OVER_CL22(bp
, params
->port
,
1037 MDIO_REG_BANK_COMBO_IEEE0
,
1038 MDIO_COMBO_IEEE0_MII_CONTROL
,
1041 if (!(mii_control
& MDIO_COMBO_IEEO_MII_CONTROL_RESET
)) {
1047 DP(NETIF_MSG_LINK
, "BUG! XGXS is still in reset!\n");
1052 static void bnx2x_set_swap_lanes(struct link_params
*params
)
1054 struct bnx2x
*bp
= params
->bp
;
1055 /* Each two bits represents a lane number:
1056 No swap is 0123 => 0x1b no need to enable the swap */
1057 u16 ser_lane
, rx_lane_swap
, tx_lane_swap
;
1059 ser_lane
= ((params
->lane_config
&
1060 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
1061 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
1062 rx_lane_swap
= ((params
->lane_config
&
1063 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK
) >>
1064 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT
);
1065 tx_lane_swap
= ((params
->lane_config
&
1066 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK
) >>
1067 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT
);
1069 if (rx_lane_swap
!= 0x1b) {
1070 CL45_WR_OVER_CL22(bp
, params
->port
,
1072 MDIO_REG_BANK_XGXS_BLOCK2
,
1073 MDIO_XGXS_BLOCK2_RX_LN_SWAP
,
1075 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE
|
1076 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE
));
1078 CL45_WR_OVER_CL22(bp
, params
->port
,
1080 MDIO_REG_BANK_XGXS_BLOCK2
,
1081 MDIO_XGXS_BLOCK2_RX_LN_SWAP
, 0);
1084 if (tx_lane_swap
!= 0x1b) {
1085 CL45_WR_OVER_CL22(bp
, params
->port
,
1087 MDIO_REG_BANK_XGXS_BLOCK2
,
1088 MDIO_XGXS_BLOCK2_TX_LN_SWAP
,
1090 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE
));
1092 CL45_WR_OVER_CL22(bp
, params
->port
,
1094 MDIO_REG_BANK_XGXS_BLOCK2
,
1095 MDIO_XGXS_BLOCK2_TX_LN_SWAP
, 0);
1099 static void bnx2x_set_parallel_detection(struct link_params
*params
,
1102 struct bnx2x
*bp
= params
->bp
;
1105 CL45_RD_OVER_CL22(bp
, params
->port
,
1107 MDIO_REG_BANK_SERDES_DIGITAL
,
1108 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2
,
1110 if (params
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)
1111 control2
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN
;
1113 control2
&= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN
;
1114 DP(NETIF_MSG_LINK
, "params->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1115 params
->speed_cap_mask
, control2
);
1116 CL45_WR_OVER_CL22(bp
, params
->port
,
1118 MDIO_REG_BANK_SERDES_DIGITAL
,
1119 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2
,
1122 if ((phy_flags
& PHY_XGXS_FLAG
) &&
1123 (params
->speed_cap_mask
&
1124 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)) {
1125 DP(NETIF_MSG_LINK
, "XGXS\n");
1127 CL45_WR_OVER_CL22(bp
, params
->port
,
1129 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
1130 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK
,
1131 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT
);
1133 CL45_RD_OVER_CL22(bp
, params
->port
,
1135 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
1136 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL
,
1141 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN
;
1143 CL45_WR_OVER_CL22(bp
, params
->port
,
1145 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
1146 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL
,
1149 /* Disable parallel detection of HiG */
1150 CL45_WR_OVER_CL22(bp
, params
->port
,
1152 MDIO_REG_BANK_XGXS_BLOCK2
,
1153 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G
,
1154 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS
|
1155 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS
);
1159 static void bnx2x_set_autoneg(struct link_params
*params
,
1160 struct link_vars
*vars
,
1163 struct bnx2x
*bp
= params
->bp
;
1168 CL45_RD_OVER_CL22(bp
, params
->port
,
1170 MDIO_REG_BANK_COMBO_IEEE0
,
1171 MDIO_COMBO_IEEE0_MII_CONTROL
, ®_val
);
1173 /* CL37 Autoneg Enabled */
1174 if (vars
->line_speed
== SPEED_AUTO_NEG
)
1175 reg_val
|= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
;
1176 else /* CL37 Autoneg Disabled */
1177 reg_val
&= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
1178 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN
);
1180 CL45_WR_OVER_CL22(bp
, params
->port
,
1182 MDIO_REG_BANK_COMBO_IEEE0
,
1183 MDIO_COMBO_IEEE0_MII_CONTROL
, reg_val
);
1185 /* Enable/Disable Autodetection */
1187 CL45_RD_OVER_CL22(bp
, params
->port
,
1189 MDIO_REG_BANK_SERDES_DIGITAL
,
1190 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
, ®_val
);
1191 reg_val
&= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN
|
1192 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT
);
1193 reg_val
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE
;
1194 if (vars
->line_speed
== SPEED_AUTO_NEG
)
1195 reg_val
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET
;
1197 reg_val
&= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET
;
1199 CL45_WR_OVER_CL22(bp
, params
->port
,
1201 MDIO_REG_BANK_SERDES_DIGITAL
,
1202 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
, reg_val
);
1204 /* Enable TetonII and BAM autoneg */
1205 CL45_RD_OVER_CL22(bp
, params
->port
,
1207 MDIO_REG_BANK_BAM_NEXT_PAGE
,
1208 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL
,
1210 if (vars
->line_speed
== SPEED_AUTO_NEG
) {
1211 /* Enable BAM aneg Mode and TetonII aneg Mode */
1212 reg_val
|= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE
|
1213 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN
);
1215 /* TetonII and BAM Autoneg Disabled */
1216 reg_val
&= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE
|
1217 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN
);
1219 CL45_WR_OVER_CL22(bp
, params
->port
,
1221 MDIO_REG_BANK_BAM_NEXT_PAGE
,
1222 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL
,
1226 /* Enable Cl73 FSM status bits */
1227 CL45_WR_OVER_CL22(bp
, params
->port
,
1229 MDIO_REG_BANK_CL73_USERB0
,
1230 MDIO_CL73_USERB0_CL73_UCTRL
,
1233 /* Enable BAM Station Manager*/
1234 CL45_WR_OVER_CL22(bp
, params
->port
,
1236 MDIO_REG_BANK_CL73_USERB0
,
1237 MDIO_CL73_USERB0_CL73_BAM_CTRL1
,
1238 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN
|
1239 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN
|
1240 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN
);
1242 /* Advertise CL73 link speeds */
1243 CL45_RD_OVER_CL22(bp
, params
->port
,
1245 MDIO_REG_BANK_CL73_IEEEB1
,
1246 MDIO_CL73_IEEEB1_AN_ADV2
,
1248 if (params
->speed_cap_mask
&
1249 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
1250 reg_val
|= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4
;
1251 if (params
->speed_cap_mask
&
1252 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)
1253 reg_val
|= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX
;
1255 CL45_WR_OVER_CL22(bp
, params
->port
,
1257 MDIO_REG_BANK_CL73_IEEEB1
,
1258 MDIO_CL73_IEEEB1_AN_ADV2
,
1261 /* CL73 Autoneg Enabled */
1262 reg_val
= MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN
;
1264 } else /* CL73 Autoneg Disabled */
1267 CL45_WR_OVER_CL22(bp
, params
->port
,
1269 MDIO_REG_BANK_CL73_IEEEB0
,
1270 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
, reg_val
);
1273 /* program SerDes, forced speed */
1274 static void bnx2x_program_serdes(struct link_params
*params
,
1275 struct link_vars
*vars
)
1277 struct bnx2x
*bp
= params
->bp
;
1280 /* program duplex, disable autoneg and sgmii*/
1281 CL45_RD_OVER_CL22(bp
, params
->port
,
1283 MDIO_REG_BANK_COMBO_IEEE0
,
1284 MDIO_COMBO_IEEE0_MII_CONTROL
, ®_val
);
1285 reg_val
&= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
|
1286 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
1287 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK
);
1288 if (params
->req_duplex
== DUPLEX_FULL
)
1289 reg_val
|= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
;
1290 CL45_WR_OVER_CL22(bp
, params
->port
,
1292 MDIO_REG_BANK_COMBO_IEEE0
,
1293 MDIO_COMBO_IEEE0_MII_CONTROL
, reg_val
);
1296 - needed only if the speed is greater than 1G (2.5G or 10G) */
1297 CL45_RD_OVER_CL22(bp
, params
->port
,
1299 MDIO_REG_BANK_SERDES_DIGITAL
,
1300 MDIO_SERDES_DIGITAL_MISC1
, ®_val
);
1301 /* clearing the speed value before setting the right speed */
1302 DP(NETIF_MSG_LINK
, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val
);
1304 reg_val
&= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK
|
1305 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL
);
1307 if (!((vars
->line_speed
== SPEED_1000
) ||
1308 (vars
->line_speed
== SPEED_100
) ||
1309 (vars
->line_speed
== SPEED_10
))) {
1311 reg_val
|= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M
|
1312 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL
);
1313 if (vars
->line_speed
== SPEED_10000
)
1315 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4
;
1316 if (vars
->line_speed
== SPEED_13000
)
1318 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G
;
1321 CL45_WR_OVER_CL22(bp
, params
->port
,
1323 MDIO_REG_BANK_SERDES_DIGITAL
,
1324 MDIO_SERDES_DIGITAL_MISC1
, reg_val
);
1328 static void bnx2x_set_brcm_cl37_advertisment(struct link_params
*params
)
1330 struct bnx2x
*bp
= params
->bp
;
1333 /* configure the 48 bits for BAM AN */
1335 /* set extended capabilities */
1336 if (params
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
)
1337 val
|= MDIO_OVER_1G_UP1_2_5G
;
1338 if (params
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
1339 val
|= MDIO_OVER_1G_UP1_10G
;
1340 CL45_WR_OVER_CL22(bp
, params
->port
,
1342 MDIO_REG_BANK_OVER_1G
,
1343 MDIO_OVER_1G_UP1
, val
);
1345 CL45_WR_OVER_CL22(bp
, params
->port
,
1347 MDIO_REG_BANK_OVER_1G
,
1348 MDIO_OVER_1G_UP3
, 0x400);
1351 static void bnx2x_calc_ieee_aneg_adv(struct link_params
*params
, u16
*ieee_fc
)
1353 struct bnx2x
*bp
= params
->bp
;
1354 *ieee_fc
= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX
;
1355 /* resolve pause mode and advertisement
1356 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
1358 switch (params
->req_flow_ctrl
) {
1359 case BNX2X_FLOW_CTRL_AUTO
:
1360 if (params
->req_fc_auto_adv
== BNX2X_FLOW_CTRL_BOTH
) {
1362 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
1365 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
;
1368 case BNX2X_FLOW_CTRL_TX
:
1370 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
;
1373 case BNX2X_FLOW_CTRL_RX
:
1374 case BNX2X_FLOW_CTRL_BOTH
:
1375 *ieee_fc
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
1378 case BNX2X_FLOW_CTRL_NONE
:
1380 *ieee_fc
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE
;
1383 DP(NETIF_MSG_LINK
, "ieee_fc = 0x%x\n", *ieee_fc
);
1386 static void bnx2x_set_ieee_aneg_advertisment(struct link_params
*params
,
1389 struct bnx2x
*bp
= params
->bp
;
1391 /* for AN, we are always publishing full duplex */
1393 CL45_WR_OVER_CL22(bp
, params
->port
,
1395 MDIO_REG_BANK_COMBO_IEEE0
,
1396 MDIO_COMBO_IEEE0_AUTO_NEG_ADV
, ieee_fc
);
1397 CL45_RD_OVER_CL22(bp
, params
->port
,
1399 MDIO_REG_BANK_CL73_IEEEB1
,
1400 MDIO_CL73_IEEEB1_AN_ADV1
, &val
);
1401 val
&= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH
;
1402 val
|= ((ieee_fc
<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK
);
1403 CL45_WR_OVER_CL22(bp
, params
->port
,
1405 MDIO_REG_BANK_CL73_IEEEB1
,
1406 MDIO_CL73_IEEEB1_AN_ADV1
, val
);
1409 static void bnx2x_restart_autoneg(struct link_params
*params
, u8 enable_cl73
)
1411 struct bnx2x
*bp
= params
->bp
;
1414 DP(NETIF_MSG_LINK
, "bnx2x_restart_autoneg\n");
1415 /* Enable and restart BAM/CL37 aneg */
1418 CL45_RD_OVER_CL22(bp
, params
->port
,
1420 MDIO_REG_BANK_CL73_IEEEB0
,
1421 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
,
1424 CL45_WR_OVER_CL22(bp
, params
->port
,
1426 MDIO_REG_BANK_CL73_IEEEB0
,
1427 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
,
1429 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN
|
1430 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN
));
1433 CL45_RD_OVER_CL22(bp
, params
->port
,
1435 MDIO_REG_BANK_COMBO_IEEE0
,
1436 MDIO_COMBO_IEEE0_MII_CONTROL
,
1439 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
1441 CL45_WR_OVER_CL22(bp
, params
->port
,
1443 MDIO_REG_BANK_COMBO_IEEE0
,
1444 MDIO_COMBO_IEEE0_MII_CONTROL
,
1446 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
1447 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN
));
1451 static void bnx2x_initialize_sgmii_process(struct link_params
*params
,
1452 struct link_vars
*vars
)
1454 struct bnx2x
*bp
= params
->bp
;
1457 /* in SGMII mode, the unicore is always slave */
1459 CL45_RD_OVER_CL22(bp
, params
->port
,
1461 MDIO_REG_BANK_SERDES_DIGITAL
,
1462 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
,
1464 control1
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT
;
1465 /* set sgmii mode (and not fiber) */
1466 control1
&= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE
|
1467 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET
|
1468 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE
);
1469 CL45_WR_OVER_CL22(bp
, params
->port
,
1471 MDIO_REG_BANK_SERDES_DIGITAL
,
1472 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
,
1475 /* if forced speed */
1476 if (!(vars
->line_speed
== SPEED_AUTO_NEG
)) {
1477 /* set speed, disable autoneg */
1480 CL45_RD_OVER_CL22(bp
, params
->port
,
1482 MDIO_REG_BANK_COMBO_IEEE0
,
1483 MDIO_COMBO_IEEE0_MII_CONTROL
,
1485 mii_control
&= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
1486 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK
|
1487 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
);
1489 switch (vars
->line_speed
) {
1492 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100
;
1496 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000
;
1499 /* there is nothing to set for 10M */
1502 /* invalid speed for SGMII */
1503 DP(NETIF_MSG_LINK
, "Invalid line_speed 0x%x\n",
1508 /* setting the full duplex */
1509 if (params
->req_duplex
== DUPLEX_FULL
)
1511 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
;
1512 CL45_WR_OVER_CL22(bp
, params
->port
,
1514 MDIO_REG_BANK_COMBO_IEEE0
,
1515 MDIO_COMBO_IEEE0_MII_CONTROL
,
1518 } else { /* AN mode */
1519 /* enable and restart AN */
1520 bnx2x_restart_autoneg(params
, 0);
1529 static void bnx2x_pause_resolve(struct link_vars
*vars
, u32 pause_result
)
1531 switch (pause_result
) { /* ASYM P ASYM P */
1532 case 0xb: /* 1 0 1 1 */
1533 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_TX
;
1536 case 0xe: /* 1 1 1 0 */
1537 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_RX
;
1540 case 0x5: /* 0 1 0 1 */
1541 case 0x7: /* 0 1 1 1 */
1542 case 0xd: /* 1 1 0 1 */
1543 case 0xf: /* 1 1 1 1 */
1544 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_BOTH
;
1552 static u8
bnx2x_ext_phy_resolve_fc(struct link_params
*params
,
1553 struct link_vars
*vars
)
1555 struct bnx2x
*bp
= params
->bp
;
1557 u16 ld_pause
; /* local */
1558 u16 lp_pause
; /* link partner */
1559 u16 an_complete
; /* AN complete */
1563 u8 port
= params
->port
;
1564 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
1565 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
1568 bnx2x_cl45_read(bp
, port
,
1572 MDIO_AN_REG_STATUS
, &an_complete
);
1573 bnx2x_cl45_read(bp
, port
,
1577 MDIO_AN_REG_STATUS
, &an_complete
);
1579 if (an_complete
& MDIO_AN_REG_STATUS_AN_COMPLETE
) {
1581 bnx2x_cl45_read(bp
, port
,
1585 MDIO_AN_REG_ADV_PAUSE
, &ld_pause
);
1586 bnx2x_cl45_read(bp
, port
,
1590 MDIO_AN_REG_LP_AUTO_NEG
, &lp_pause
);
1591 pause_result
= (ld_pause
&
1592 MDIO_AN_REG_ADV_PAUSE_MASK
) >> 8;
1593 pause_result
|= (lp_pause
&
1594 MDIO_AN_REG_ADV_PAUSE_MASK
) >> 10;
1595 DP(NETIF_MSG_LINK
, "Ext PHY pause result 0x%x \n",
1597 bnx2x_pause_resolve(vars
, pause_result
);
1598 if (vars
->flow_ctrl
== BNX2X_FLOW_CTRL_NONE
&&
1599 ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
) {
1600 bnx2x_cl45_read(bp
, port
,
1604 MDIO_AN_REG_CL37_FC_LD
, &ld_pause
);
1606 bnx2x_cl45_read(bp
, port
,
1610 MDIO_AN_REG_CL37_FC_LP
, &lp_pause
);
1611 pause_result
= (ld_pause
&
1612 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) >> 5;
1613 pause_result
|= (lp_pause
&
1614 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) >> 7;
1616 bnx2x_pause_resolve(vars
, pause_result
);
1617 DP(NETIF_MSG_LINK
, "Ext PHY CL37 pause result 0x%x \n",
1624 static u8
bnx2x_direct_parallel_detect_used(struct link_params
*params
)
1626 struct bnx2x
*bp
= params
->bp
;
1627 u16 pd_10g
, status2_1000x
;
1628 CL45_RD_OVER_CL22(bp
, params
->port
,
1630 MDIO_REG_BANK_SERDES_DIGITAL
,
1631 MDIO_SERDES_DIGITAL_A_1000X_STATUS2
,
1633 CL45_RD_OVER_CL22(bp
, params
->port
,
1635 MDIO_REG_BANK_SERDES_DIGITAL
,
1636 MDIO_SERDES_DIGITAL_A_1000X_STATUS2
,
1638 if (status2_1000x
& MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED
) {
1639 DP(NETIF_MSG_LINK
, "1G parallel detect link on port %d\n",
1644 CL45_RD_OVER_CL22(bp
, params
->port
,
1646 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
1647 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS
,
1650 if (pd_10g
& MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK
) {
1651 DP(NETIF_MSG_LINK
, "10G parallel detect link on port %d\n",
1658 static void bnx2x_flow_ctrl_resolve(struct link_params
*params
,
1659 struct link_vars
*vars
,
1662 struct bnx2x
*bp
= params
->bp
;
1663 u16 ld_pause
; /* local driver */
1664 u16 lp_pause
; /* link partner */
1667 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
1669 /* resolve from gp_status in case of AN complete and not sgmii */
1670 if ((params
->req_flow_ctrl
== BNX2X_FLOW_CTRL_AUTO
) &&
1671 (gp_status
& MDIO_AN_CL73_OR_37_COMPLETE
) &&
1672 (!(vars
->phy_flags
& PHY_SGMII_FLAG
)) &&
1673 (XGXS_EXT_PHY_TYPE(params
->ext_phy_config
) ==
1674 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
)) {
1675 if (bnx2x_direct_parallel_detect_used(params
)) {
1676 vars
->flow_ctrl
= params
->req_fc_auto_adv
;
1680 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE
|
1681 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE
)) ==
1682 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE
|
1683 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE
)) {
1685 CL45_RD_OVER_CL22(bp
, params
->port
,
1687 MDIO_REG_BANK_CL73_IEEEB1
,
1688 MDIO_CL73_IEEEB1_AN_ADV1
,
1690 CL45_RD_OVER_CL22(bp
, params
->port
,
1692 MDIO_REG_BANK_CL73_IEEEB1
,
1693 MDIO_CL73_IEEEB1_AN_LP_ADV1
,
1695 pause_result
= (ld_pause
&
1696 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK
)
1698 pause_result
|= (lp_pause
&
1699 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK
)
1701 DP(NETIF_MSG_LINK
, "pause_result CL73 0x%x\n",
1705 CL45_RD_OVER_CL22(bp
, params
->port
,
1707 MDIO_REG_BANK_COMBO_IEEE0
,
1708 MDIO_COMBO_IEEE0_AUTO_NEG_ADV
,
1710 CL45_RD_OVER_CL22(bp
, params
->port
,
1712 MDIO_REG_BANK_COMBO_IEEE0
,
1713 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1
,
1715 pause_result
= (ld_pause
&
1716 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
)>>5;
1717 pause_result
|= (lp_pause
&
1718 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
)>>7;
1719 DP(NETIF_MSG_LINK
, "pause_result CL37 0x%x\n",
1722 bnx2x_pause_resolve(vars
, pause_result
);
1723 } else if ((params
->req_flow_ctrl
== BNX2X_FLOW_CTRL_AUTO
) &&
1724 (bnx2x_ext_phy_resolve_fc(params
, vars
))) {
1727 if (params
->req_flow_ctrl
== BNX2X_FLOW_CTRL_AUTO
)
1728 vars
->flow_ctrl
= params
->req_fc_auto_adv
;
1730 vars
->flow_ctrl
= params
->req_flow_ctrl
;
1732 DP(NETIF_MSG_LINK
, "flow_ctrl 0x%x\n", vars
->flow_ctrl
);
1735 static void bnx2x_check_fallback_to_cl37(struct link_params
*params
)
1737 struct bnx2x
*bp
= params
->bp
;
1738 u16 rx_status
, ustat_val
, cl37_fsm_recieved
;
1739 DP(NETIF_MSG_LINK
, "bnx2x_check_fallback_to_cl37\n");
1740 /* Step 1: Make sure signal is detected */
1741 CL45_RD_OVER_CL22(bp
, params
->port
,
1746 if ((rx_status
& MDIO_RX0_RX_STATUS_SIGDET
) !=
1747 (MDIO_RX0_RX_STATUS_SIGDET
)) {
1748 DP(NETIF_MSG_LINK
, "Signal is not detected. Restoring CL73."
1749 "rx_status(0x80b0) = 0x%x\n", rx_status
);
1750 CL45_WR_OVER_CL22(bp
, params
->port
,
1752 MDIO_REG_BANK_CL73_IEEEB0
,
1753 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
,
1754 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN
);
1757 /* Step 2: Check CL73 state machine */
1758 CL45_RD_OVER_CL22(bp
, params
->port
,
1760 MDIO_REG_BANK_CL73_USERB0
,
1761 MDIO_CL73_USERB0_CL73_USTAT1
,
1764 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK
|
1765 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37
)) !=
1766 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK
|
1767 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37
)) {
1768 DP(NETIF_MSG_LINK
, "CL73 state-machine is not stable. "
1769 "ustat_val(0x8371) = 0x%x\n", ustat_val
);
1772 /* Step 3: Check CL37 Message Pages received to indicate LP
1773 supports only CL37 */
1774 CL45_RD_OVER_CL22(bp
, params
->port
,
1776 MDIO_REG_BANK_REMOTE_PHY
,
1777 MDIO_REMOTE_PHY_MISC_RX_STATUS
,
1778 &cl37_fsm_recieved
);
1779 if ((cl37_fsm_recieved
&
1780 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG
|
1781 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG
)) !=
1782 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG
|
1783 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG
)) {
1784 DP(NETIF_MSG_LINK
, "No CL37 FSM were received. "
1785 "misc_rx_status(0x8330) = 0x%x\n",
1789 /* The combined cl37/cl73 fsm state information indicating that we are
1790 connected to a device which does not support cl73, but does support
1791 cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */
1793 CL45_WR_OVER_CL22(bp
, params
->port
,
1795 MDIO_REG_BANK_CL73_IEEEB0
,
1796 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
,
1798 /* Restart CL37 autoneg */
1799 bnx2x_restart_autoneg(params
, 0);
1800 DP(NETIF_MSG_LINK
, "Disabling CL73, and restarting CL37 autoneg\n");
1802 static u8
bnx2x_link_settings_status(struct link_params
*params
,
1803 struct link_vars
*vars
,
1807 struct bnx2x
*bp
= params
->bp
;
1810 vars
->link_status
= 0;
1812 if (gp_status
& MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS
) {
1813 DP(NETIF_MSG_LINK
, "phy link up gp_status=0x%x\n",
1816 vars
->phy_link_up
= 1;
1817 vars
->link_status
|= LINK_STATUS_LINK_UP
;
1819 if (gp_status
& MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS
)
1820 vars
->duplex
= DUPLEX_FULL
;
1822 vars
->duplex
= DUPLEX_HALF
;
1824 bnx2x_flow_ctrl_resolve(params
, vars
, gp_status
);
1826 switch (gp_status
& GP_STATUS_SPEED_MASK
) {
1828 new_line_speed
= SPEED_10
;
1829 if (vars
->duplex
== DUPLEX_FULL
)
1830 vars
->link_status
|= LINK_10TFD
;
1832 vars
->link_status
|= LINK_10THD
;
1835 case GP_STATUS_100M
:
1836 new_line_speed
= SPEED_100
;
1837 if (vars
->duplex
== DUPLEX_FULL
)
1838 vars
->link_status
|= LINK_100TXFD
;
1840 vars
->link_status
|= LINK_100TXHD
;
1844 case GP_STATUS_1G_KX
:
1845 new_line_speed
= SPEED_1000
;
1846 if (vars
->duplex
== DUPLEX_FULL
)
1847 vars
->link_status
|= LINK_1000TFD
;
1849 vars
->link_status
|= LINK_1000THD
;
1852 case GP_STATUS_2_5G
:
1853 new_line_speed
= SPEED_2500
;
1854 if (vars
->duplex
== DUPLEX_FULL
)
1855 vars
->link_status
|= LINK_2500TFD
;
1857 vars
->link_status
|= LINK_2500THD
;
1863 "link speed unsupported gp_status 0x%x\n",
1867 case GP_STATUS_10G_KX4
:
1868 case GP_STATUS_10G_HIG
:
1869 case GP_STATUS_10G_CX4
:
1870 new_line_speed
= SPEED_10000
;
1871 vars
->link_status
|= LINK_10GTFD
;
1874 case GP_STATUS_12G_HIG
:
1875 new_line_speed
= SPEED_12000
;
1876 vars
->link_status
|= LINK_12GTFD
;
1879 case GP_STATUS_12_5G
:
1880 new_line_speed
= SPEED_12500
;
1881 vars
->link_status
|= LINK_12_5GTFD
;
1885 new_line_speed
= SPEED_13000
;
1886 vars
->link_status
|= LINK_13GTFD
;
1890 new_line_speed
= SPEED_15000
;
1891 vars
->link_status
|= LINK_15GTFD
;
1895 new_line_speed
= SPEED_16000
;
1896 vars
->link_status
|= LINK_16GTFD
;
1901 "link speed unsupported gp_status 0x%x\n",
1906 /* Upon link speed change set the NIG into drain mode.
1907 Comes to deals with possible FIFO glitch due to clk change
1908 when speed is decreased without link down indicator */
1909 if (new_line_speed
!= vars
->line_speed
) {
1910 if (XGXS_EXT_PHY_TYPE(params
->ext_phy_config
) !=
1911 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
&&
1913 DP(NETIF_MSG_LINK
, "Internal link speed %d is"
1914 " different than the external"
1915 " link speed %d\n", new_line_speed
,
1917 vars
->phy_link_up
= 0;
1920 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
1921 + params
->port
*4, 0);
1924 vars
->line_speed
= new_line_speed
;
1925 vars
->link_status
|= LINK_STATUS_SERDES_LINK
;
1927 if ((params
->req_line_speed
== SPEED_AUTO_NEG
) &&
1928 ((XGXS_EXT_PHY_TYPE(params
->ext_phy_config
) ==
1929 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) ||
1930 (XGXS_EXT_PHY_TYPE(params
->ext_phy_config
) ==
1931 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
) ||
1932 (XGXS_EXT_PHY_TYPE(params
->ext_phy_config
) ==
1933 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
) ||
1934 (XGXS_EXT_PHY_TYPE(params
->ext_phy_config
) ==
1935 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
))) {
1936 vars
->autoneg
= AUTO_NEG_ENABLED
;
1938 if (gp_status
& MDIO_AN_CL73_OR_37_COMPLETE
) {
1939 vars
->autoneg
|= AUTO_NEG_COMPLETE
;
1940 vars
->link_status
|=
1941 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
;
1944 vars
->autoneg
|= AUTO_NEG_PARALLEL_DETECTION_USED
;
1945 vars
->link_status
|=
1946 LINK_STATUS_PARALLEL_DETECTION_USED
;
1949 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
1950 vars
->link_status
|=
1951 LINK_STATUS_TX_FLOW_CONTROL_ENABLED
;
1953 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_RX
)
1954 vars
->link_status
|=
1955 LINK_STATUS_RX_FLOW_CONTROL_ENABLED
;
1957 } else { /* link_down */
1958 DP(NETIF_MSG_LINK
, "phy link down\n");
1960 vars
->phy_link_up
= 0;
1962 vars
->duplex
= DUPLEX_FULL
;
1963 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
1964 vars
->autoneg
= AUTO_NEG_DISABLED
;
1965 vars
->mac_type
= MAC_TYPE_NONE
;
1967 if ((params
->req_line_speed
== SPEED_AUTO_NEG
) &&
1968 ((XGXS_EXT_PHY_TYPE(params
->ext_phy_config
) ==
1969 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
))) {
1970 /* Check signal is detected */
1971 bnx2x_check_fallback_to_cl37(params
);
1975 DP(NETIF_MSG_LINK
, "gp_status 0x%x phy_link_up %x line_speed %x \n",
1976 gp_status
, vars
->phy_link_up
, vars
->line_speed
);
1977 DP(NETIF_MSG_LINK
, "duplex %x flow_ctrl 0x%x"
1980 vars
->flow_ctrl
, vars
->autoneg
);
1981 DP(NETIF_MSG_LINK
, "link_status 0x%x\n", vars
->link_status
);
1986 static void bnx2x_set_gmii_tx_driver(struct link_params
*params
)
1988 struct bnx2x
*bp
= params
->bp
;
1994 CL45_RD_OVER_CL22(bp
, params
->port
,
1996 MDIO_REG_BANK_OVER_1G
,
1997 MDIO_OVER_1G_LP_UP2
, &lp_up2
);
1999 /* bits [10:7] at lp_up2, positioned at [15:12] */
2000 lp_up2
= (((lp_up2
& MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK
) >>
2001 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT
) <<
2002 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT
);
2007 for (bank
= MDIO_REG_BANK_TX0
; bank
<= MDIO_REG_BANK_TX3
;
2008 bank
+= (MDIO_REG_BANK_TX1
- MDIO_REG_BANK_TX0
)) {
2009 CL45_RD_OVER_CL22(bp
, params
->port
,
2012 MDIO_TX0_TX_DRIVER
, &tx_driver
);
2014 /* replace tx_driver bits [15:12] */
2016 (tx_driver
& MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK
)) {
2017 tx_driver
&= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK
;
2018 tx_driver
|= lp_up2
;
2019 CL45_WR_OVER_CL22(bp
, params
->port
,
2022 MDIO_TX0_TX_DRIVER
, tx_driver
);
2027 static u8
bnx2x_emac_program(struct link_params
*params
,
2028 u32 line_speed
, u32 duplex
)
2030 struct bnx2x
*bp
= params
->bp
;
2031 u8 port
= params
->port
;
2034 DP(NETIF_MSG_LINK
, "setting link speed & duplex\n");
2035 bnx2x_bits_dis(bp
, GRCBASE_EMAC0
+ port
*0x400 +
2037 (EMAC_MODE_25G_MODE
|
2038 EMAC_MODE_PORT_MII_10M
|
2039 EMAC_MODE_HALF_DUPLEX
));
2040 switch (line_speed
) {
2042 mode
|= EMAC_MODE_PORT_MII_10M
;
2046 mode
|= EMAC_MODE_PORT_MII
;
2050 mode
|= EMAC_MODE_PORT_GMII
;
2054 mode
|= (EMAC_MODE_25G_MODE
| EMAC_MODE_PORT_GMII
);
2058 /* 10G not valid for EMAC */
2059 DP(NETIF_MSG_LINK
, "Invalid line_speed 0x%x\n", line_speed
);
2063 if (duplex
== DUPLEX_HALF
)
2064 mode
|= EMAC_MODE_HALF_DUPLEX
;
2066 GRCBASE_EMAC0
+ port
*0x400 + EMAC_REG_EMAC_MODE
,
2069 bnx2x_set_led(params
, LED_MODE_OPER
, line_speed
);
2073 /*****************************************************************************/
2074 /* External Phy section */
2075 /*****************************************************************************/
2076 void bnx2x_ext_phy_hw_reset(struct bnx2x
*bp
, u8 port
)
2078 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_1
,
2079 MISC_REGISTERS_GPIO_OUTPUT_LOW
, port
);
2081 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_1
,
2082 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, port
);
2085 static void bnx2x_ext_phy_reset(struct link_params
*params
,
2086 struct link_vars
*vars
)
2088 struct bnx2x
*bp
= params
->bp
;
2090 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
2092 DP(NETIF_MSG_LINK
, "Port %x: bnx2x_ext_phy_reset\n", params
->port
);
2093 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
2094 /* The PHY reset is controled by GPIO 1
2095 * Give it 1ms of reset pulse
2097 if (vars
->phy_flags
& PHY_XGXS_FLAG
) {
2099 switch (ext_phy_type
) {
2100 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
2101 DP(NETIF_MSG_LINK
, "XGXS Direct\n");
2104 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
:
2105 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
:
2106 DP(NETIF_MSG_LINK
, "XGXS 8705/8706\n");
2108 /* Restore normal power mode*/
2109 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
2110 MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
2114 bnx2x_ext_phy_hw_reset(bp
, params
->port
);
2116 bnx2x_cl45_write(bp
, params
->port
,
2120 MDIO_PMA_REG_CTRL
, 0xa040);
2123 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
2126 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
2128 /* Restore normal power mode*/
2129 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
2130 MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
2133 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_1
,
2134 MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
2137 bnx2x_cl45_write(bp
, params
->port
,
2145 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
:
2146 DP(NETIF_MSG_LINK
, "XGXS 8072\n");
2148 /* Unset Low Power Mode and SW reset */
2149 /* Restore normal power mode*/
2150 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
2151 MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
2154 bnx2x_cl45_write(bp
, params
->port
,
2162 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
:
2163 DP(NETIF_MSG_LINK
, "XGXS 8073\n");
2165 /* Restore normal power mode*/
2166 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
2167 MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
2170 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_1
,
2171 MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
2175 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
:
2176 DP(NETIF_MSG_LINK
, "XGXS SFX7101\n");
2178 /* Restore normal power mode*/
2179 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
2180 MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
2184 bnx2x_ext_phy_hw_reset(bp
, params
->port
);
2187 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
:
2188 /* Restore normal power mode*/
2189 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
2190 MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
2194 bnx2x_ext_phy_hw_reset(bp
, params
->port
);
2196 bnx2x_cl45_write(bp
, params
->port
,
2203 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823
:
2205 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
:
2206 DP(NETIF_MSG_LINK
, "XGXS PHY Failure detected\n");
2210 DP(NETIF_MSG_LINK
, "BAD XGXS ext_phy_config 0x%x\n",
2211 params
->ext_phy_config
);
2215 } else { /* SerDes */
2216 ext_phy_type
= SERDES_EXT_PHY_TYPE(params
->ext_phy_config
);
2217 switch (ext_phy_type
) {
2218 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT
:
2219 DP(NETIF_MSG_LINK
, "SerDes Direct\n");
2222 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482
:
2223 DP(NETIF_MSG_LINK
, "SerDes 5482\n");
2224 bnx2x_ext_phy_hw_reset(bp
, params
->port
);
2228 DP(NETIF_MSG_LINK
, "BAD SerDes ext_phy_config 0x%x\n",
2229 params
->ext_phy_config
);
2235 static void bnx2x_save_spirom_version(struct bnx2x
*bp
, u8 port
,
2236 u32 shmem_base
, u32 spirom_ver
)
2238 DP(NETIF_MSG_LINK
, "FW version 0x%x:0x%x for port %d\n",
2239 (u16
)(spirom_ver
>>16), (u16
)spirom_ver
, port
);
2240 REG_WR(bp
, shmem_base
+
2241 offsetof(struct shmem_region
,
2242 port_mb
[port
].ext_phy_fw_version
),
2246 static void bnx2x_save_bcm_spirom_ver(struct bnx2x
*bp
, u8 port
,
2247 u32 ext_phy_type
, u8 ext_phy_addr
,
2250 u16 fw_ver1
, fw_ver2
;
2252 bnx2x_cl45_read(bp
, port
, ext_phy_type
, ext_phy_addr
, MDIO_PMA_DEVAD
,
2253 MDIO_PMA_REG_ROM_VER1
, &fw_ver1
);
2254 bnx2x_cl45_read(bp
, port
, ext_phy_type
, ext_phy_addr
, MDIO_PMA_DEVAD
,
2255 MDIO_PMA_REG_ROM_VER2
, &fw_ver2
);
2256 bnx2x_save_spirom_version(bp
, port
, shmem_base
,
2257 (u32
)(fw_ver1
<<16 | fw_ver2
));
2261 static void bnx2x_save_8481_spirom_version(struct bnx2x
*bp
, u8 port
,
2262 u8 ext_phy_addr
, u32 shmem_base
)
2264 u16 val
, fw_ver1
, fw_ver2
, cnt
;
2265 /* For the 32 bits registers in 8481, access via MDIO2ARM interface.*/
2266 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
2267 bnx2x_cl45_write(bp
, port
,
2268 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2269 ext_phy_addr
, MDIO_PMA_DEVAD
,
2271 bnx2x_cl45_write(bp
, port
,
2272 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2277 bnx2x_cl45_write(bp
, port
,
2278 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2283 bnx2x_cl45_write(bp
, port
,
2284 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2289 bnx2x_cl45_write(bp
, port
,
2290 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2296 for (cnt
= 0; cnt
< 100; cnt
++) {
2297 bnx2x_cl45_read(bp
, port
,
2298 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2308 DP(NETIF_MSG_LINK
, "Unable to read 8481 phy fw version(1)\n");
2309 bnx2x_save_spirom_version(bp
, port
,
2315 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
2316 bnx2x_cl45_write(bp
, port
,
2317 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2318 ext_phy_addr
, MDIO_PMA_DEVAD
,
2320 bnx2x_cl45_write(bp
, port
,
2321 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2322 ext_phy_addr
, MDIO_PMA_DEVAD
,
2324 bnx2x_cl45_write(bp
, port
,
2325 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2326 ext_phy_addr
, MDIO_PMA_DEVAD
,
2328 for (cnt
= 0; cnt
< 100; cnt
++) {
2329 bnx2x_cl45_read(bp
, port
,
2330 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2340 DP(NETIF_MSG_LINK
, "Unable to read 8481 phy fw version(2)\n");
2341 bnx2x_save_spirom_version(bp
, port
,
2346 /* lower 16 bits of the register SPI_FW_STATUS */
2347 bnx2x_cl45_read(bp
, port
,
2348 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2353 /* upper 16 bits of register SPI_FW_STATUS */
2354 bnx2x_cl45_read(bp
, port
,
2355 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2361 bnx2x_save_spirom_version(bp
, port
,
2362 shmem_base
, (fw_ver2
<<16) | fw_ver1
);
2365 static void bnx2x_bcm8072_external_rom_boot(struct link_params
*params
)
2367 struct bnx2x
*bp
= params
->bp
;
2368 u8 port
= params
->port
;
2369 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
2370 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
2372 /* Need to wait 200ms after reset */
2374 /* Boot port from external ROM
2375 * Set ser_boot_ctl bit in the MISC_CTRL1 register
2377 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2379 MDIO_PMA_REG_MISC_CTRL1
, 0x0001);
2381 /* Reset internal microprocessor */
2382 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2384 MDIO_PMA_REG_GEN_CTRL
,
2385 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP
);
2386 /* set micro reset = 0 */
2387 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2389 MDIO_PMA_REG_GEN_CTRL
,
2390 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET
);
2391 /* Reset internal microprocessor */
2392 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2394 MDIO_PMA_REG_GEN_CTRL
,
2395 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP
);
2396 /* wait for 100ms for code download via SPI port */
2399 /* Clear ser_boot_ctl bit */
2400 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2402 MDIO_PMA_REG_MISC_CTRL1
, 0x0000);
2406 bnx2x_save_bcm_spirom_ver(bp
, port
,
2409 params
->shmem_base
);
2412 static u8
bnx2x_8073_is_snr_needed(struct link_params
*params
)
2414 /* This is only required for 8073A1, version 102 only */
2416 struct bnx2x
*bp
= params
->bp
;
2417 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
2420 /* Read 8073 HW revision*/
2421 bnx2x_cl45_read(bp
, params
->port
,
2422 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
2425 MDIO_PMA_REG_8073_CHIP_REV
, &val
);
2428 /* No need to workaround in 8073 A1 */
2432 bnx2x_cl45_read(bp
, params
->port
,
2433 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
2436 MDIO_PMA_REG_ROM_VER2
, &val
);
2438 /* SNR should be applied only for version 0x102 */
2445 static u8
bnx2x_bcm8073_xaui_wa(struct link_params
*params
)
2447 struct bnx2x
*bp
= params
->bp
;
2448 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
2449 u16 val
, cnt
, cnt1
;
2451 bnx2x_cl45_read(bp
, params
->port
,
2452 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
2455 MDIO_PMA_REG_8073_CHIP_REV
, &val
);
2458 /* No need to workaround in 8073 A1 */
2461 /* XAUI workaround in 8073 A0: */
2463 /* After loading the boot ROM and restarting Autoneg,
2464 poll Dev1, Reg $C820: */
2466 for (cnt
= 0; cnt
< 1000; cnt
++) {
2467 bnx2x_cl45_read(bp
, params
->port
,
2468 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
2471 MDIO_PMA_REG_8073_SPEED_LINK_STATUS
,
2473 /* If bit [14] = 0 or bit [13] = 0, continue on with
2474 system initialization (XAUI work-around not required,
2475 as these bits indicate 2.5G or 1G link up). */
2476 if (!(val
& (1<<14)) || !(val
& (1<<13))) {
2477 DP(NETIF_MSG_LINK
, "XAUI work-around not required\n");
2479 } else if (!(val
& (1<<15))) {
2480 DP(NETIF_MSG_LINK
, "clc bit 15 went off\n");
2481 /* If bit 15 is 0, then poll Dev1, Reg $C841 until
2482 it's MSB (bit 15) goes to 1 (indicating that the
2483 XAUI workaround has completed),
2484 then continue on with system initialization.*/
2485 for (cnt1
= 0; cnt1
< 1000; cnt1
++) {
2486 bnx2x_cl45_read(bp
, params
->port
,
2487 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
2490 MDIO_PMA_REG_8073_XAUI_WA
, &val
);
2491 if (val
& (1<<15)) {
2493 "XAUI workaround has completed\n");
2502 DP(NETIF_MSG_LINK
, "Warning: XAUI work-around timeout !!!\n");
2506 static void bnx2x_bcm8073_bcm8727_external_rom_boot(struct bnx2x
*bp
, u8 port
,
2511 /* Boot port from external ROM */
2513 bnx2x_cl45_write(bp
, port
,
2517 MDIO_PMA_REG_GEN_CTRL
,
2520 /* ucode reboot and rst */
2521 bnx2x_cl45_write(bp
, port
,
2525 MDIO_PMA_REG_GEN_CTRL
,
2528 bnx2x_cl45_write(bp
, port
,
2532 MDIO_PMA_REG_MISC_CTRL1
, 0x0001);
2534 /* Reset internal microprocessor */
2535 bnx2x_cl45_write(bp
, port
,
2539 MDIO_PMA_REG_GEN_CTRL
,
2540 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET
);
2542 /* Release srst bit */
2543 bnx2x_cl45_write(bp
, port
,
2547 MDIO_PMA_REG_GEN_CTRL
,
2548 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP
);
2550 /* wait for 100ms for code download via SPI port */
2553 /* Clear ser_boot_ctl bit */
2554 bnx2x_cl45_write(bp
, port
,
2558 MDIO_PMA_REG_MISC_CTRL1
, 0x0000);
2560 bnx2x_save_bcm_spirom_ver(bp
, port
,
2566 static void bnx2x_bcm8073_external_rom_boot(struct bnx2x
*bp
, u8 port
,
2570 bnx2x_bcm8073_bcm8727_external_rom_boot(bp
, port
, ext_phy_addr
,
2571 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
2575 static void bnx2x_bcm8727_external_rom_boot(struct bnx2x
*bp
, u8 port
,
2579 bnx2x_bcm8073_bcm8727_external_rom_boot(bp
, port
, ext_phy_addr
,
2580 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
2585 static void bnx2x_bcm8726_external_rom_boot(struct link_params
*params
)
2587 struct bnx2x
*bp
= params
->bp
;
2588 u8 port
= params
->port
;
2589 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
2590 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
2592 /* Need to wait 100ms after reset */
2595 /* Micro controller re-boot */
2596 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2598 MDIO_PMA_REG_GEN_CTRL
,
2601 /* Set soft reset */
2602 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2604 MDIO_PMA_REG_GEN_CTRL
,
2605 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET
);
2607 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2609 MDIO_PMA_REG_MISC_CTRL1
, 0x0001);
2611 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2613 MDIO_PMA_REG_GEN_CTRL
,
2614 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP
);
2616 /* wait for 150ms for microcode load */
2619 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
2620 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2622 MDIO_PMA_REG_MISC_CTRL1
, 0x0000);
2625 bnx2x_save_bcm_spirom_ver(bp
, port
,
2628 params
->shmem_base
);
2631 static void bnx2x_sfp_set_transmitter(struct bnx2x
*bp
, u8 port
,
2632 u32 ext_phy_type
, u8 ext_phy_addr
,
2637 DP(NETIF_MSG_LINK
, "Setting transmitter tx_en=%x for port %x\n",
2639 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
2640 bnx2x_cl45_read(bp
, port
,
2644 MDIO_PMA_REG_PHY_IDENTIFIER
,
2652 bnx2x_cl45_write(bp
, port
,
2656 MDIO_PMA_REG_PHY_IDENTIFIER
,
2660 static u8
bnx2x_8726_read_sfp_module_eeprom(struct link_params
*params
,
2661 u16 addr
, u8 byte_cnt
, u8
*o_buf
)
2663 struct bnx2x
*bp
= params
->bp
;
2666 u8 port
= params
->port
;
2667 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
2668 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
2670 if (byte_cnt
> 16) {
2671 DP(NETIF_MSG_LINK
, "Reading from eeprom is"
2672 " is limited to 0xf\n");
2675 /* Set the read command byte count */
2676 bnx2x_cl45_write(bp
, port
,
2680 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT
,
2681 (byte_cnt
| 0xa000));
2683 /* Set the read command address */
2684 bnx2x_cl45_write(bp
, port
,
2688 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR
,
2691 /* Activate read command */
2692 bnx2x_cl45_write(bp
, port
,
2696 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
,
2699 /* Wait up to 500us for command complete status */
2700 for (i
= 0; i
< 100; i
++) {
2701 bnx2x_cl45_read(bp
, port
,
2705 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
2706 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
2707 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
)
2712 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) !=
2713 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
) {
2715 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
2716 (val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
));
2720 /* Read the buffer */
2721 for (i
= 0; i
< byte_cnt
; i
++) {
2722 bnx2x_cl45_read(bp
, port
,
2726 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF
+ i
, &val
);
2727 o_buf
[i
] = (u8
)(val
& MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK
);
2730 for (i
= 0; i
< 100; i
++) {
2731 bnx2x_cl45_read(bp
, port
,
2735 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
2736 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
2737 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE
)
2744 static u8
bnx2x_8727_read_sfp_module_eeprom(struct link_params
*params
,
2745 u16 addr
, u8 byte_cnt
, u8
*o_buf
)
2747 struct bnx2x
*bp
= params
->bp
;
2749 u8 port
= params
->port
;
2750 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
2751 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
2753 if (byte_cnt
> 16) {
2754 DP(NETIF_MSG_LINK
, "Reading from eeprom is"
2755 " is limited to 0xf\n");
2759 /* Need to read from 1.8000 to clear it */
2760 bnx2x_cl45_read(bp
, port
,
2761 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
2764 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
,
2767 /* Set the read command byte count */
2768 bnx2x_cl45_write(bp
, port
,
2772 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT
,
2773 ((byte_cnt
< 2) ? 2 : byte_cnt
));
2775 /* Set the read command address */
2776 bnx2x_cl45_write(bp
, port
,
2780 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR
,
2782 /* Set the destination address */
2783 bnx2x_cl45_write(bp
, port
,
2788 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF
);
2790 /* Activate read command */
2791 bnx2x_cl45_write(bp
, port
,
2795 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
,
2797 /* Wait appropriate time for two-wire command to finish before
2798 polling the status register */
2801 /* Wait up to 500us for command complete status */
2802 for (i
= 0; i
< 100; i
++) {
2803 bnx2x_cl45_read(bp
, port
,
2807 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
2808 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
2809 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
)
2814 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) !=
2815 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
) {
2817 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
2818 (val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
));
2822 /* Read the buffer */
2823 for (i
= 0; i
< byte_cnt
; i
++) {
2824 bnx2x_cl45_read(bp
, port
,
2828 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF
+ i
, &val
);
2829 o_buf
[i
] = (u8
)(val
& MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK
);
2832 for (i
= 0; i
< 100; i
++) {
2833 bnx2x_cl45_read(bp
, port
,
2837 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
2838 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
2839 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE
)
2847 u8
bnx2x_read_sfp_module_eeprom(struct link_params
*params
, u16 addr
,
2848 u8 byte_cnt
, u8
*o_buf
)
2850 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
2852 if (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
)
2853 return bnx2x_8726_read_sfp_module_eeprom(params
, addr
,
2855 else if (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
)
2856 return bnx2x_8727_read_sfp_module_eeprom(params
, addr
,
2861 static u8
bnx2x_get_edc_mode(struct link_params
*params
,
2864 struct bnx2x
*bp
= params
->bp
;
2865 u8 val
, check_limiting_mode
= 0;
2866 *edc_mode
= EDC_MODE_LIMITING
;
2868 /* First check for copper cable */
2869 if (bnx2x_read_sfp_module_eeprom(params
,
2870 SFP_EEPROM_CON_TYPE_ADDR
,
2873 DP(NETIF_MSG_LINK
, "Failed to read from SFP+ module EEPROM\n");
2878 case SFP_EEPROM_CON_TYPE_VAL_COPPER
:
2880 u8 copper_module_type
;
2882 /* Check if its active cable( includes SFP+ module)
2884 if (bnx2x_read_sfp_module_eeprom(params
,
2885 SFP_EEPROM_FC_TX_TECH_ADDR
,
2887 &copper_module_type
) !=
2890 "Failed to read copper-cable-type"
2891 " from SFP+ EEPROM\n");
2895 if (copper_module_type
&
2896 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE
) {
2897 DP(NETIF_MSG_LINK
, "Active Copper cable detected\n");
2898 check_limiting_mode
= 1;
2899 } else if (copper_module_type
&
2900 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE
) {
2901 DP(NETIF_MSG_LINK
, "Passive Copper"
2902 " cable detected\n");
2904 EDC_MODE_PASSIVE_DAC
;
2906 DP(NETIF_MSG_LINK
, "Unknown copper-cable-"
2907 "type 0x%x !!!\n", copper_module_type
);
2912 case SFP_EEPROM_CON_TYPE_VAL_LC
:
2913 DP(NETIF_MSG_LINK
, "Optic module detected\n");
2914 check_limiting_mode
= 1;
2917 DP(NETIF_MSG_LINK
, "Unable to determine module type 0x%x !!!\n",
2922 if (check_limiting_mode
) {
2923 u8 options
[SFP_EEPROM_OPTIONS_SIZE
];
2924 if (bnx2x_read_sfp_module_eeprom(params
,
2925 SFP_EEPROM_OPTIONS_ADDR
,
2926 SFP_EEPROM_OPTIONS_SIZE
,
2928 DP(NETIF_MSG_LINK
, "Failed to read Option"
2929 " field from module EEPROM\n");
2932 if ((options
[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK
))
2933 *edc_mode
= EDC_MODE_LINEAR
;
2935 *edc_mode
= EDC_MODE_LIMITING
;
2937 DP(NETIF_MSG_LINK
, "EDC mode is set to 0x%x\n", *edc_mode
);
2941 /* This function read the relevant field from the module ( SFP+ ),
2942 and verify it is compliant with this board */
2943 static u8
bnx2x_verify_sfp_module(struct link_params
*params
)
2945 struct bnx2x
*bp
= params
->bp
;
2948 char vendor_name
[SFP_EEPROM_VENDOR_NAME_SIZE
+1];
2949 char vendor_pn
[SFP_EEPROM_PART_NO_SIZE
+1];
2951 val
= REG_RD(bp
, params
->shmem_base
+
2952 offsetof(struct shmem_region
, dev_info
.
2953 port_feature_config
[params
->port
].config
));
2954 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
2955 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT
) {
2956 DP(NETIF_MSG_LINK
, "NOT enforcing module verification\n");
2960 /* Ask the FW to validate the module */
2961 if (!(params
->feature_config_flags
&
2962 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY
)) {
2963 DP(NETIF_MSG_LINK
, "FW does not support OPT MDL "
2968 fw_resp
= bnx2x_fw_command(bp
, DRV_MSG_CODE_VRFY_OPT_MDL
);
2969 if (fw_resp
== FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS
) {
2970 DP(NETIF_MSG_LINK
, "Approved module\n");
2974 /* format the warning message */
2975 if (bnx2x_read_sfp_module_eeprom(params
,
2976 SFP_EEPROM_VENDOR_NAME_ADDR
,
2977 SFP_EEPROM_VENDOR_NAME_SIZE
,
2979 vendor_name
[0] = '\0';
2981 vendor_name
[SFP_EEPROM_VENDOR_NAME_SIZE
] = '\0';
2982 if (bnx2x_read_sfp_module_eeprom(params
,
2983 SFP_EEPROM_PART_NO_ADDR
,
2984 SFP_EEPROM_PART_NO_SIZE
,
2986 vendor_pn
[0] = '\0';
2988 vendor_pn
[SFP_EEPROM_PART_NO_SIZE
] = '\0';
2990 printk(KERN_INFO PFX
"Warning: "
2991 "Unqualified SFP+ module "
2992 "detected on %s, Port %d from %s part number %s\n"
2993 , bp
->dev
->name
, params
->port
,
2994 vendor_name
, vendor_pn
);
2998 static u8
bnx2x_bcm8726_set_limiting_mode(struct link_params
*params
,
3001 struct bnx2x
*bp
= params
->bp
;
3002 u8 port
= params
->port
;
3003 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
3004 u16 cur_limiting_mode
;
3006 bnx2x_cl45_read(bp
, port
,
3007 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
,
3010 MDIO_PMA_REG_ROM_VER2
,
3011 &cur_limiting_mode
);
3012 DP(NETIF_MSG_LINK
, "Current Limiting mode is 0x%x\n",
3015 if (edc_mode
== EDC_MODE_LIMITING
) {
3017 "Setting LIMITING MODE\n");
3018 bnx2x_cl45_write(bp
, port
,
3019 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
,
3022 MDIO_PMA_REG_ROM_VER2
,
3024 } else { /* LRM mode ( default )*/
3026 DP(NETIF_MSG_LINK
, "Setting LRM MODE\n");
3028 /* Changing to LRM mode takes quite few seconds.
3029 So do it only if current mode is limiting
3030 ( default is LRM )*/
3031 if (cur_limiting_mode
!= EDC_MODE_LIMITING
)
3034 bnx2x_cl45_write(bp
, port
,
3035 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
,
3038 MDIO_PMA_REG_LRM_MODE
,
3040 bnx2x_cl45_write(bp
, port
,
3041 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
,
3044 MDIO_PMA_REG_ROM_VER2
,
3046 bnx2x_cl45_write(bp
, port
,
3047 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
,
3050 MDIO_PMA_REG_MISC_CTRL0
,
3052 bnx2x_cl45_write(bp
, port
,
3053 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
,
3056 MDIO_PMA_REG_LRM_MODE
,
3062 static u8
bnx2x_bcm8727_set_limiting_mode(struct link_params
*params
,
3065 struct bnx2x
*bp
= params
->bp
;
3066 u8 port
= params
->port
;
3069 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
3071 bnx2x_cl45_read(bp
, port
,
3072 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
3075 MDIO_PMA_REG_PHY_IDENTIFIER
,
3078 bnx2x_cl45_write(bp
, port
,
3079 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
3082 MDIO_PMA_REG_PHY_IDENTIFIER
,
3083 (phy_identifier
& ~(1<<9)));
3085 bnx2x_cl45_read(bp
, port
,
3086 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
3089 MDIO_PMA_REG_ROM_VER2
,
3091 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
3092 bnx2x_cl45_write(bp
, port
,
3093 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
3096 MDIO_PMA_REG_ROM_VER2
,
3097 (rom_ver2_val
& 0xff00) | (edc_mode
& 0x00ff));
3099 bnx2x_cl45_write(bp
, port
,
3100 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
3103 MDIO_PMA_REG_PHY_IDENTIFIER
,
3104 (phy_identifier
| (1<<9)));
3110 static u8
bnx2x_wait_for_sfp_module_initialized(struct link_params
*params
)
3113 struct bnx2x
*bp
= params
->bp
;
3115 /* Initialization time after hot-plug may take up to 300ms for some
3116 phys type ( e.g. JDSU ) */
3117 for (timeout
= 0; timeout
< 60; timeout
++) {
3118 if (bnx2x_read_sfp_module_eeprom(params
, 1, 1, &val
)
3120 DP(NETIF_MSG_LINK
, "SFP+ module initialization "
3121 "took %d ms\n", timeout
* 5);
3129 static void bnx2x_8727_power_module(struct bnx2x
*bp
,
3130 struct link_params
*params
,
3131 u8 ext_phy_addr
, u8 is_power_up
) {
3132 /* Make sure GPIOs are not using for LED mode */
3134 u8 port
= params
->port
;
3136 * In the GPIO register, bit 4 is use to detemine if the GPIOs are
3137 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
3139 * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
3140 * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
3141 * where the 1st bit is the over-current(only input), and 2nd bit is
3142 * for power( only output )
3146 * In case of NOC feature is disabled and power is up, set GPIO control
3147 * as input to enable listening of over-current indication
3150 if (!(params
->feature_config_flags
&
3151 FEATURE_CONFIG_BCM8727_NOC
) && is_power_up
)
3155 * Set GPIO control to OUTPUT, and set the power bit
3156 * to according to the is_power_up
3158 val
= ((!(is_power_up
)) << 1);
3160 bnx2x_cl45_write(bp
, port
,
3161 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
3164 MDIO_PMA_REG_8727_GPIO_CTRL
,
3168 static u8
bnx2x_sfp_module_detection(struct link_params
*params
)
3170 struct bnx2x
*bp
= params
->bp
;
3173 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
3174 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
3175 u32 val
= REG_RD(bp
, params
->shmem_base
+
3176 offsetof(struct shmem_region
, dev_info
.
3177 port_feature_config
[params
->port
].config
));
3179 DP(NETIF_MSG_LINK
, "SFP+ module plugged in/out detected on port %d\n",
3182 if (bnx2x_get_edc_mode(params
, &edc_mode
) != 0) {
3183 DP(NETIF_MSG_LINK
, "Failed to get valid module type\n");
3185 } else if (bnx2x_verify_sfp_module(params
) !=
3187 /* check SFP+ module compatibility */
3188 DP(NETIF_MSG_LINK
, "Module verification failed!!\n");
3190 /* Turn on fault module-detected led */
3191 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_0
,
3192 MISC_REGISTERS_GPIO_HIGH
,
3194 if ((ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
) &&
3195 ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
3196 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN
)) {
3197 /* Shutdown SFP+ module */
3198 DP(NETIF_MSG_LINK
, "Shutdown SFP+ module!!\n");
3199 bnx2x_8727_power_module(bp
, params
,
3204 /* Turn off fault module-detected led */
3205 DP(NETIF_MSG_LINK
, "Turn off fault module-detected led\n");
3206 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_0
,
3207 MISC_REGISTERS_GPIO_LOW
,
3211 /* power up the SFP module */
3212 if (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
)
3213 bnx2x_8727_power_module(bp
, params
, ext_phy_addr
, 1);
3215 /* Check and set limiting mode / LRM mode on 8726.
3216 On 8727 it is done automatically */
3217 if (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
)
3218 bnx2x_bcm8726_set_limiting_mode(params
, edc_mode
);
3220 bnx2x_bcm8727_set_limiting_mode(params
, edc_mode
);
3222 * Enable transmit for this module if the module is approved, or
3223 * if unapproved modules should also enable the Tx laser
3226 (val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) !=
3227 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER
)
3228 bnx2x_sfp_set_transmitter(bp
, params
->port
,
3229 ext_phy_type
, ext_phy_addr
, 1);
3231 bnx2x_sfp_set_transmitter(bp
, params
->port
,
3232 ext_phy_type
, ext_phy_addr
, 0);
3237 void bnx2x_handle_module_detect_int(struct link_params
*params
)
3239 struct bnx2x
*bp
= params
->bp
;
3241 u8 port
= params
->port
;
3243 /* Set valid module led off */
3244 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_0
,
3245 MISC_REGISTERS_GPIO_HIGH
,
3248 /* Get current gpio val refelecting module plugged in / out*/
3249 gpio_val
= bnx2x_get_gpio(bp
, MISC_REGISTERS_GPIO_3
, port
);
3251 /* Call the handling function in case module is detected */
3252 if (gpio_val
== 0) {
3254 bnx2x_set_gpio_int(bp
, MISC_REGISTERS_GPIO_3
,
3255 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR
,
3258 if (bnx2x_wait_for_sfp_module_initialized(params
) ==
3260 bnx2x_sfp_module_detection(params
);
3262 DP(NETIF_MSG_LINK
, "SFP+ module is not initialized\n");
3264 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
3267 XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
3268 u32 val
= REG_RD(bp
, params
->shmem_base
+
3269 offsetof(struct shmem_region
, dev_info
.
3270 port_feature_config
[params
->port
].
3273 bnx2x_set_gpio_int(bp
, MISC_REGISTERS_GPIO_3
,
3274 MISC_REGISTERS_GPIO_INT_OUTPUT_SET
,
3276 /* Module was plugged out. */
3277 /* Disable transmit for this module */
3278 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
3279 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER
)
3280 bnx2x_sfp_set_transmitter(bp
, params
->port
,
3281 ext_phy_type
, ext_phy_addr
, 0);
3285 static void bnx2x_bcm807x_force_10G(struct link_params
*params
)
3287 struct bnx2x
*bp
= params
->bp
;
3288 u8 port
= params
->port
;
3289 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
3290 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
3292 /* Force KR or KX */
3293 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3297 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3299 MDIO_PMA_REG_10G_CTRL2
,
3301 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3303 MDIO_PMA_REG_BCM_CTRL
,
3305 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3311 static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params
*params
)
3313 struct bnx2x
*bp
= params
->bp
;
3314 u8 port
= params
->port
;
3316 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
3317 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
3319 bnx2x_cl45_read(bp
, params
->port
,
3320 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
3323 MDIO_PMA_REG_8073_CHIP_REV
, &val
);
3326 /* Mustn't set low power mode in 8073 A0 */
3330 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
3331 bnx2x_cl45_read(bp
, port
, ext_phy_type
, ext_phy_addr
,
3333 MDIO_XS_PLL_SEQUENCER
, &val
);
3335 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3336 MDIO_XS_DEVAD
, MDIO_XS_PLL_SEQUENCER
, val
);
3339 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3340 MDIO_XS_DEVAD
, 0x805E, 0x1077);
3341 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3342 MDIO_XS_DEVAD
, 0x805D, 0x0000);
3343 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3344 MDIO_XS_DEVAD
, 0x805C, 0x030B);
3345 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3346 MDIO_XS_DEVAD
, 0x805B, 0x1240);
3347 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3348 MDIO_XS_DEVAD
, 0x805A, 0x2490);
3351 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3352 MDIO_XS_DEVAD
, 0x80A7, 0x0C74);
3353 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3354 MDIO_XS_DEVAD
, 0x80A6, 0x9041);
3355 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3356 MDIO_XS_DEVAD
, 0x80A5, 0x4640);
3359 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3360 MDIO_XS_DEVAD
, 0x80FE, 0x01C4);
3361 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3362 MDIO_XS_DEVAD
, 0x80FD, 0x9249);
3363 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3364 MDIO_XS_DEVAD
, 0x80FC, 0x2015);
3366 /* Enable PLL sequencer (use read-modify-write to set bit 13) */
3367 bnx2x_cl45_read(bp
, port
, ext_phy_type
, ext_phy_addr
,
3369 MDIO_XS_PLL_SEQUENCER
, &val
);
3371 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3372 MDIO_XS_DEVAD
, MDIO_XS_PLL_SEQUENCER
, val
);
3375 static void bnx2x_8073_set_pause_cl37(struct link_params
*params
,
3376 struct link_vars
*vars
)
3378 struct bnx2x
*bp
= params
->bp
;
3380 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
3381 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
3383 bnx2x_cl45_read(bp
, params
->port
,
3387 MDIO_AN_REG_CL37_FC_LD
, &cl37_val
);
3389 cl37_val
&= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
3390 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3392 if ((vars
->ieee_fc
&
3393 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC
) ==
3394 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC
) {
3395 cl37_val
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC
;
3397 if ((vars
->ieee_fc
&
3398 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) ==
3399 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) {
3400 cl37_val
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
;
3402 if ((vars
->ieee_fc
&
3403 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) ==
3404 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) {
3405 cl37_val
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
3408 "Ext phy AN advertize cl37 0x%x\n", cl37_val
);
3410 bnx2x_cl45_write(bp
, params
->port
,
3414 MDIO_AN_REG_CL37_FC_LD
, cl37_val
);
3418 static void bnx2x_ext_phy_set_pause(struct link_params
*params
,
3419 struct link_vars
*vars
)
3421 struct bnx2x
*bp
= params
->bp
;
3423 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
3424 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
3426 /* read modify write pause advertizing */
3427 bnx2x_cl45_read(bp
, params
->port
,
3431 MDIO_AN_REG_ADV_PAUSE
, &val
);
3433 val
&= ~MDIO_AN_REG_ADV_PAUSE_BOTH
;
3435 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3437 if ((vars
->ieee_fc
&
3438 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) ==
3439 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) {
3440 val
|= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC
;
3442 if ((vars
->ieee_fc
&
3443 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) ==
3444 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) {
3446 MDIO_AN_REG_ADV_PAUSE_PAUSE
;
3449 "Ext phy AN advertize 0x%x\n", val
);
3450 bnx2x_cl45_write(bp
, params
->port
,
3454 MDIO_AN_REG_ADV_PAUSE
, val
);
3456 static void bnx2x_set_preemphasis(struct link_params
*params
)
3459 struct bnx2x
*bp
= params
->bp
;
3461 for (bank
= MDIO_REG_BANK_RX0
, i
= 0; bank
<= MDIO_REG_BANK_RX3
;
3462 bank
+= (MDIO_REG_BANK_RX1
-MDIO_REG_BANK_RX0
), i
++) {
3463 CL45_WR_OVER_CL22(bp
, params
->port
,
3466 MDIO_RX0_RX_EQ_BOOST
,
3467 params
->xgxs_config_rx
[i
]);
3470 for (bank
= MDIO_REG_BANK_TX0
, i
= 0; bank
<= MDIO_REG_BANK_TX3
;
3471 bank
+= (MDIO_REG_BANK_TX1
- MDIO_REG_BANK_TX0
), i
++) {
3472 CL45_WR_OVER_CL22(bp
, params
->port
,
3476 params
->xgxs_config_tx
[i
]);
3481 static void bnx2x_8481_set_led4(struct link_params
*params
,
3482 u32 ext_phy_type
, u8 ext_phy_addr
)
3484 struct bnx2x
*bp
= params
->bp
;
3486 /* PHYC_CTL_LED_CTL */
3487 bnx2x_cl45_write(bp
, params
->port
,
3491 MDIO_PMA_REG_8481_LINK_SIGNAL
, 0xa482);
3493 /* Unmask LED4 for 10G link */
3494 bnx2x_cl45_write(bp
, params
->port
,
3498 MDIO_PMA_REG_8481_SIGNAL_MASK
, (1<<6));
3499 /* 'Interrupt Mask' */
3500 bnx2x_cl45_write(bp
, params
->port
,
3506 static void bnx2x_8481_set_legacy_led_mode(struct link_params
*params
,
3507 u32 ext_phy_type
, u8 ext_phy_addr
)
3509 struct bnx2x
*bp
= params
->bp
;
3511 /* LED1 (10G Link): Disable LED1 when 10/100/1000 link */
3512 /* LED2 (1G/100/10 Link): Enable LED2 when 10/100/1000 link) */
3513 bnx2x_cl45_write(bp
, params
->port
,
3517 MDIO_AN_REG_8481_LEGACY_SHADOW
,
3518 (1<<15) | (0xd << 10) | (0xc<<4) | 0xe);
3521 static void bnx2x_8481_set_10G_led_mode(struct link_params
*params
,
3522 u32 ext_phy_type
, u8 ext_phy_addr
)
3524 struct bnx2x
*bp
= params
->bp
;
3527 /* LED1 (10G Link) */
3528 /* Enable continuse based on source 7(10G-link) */
3529 bnx2x_cl45_read(bp
, params
->port
,
3533 MDIO_PMA_REG_8481_LINK_SIGNAL
,
3535 /* Set bit 2 to 0, and bits [1:0] to 10 */
3536 val1
&= ~((1<<0) | (1<<2) | (1<<7)); /* Clear bits 0,2,7*/
3537 val1
|= ((1<<1) | (1<<6)); /* Set bit 1, 6 */
3539 bnx2x_cl45_write(bp
, params
->port
,
3543 MDIO_PMA_REG_8481_LINK_SIGNAL
,
3546 /* Unmask LED1 for 10G link */
3547 bnx2x_cl45_read(bp
, params
->port
,
3551 MDIO_PMA_REG_8481_LED1_MASK
,
3553 /* Set bit 2 to 0, and bits [1:0] to 10 */
3555 bnx2x_cl45_write(bp
, params
->port
,
3559 MDIO_PMA_REG_8481_LED1_MASK
,
3562 /* LED2 (1G/100/10G Link) */
3563 /* Mask LED2 for 10G link */
3564 bnx2x_cl45_write(bp
, params
->port
,
3568 MDIO_PMA_REG_8481_LED2_MASK
,
3571 /* Unmask LED3 for 10G link */
3572 bnx2x_cl45_write(bp
, params
->port
,
3576 MDIO_PMA_REG_8481_LED3_MASK
,
3578 bnx2x_cl45_write(bp
, params
->port
,
3582 MDIO_PMA_REG_8481_LED3_BLINK
,
3587 static void bnx2x_init_internal_phy(struct link_params
*params
,
3588 struct link_vars
*vars
,
3591 struct bnx2x
*bp
= params
->bp
;
3593 if (!(vars
->phy_flags
& PHY_SGMII_FLAG
)) {
3594 if ((XGXS_EXT_PHY_TYPE(params
->ext_phy_config
) ==
3595 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) &&
3596 (params
->feature_config_flags
&
3597 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
))
3598 bnx2x_set_preemphasis(params
);
3600 /* forced speed requested? */
3601 if (vars
->line_speed
!= SPEED_AUTO_NEG
||
3602 ((XGXS_EXT_PHY_TYPE(params
->ext_phy_config
) ==
3603 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) &&
3604 params
->loopback_mode
== LOOPBACK_EXT
)) {
3605 DP(NETIF_MSG_LINK
, "not SGMII, no AN\n");
3607 /* disable autoneg */
3608 bnx2x_set_autoneg(params
, vars
, 0);
3610 /* program speed and duplex */
3611 bnx2x_program_serdes(params
, vars
);
3613 } else { /* AN_mode */
3614 DP(NETIF_MSG_LINK
, "not SGMII, AN\n");
3617 bnx2x_set_brcm_cl37_advertisment(params
);
3619 /* program duplex & pause advertisement (for aneg) */
3620 bnx2x_set_ieee_aneg_advertisment(params
,
3623 /* enable autoneg */
3624 bnx2x_set_autoneg(params
, vars
, enable_cl73
);
3626 /* enable and restart AN */
3627 bnx2x_restart_autoneg(params
, enable_cl73
);
3630 } else { /* SGMII mode */
3631 DP(NETIF_MSG_LINK
, "SGMII\n");
3633 bnx2x_initialize_sgmii_process(params
, vars
);
3637 static u8
bnx2x_ext_phy_init(struct link_params
*params
, struct link_vars
*vars
)
3639 struct bnx2x
*bp
= params
->bp
;
3647 if (vars
->phy_flags
& PHY_XGXS_FLAG
) {
3648 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
3650 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
3651 /* Make sure that the soft reset is off (expect for the 8072:
3652 * due to the lock, it will be done inside the specific
3655 if ((ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) &&
3656 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
) &&
3657 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
) &&
3658 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
) &&
3659 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
)) {
3660 /* Wait for soft reset to get cleared upto 1 sec */
3661 for (cnt
= 0; cnt
< 1000; cnt
++) {
3662 bnx2x_cl45_read(bp
, params
->port
,
3666 MDIO_PMA_REG_CTRL
, &ctrl
);
3667 if (!(ctrl
& (1<<15)))
3671 DP(NETIF_MSG_LINK
, "control reg 0x%x (after %d ms)\n",
3675 switch (ext_phy_type
) {
3676 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
3679 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
:
3680 DP(NETIF_MSG_LINK
, "XGXS 8705\n");
3682 bnx2x_cl45_write(bp
, params
->port
,
3686 MDIO_PMA_REG_MISC_CTRL
,
3688 bnx2x_cl45_write(bp
, params
->port
,
3692 MDIO_PMA_REG_PHY_IDENTIFIER
,
3694 bnx2x_cl45_write(bp
, params
->port
,
3698 MDIO_PMA_REG_CMU_PLL_BYPASS
,
3700 bnx2x_cl45_write(bp
, params
->port
,
3704 MDIO_WIS_REG_LASI_CNTL
, 0x1);
3706 /* BCM8705 doesn't have microcode, hence the 0 */
3707 bnx2x_save_spirom_version(bp
, params
->port
,
3708 params
->shmem_base
, 0);
3711 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
:
3712 /* Wait until fw is loaded */
3713 for (cnt
= 0; cnt
< 100; cnt
++) {
3714 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
3715 ext_phy_addr
, MDIO_PMA_DEVAD
,
3716 MDIO_PMA_REG_ROM_VER1
, &val
);
3721 DP(NETIF_MSG_LINK
, "XGXS 8706 is initialized "
3722 "after %d ms\n", cnt
);
3723 if ((params
->feature_config_flags
&
3724 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
)) {
3727 for (i
= 0; i
< 4; i
++) {
3728 reg
= MDIO_XS_8706_REG_BANK_RX0
+
3729 i
*(MDIO_XS_8706_REG_BANK_RX1
-
3730 MDIO_XS_8706_REG_BANK_RX0
);
3731 bnx2x_cl45_read(bp
, params
->port
,
3736 /* Clear first 3 bits of the control */
3738 /* Set control bits according to
3740 val
|= (params
->xgxs_config_rx
[i
] &
3742 DP(NETIF_MSG_LINK
, "Setting RX"
3743 "Equalizer to BCM8706 reg 0x%x"
3744 " <-- val 0x%x\n", reg
, val
);
3745 bnx2x_cl45_write(bp
, params
->port
,
3753 if (params
->req_line_speed
== SPEED_10000
) {
3754 DP(NETIF_MSG_LINK
, "XGXS 8706 force 10Gbps\n");
3756 bnx2x_cl45_write(bp
, params
->port
,
3760 MDIO_PMA_REG_DIGITAL_CTRL
,
3762 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3763 ext_phy_addr
, MDIO_PMA_DEVAD
,
3764 MDIO_PMA_REG_LASI_CTRL
, 1);
3766 /* Force 1Gbps using autoneg with 1G
3769 /* Allow CL37 through CL73 */
3770 DP(NETIF_MSG_LINK
, "XGXS 8706 AutoNeg\n");
3771 bnx2x_cl45_write(bp
, params
->port
,
3775 MDIO_AN_REG_CL37_CL73
,
3778 /* Enable Full-Duplex advertisment on CL37 */
3779 bnx2x_cl45_write(bp
, params
->port
,
3783 MDIO_AN_REG_CL37_FC_LP
,
3785 /* Enable CL37 AN */
3786 bnx2x_cl45_write(bp
, params
->port
,
3790 MDIO_AN_REG_CL37_AN
,
3793 bnx2x_cl45_write(bp
, params
->port
,
3797 MDIO_AN_REG_ADV
, (1<<5));
3799 /* Enable clause 73 AN */
3800 bnx2x_cl45_write(bp
, params
->port
,
3806 bnx2x_cl45_write(bp
, params
->port
,
3810 MDIO_PMA_REG_RX_ALARM_CTRL
,
3812 bnx2x_cl45_write(bp
, params
->port
,
3816 MDIO_PMA_REG_LASI_CTRL
, 0x0004);
3819 bnx2x_save_bcm_spirom_ver(bp
, params
->port
,
3822 params
->shmem_base
);
3824 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
3825 DP(NETIF_MSG_LINK
, "Initializing BCM8726\n");
3826 bnx2x_bcm8726_external_rom_boot(params
);
3828 /* Need to call module detected on initialization since
3829 the module detection triggered by actual module
3830 insertion might occur before driver is loaded, and when
3831 driver is loaded, it reset all registers, including the
3833 bnx2x_sfp_module_detection(params
);
3835 /* Set Flow control */
3836 bnx2x_ext_phy_set_pause(params
, vars
);
3837 if (params
->req_line_speed
== SPEED_1000
) {
3838 DP(NETIF_MSG_LINK
, "Setting 1G force\n");
3839 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3840 ext_phy_addr
, MDIO_PMA_DEVAD
,
3841 MDIO_PMA_REG_CTRL
, 0x40);
3842 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3843 ext_phy_addr
, MDIO_PMA_DEVAD
,
3844 MDIO_PMA_REG_10G_CTRL2
, 0xD);
3845 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3846 ext_phy_addr
, MDIO_PMA_DEVAD
,
3847 MDIO_PMA_REG_LASI_CTRL
, 0x5);
3848 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3849 ext_phy_addr
, MDIO_PMA_DEVAD
,
3850 MDIO_PMA_REG_RX_ALARM_CTRL
,
3852 } else if ((params
->req_line_speed
==
3854 ((params
->speed_cap_mask
&
3855 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
))) {
3856 DP(NETIF_MSG_LINK
, "Setting 1G clause37 \n");
3857 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3858 ext_phy_addr
, MDIO_AN_DEVAD
,
3859 MDIO_AN_REG_ADV
, 0x20);
3860 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3861 ext_phy_addr
, MDIO_AN_DEVAD
,
3862 MDIO_AN_REG_CL37_CL73
, 0x040c);
3863 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3864 ext_phy_addr
, MDIO_AN_DEVAD
,
3865 MDIO_AN_REG_CL37_FC_LD
, 0x0020);
3866 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3867 ext_phy_addr
, MDIO_AN_DEVAD
,
3868 MDIO_AN_REG_CL37_AN
, 0x1000);
3869 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3870 ext_phy_addr
, MDIO_AN_DEVAD
,
3871 MDIO_AN_REG_CTRL
, 0x1200);
3873 /* Enable RX-ALARM control to receive
3874 interrupt for 1G speed change */
3875 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3876 ext_phy_addr
, MDIO_PMA_DEVAD
,
3877 MDIO_PMA_REG_LASI_CTRL
, 0x4);
3878 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3879 ext_phy_addr
, MDIO_PMA_DEVAD
,
3880 MDIO_PMA_REG_RX_ALARM_CTRL
,
3883 } else { /* Default 10G. Set only LASI control */
3884 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3885 ext_phy_addr
, MDIO_PMA_DEVAD
,
3886 MDIO_PMA_REG_LASI_CTRL
, 1);
3889 /* Set TX PreEmphasis if needed */
3890 if ((params
->feature_config_flags
&
3891 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
)) {
3892 DP(NETIF_MSG_LINK
, "Setting TX_CTRL1 0x%x,"
3894 params
->xgxs_config_tx
[0],
3895 params
->xgxs_config_tx
[1]);
3896 bnx2x_cl45_write(bp
, params
->port
,
3900 MDIO_PMA_REG_8726_TX_CTRL1
,
3901 params
->xgxs_config_tx
[0]);
3903 bnx2x_cl45_write(bp
, params
->port
,
3907 MDIO_PMA_REG_8726_TX_CTRL2
,
3908 params
->xgxs_config_tx
[1]);
3911 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
:
3912 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
:
3915 u16 rx_alarm_ctrl_val
;
3918 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
) {
3919 rx_alarm_ctrl_val
= 0x400;
3920 lasi_ctrl_val
= 0x0004;
3922 rx_alarm_ctrl_val
= (1<<2);
3923 lasi_ctrl_val
= 0x0004;
3927 bnx2x_cl45_write(bp
, params
->port
,
3931 MDIO_PMA_REG_RX_ALARM_CTRL
,
3934 bnx2x_cl45_write(bp
, params
->port
,
3938 MDIO_PMA_REG_LASI_CTRL
,
3941 bnx2x_8073_set_pause_cl37(params
, vars
);
3944 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
)
3945 bnx2x_bcm8072_external_rom_boot(params
);
3947 /* In case of 8073 with long xaui lines,
3948 don't set the 8073 xaui low power*/
3949 bnx2x_bcm8073_set_xaui_low_power_mode(params
);
3951 bnx2x_cl45_read(bp
, params
->port
,
3955 MDIO_PMA_REG_M8051_MSGOUT_REG
,
3958 bnx2x_cl45_read(bp
, params
->port
,
3962 MDIO_PMA_REG_RX_ALARM
, &tmp1
);
3964 DP(NETIF_MSG_LINK
, "Before rom RX_ALARM(port1):"
3967 /* If this is forced speed, set to KR or KX
3968 * (all other are not supported)
3970 if (params
->loopback_mode
== LOOPBACK_EXT
) {
3971 bnx2x_bcm807x_force_10G(params
);
3973 "Forced speed 10G on 807X\n");
3976 bnx2x_cl45_write(bp
, params
->port
,
3977 ext_phy_type
, ext_phy_addr
,
3979 MDIO_PMA_REG_BCM_CTRL
,
3982 if (params
->req_line_speed
!= SPEED_AUTO_NEG
) {
3983 if (params
->req_line_speed
== SPEED_10000
) {
3985 } else if (params
->req_line_speed
==
3988 /* Note that 2.5G works only
3989 when used with 1G advertisment */
3995 if (params
->speed_cap_mask
&
3996 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
3999 /* Note that 2.5G works only when
4000 used with 1G advertisment */
4001 if (params
->speed_cap_mask
&
4002 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
|
4003 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
))
4006 "807x autoneg val = 0x%x\n", val
);
4009 bnx2x_cl45_write(bp
, params
->port
,
4013 MDIO_AN_REG_ADV
, val
);
4015 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
) {
4016 bnx2x_cl45_read(bp
, params
->port
,
4020 MDIO_AN_REG_8073_2_5G
, &tmp1
);
4022 if (((params
->speed_cap_mask
&
4023 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
) &&
4024 (params
->req_line_speed
==
4026 (params
->req_line_speed
==
4029 /* Allow 2.5G for A1 and above */
4030 bnx2x_cl45_read(bp
, params
->port
,
4031 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
4034 MDIO_PMA_REG_8073_CHIP_REV
, &phy_ver
);
4035 DP(NETIF_MSG_LINK
, "Add 2.5G\n");
4041 DP(NETIF_MSG_LINK
, "Disable 2.5G\n");
4045 bnx2x_cl45_write(bp
, params
->port
,
4049 MDIO_AN_REG_8073_2_5G
, tmp1
);
4052 /* Add support for CL37 (passive mode) II */
4054 bnx2x_cl45_read(bp
, params
->port
,
4058 MDIO_AN_REG_CL37_FC_LD
,
4061 bnx2x_cl45_write(bp
, params
->port
,
4065 MDIO_AN_REG_CL37_FC_LD
, (tmp1
|
4066 ((params
->req_duplex
== DUPLEX_FULL
) ?
4069 /* Add support for CL37 (passive mode) III */
4070 bnx2x_cl45_write(bp
, params
->port
,
4074 MDIO_AN_REG_CL37_AN
, 0x1000);
4077 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
) {
4078 /* The SNR will improve about 2db by changing
4079 BW and FEE main tap. Rest commands are executed
4081 /*Change FFE main cursor to 5 in EDC register*/
4082 if (bnx2x_8073_is_snr_needed(params
))
4083 bnx2x_cl45_write(bp
, params
->port
,
4087 MDIO_PMA_REG_EDC_FFE_MAIN
,
4090 /* Enable FEC (Forware Error Correction)
4091 Request in the AN */
4092 bnx2x_cl45_read(bp
, params
->port
,
4096 MDIO_AN_REG_ADV2
, &tmp1
);
4100 bnx2x_cl45_write(bp
, params
->port
,
4104 MDIO_AN_REG_ADV2
, tmp1
);
4108 bnx2x_ext_phy_set_pause(params
, vars
);
4110 /* Restart autoneg */
4112 bnx2x_cl45_write(bp
, params
->port
,
4116 MDIO_AN_REG_CTRL
, 0x1200);
4117 DP(NETIF_MSG_LINK
, "807x Autoneg Restart: "
4118 "Advertise 1G=%x, 10G=%x\n",
4119 ((val
& (1<<5)) > 0),
4120 ((val
& (1<<7)) > 0));
4124 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
4127 u16 rx_alarm_ctrl_val
;
4130 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
4133 rx_alarm_ctrl_val
= (1<<2) | (1<<5) ;
4134 lasi_ctrl_val
= 0x0004;
4136 DP(NETIF_MSG_LINK
, "Initializing BCM8727\n");
4138 bnx2x_cl45_write(bp
, params
->port
,
4142 MDIO_PMA_REG_RX_ALARM_CTRL
,
4145 bnx2x_cl45_write(bp
, params
->port
,
4149 MDIO_PMA_REG_LASI_CTRL
,
4152 /* Initially configure MOD_ABS to interrupt when
4153 module is presence( bit 8) */
4154 bnx2x_cl45_read(bp
, params
->port
,
4158 MDIO_PMA_REG_PHY_IDENTIFIER
, &mod_abs
);
4159 /* Set EDC off by setting OPTXLOS signal input to low
4161 When the EDC is off it locks onto a reference clock and
4162 avoids becoming 'lost'.*/
4163 mod_abs
&= ~((1<<8) | (1<<9));
4164 bnx2x_cl45_write(bp
, params
->port
,
4168 MDIO_PMA_REG_PHY_IDENTIFIER
, mod_abs
);
4170 /* Make MOD_ABS give interrupt on change */
4171 bnx2x_cl45_read(bp
, params
->port
,
4175 MDIO_PMA_REG_8727_PCS_OPT_CTRL
,
4178 bnx2x_cl45_write(bp
, params
->port
,
4182 MDIO_PMA_REG_8727_PCS_OPT_CTRL
,
4185 /* Set 8727 GPIOs to input to allow reading from the
4186 8727 GPIO0 status which reflect SFP+ module
4189 bnx2x_cl45_read(bp
, params
->port
,
4190 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
4193 MDIO_PMA_REG_8727_PCS_OPT_CTRL
,
4195 val
&= 0xff8f; /* Reset bits 4-6 */
4196 bnx2x_cl45_write(bp
, params
->port
,
4197 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
4200 MDIO_PMA_REG_8727_PCS_OPT_CTRL
,
4203 bnx2x_8727_power_module(bp
, params
, ext_phy_addr
, 1);
4204 bnx2x_bcm8073_set_xaui_low_power_mode(params
);
4206 bnx2x_cl45_read(bp
, params
->port
,
4210 MDIO_PMA_REG_M8051_MSGOUT_REG
,
4213 bnx2x_cl45_read(bp
, params
->port
,
4217 MDIO_PMA_REG_RX_ALARM
, &tmp1
);
4219 /* Set option 1G speed */
4220 if (params
->req_line_speed
== SPEED_1000
) {
4222 DP(NETIF_MSG_LINK
, "Setting 1G force\n");
4223 bnx2x_cl45_write(bp
, params
->port
,
4227 MDIO_PMA_REG_CTRL
, 0x40);
4228 bnx2x_cl45_write(bp
, params
->port
,
4232 MDIO_PMA_REG_10G_CTRL2
, 0xD);
4233 bnx2x_cl45_read(bp
, params
->port
,
4237 MDIO_PMA_REG_10G_CTRL2
, &tmp1
);
4238 DP(NETIF_MSG_LINK
, "1.7 = 0x%x \n", tmp1
);
4240 } else if ((params
->req_line_speed
==
4242 ((params
->speed_cap_mask
&
4243 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
))) {
4245 DP(NETIF_MSG_LINK
, "Setting 1G clause37 \n");
4246 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
4247 ext_phy_addr
, MDIO_AN_DEVAD
,
4248 MDIO_PMA_REG_8727_MISC_CTRL
, 0);
4249 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
4250 ext_phy_addr
, MDIO_AN_DEVAD
,
4251 MDIO_AN_REG_CL37_AN
, 0x1300);
4253 /* Since the 8727 has only single reset pin,
4254 need to set the 10G registers although it is
4256 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
4257 ext_phy_addr
, MDIO_AN_DEVAD
,
4258 MDIO_AN_REG_CTRL
, 0x0020);
4259 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
4260 ext_phy_addr
, MDIO_AN_DEVAD
,
4262 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
4263 ext_phy_addr
, MDIO_PMA_DEVAD
,
4264 MDIO_PMA_REG_CTRL
, 0x2040);
4265 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
4266 ext_phy_addr
, MDIO_PMA_DEVAD
,
4267 MDIO_PMA_REG_10G_CTRL2
, 0x0008);
4270 /* Set 2-wire transfer rate to 400Khz since 100Khz
4271 is not operational */
4272 bnx2x_cl45_write(bp
, params
->port
,
4276 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR
,
4279 /* Set TX PreEmphasis if needed */
4280 if ((params
->feature_config_flags
&
4281 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
)) {
4282 DP(NETIF_MSG_LINK
, "Setting TX_CTRL1 0x%x,"
4284 params
->xgxs_config_tx
[0],
4285 params
->xgxs_config_tx
[1]);
4286 bnx2x_cl45_write(bp
, params
->port
,
4290 MDIO_PMA_REG_8727_TX_CTRL1
,
4291 params
->xgxs_config_tx
[0]);
4293 bnx2x_cl45_write(bp
, params
->port
,
4297 MDIO_PMA_REG_8727_TX_CTRL2
,
4298 params
->xgxs_config_tx
[1]);
4304 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
:
4306 u16 fw_ver1
, fw_ver2
;
4308 "Setting the SFX7101 LASI indication\n");
4310 bnx2x_cl45_write(bp
, params
->port
,
4314 MDIO_PMA_REG_LASI_CTRL
, 0x1);
4316 "Setting the SFX7101 LED to blink on traffic\n");
4317 bnx2x_cl45_write(bp
, params
->port
,
4321 MDIO_PMA_REG_7107_LED_CNTL
, (1<<3));
4323 bnx2x_ext_phy_set_pause(params
, vars
);
4324 /* Restart autoneg */
4325 bnx2x_cl45_read(bp
, params
->port
,
4329 MDIO_AN_REG_CTRL
, &val
);
4331 bnx2x_cl45_write(bp
, params
->port
,
4335 MDIO_AN_REG_CTRL
, val
);
4337 /* Save spirom version */
4338 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4339 ext_phy_addr
, MDIO_PMA_DEVAD
,
4340 MDIO_PMA_REG_7101_VER1
, &fw_ver1
);
4342 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4343 ext_phy_addr
, MDIO_PMA_DEVAD
,
4344 MDIO_PMA_REG_7101_VER2
, &fw_ver2
);
4346 bnx2x_save_spirom_version(params
->bp
, params
->port
,
4348 (u32
)(fw_ver1
<<16 | fw_ver2
));
4351 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
:
4352 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823
:
4353 /* This phy uses the NIG latch mechanism since link
4354 indication arrives through its LED4 and not via
4355 its LASI signal, so we get steady signal
4356 instead of clear on read */
4357 bnx2x_bits_en(bp
, NIG_REG_LATCH_BC_0
+ params
->port
*4,
4358 1 << NIG_LATCH_BC_ENABLE_MI_INT
);
4360 bnx2x_cl45_write(bp
, params
->port
,
4361 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
4364 MDIO_PMA_REG_CTRL
, 0x0000);
4366 bnx2x_8481_set_led4(params
, ext_phy_type
, ext_phy_addr
);
4367 if (params
->req_line_speed
== SPEED_AUTO_NEG
) {
4369 u16 autoneg_val
, an_1000_val
, an_10_100_val
;
4370 /* set 1000 speed advertisement */
4371 bnx2x_cl45_read(bp
, params
->port
,
4375 MDIO_AN_REG_8481_1000T_CTRL
,
4378 if (params
->speed_cap_mask
&
4379 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
) {
4380 an_1000_val
|= (1<<8);
4381 if (params
->req_duplex
== DUPLEX_FULL
)
4382 an_1000_val
|= (1<<9);
4383 DP(NETIF_MSG_LINK
, "Advertising 1G\n");
4385 an_1000_val
&= ~((1<<8) | (1<<9));
4387 bnx2x_cl45_write(bp
, params
->port
,
4391 MDIO_AN_REG_8481_1000T_CTRL
,
4394 /* set 100 speed advertisement */
4395 bnx2x_cl45_read(bp
, params
->port
,
4399 MDIO_AN_REG_8481_LEGACY_AN_ADV
,
4402 if (params
->speed_cap_mask
&
4403 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
|
4404 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
)) {
4405 an_10_100_val
|= (1<<7);
4406 if (params
->req_duplex
== DUPLEX_FULL
)
4407 an_10_100_val
|= (1<<8);
4409 "Advertising 100M\n");
4411 an_10_100_val
&= ~((1<<7) | (1<<8));
4413 /* set 10 speed advertisement */
4414 if (params
->speed_cap_mask
&
4415 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
|
4416 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
)) {
4417 an_10_100_val
|= (1<<5);
4418 if (params
->req_duplex
== DUPLEX_FULL
)
4419 an_10_100_val
|= (1<<6);
4420 DP(NETIF_MSG_LINK
, "Advertising 10M\n");
4423 an_10_100_val
&= ~((1<<5) | (1<<6));
4425 bnx2x_cl45_write(bp
, params
->port
,
4429 MDIO_AN_REG_8481_LEGACY_AN_ADV
,
4432 bnx2x_cl45_read(bp
, params
->port
,
4436 MDIO_AN_REG_8481_LEGACY_MII_CTRL
,
4439 /* Disable forced speed */
4440 autoneg_val
&= ~(1<<6|1<<13);
4442 /* Enable autoneg and restart autoneg
4443 for legacy speeds */
4444 autoneg_val
|= (1<<9|1<<12);
4446 if (params
->req_duplex
== DUPLEX_FULL
)
4447 autoneg_val
|= (1<<8);
4449 autoneg_val
&= ~(1<<8);
4451 bnx2x_cl45_write(bp
, params
->port
,
4455 MDIO_AN_REG_8481_LEGACY_MII_CTRL
,
4458 if (params
->speed_cap_mask
&
4459 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
) {
4460 DP(NETIF_MSG_LINK
, "Advertising 10G\n");
4461 /* Restart autoneg for 10G*/
4463 bnx2x_cl45_write(bp
, params
->port
,
4467 MDIO_AN_REG_CTRL
, 0x3200);
4471 u16 autoneg_ctrl
, pma_ctrl
;
4472 bnx2x_cl45_read(bp
, params
->port
,
4476 MDIO_AN_REG_8481_LEGACY_MII_CTRL
,
4479 /* Disable autoneg */
4480 autoneg_ctrl
&= ~(1<<12);
4482 /* Set 1000 force */
4483 switch (params
->req_line_speed
) {
4486 "Unable to set 10G force !\n");
4489 bnx2x_cl45_read(bp
, params
->port
,
4495 autoneg_ctrl
&= ~(1<<13);
4496 autoneg_ctrl
|= (1<<6);
4497 pma_ctrl
&= ~(1<<13);
4500 "Setting 1000M force\n");
4501 bnx2x_cl45_write(bp
, params
->port
,
4509 autoneg_ctrl
|= (1<<13);
4510 autoneg_ctrl
&= ~(1<<6);
4512 "Setting 100M force\n");
4515 autoneg_ctrl
&= ~(1<<13);
4516 autoneg_ctrl
&= ~(1<<6);
4518 "Setting 10M force\n");
4523 if (params
->req_duplex
== DUPLEX_FULL
) {
4524 autoneg_ctrl
|= (1<<8);
4526 "Setting full duplex\n");
4528 autoneg_ctrl
&= ~(1<<8);
4530 /* Update autoneg ctrl and pma ctrl */
4531 bnx2x_cl45_write(bp
, params
->port
,
4535 MDIO_AN_REG_8481_LEGACY_MII_CTRL
,
4539 /* Save spirom version */
4540 bnx2x_save_8481_spirom_version(bp
, params
->port
,
4542 params
->shmem_base
);
4544 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
:
4546 "XGXS PHY Failure detected 0x%x\n",
4547 params
->ext_phy_config
);
4551 DP(NETIF_MSG_LINK
, "BAD XGXS ext_phy_config 0x%x\n",
4552 params
->ext_phy_config
);
4557 } else { /* SerDes */
4559 ext_phy_type
= SERDES_EXT_PHY_TYPE(params
->ext_phy_config
);
4560 switch (ext_phy_type
) {
4561 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT
:
4562 DP(NETIF_MSG_LINK
, "SerDes Direct\n");
4565 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482
:
4566 DP(NETIF_MSG_LINK
, "SerDes 5482\n");
4570 DP(NETIF_MSG_LINK
, "BAD SerDes ext_phy_config 0x%x\n",
4571 params
->ext_phy_config
);
4578 static void bnx2x_8727_handle_mod_abs(struct link_params
*params
)
4580 struct bnx2x
*bp
= params
->bp
;
4581 u16 mod_abs
, rx_alarm_status
;
4582 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
4583 u32 val
= REG_RD(bp
, params
->shmem_base
+
4584 offsetof(struct shmem_region
, dev_info
.
4585 port_feature_config
[params
->port
].
4587 bnx2x_cl45_read(bp
, params
->port
,
4588 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
4591 MDIO_PMA_REG_PHY_IDENTIFIER
, &mod_abs
);
4592 if (mod_abs
& (1<<8)) {
4594 /* Module is absent */
4595 DP(NETIF_MSG_LINK
, "MOD_ABS indication "
4596 "show module is absent\n");
4598 /* 1. Set mod_abs to detect next module
4600 2. Set EDC off by setting OPTXLOS signal input to low
4602 When the EDC is off it locks onto a reference clock and
4603 avoids becoming 'lost'.*/
4604 mod_abs
&= ~((1<<8)|(1<<9));
4605 bnx2x_cl45_write(bp
, params
->port
,
4606 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
4609 MDIO_PMA_REG_PHY_IDENTIFIER
, mod_abs
);
4611 /* Clear RX alarm since it stays up as long as
4612 the mod_abs wasn't changed */
4613 bnx2x_cl45_read(bp
, params
->port
,
4614 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
4617 MDIO_PMA_REG_RX_ALARM
, &rx_alarm_status
);
4620 /* Module is present */
4621 DP(NETIF_MSG_LINK
, "MOD_ABS indication "
4622 "show module is present\n");
4623 /* First thing, disable transmitter,
4624 and if the module is ok, the
4625 module_detection will enable it*/
4627 /* 1. Set mod_abs to detect next module
4628 absent event ( bit 8)
4629 2. Restore the default polarity of the OPRXLOS signal and
4630 this signal will then correctly indicate the presence or
4631 absence of the Rx signal. (bit 9) */
4632 mod_abs
|= ((1<<8)|(1<<9));
4633 bnx2x_cl45_write(bp
, params
->port
,
4634 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
4637 MDIO_PMA_REG_PHY_IDENTIFIER
, mod_abs
);
4639 /* Clear RX alarm since it stays up as long as
4640 the mod_abs wasn't changed. This is need to be done
4641 before calling the module detection, otherwise it will clear
4642 the link update alarm */
4643 bnx2x_cl45_read(bp
, params
->port
,
4644 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
4647 MDIO_PMA_REG_RX_ALARM
, &rx_alarm_status
);
4650 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
4651 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER
)
4652 bnx2x_sfp_set_transmitter(bp
, params
->port
,
4653 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
4656 if (bnx2x_wait_for_sfp_module_initialized(params
)
4658 bnx2x_sfp_module_detection(params
);
4660 DP(NETIF_MSG_LINK
, "SFP+ module is not initialized\n");
4663 DP(NETIF_MSG_LINK
, "8727 RX_ALARM_STATUS 0x%x\n",
4665 /* No need to check link status in case of
4666 module plugged in/out */
4670 static u8
bnx2x_ext_phy_is_link_up(struct link_params
*params
,
4671 struct link_vars
*vars
,
4674 struct bnx2x
*bp
= params
->bp
;
4678 u16 rx_sd
, pcs_status
;
4679 u8 ext_phy_link_up
= 0;
4680 u8 port
= params
->port
;
4682 if (vars
->phy_flags
& PHY_XGXS_FLAG
) {
4683 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
4684 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
4685 switch (ext_phy_type
) {
4686 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
4687 DP(NETIF_MSG_LINK
, "XGXS Direct\n");
4688 ext_phy_link_up
= 1;
4691 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
:
4692 DP(NETIF_MSG_LINK
, "XGXS 8705\n");
4693 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4696 MDIO_WIS_REG_LASI_STATUS
, &val1
);
4697 DP(NETIF_MSG_LINK
, "8705 LASI status 0x%x\n", val1
);
4699 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4702 MDIO_WIS_REG_LASI_STATUS
, &val1
);
4703 DP(NETIF_MSG_LINK
, "8705 LASI status 0x%x\n", val1
);
4705 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4708 MDIO_PMA_REG_RX_SD
, &rx_sd
);
4710 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4714 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4719 DP(NETIF_MSG_LINK
, "8705 1.c809 val=0x%x\n", val1
);
4720 ext_phy_link_up
= ((rx_sd
& 0x1) && (val1
& (1<<9)) &&
4721 ((val1
& (1<<8)) == 0));
4722 if (ext_phy_link_up
)
4723 vars
->line_speed
= SPEED_10000
;
4726 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
:
4727 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
4728 DP(NETIF_MSG_LINK
, "XGXS 8706/8726\n");
4730 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4732 MDIO_PMA_DEVAD
, MDIO_PMA_REG_RX_ALARM
,
4734 /* clear LASI indication*/
4735 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4737 MDIO_PMA_DEVAD
, MDIO_PMA_REG_LASI_STATUS
,
4739 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4741 MDIO_PMA_DEVAD
, MDIO_PMA_REG_LASI_STATUS
,
4743 DP(NETIF_MSG_LINK
, "8706/8726 LASI status 0x%x-->"
4744 "0x%x\n", val1
, val2
);
4746 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4748 MDIO_PMA_DEVAD
, MDIO_PMA_REG_RX_SD
,
4750 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4752 MDIO_PCS_DEVAD
, MDIO_PCS_REG_STATUS
,
4754 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4756 MDIO_AN_DEVAD
, MDIO_AN_REG_LINK_STATUS
,
4758 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4760 MDIO_AN_DEVAD
, MDIO_AN_REG_LINK_STATUS
,
4763 DP(NETIF_MSG_LINK
, "8706/8726 rx_sd 0x%x"
4764 " pcs_status 0x%x 1Gbps link_status 0x%x\n",
4765 rx_sd
, pcs_status
, val2
);
4766 /* link is up if both bit 0 of pmd_rx_sd and
4767 * bit 0 of pcs_status are set, or if the autoneg bit
4770 ext_phy_link_up
= ((rx_sd
& pcs_status
& 0x1) ||
4772 if (ext_phy_link_up
) {
4774 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
) {
4775 /* If transmitter is disabled,
4776 ignore false link up indication */
4777 bnx2x_cl45_read(bp
, params
->port
,
4781 MDIO_PMA_REG_PHY_IDENTIFIER
,
4783 if (val1
& (1<<15)) {
4784 DP(NETIF_MSG_LINK
, "Tx is "
4786 ext_phy_link_up
= 0;
4791 vars
->line_speed
= SPEED_1000
;
4793 vars
->line_speed
= SPEED_10000
;
4797 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
4799 u16 link_status
= 0;
4800 u16 rx_alarm_status
;
4801 /* Check the LASI */
4802 bnx2x_cl45_read(bp
, params
->port
,
4806 MDIO_PMA_REG_RX_ALARM
, &rx_alarm_status
);
4808 DP(NETIF_MSG_LINK
, "8727 RX_ALARM_STATUS 0x%x\n",
4811 bnx2x_cl45_read(bp
, params
->port
,
4815 MDIO_PMA_REG_LASI_STATUS
, &val1
);
4818 "8727 LASI status 0x%x\n",
4822 bnx2x_cl45_read(bp
, params
->port
,
4826 MDIO_PMA_REG_M8051_MSGOUT_REG
,
4830 * If a module is present and there is need to check
4833 if (!(params
->feature_config_flags
&
4834 FEATURE_CONFIG_BCM8727_NOC
) &&
4835 !(rx_alarm_status
& (1<<5))) {
4836 /* Check over-current using 8727 GPIO0 input*/
4837 bnx2x_cl45_read(bp
, params
->port
,
4841 MDIO_PMA_REG_8727_GPIO_CTRL
,
4844 if ((val1
& (1<<8)) == 0) {
4845 DP(NETIF_MSG_LINK
, "8727 Power fault"
4846 " has been detected on "
4849 printk(KERN_ERR PFX
"Error: Power"
4850 " fault on %s Port %d has"
4851 " been detected and the"
4852 " power to that SFP+ module"
4853 " has been removed to prevent"
4854 " failure of the card. Please"
4855 " remove the SFP+ module and"
4856 " restart the system to clear"
4858 , bp
->dev
->name
, params
->port
);
4860 * Disable all RX_ALARMs except for
4863 bnx2x_cl45_write(bp
, params
->port
,
4867 MDIO_PMA_REG_RX_ALARM_CTRL
,
4870 bnx2x_cl45_read(bp
, params
->port
,
4874 MDIO_PMA_REG_PHY_IDENTIFIER
,
4876 /* Wait for module_absent_event */
4878 bnx2x_cl45_write(bp
, params
->port
,
4882 MDIO_PMA_REG_PHY_IDENTIFIER
,
4884 /* Clear RX alarm */
4885 bnx2x_cl45_read(bp
, params
->port
,
4889 MDIO_PMA_REG_RX_ALARM
,
4893 } /* Over current check */
4895 /* When module absent bit is set, check module */
4896 if (rx_alarm_status
& (1<<5)) {
4897 bnx2x_8727_handle_mod_abs(params
);
4898 /* Enable all mod_abs and link detection bits */
4899 bnx2x_cl45_write(bp
, params
->port
,
4903 MDIO_PMA_REG_RX_ALARM_CTRL
,
4907 /* If transmitter is disabled,
4908 ignore false link up indication */
4909 bnx2x_cl45_read(bp
, params
->port
,
4913 MDIO_PMA_REG_PHY_IDENTIFIER
,
4915 if (val1
& (1<<15)) {
4916 DP(NETIF_MSG_LINK
, "Tx is disabled\n");
4917 ext_phy_link_up
= 0;
4921 bnx2x_cl45_read(bp
, params
->port
,
4925 MDIO_PMA_REG_8073_SPEED_LINK_STATUS
,
4928 /* Bits 0..2 --> speed detected,
4929 bits 13..15--> link is down */
4930 if ((link_status
& (1<<2)) &&
4931 (!(link_status
& (1<<15)))) {
4932 ext_phy_link_up
= 1;
4933 vars
->line_speed
= SPEED_10000
;
4934 } else if ((link_status
& (1<<0)) &&
4935 (!(link_status
& (1<<13)))) {
4936 ext_phy_link_up
= 1;
4937 vars
->line_speed
= SPEED_1000
;
4939 "port %x: External link"
4940 " up in 1G\n", params
->port
);
4942 ext_phy_link_up
= 0;
4944 "port %x: External link"
4945 " is down\n", params
->port
);
4950 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
:
4951 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
:
4953 u16 link_status
= 0;
4954 u16 an1000_status
= 0;
4957 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
) {
4958 bnx2x_cl45_read(bp
, params
->port
,
4962 MDIO_PCS_REG_LASI_STATUS
, &val1
);
4963 bnx2x_cl45_read(bp
, params
->port
,
4967 MDIO_PCS_REG_LASI_STATUS
, &val2
);
4969 "870x LASI status 0x%x->0x%x\n",
4972 /* In 8073, port1 is directed through emac0 and
4973 * port0 is directed through emac1
4975 bnx2x_cl45_read(bp
, params
->port
,
4979 MDIO_PMA_REG_LASI_STATUS
, &val1
);
4982 "8703 LASI status 0x%x\n",
4986 /* clear the interrupt LASI status register */
4987 bnx2x_cl45_read(bp
, params
->port
,
4991 MDIO_PCS_REG_STATUS
, &val2
);
4992 bnx2x_cl45_read(bp
, params
->port
,
4996 MDIO_PCS_REG_STATUS
, &val1
);
4997 DP(NETIF_MSG_LINK
, "807x PCS status 0x%x->0x%x\n",
5000 bnx2x_cl45_read(bp
, params
->port
,
5004 MDIO_PMA_REG_M8051_MSGOUT_REG
,
5007 /* Check the LASI */
5008 bnx2x_cl45_read(bp
, params
->port
,
5012 MDIO_PMA_REG_RX_ALARM
, &val2
);
5014 DP(NETIF_MSG_LINK
, "KR 0x9003 0x%x\n", val2
);
5016 /* Check the link status */
5017 bnx2x_cl45_read(bp
, params
->port
,
5021 MDIO_PCS_REG_STATUS
, &val2
);
5022 DP(NETIF_MSG_LINK
, "KR PCS status 0x%x\n", val2
);
5024 bnx2x_cl45_read(bp
, params
->port
,
5028 MDIO_PMA_REG_STATUS
, &val2
);
5029 bnx2x_cl45_read(bp
, params
->port
,
5033 MDIO_PMA_REG_STATUS
, &val1
);
5034 ext_phy_link_up
= ((val1
& 4) == 4);
5035 DP(NETIF_MSG_LINK
, "PMA_REG_STATUS=0x%x\n", val1
);
5037 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
) {
5039 if (ext_phy_link_up
&&
5040 ((params
->req_line_speed
!=
5042 if (bnx2x_bcm8073_xaui_wa(params
)
5044 ext_phy_link_up
= 0;
5048 bnx2x_cl45_read(bp
, params
->port
,
5052 MDIO_AN_REG_LINK_STATUS
,
5054 bnx2x_cl45_read(bp
, params
->port
,
5058 MDIO_AN_REG_LINK_STATUS
,
5061 /* Check the link status on 1.1.2 */
5062 bnx2x_cl45_read(bp
, params
->port
,
5066 MDIO_PMA_REG_STATUS
, &val2
);
5067 bnx2x_cl45_read(bp
, params
->port
,
5071 MDIO_PMA_REG_STATUS
, &val1
);
5072 DP(NETIF_MSG_LINK
, "KR PMA status 0x%x->0x%x,"
5073 "an_link_status=0x%x\n",
5074 val2
, val1
, an1000_status
);
5076 ext_phy_link_up
= (((val1
& 4) == 4) ||
5077 (an1000_status
& (1<<1)));
5078 if (ext_phy_link_up
&&
5079 bnx2x_8073_is_snr_needed(params
)) {
5080 /* The SNR will improve about 2dbby
5081 changing the BW and FEE main tap.*/
5083 /* The 1st write to change FFE main
5084 tap is set before restart AN */
5085 /* Change PLL Bandwidth in EDC
5087 bnx2x_cl45_write(bp
, port
, ext_phy_type
,
5090 MDIO_PMA_REG_PLL_BANDWIDTH
,
5093 /* Change CDR Bandwidth in EDC
5095 bnx2x_cl45_write(bp
, port
, ext_phy_type
,
5098 MDIO_PMA_REG_CDR_BANDWIDTH
,
5101 bnx2x_cl45_read(bp
, params
->port
,
5105 MDIO_PMA_REG_8073_SPEED_LINK_STATUS
,
5108 /* Bits 0..2 --> speed detected,
5109 bits 13..15--> link is down */
5110 if ((link_status
& (1<<2)) &&
5111 (!(link_status
& (1<<15)))) {
5112 ext_phy_link_up
= 1;
5113 vars
->line_speed
= SPEED_10000
;
5115 "port %x: External link"
5116 " up in 10G\n", params
->port
);
5117 } else if ((link_status
& (1<<1)) &&
5118 (!(link_status
& (1<<14)))) {
5119 ext_phy_link_up
= 1;
5120 vars
->line_speed
= SPEED_2500
;
5122 "port %x: External link"
5123 " up in 2.5G\n", params
->port
);
5124 } else if ((link_status
& (1<<0)) &&
5125 (!(link_status
& (1<<13)))) {
5126 ext_phy_link_up
= 1;
5127 vars
->line_speed
= SPEED_1000
;
5129 "port %x: External link"
5130 " up in 1G\n", params
->port
);
5132 ext_phy_link_up
= 0;
5134 "port %x: External link"
5135 " is down\n", params
->port
);
5138 /* See if 1G link is up for the 8072 */
5139 bnx2x_cl45_read(bp
, params
->port
,
5143 MDIO_AN_REG_LINK_STATUS
,
5145 bnx2x_cl45_read(bp
, params
->port
,
5149 MDIO_AN_REG_LINK_STATUS
,
5151 if (an1000_status
& (1<<1)) {
5152 ext_phy_link_up
= 1;
5153 vars
->line_speed
= SPEED_1000
;
5155 "port %x: External link"
5156 " up in 1G\n", params
->port
);
5157 } else if (ext_phy_link_up
) {
5158 ext_phy_link_up
= 1;
5159 vars
->line_speed
= SPEED_10000
;
5161 "port %x: External link"
5162 " up in 10G\n", params
->port
);
5169 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
:
5170 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
5173 MDIO_PMA_REG_LASI_STATUS
, &val2
);
5174 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
5177 MDIO_PMA_REG_LASI_STATUS
, &val1
);
5179 "10G-base-T LASI status 0x%x->0x%x\n",
5181 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
5184 MDIO_PMA_REG_STATUS
, &val2
);
5185 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
5188 MDIO_PMA_REG_STATUS
, &val1
);
5190 "10G-base-T PMA status 0x%x->0x%x\n",
5192 ext_phy_link_up
= ((val1
& 4) == 4);
5194 * print the AN outcome of the SFX7101 PHY
5196 if (ext_phy_link_up
) {
5197 bnx2x_cl45_read(bp
, params
->port
,
5201 MDIO_AN_REG_MASTER_STATUS
,
5203 vars
->line_speed
= SPEED_10000
;
5205 "SFX7101 AN status 0x%x->Master=%x\n",
5210 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
:
5211 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823
:
5212 /* Check 10G-BaseT link status */
5213 /* Check PMD signal ok */
5214 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
5219 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
5222 MDIO_PMA_REG_8481_PMD_SIGNAL
,
5224 DP(NETIF_MSG_LINK
, "PMD_SIGNAL 1.a811 = 0x%x\n", val2
);
5226 /* Check link 10G */
5227 if (val2
& (1<<11)) {
5228 vars
->line_speed
= SPEED_10000
;
5229 ext_phy_link_up
= 1;
5230 bnx2x_8481_set_10G_led_mode(params
,
5233 } else { /* Check Legacy speed link */
5234 u16 legacy_status
, legacy_speed
;
5236 /* Enable expansion register 0x42
5237 (Operation mode status) */
5238 bnx2x_cl45_write(bp
, params
->port
,
5242 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS
,
5245 /* Get legacy speed operation status */
5246 bnx2x_cl45_read(bp
, params
->port
,
5250 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW
,
5253 DP(NETIF_MSG_LINK
, "Legacy speed status"
5254 " = 0x%x\n", legacy_status
);
5255 ext_phy_link_up
= ((legacy_status
& (1<<11))
5257 if (ext_phy_link_up
) {
5258 legacy_speed
= (legacy_status
& (3<<9));
5259 if (legacy_speed
== (0<<9))
5260 vars
->line_speed
= SPEED_10
;
5261 else if (legacy_speed
== (1<<9))
5264 else if (legacy_speed
== (2<<9))
5267 else /* Should not happen */
5268 vars
->line_speed
= 0;
5270 if (legacy_status
& (1<<8))
5271 vars
->duplex
= DUPLEX_FULL
;
5273 vars
->duplex
= DUPLEX_HALF
;
5275 DP(NETIF_MSG_LINK
, "Link is up "
5276 "in %dMbps, is_duplex_full"
5279 (vars
->duplex
== DUPLEX_FULL
));
5280 bnx2x_8481_set_legacy_led_mode(params
,
5287 DP(NETIF_MSG_LINK
, "BAD XGXS ext_phy_config 0x%x\n",
5288 params
->ext_phy_config
);
5289 ext_phy_link_up
= 0;
5292 /* Set SGMII mode for external phy */
5293 if (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) {
5294 if (vars
->line_speed
< SPEED_1000
)
5295 vars
->phy_flags
|= PHY_SGMII_FLAG
;
5297 vars
->phy_flags
&= ~PHY_SGMII_FLAG
;
5300 } else { /* SerDes */
5301 ext_phy_type
= SERDES_EXT_PHY_TYPE(params
->ext_phy_config
);
5302 switch (ext_phy_type
) {
5303 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT
:
5304 DP(NETIF_MSG_LINK
, "SerDes Direct\n");
5305 ext_phy_link_up
= 1;
5308 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482
:
5309 DP(NETIF_MSG_LINK
, "SerDes 5482\n");
5310 ext_phy_link_up
= 1;
5315 "BAD SerDes ext_phy_config 0x%x\n",
5316 params
->ext_phy_config
);
5317 ext_phy_link_up
= 0;
5322 return ext_phy_link_up
;
5325 static void bnx2x_link_int_enable(struct link_params
*params
)
5327 u8 port
= params
->port
;
5330 struct bnx2x
*bp
= params
->bp
;
5332 /* setting the status to report on link up
5333 for either XGXS or SerDes */
5335 if (params
->switch_cfg
== SWITCH_CFG_10G
) {
5336 mask
= (NIG_MASK_XGXS0_LINK10G
|
5337 NIG_MASK_XGXS0_LINK_STATUS
);
5338 DP(NETIF_MSG_LINK
, "enabled XGXS interrupt\n");
5339 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
5340 if ((ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) &&
5341 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
) &&
5343 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
)) {
5344 mask
|= NIG_MASK_MI_INT
;
5345 DP(NETIF_MSG_LINK
, "enabled external phy int\n");
5348 } else { /* SerDes */
5349 mask
= NIG_MASK_SERDES0_LINK_STATUS
;
5350 DP(NETIF_MSG_LINK
, "enabled SerDes interrupt\n");
5351 ext_phy_type
= SERDES_EXT_PHY_TYPE(params
->ext_phy_config
);
5352 if ((ext_phy_type
!=
5353 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT
) &&
5355 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN
)) {
5356 mask
|= NIG_MASK_MI_INT
;
5357 DP(NETIF_MSG_LINK
, "enabled external phy int\n");
5361 NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4,
5364 DP(NETIF_MSG_LINK
, "port %x, is_xgxs %x, int_status 0x%x\n", port
,
5365 (params
->switch_cfg
== SWITCH_CFG_10G
),
5366 REG_RD(bp
, NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4));
5367 DP(NETIF_MSG_LINK
, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5368 REG_RD(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4),
5369 REG_RD(bp
, NIG_REG_EMAC0_STATUS_MISC_MI_INT
+ port
*0x18),
5370 REG_RD(bp
, NIG_REG_SERDES0_STATUS_LINK_STATUS
+port
*0x3c));
5371 DP(NETIF_MSG_LINK
, " 10G %x, XGXS_LINK %x\n",
5372 REG_RD(bp
, NIG_REG_XGXS0_STATUS_LINK10G
+ port
*0x68),
5373 REG_RD(bp
, NIG_REG_XGXS0_STATUS_LINK_STATUS
+ port
*0x68));
5376 static void bnx2x_8481_rearm_latch_signal(struct bnx2x
*bp
, u8 port
,
5379 u32 latch_status
= 0, is_mi_int_status
;
5380 /* Disable the MI INT ( external phy int )
5381 * by writing 1 to the status register. Link down indication
5382 * is high-active-signal, so in this case we need to write the
5383 * status to clear the XOR
5385 /* Read Latched signals */
5386 latch_status
= REG_RD(bp
,
5387 NIG_REG_LATCH_STATUS_0
+ port
*8);
5388 is_mi_int_status
= REG_RD(bp
,
5389 NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4);
5390 DP(NETIF_MSG_LINK
, "original_signal = 0x%x, nig_status = 0x%x,"
5391 "latch_status = 0x%x\n",
5392 is_mi_int
, is_mi_int_status
, latch_status
);
5393 /* Handle only those with latched-signal=up.*/
5394 if (latch_status
& 1) {
5395 /* For all latched-signal=up,Write original_signal to status */
5398 NIG_REG_STATUS_INTERRUPT_PORT0
5400 NIG_STATUS_EMAC0_MI_INT
);
5403 NIG_REG_STATUS_INTERRUPT_PORT0
5405 NIG_STATUS_EMAC0_MI_INT
);
5406 /* For all latched-signal=up : Re-Arm Latch signals */
5407 REG_WR(bp
, NIG_REG_LATCH_STATUS_0
+ port
*8,
5408 (latch_status
& 0xfffe) | (latch_status
& 1));
5414 static void bnx2x_link_int_ack(struct link_params
*params
,
5415 struct link_vars
*vars
, u8 is_10g
,
5418 struct bnx2x
*bp
= params
->bp
;
5419 u8 port
= params
->port
;
5421 /* first reset all status
5422 * we assume only one line will be change at a time */
5423 bnx2x_bits_dis(bp
, NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4,
5424 (NIG_STATUS_XGXS0_LINK10G
|
5425 NIG_STATUS_XGXS0_LINK_STATUS
|
5426 NIG_STATUS_SERDES0_LINK_STATUS
));
5427 if ((XGXS_EXT_PHY_TYPE(params
->ext_phy_config
)
5428 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
) ||
5429 (XGXS_EXT_PHY_TYPE(params
->ext_phy_config
)
5430 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823
)) {
5431 bnx2x_8481_rearm_latch_signal(bp
, port
, is_mi_int
);
5433 if (vars
->phy_link_up
) {
5435 /* Disable the 10G link interrupt
5436 * by writing 1 to the status register
5438 DP(NETIF_MSG_LINK
, "10G XGXS phy link up\n");
5440 NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4,
5441 NIG_STATUS_XGXS0_LINK10G
);
5443 } else if (params
->switch_cfg
== SWITCH_CFG_10G
) {
5444 /* Disable the link interrupt
5445 * by writing 1 to the relevant lane
5446 * in the status register
5448 u32 ser_lane
= ((params
->lane_config
&
5449 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
5450 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
5452 DP(NETIF_MSG_LINK
, "%d speed XGXS phy link up\n",
5455 NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4,
5457 NIG_STATUS_XGXS0_LINK_STATUS_SIZE
));
5459 } else { /* SerDes */
5460 DP(NETIF_MSG_LINK
, "SerDes phy link up\n");
5461 /* Disable the link interrupt
5462 * by writing 1 to the status register
5465 NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4,
5466 NIG_STATUS_SERDES0_LINK_STATUS
);
5469 } else { /* link_down */
5473 static u8
bnx2x_format_ver(u32 num
, u8
*str
, u16 len
)
5476 u32 mask
= 0xf0000000;
5480 /* Need more than 10chars for this format */
5487 digit
= ((num
& mask
) >> shift
);
5489 *str_ptr
= digit
+ '0';
5491 *str_ptr
= digit
- 0xa + 'a';
5503 u8
bnx2x_get_ext_phy_fw_version(struct link_params
*params
, u8 driver_loaded
,
5504 u8
*version
, u16 len
)
5507 u32 ext_phy_type
= 0;
5511 if (version
== NULL
|| params
== NULL
)
5515 spirom_ver
= REG_RD(bp
, params
->shmem_base
+
5516 offsetof(struct shmem_region
,
5517 port_mb
[params
->port
].ext_phy_fw_version
));
5520 /* reset the returned value to zero */
5521 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
5522 switch (ext_phy_type
) {
5523 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
:
5528 version
[0] = (spirom_ver
& 0xFF);
5529 version
[1] = (spirom_ver
& 0xFF00) >> 8;
5530 version
[2] = (spirom_ver
& 0xFF0000) >> 16;
5531 version
[3] = (spirom_ver
& 0xFF000000) >> 24;
5535 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
:
5536 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
:
5537 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
5538 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
:
5539 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
5540 status
= bnx2x_format_ver(spirom_ver
, version
, len
);
5542 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
:
5543 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823
:
5544 spirom_ver
= ((spirom_ver
& 0xF80) >> 7) << 16 |
5545 (spirom_ver
& 0x7F);
5546 status
= bnx2x_format_ver(spirom_ver
, version
, len
);
5548 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
5549 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
:
5553 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
:
5554 DP(NETIF_MSG_LINK
, "bnx2x_get_ext_phy_fw_version:"
5555 " type is FAILURE!\n");
5565 static void bnx2x_set_xgxs_loopback(struct link_params
*params
,
5566 struct link_vars
*vars
,
5569 u8 port
= params
->port
;
5570 struct bnx2x
*bp
= params
->bp
;
5575 DP(NETIF_MSG_LINK
, "XGXS 10G loopback enable\n");
5577 /* change the uni_phy_addr in the nig */
5578 md_devad
= REG_RD(bp
, (NIG_REG_XGXS0_CTRL_MD_DEVAD
+
5581 REG_WR(bp
, NIG_REG_XGXS0_CTRL_MD_DEVAD
+ port
*0x18, 0x5);
5583 bnx2x_cl45_write(bp
, port
, 0,
5586 (MDIO_REG_BANK_AER_BLOCK
+
5587 (MDIO_AER_BLOCK_AER_REG
& 0xf)),
5590 bnx2x_cl45_write(bp
, port
, 0,
5593 (MDIO_REG_BANK_CL73_IEEEB0
+
5594 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL
& 0xf)),
5597 /* set aer mmd back */
5598 bnx2x_set_aer_mmd(params
, vars
);
5601 REG_WR(bp
, NIG_REG_XGXS0_CTRL_MD_DEVAD
+ port
*0x18,
5607 DP(NETIF_MSG_LINK
, "XGXS 1G loopback enable\n");
5609 CL45_RD_OVER_CL22(bp
, port
,
5611 MDIO_REG_BANK_COMBO_IEEE0
,
5612 MDIO_COMBO_IEEE0_MII_CONTROL
,
5615 CL45_WR_OVER_CL22(bp
, port
,
5617 MDIO_REG_BANK_COMBO_IEEE0
,
5618 MDIO_COMBO_IEEE0_MII_CONTROL
,
5620 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK
));
5625 static void bnx2x_ext_phy_loopback(struct link_params
*params
)
5627 struct bnx2x
*bp
= params
->bp
;
5631 if (params
->switch_cfg
== SWITCH_CFG_10G
) {
5632 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
5633 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
5634 /* CL37 Autoneg Enabled */
5635 switch (ext_phy_type
) {
5636 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
5637 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
:
5639 "ext_phy_loopback: We should not get here\n");
5641 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
:
5642 DP(NETIF_MSG_LINK
, "ext_phy_loopback: 8705\n");
5644 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
:
5645 DP(NETIF_MSG_LINK
, "ext_phy_loopback: 8706\n");
5647 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
5648 DP(NETIF_MSG_LINK
, "PMA/PMD ext_phy_loopback: 8726\n");
5649 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
5655 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
:
5656 /* SFX7101_XGXS_TEST1 */
5657 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
5660 MDIO_XS_SFX7101_XGXS_TEST1
,
5663 "ext_phy_loopback: set ext phy loopback\n");
5665 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
:
5668 } /* switch external PHY type */
5671 ext_phy_type
= SERDES_EXT_PHY_TYPE(params
->ext_phy_config
);
5672 ext_phy_addr
= (params
->ext_phy_config
&
5673 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK
)
5674 >> PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT
;
5680 *------------------------------------------------------------------------
5681 * bnx2x_override_led_value -
5683 * Override the led value of the requsted led
5685 *------------------------------------------------------------------------
5687 u8
bnx2x_override_led_value(struct bnx2x
*bp
, u8 port
,
5688 u32 led_idx
, u32 value
)
5692 /* If port 0 then use EMAC0, else use EMAC1*/
5693 u32 emac_base
= (port
) ? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
5696 "bnx2x_override_led_value() port %x led_idx %d value %d\n",
5697 port
, led_idx
, value
);
5700 case 0: /* 10MB led */
5701 /* Read the current value of the LED register in
5703 reg_val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_LED
);
5704 /* Set the OVERRIDE bit to 1 */
5705 reg_val
|= EMAC_LED_OVERRIDE
;
5706 /* If value is 1, set the 10M_OVERRIDE bit,
5707 otherwise reset it.*/
5708 reg_val
= (value
== 1) ? (reg_val
| EMAC_LED_10MB_OVERRIDE
) :
5709 (reg_val
& ~EMAC_LED_10MB_OVERRIDE
);
5710 REG_WR(bp
, emac_base
+ EMAC_REG_EMAC_LED
, reg_val
);
5712 case 1: /*100MB led */
5713 /*Read the current value of the LED register in
5715 reg_val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_LED
);
5716 /* Set the OVERRIDE bit to 1 */
5717 reg_val
|= EMAC_LED_OVERRIDE
;
5718 /* If value is 1, set the 100M_OVERRIDE bit,
5719 otherwise reset it.*/
5720 reg_val
= (value
== 1) ? (reg_val
| EMAC_LED_100MB_OVERRIDE
) :
5721 (reg_val
& ~EMAC_LED_100MB_OVERRIDE
);
5722 REG_WR(bp
, emac_base
+ EMAC_REG_EMAC_LED
, reg_val
);
5724 case 2: /* 1000MB led */
5725 /* Read the current value of the LED register in the
5727 reg_val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_LED
);
5728 /* Set the OVERRIDE bit to 1 */
5729 reg_val
|= EMAC_LED_OVERRIDE
;
5730 /* If value is 1, set the 1000M_OVERRIDE bit, otherwise
5732 reg_val
= (value
== 1) ? (reg_val
| EMAC_LED_1000MB_OVERRIDE
) :
5733 (reg_val
& ~EMAC_LED_1000MB_OVERRIDE
);
5734 REG_WR(bp
, emac_base
+ EMAC_REG_EMAC_LED
, reg_val
);
5736 case 3: /* 2500MB led */
5737 /* Read the current value of the LED register in the
5739 reg_val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_LED
);
5740 /* Set the OVERRIDE bit to 1 */
5741 reg_val
|= EMAC_LED_OVERRIDE
;
5742 /* If value is 1, set the 2500M_OVERRIDE bit, otherwise
5744 reg_val
= (value
== 1) ? (reg_val
| EMAC_LED_2500MB_OVERRIDE
) :
5745 (reg_val
& ~EMAC_LED_2500MB_OVERRIDE
);
5746 REG_WR(bp
, emac_base
+ EMAC_REG_EMAC_LED
, reg_val
);
5748 case 4: /*10G led */
5750 REG_WR(bp
, NIG_REG_LED_10G_P0
,
5753 REG_WR(bp
, NIG_REG_LED_10G_P1
,
5757 case 5: /* TRAFFIC led */
5758 /* Find if the traffic control is via BMAC or EMAC */
5760 reg_val
= REG_RD(bp
, NIG_REG_NIG_EMAC0_EN
);
5762 reg_val
= REG_RD(bp
, NIG_REG_NIG_EMAC1_EN
);
5764 /* Override the traffic led in the EMAC:*/
5766 /* Read the current value of the LED register in
5768 reg_val
= REG_RD(bp
, emac_base
+
5770 /* Set the TRAFFIC_OVERRIDE bit to 1 */
5771 reg_val
|= EMAC_LED_OVERRIDE
;
5772 /* If value is 1, set the TRAFFIC bit, otherwise
5774 reg_val
= (value
== 1) ? (reg_val
| EMAC_LED_TRAFFIC
) :
5775 (reg_val
& ~EMAC_LED_TRAFFIC
);
5776 REG_WR(bp
, emac_base
+ EMAC_REG_EMAC_LED
, reg_val
);
5777 } else { /* Override the traffic led in the BMAC: */
5778 REG_WR(bp
, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5780 REG_WR(bp
, NIG_REG_LED_CONTROL_TRAFFIC_P0
+ port
*4,
5786 "bnx2x_override_led_value() unknown led index %d "
5787 "(should be 0-5)\n", led_idx
);
5795 u8
bnx2x_set_led(struct link_params
*params
, u8 mode
, u32 speed
)
5797 u8 port
= params
->port
;
5798 u16 hw_led_mode
= params
->hw_led_mode
;
5801 u32 emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
5802 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
5803 struct bnx2x
*bp
= params
->bp
;
5804 DP(NETIF_MSG_LINK
, "bnx2x_set_led: port %x, mode %d\n", port
, mode
);
5805 DP(NETIF_MSG_LINK
, "speed 0x%x, hw_led_mode 0x%x\n",
5806 speed
, hw_led_mode
);
5809 REG_WR(bp
, NIG_REG_LED_10G_P0
+ port
*4, 0);
5810 REG_WR(bp
, NIG_REG_LED_MODE_P0
+ port
*4,
5811 SHARED_HW_CFG_LED_MAC1
);
5813 tmp
= EMAC_RD(bp
, EMAC_REG_EMAC_LED
);
5814 EMAC_WR(bp
, EMAC_REG_EMAC_LED
, (tmp
| EMAC_LED_OVERRIDE
));
5818 if (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) {
5819 REG_WR(bp
, NIG_REG_LED_MODE_P0
+ port
*4, 0);
5820 REG_WR(bp
, NIG_REG_LED_10G_P0
+ port
*4, 1);
5822 REG_WR(bp
, NIG_REG_LED_MODE_P0
+ port
*4,
5826 REG_WR(bp
, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
+
5828 /* Set blinking rate to ~15.9Hz */
5829 REG_WR(bp
, NIG_REG_LED_CONTROL_BLINK_RATE_P0
+ port
*4,
5830 LED_BLINK_RATE_VAL
);
5831 REG_WR(bp
, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0
+
5833 tmp
= EMAC_RD(bp
, EMAC_REG_EMAC_LED
);
5834 EMAC_WR(bp
, EMAC_REG_EMAC_LED
,
5835 (tmp
& (~EMAC_LED_OVERRIDE
)));
5837 if (CHIP_IS_E1(bp
) &&
5838 ((speed
== SPEED_2500
) ||
5839 (speed
== SPEED_1000
) ||
5840 (speed
== SPEED_100
) ||
5841 (speed
== SPEED_10
))) {
5842 /* On Everest 1 Ax chip versions for speeds less than
5843 10G LED scheme is different */
5844 REG_WR(bp
, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5846 REG_WR(bp
, NIG_REG_LED_CONTROL_TRAFFIC_P0
+
5848 REG_WR(bp
, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0
+
5855 DP(NETIF_MSG_LINK
, "bnx2x_set_led: Invalid led mode %d\n",
5863 u8
bnx2x_test_link(struct link_params
*params
, struct link_vars
*vars
)
5865 struct bnx2x
*bp
= params
->bp
;
5868 CL45_RD_OVER_CL22(bp
, params
->port
,
5870 MDIO_REG_BANK_GP_STATUS
,
5871 MDIO_GP_STATUS_TOP_AN_STATUS1
,
5873 /* link is up only if both local phy and external phy are up */
5874 if ((gp_status
& MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS
) &&
5875 bnx2x_ext_phy_is_link_up(params
, vars
, 1))
5881 static u8
bnx2x_link_initialize(struct link_params
*params
,
5882 struct link_vars
*vars
)
5884 struct bnx2x
*bp
= params
->bp
;
5885 u8 port
= params
->port
;
5888 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
5890 /* Activate the external PHY */
5891 bnx2x_ext_phy_reset(params
, vars
);
5893 bnx2x_set_aer_mmd(params
, vars
);
5895 if (vars
->phy_flags
& PHY_XGXS_FLAG
)
5896 bnx2x_set_master_ln(params
);
5898 rc
= bnx2x_reset_unicore(params
);
5899 /* reset the SerDes and wait for reset bit return low */
5903 bnx2x_set_aer_mmd(params
, vars
);
5905 /* setting the masterLn_def again after the reset */
5906 if (vars
->phy_flags
& PHY_XGXS_FLAG
) {
5907 bnx2x_set_master_ln(params
);
5908 bnx2x_set_swap_lanes(params
);
5911 if (vars
->phy_flags
& PHY_XGXS_FLAG
) {
5912 if ((params
->req_line_speed
&&
5913 ((params
->req_line_speed
== SPEED_100
) ||
5914 (params
->req_line_speed
== SPEED_10
))) ||
5915 (!params
->req_line_speed
&&
5916 (params
->speed_cap_mask
>=
5917 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
) &&
5918 (params
->speed_cap_mask
<
5919 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)
5921 vars
->phy_flags
|= PHY_SGMII_FLAG
;
5923 vars
->phy_flags
&= ~PHY_SGMII_FLAG
;
5926 /* In case of external phy existance, the line speed would be the
5927 line speed linked up by the external phy. In case it is direct only,
5928 then the line_speed during initialization will be equal to the
5930 vars
->line_speed
= params
->req_line_speed
;
5932 bnx2x_calc_ieee_aneg_adv(params
, &vars
->ieee_fc
);
5934 /* init ext phy and enable link state int */
5935 non_ext_phy
= ((ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) ||
5936 (params
->loopback_mode
== LOOPBACK_XGXS_10
));
5939 (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
) ||
5940 (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
) ||
5941 (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
) ||
5942 (params
->loopback_mode
== LOOPBACK_EXT_PHY
)) {
5943 if (params
->req_line_speed
== SPEED_AUTO_NEG
)
5944 bnx2x_set_parallel_detection(params
, vars
->phy_flags
);
5945 bnx2x_init_internal_phy(params
, vars
, non_ext_phy
);
5949 rc
|= bnx2x_ext_phy_init(params
, vars
);
5951 bnx2x_bits_dis(bp
, NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4,
5952 (NIG_STATUS_XGXS0_LINK10G
|
5953 NIG_STATUS_XGXS0_LINK_STATUS
|
5954 NIG_STATUS_SERDES0_LINK_STATUS
));
5961 u8
bnx2x_phy_init(struct link_params
*params
, struct link_vars
*vars
)
5963 struct bnx2x
*bp
= params
->bp
;
5966 DP(NETIF_MSG_LINK
, "Phy Initialization started\n");
5967 DP(NETIF_MSG_LINK
, "req_speed %d, req_flowctrl %d\n",
5968 params
->req_line_speed
, params
->req_flow_ctrl
);
5969 vars
->link_status
= 0;
5970 vars
->phy_link_up
= 0;
5972 vars
->line_speed
= 0;
5973 vars
->duplex
= DUPLEX_FULL
;
5974 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
5975 vars
->mac_type
= MAC_TYPE_NONE
;
5977 if (params
->switch_cfg
== SWITCH_CFG_1G
)
5978 vars
->phy_flags
= PHY_SERDES_FLAG
;
5980 vars
->phy_flags
= PHY_XGXS_FLAG
;
5982 /* disable attentions */
5983 bnx2x_bits_dis(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ params
->port
*4,
5984 (NIG_MASK_XGXS0_LINK_STATUS
|
5985 NIG_MASK_XGXS0_LINK10G
|
5986 NIG_MASK_SERDES0_LINK_STATUS
|
5989 bnx2x_emac_init(params
, vars
);
5991 if (CHIP_REV_IS_FPGA(bp
)) {
5994 vars
->line_speed
= SPEED_10000
;
5995 vars
->duplex
= DUPLEX_FULL
;
5996 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
5997 vars
->link_status
= (LINK_STATUS_LINK_UP
| LINK_10GTFD
);
5998 /* enable on E1.5 FPGA */
5999 if (CHIP_IS_E1H(bp
)) {
6001 (BNX2X_FLOW_CTRL_TX
|
6002 BNX2X_FLOW_CTRL_RX
);
6003 vars
->link_status
|=
6004 (LINK_STATUS_TX_FLOW_CONTROL_ENABLED
|
6005 LINK_STATUS_RX_FLOW_CONTROL_ENABLED
);
6008 bnx2x_emac_enable(params
, vars
, 0);
6009 bnx2x_pbf_update(params
, vars
->flow_ctrl
, vars
->line_speed
);
6011 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
*4, 0);
6013 /* update shared memory */
6014 bnx2x_update_mng(params
, vars
->link_status
);
6019 if (CHIP_REV_IS_EMUL(bp
)) {
6022 vars
->line_speed
= SPEED_10000
;
6023 vars
->duplex
= DUPLEX_FULL
;
6024 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
6025 vars
->link_status
= (LINK_STATUS_LINK_UP
| LINK_10GTFD
);
6027 bnx2x_bmac_enable(params
, vars
, 0);
6029 bnx2x_pbf_update(params
, vars
->flow_ctrl
, vars
->line_speed
);
6031 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
6032 + params
->port
*4, 0);
6034 /* update shared memory */
6035 bnx2x_update_mng(params
, vars
->link_status
);
6040 if (params
->loopback_mode
== LOOPBACK_BMAC
) {
6043 vars
->line_speed
= SPEED_10000
;
6044 vars
->duplex
= DUPLEX_FULL
;
6045 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
6046 vars
->mac_type
= MAC_TYPE_BMAC
;
6048 vars
->phy_flags
= PHY_XGXS_FLAG
;
6050 bnx2x_phy_deassert(params
, vars
->phy_flags
);
6051 /* set bmac loopback */
6052 bnx2x_bmac_enable(params
, vars
, 1);
6054 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+
6057 } else if (params
->loopback_mode
== LOOPBACK_EMAC
) {
6060 vars
->line_speed
= SPEED_1000
;
6061 vars
->duplex
= DUPLEX_FULL
;
6062 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
6063 vars
->mac_type
= MAC_TYPE_EMAC
;
6065 vars
->phy_flags
= PHY_XGXS_FLAG
;
6067 bnx2x_phy_deassert(params
, vars
->phy_flags
);
6068 /* set bmac loopback */
6069 bnx2x_emac_enable(params
, vars
, 1);
6070 bnx2x_emac_program(params
, vars
->line_speed
,
6072 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+
6075 } else if ((params
->loopback_mode
== LOOPBACK_XGXS_10
) ||
6076 (params
->loopback_mode
== LOOPBACK_EXT_PHY
)) {
6079 vars
->line_speed
= SPEED_10000
;
6080 vars
->duplex
= DUPLEX_FULL
;
6081 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
6083 vars
->phy_flags
= PHY_XGXS_FLAG
;
6086 NIG_REG_XGXS0_CTRL_PHY_ADDR
+
6088 params
->phy_addr
= (u8
)val
;
6090 bnx2x_phy_deassert(params
, vars
->phy_flags
);
6091 bnx2x_link_initialize(params
, vars
);
6093 vars
->mac_type
= MAC_TYPE_BMAC
;
6095 bnx2x_bmac_enable(params
, vars
, 0);
6097 if (params
->loopback_mode
== LOOPBACK_XGXS_10
) {
6098 /* set 10G XGXS loopback */
6099 bnx2x_set_xgxs_loopback(params
, vars
, 1);
6101 /* set external phy loopback */
6102 bnx2x_ext_phy_loopback(params
);
6104 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+
6107 bnx2x_set_led(params
, LED_MODE_OPER
, vars
->line_speed
);
6111 bnx2x_phy_deassert(params
, vars
->phy_flags
);
6112 switch (params
->switch_cfg
) {
6114 vars
->phy_flags
|= PHY_SERDES_FLAG
;
6115 if ((params
->ext_phy_config
&
6116 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK
) ==
6117 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482
) {
6118 vars
->phy_flags
|= PHY_SGMII_FLAG
;
6122 NIG_REG_SERDES0_CTRL_PHY_ADDR
+
6125 params
->phy_addr
= (u8
)val
;
6128 case SWITCH_CFG_10G
:
6129 vars
->phy_flags
|= PHY_XGXS_FLAG
;
6131 NIG_REG_XGXS0_CTRL_PHY_ADDR
+
6133 params
->phy_addr
= (u8
)val
;
6137 DP(NETIF_MSG_LINK
, "Invalid switch_cfg\n");
6140 DP(NETIF_MSG_LINK
, "Phy address = 0x%x\n", params
->phy_addr
);
6142 bnx2x_link_initialize(params
, vars
);
6144 bnx2x_link_int_enable(params
);
6149 static void bnx2x_8726_reset_phy(struct bnx2x
*bp
, u8 port
, u8 ext_phy_addr
)
6151 DP(NETIF_MSG_LINK
, "bnx2x_8726_reset_phy port %d\n", port
);
6153 /* Set serial boot control for external load */
6154 bnx2x_cl45_write(bp
, port
,
6155 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
, ext_phy_addr
,
6157 MDIO_PMA_REG_GEN_CTRL
, 0x0001);
6160 u8
bnx2x_link_reset(struct link_params
*params
, struct link_vars
*vars
,
6163 struct bnx2x
*bp
= params
->bp
;
6164 u32 ext_phy_config
= params
->ext_phy_config
;
6165 u8 port
= params
->port
;
6166 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(ext_phy_config
);
6167 u32 val
= REG_RD(bp
, params
->shmem_base
+
6168 offsetof(struct shmem_region
, dev_info
.
6169 port_feature_config
[params
->port
].
6171 DP(NETIF_MSG_LINK
, "Resetting the link of port %d\n", port
);
6172 /* disable attentions */
6173 vars
->link_status
= 0;
6174 bnx2x_update_mng(params
, vars
->link_status
);
6175 bnx2x_bits_dis(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4,
6176 (NIG_MASK_XGXS0_LINK_STATUS
|
6177 NIG_MASK_XGXS0_LINK10G
|
6178 NIG_MASK_SERDES0_LINK_STATUS
|
6181 /* activate nig drain */
6182 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+ port
*4, 1);
6184 /* disable nig egress interface */
6185 REG_WR(bp
, NIG_REG_BMAC0_OUT_EN
+ port
*4, 0);
6186 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_OUT_EN
+ port
*4, 0);
6188 /* Stop BigMac rx */
6189 bnx2x_bmac_rx_disable(bp
, port
);
6192 REG_WR(bp
, NIG_REG_NIG_EMAC0_EN
+ port
*4, 0);
6195 /* The PHY reset is controled by GPIO 1
6196 * Hold it as vars low
6198 /* clear link led */
6199 bnx2x_set_led(params
, LED_MODE_OFF
, 0);
6200 if (reset_ext_phy
) {
6201 switch (ext_phy_type
) {
6202 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
6203 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
:
6206 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
6209 /* Disable Transmitter */
6211 XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
6212 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
6213 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER
)
6214 bnx2x_sfp_set_transmitter(bp
, port
,
6215 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
6219 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
:
6220 DP(NETIF_MSG_LINK
, "Setting 8073 port %d into "
6223 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
6224 MISC_REGISTERS_GPIO_OUTPUT_LOW
,
6227 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
6230 XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
6231 /* Set soft reset */
6232 bnx2x_8726_reset_phy(bp
, params
->port
, ext_phy_addr
);
6235 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823
:
6238 XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
6239 bnx2x_cl45_write(bp
, port
,
6240 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
6243 MDIO_AN_REG_CTRL
, 0x0000);
6244 bnx2x_cl45_write(bp
, port
,
6245 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
6248 MDIO_PMA_REG_CTRL
, 1);
6253 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_1
,
6254 MISC_REGISTERS_GPIO_OUTPUT_LOW
,
6256 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
6257 MISC_REGISTERS_GPIO_OUTPUT_LOW
,
6259 DP(NETIF_MSG_LINK
, "reset external PHY\n");
6262 /* reset the SerDes/XGXS */
6263 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_CLEAR
,
6264 (0x1ff << (port
*16)));
6267 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
6268 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
6270 /* disable nig ingress interface */
6271 REG_WR(bp
, NIG_REG_BMAC0_IN_EN
+ port
*4, 0);
6272 REG_WR(bp
, NIG_REG_EMAC0_IN_EN
+ port
*4, 0);
6273 REG_WR(bp
, NIG_REG_BMAC0_OUT_EN
+ port
*4, 0);
6274 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_OUT_EN
+ port
*4, 0);
6279 static u8
bnx2x_update_link_down(struct link_params
*params
,
6280 struct link_vars
*vars
)
6282 struct bnx2x
*bp
= params
->bp
;
6283 u8 port
= params
->port
;
6285 DP(NETIF_MSG_LINK
, "Port %x: Link is down\n", port
);
6286 bnx2x_set_led(params
, LED_MODE_OFF
, 0);
6288 /* indicate no mac active */
6289 vars
->mac_type
= MAC_TYPE_NONE
;
6291 /* update shared memory */
6292 vars
->link_status
= 0;
6293 vars
->line_speed
= 0;
6294 bnx2x_update_mng(params
, vars
->link_status
);
6296 /* activate nig drain */
6297 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+ port
*4, 1);
6300 REG_WR(bp
, NIG_REG_NIG_EMAC0_EN
+ port
*4, 0);
6305 bnx2x_bmac_rx_disable(bp
, params
->port
);
6306 REG_WR(bp
, GRCBASE_MISC
+
6307 MISC_REGISTERS_RESET_REG_2_CLEAR
,
6308 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
6312 static u8
bnx2x_update_link_up(struct link_params
*params
,
6313 struct link_vars
*vars
,
6314 u8 link_10g
, u32 gp_status
)
6316 struct bnx2x
*bp
= params
->bp
;
6317 u8 port
= params
->port
;
6320 vars
->link_status
|= LINK_STATUS_LINK_UP
;
6322 bnx2x_bmac_enable(params
, vars
, 0);
6323 bnx2x_set_led(params
, LED_MODE_OPER
, SPEED_10000
);
6325 rc
= bnx2x_emac_program(params
, vars
->line_speed
,
6328 bnx2x_emac_enable(params
, vars
, 0);
6331 if (gp_status
& MDIO_AN_CL73_OR_37_COMPLETE
) {
6332 if (!(vars
->phy_flags
&
6334 bnx2x_set_gmii_tx_driver(params
);
6339 rc
|= bnx2x_pbf_update(params
, vars
->flow_ctrl
,
6343 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+ port
*4, 0);
6345 /* update shared memory */
6346 bnx2x_update_mng(params
, vars
->link_status
);
6350 /* This function should called upon link interrupt */
6351 /* In case vars->link_up, driver needs to
6354 3. Update the shared memory
6358 1. Update shared memory
6363 u8
bnx2x_link_update(struct link_params
*params
, struct link_vars
*vars
)
6365 struct bnx2x
*bp
= params
->bp
;
6366 u8 port
= params
->port
;
6369 u8 ext_phy_link_up
, rc
= 0;
6373 DP(NETIF_MSG_LINK
, "port %x, XGXS?%x, int_status 0x%x\n",
6374 port
, (vars
->phy_flags
& PHY_XGXS_FLAG
),
6375 REG_RD(bp
, NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4));
6377 is_mi_int
= (u8
)(REG_RD(bp
, NIG_REG_EMAC0_STATUS_MISC_MI_INT
+
6379 DP(NETIF_MSG_LINK
, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6380 REG_RD(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4),
6383 NIG_REG_SERDES0_STATUS_LINK_STATUS
+ port
*0x3c));
6385 DP(NETIF_MSG_LINK
, " 10G %x, XGXS_LINK %x\n",
6386 REG_RD(bp
, NIG_REG_XGXS0_STATUS_LINK10G
+ port
*0x68),
6387 REG_RD(bp
, NIG_REG_XGXS0_STATUS_LINK_STATUS
+ port
*0x68));
6390 REG_WR(bp
, NIG_REG_NIG_EMAC0_EN
+ port
*4, 0);
6392 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
6394 /* Check external link change only for non-direct */
6395 ext_phy_link_up
= bnx2x_ext_phy_is_link_up(params
, vars
, is_mi_int
);
6397 /* Read gp_status */
6398 CL45_RD_OVER_CL22(bp
, port
, params
->phy_addr
,
6399 MDIO_REG_BANK_GP_STATUS
,
6400 MDIO_GP_STATUS_TOP_AN_STATUS1
,
6403 rc
= bnx2x_link_settings_status(params
, vars
, gp_status
,
6408 /* anything 10 and over uses the bmac */
6409 link_10g
= ((vars
->line_speed
== SPEED_10000
) ||
6410 (vars
->line_speed
== SPEED_12000
) ||
6411 (vars
->line_speed
== SPEED_12500
) ||
6412 (vars
->line_speed
== SPEED_13000
) ||
6413 (vars
->line_speed
== SPEED_15000
) ||
6414 (vars
->line_speed
== SPEED_16000
));
6416 bnx2x_link_int_ack(params
, vars
, link_10g
, is_mi_int
);
6418 /* In case external phy link is up, and internal link is down
6419 ( not initialized yet probably after link initialization, it needs
6421 Note that after link down-up as result of cable plug,
6422 the xgxs link would probably become up again without the need to
6425 if ((ext_phy_type
!= PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT
) &&
6426 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
) &&
6427 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
) &&
6428 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
) &&
6429 (ext_phy_link_up
&& !vars
->phy_link_up
))
6430 bnx2x_init_internal_phy(params
, vars
, 0);
6432 /* link is up only if both local phy and external phy are up */
6433 vars
->link_up
= (ext_phy_link_up
&& vars
->phy_link_up
);
6436 rc
= bnx2x_update_link_up(params
, vars
, link_10g
, gp_status
);
6438 rc
= bnx2x_update_link_down(params
, vars
);
6443 static u8
bnx2x_8073_common_init_phy(struct bnx2x
*bp
, u32 shmem_base
)
6445 u8 ext_phy_addr
[PORT_MAX
];
6449 /* PART1 - Reset both phys */
6450 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
6451 /* Extract the ext phy address for the port */
6452 u32 ext_phy_config
= REG_RD(bp
, shmem_base
+
6453 offsetof(struct shmem_region
,
6454 dev_info
.port_hw_config
[port
].external_phy_config
));
6456 /* disable attentions */
6457 bnx2x_bits_dis(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4,
6458 (NIG_MASK_XGXS0_LINK_STATUS
|
6459 NIG_MASK_XGXS0_LINK10G
|
6460 NIG_MASK_SERDES0_LINK_STATUS
|
6463 ext_phy_addr
[port
] = XGXS_EXT_PHY_ADDR(ext_phy_config
);
6465 /* Need to take the phy out of low power mode in order
6466 to write to access its registers */
6467 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
6468 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, port
);
6471 bnx2x_cl45_write(bp
, port
,
6472 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
6479 /* Add delay of 150ms after reset */
6482 /* PART2 - Download firmware to both phys */
6483 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
6486 bnx2x_bcm8073_external_rom_boot(bp
, port
,
6487 ext_phy_addr
[port
], shmem_base
);
6489 bnx2x_cl45_read(bp
, port
, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
6492 MDIO_PMA_REG_ROM_VER1
, &fw_ver1
);
6493 if (fw_ver1
== 0 || fw_ver1
== 0x4321) {
6495 "bnx2x_8073_common_init_phy port %x:"
6496 "Download failed. fw version = 0x%x\n",
6501 /* Only set bit 10 = 1 (Tx power down) */
6502 bnx2x_cl45_read(bp
, port
,
6503 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
6506 MDIO_PMA_REG_TX_POWER_DOWN
, &val
);
6508 /* Phase1 of TX_POWER_DOWN reset */
6509 bnx2x_cl45_write(bp
, port
,
6510 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
6513 MDIO_PMA_REG_TX_POWER_DOWN
,
6517 /* Toggle Transmitter: Power down and then up with 600ms
6521 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
6522 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
6523 /* Phase2 of POWER_DOWN_RESET */
6524 /* Release bit 10 (Release Tx power down) */
6525 bnx2x_cl45_read(bp
, port
,
6526 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
6529 MDIO_PMA_REG_TX_POWER_DOWN
, &val
);
6531 bnx2x_cl45_write(bp
, port
,
6532 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
6535 MDIO_PMA_REG_TX_POWER_DOWN
, (val
& (~(1<<10))));
6538 /* Read modify write the SPI-ROM version select register */
6539 bnx2x_cl45_read(bp
, port
,
6540 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
6543 MDIO_PMA_REG_EDC_FFE_MAIN
, &val
);
6544 bnx2x_cl45_write(bp
, port
,
6545 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
6548 MDIO_PMA_REG_EDC_FFE_MAIN
, (val
| (1<<12)));
6550 /* set GPIO2 back to LOW */
6551 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
6552 MISC_REGISTERS_GPIO_OUTPUT_LOW
, port
);
6558 static u8
bnx2x_8727_common_init_phy(struct bnx2x
*bp
, u32 shmem_base
)
6560 u8 ext_phy_addr
[PORT_MAX
];
6561 s8 port
, first_port
, i
;
6562 u32 swap_val
, swap_override
;
6563 DP(NETIF_MSG_LINK
, "Executing BCM8727 common init\n");
6564 swap_val
= REG_RD(bp
, NIG_REG_PORT_SWAP
);
6565 swap_override
= REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
);
6567 bnx2x_ext_phy_hw_reset(bp
, 1 ^ (swap_val
&& swap_override
));
6570 if (swap_val
&& swap_override
)
6571 first_port
= PORT_0
;
6573 first_port
= PORT_1
;
6575 /* PART1 - Reset both phys */
6576 for (i
= 0, port
= first_port
; i
< PORT_MAX
; i
++, port
= !port
) {
6577 /* Extract the ext phy address for the port */
6578 u32 ext_phy_config
= REG_RD(bp
, shmem_base
+
6579 offsetof(struct shmem_region
,
6580 dev_info
.port_hw_config
[port
].external_phy_config
));
6582 /* disable attentions */
6583 bnx2x_bits_dis(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4,
6584 (NIG_MASK_XGXS0_LINK_STATUS
|
6585 NIG_MASK_XGXS0_LINK10G
|
6586 NIG_MASK_SERDES0_LINK_STATUS
|
6589 ext_phy_addr
[port
] = XGXS_EXT_PHY_ADDR(ext_phy_config
);
6592 bnx2x_cl45_write(bp
, port
,
6593 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
6600 /* Add delay of 150ms after reset */
6603 /* PART2 - Download firmware to both phys */
6604 for (i
= 0, port
= first_port
; i
< PORT_MAX
; i
++, port
= !port
) {
6607 bnx2x_bcm8727_external_rom_boot(bp
, port
,
6608 ext_phy_addr
[port
], shmem_base
);
6610 bnx2x_cl45_read(bp
, port
, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
6613 MDIO_PMA_REG_ROM_VER1
, &fw_ver1
);
6614 if (fw_ver1
== 0 || fw_ver1
== 0x4321) {
6616 "bnx2x_8727_common_init_phy port %x:"
6617 "Download failed. fw version = 0x%x\n",
6627 static u8
bnx2x_8726_common_init_phy(struct bnx2x
*bp
, u32 shmem_base
)
6633 /* Use port1 because of the static port-swap */
6634 /* Enable the module detection interrupt */
6635 val
= REG_RD(bp
, MISC_REG_GPIO_EVENT_EN
);
6636 val
|= ((1<<MISC_REGISTERS_GPIO_3
)|
6637 (1<<(MISC_REGISTERS_GPIO_3
+ MISC_REGISTERS_GPIO_PORT_SHIFT
)));
6638 REG_WR(bp
, MISC_REG_GPIO_EVENT_EN
, val
);
6640 bnx2x_ext_phy_hw_reset(bp
, 1);
6642 for (port
= 0; port
< PORT_MAX
; port
++) {
6643 /* Extract the ext phy address for the port */
6644 u32 ext_phy_config
= REG_RD(bp
, shmem_base
+
6645 offsetof(struct shmem_region
,
6646 dev_info
.port_hw_config
[port
].external_phy_config
));
6648 ext_phy_addr
= XGXS_EXT_PHY_ADDR(ext_phy_config
);
6649 DP(NETIF_MSG_LINK
, "8726_common_init : ext_phy_addr = 0x%x\n",
6652 bnx2x_8726_reset_phy(bp
, port
, ext_phy_addr
);
6654 /* Set fault module detected LED on */
6655 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_0
,
6656 MISC_REGISTERS_GPIO_HIGH
,
6664 static u8
bnx2x_84823_common_init_phy(struct bnx2x
*bp
, u32 shmem_base
)
6667 bnx2x_ext_phy_hw_reset(bp
, 1);
6670 u8
bnx2x_common_init_phy(struct bnx2x
*bp
, u32 shmem_base
)
6675 DP(NETIF_MSG_LINK
, "Begin common phy init\n");
6677 /* Read the ext_phy_type for arbitrary port(0) */
6678 ext_phy_type
= XGXS_EXT_PHY_TYPE(
6679 REG_RD(bp
, shmem_base
+
6680 offsetof(struct shmem_region
,
6681 dev_info
.port_hw_config
[0].external_phy_config
)));
6683 switch (ext_phy_type
) {
6684 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
:
6686 rc
= bnx2x_8073_common_init_phy(bp
, shmem_base
);
6690 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
6691 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC
:
6692 rc
= bnx2x_8727_common_init_phy(bp
, shmem_base
);
6695 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
6696 /* GPIO1 affects both ports, so there's need to pull
6697 it for single port alone */
6698 rc
= bnx2x_8726_common_init_phy(bp
, shmem_base
);
6700 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823
:
6701 rc
= bnx2x_84823_common_init_phy(bp
, shmem_base
);
6705 "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
6713 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x
*bp
, u8 port
, u8 phy_addr
)
6717 bnx2x_cl45_read(bp
, port
,
6718 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
,
6721 MDIO_PMA_REG_7101_RESET
, &val
);
6723 for (cnt
= 0; cnt
< 10; cnt
++) {
6725 /* Writes a self-clearing reset */
6726 bnx2x_cl45_write(bp
, port
,
6727 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
,
6730 MDIO_PMA_REG_7101_RESET
,
6732 /* Wait for clear */
6733 bnx2x_cl45_read(bp
, port
,
6734 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
,
6737 MDIO_PMA_REG_7101_RESET
, &val
);
6739 if ((val
& (1<<15)) == 0)