arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h

   1 /*
   2  * file:        include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
   3  * based on:
   4  * author:
   5  *
   6  * created:
   7  * description:
   8  *      blackfin serial driver head file
   9  * rev:
  10  *
  11  * modified:
  12  *
  13  *
  14  * bugs:         enter bugs at http://blackfin.uclinux.org/
  15  *
  16  * this program is free software; you can redistribute it and/or modify
  17  * it under the terms of the gnu general public license as published by
  18  * the free software foundation; either version 2, or (at your option)
  19  * any later version.
  20  *
  21  * this program is distributed in the hope that it will be useful,
  22  * but without any warranty; without even the implied warranty of
  23  * merchantability or fitness for a particular purpose.  see the
  24  * gnu general public license for more details.
  25  *
  26  * you should have received a copy of the gnu general public license
  27  * along with this program; see the file copying.
  28  * if not, write to the free software foundation,
  29  * 59 temple place - suite 330, boston, ma 02111-1307, usa.
  30  */
  31
  32 #include <linux/serial.h>
  33 #include <asm/dma.h>
  34 #include <asm/portmux.h>
  35
  36 #define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
  37 #define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
  38 #define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
  39 #define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
  40 #define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
  41 #define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
  42 #define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
  43 #define UART_GET_MSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MSR))
  44 #define UART_GET_MCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MCR))
  45
  46 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
  47 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
  48 #define UART_SET_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
  49 #define UART_CLEAR_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
  50 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
  51 #define UART_PUT_LSR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
  52 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
  53 #define UART_CLEAR_LSR(uart)    bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
  54 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
  55 #define UART_PUT_MCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
  56
  57 #define UART_SET_DLAB(uart)     /* MMRs not muxed on BF54x */
  58 #define UART_CLEAR_DLAB(uart)   /* MMRs not muxed on BF54x */
  59
  60 #define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
  61 #define UART_SET_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS))
  62 #define UART_CLEAR_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) & ~MRTS))
  63 #define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
  64 #define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
  65
  66 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
  67 # define CONFIG_SERIAL_BFIN_CTSRTS
  68
  69 # ifndef CONFIG_UART0_CTS_PIN
  70 #  define CONFIG_UART0_CTS_PIN -1
  71 # endif
  72
  73 # ifndef CONFIG_UART0_RTS_PIN
  74 #  define CONFIG_UART0_RTS_PIN -1
  75 # endif
  76
  77 # ifndef CONFIG_UART1_CTS_PIN
  78 #  define CONFIG_UART1_CTS_PIN -1
  79 # endif
  80
  81 # ifndef CONFIG_UART1_RTS_PIN
  82 #  define CONFIG_UART1_RTS_PIN -1
  83 # endif
  84 #endif
  85 /*
  86  * The pin configuration is different from schematic
  87  */
  88 struct bfin_serial_port {
  89         struct uart_port        port;
  90         unsigned int            old_status;
  91 #ifdef CONFIG_SERIAL_BFIN_DMA
  92         int                     tx_done;
  93         int                     tx_count;
  94         struct circ_buf         rx_dma_buf;
  95         struct timer_list       rx_dma_timer;
  96         int                     rx_dma_nrows;
  97         unsigned int            tx_dma_channel;
  98         unsigned int            rx_dma_channel;
  99         struct work_struct      tx_dma_workqueue;
 100 #endif
 101 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 102         struct timer_list       cts_timer;
 103         int             cts_pin;
 104         int             rts_pin;
 105 #endif
 106 };
 107
 108 struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
 109 struct bfin_serial_res {
 110         unsigned long   uart_base_addr;
 111         int             uart_irq;
 112 #ifdef CONFIG_SERIAL_BFIN_DMA
 113         unsigned int    uart_tx_dma_channel;
 114         unsigned int    uart_rx_dma_channel;
 115 #endif
 116 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 117         int     uart_cts_pin;
 118         int     uart_rts_pin;
 119 #endif
 120 };
 121
 122 struct bfin_serial_res bfin_serial_resource[] = {
 123 #ifdef CONFIG_SERIAL_BFIN_UART0
 124         {
 125         0xFFC00400,
 126         IRQ_UART0_RX,
 127 #ifdef CONFIG_SERIAL_BFIN_DMA
 128         CH_UART0_TX,
 129         CH_UART0_RX,
 130 #endif
 131 #ifdef CONFIG_BFIN_UART0_CTSRTS
 132         CONFIG_UART0_CTS_PIN,
 133         CONFIG_UART0_RTS_PIN,
 134 #endif
 135         },
 136 #endif
 137 #ifdef CONFIG_SERIAL_BFIN_UART1
 138         {
 139         0xFFC02000,
 140         IRQ_UART1_RX,
 141 #ifdef CONFIG_SERIAL_BFIN_DMA
 142         CH_UART1_TX,
 143         CH_UART1_RX,
 144 #endif
 145         },
 146 #endif
 147 #ifdef CONFIG_SERIAL_BFIN_UART2
 148         {
 149         0xFFC02100,
 150         IRQ_UART2_RX,
 151 #ifdef CONFIG_SERIAL_BFIN_DMA
 152         CH_UART2_TX,
 153         CH_UART2_RX,
 154 #endif
 155 #ifdef CONFIG_BFIN_UART2_CTSRTS
 156         CONFIG_UART2_CTS_PIN,
 157         CONFIG_UART2_RTS_PIN,
 158 #endif
 159         },
 160 #endif
 161 #ifdef CONFIG_SERIAL_BFIN_UART3
 162         {
 163         0xFFC03100,
 164         IRQ_UART3_RX,
 165 #ifdef CONFIG_SERIAL_BFIN_DMA
 166         CH_UART3_TX,
 167         CH_UART3_RX,
 168 #endif
 169         },
 170 #endif
 171 };
 172
 173 int nr_ports = ARRAY_SIZE(bfin_serial_resource);
 174
 175 #define DRIVER_NAME "bfin-uart"
 176
 177 static void bfin_serial_hw_init(struct bfin_serial_port *uart)
 178 {
 179 #ifdef CONFIG_SERIAL_BFIN_UART0
 180         peripheral_request(P_UART0_TX, DRIVER_NAME);
 181         peripheral_request(P_UART0_RX, DRIVER_NAME);
 182 #endif
 183
 184 #ifdef CONFIG_SERIAL_BFIN_UART1
 185         peripheral_request(P_UART1_TX, DRIVER_NAME);
 186         peripheral_request(P_UART1_RX, DRIVER_NAME);
 187
 188 #ifdef CONFIG_BFIN_UART1_CTSRTS
 189         peripheral_request(P_UART1_RTS, DRIVER_NAME);
 190         peripheral_request(P_UART1_CTS, DRIVER_NAME);
 191 #endif
 192 #endif
 193
 194 #ifdef CONFIG_SERIAL_BFIN_UART2
 195         peripheral_request(P_UART2_TX, DRIVER_NAME);
 196         peripheral_request(P_UART2_RX, DRIVER_NAME);
 197 #endif
 198
 199 #ifdef CONFIG_SERIAL_BFIN_UART3
 200         peripheral_request(P_UART3_TX, DRIVER_NAME);
 201         peripheral_request(P_UART3_RX, DRIVER_NAME);
 202
 203 #ifdef CONFIG_BFIN_UART3_CTSRTS
 204         peripheral_request(P_UART3_RTS, DRIVER_NAME);
 205         peripheral_request(P_UART3_CTS, DRIVER_NAME);
 206 #endif
 207 #endif
 208         SSYNC();
 209 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 210         if (uart->cts_pin >= 0) {
 211                 gpio_request(uart->cts_pin, DRIVER_NAME);
 212                 gpio_direction_input(uart->cts_pin);
 213         }
 214
 215         if (uart->rts_pin >= 0) {
 216                 gpio_request(uart->rts_pin, DRIVER_NAME);
 217                 gpio_direction_output(uart->rts_pin, 0);
 218         }
 219 #endif
 220 }