2 * 'traps.c' handles hardware traps and faults after we have saved some
5 * SuperH version: Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2000 Philipp Rumpf
7 * Copyright (C) 2000 David Howells
8 * Copyright (C) 2002 - 2007 Paul Mundt
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/kernel.h>
15 #include <linux/ptrace.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
18 #include <linux/module.h>
19 #include <linux/kallsyms.h>
21 #include <linux/bug.h>
22 #include <linux/debug_locks.h>
23 #include <linux/kdebug.h>
24 #include <linux/kexec.h>
25 #include <linux/limits.h>
26 #include <asm/system.h>
27 #include <asm/uaccess.h>
29 #include <asm/kprobes.h>
33 #define CHK_REMOTE_DEBUG(regs) \
35 if (kgdb_debug_hook && !user_mode(regs))\
36 (*kgdb_debug_hook)(regs); \
39 #define CHK_REMOTE_DEBUG(regs)
43 # define TRAP_RESERVED_INST 4
44 # define TRAP_ILLEGAL_SLOT_INST 6
45 # define TRAP_ADDRESS_ERROR 9
46 # ifdef CONFIG_CPU_SH2A
47 # define TRAP_FPU_ERROR 13
48 # define TRAP_DIVZERO_ERROR 17
49 # define TRAP_DIVOVF_ERROR 18
52 #define TRAP_RESERVED_INST 12
53 #define TRAP_ILLEGAL_SLOT_INST 13
56 static void dump_mem(const char *str
, unsigned long bottom
, unsigned long top
)
61 printk("%s(0x%08lx to 0x%08lx)\n", str
, bottom
, top
);
63 for (p
= bottom
& ~31; p
< top
; ) {
64 printk("%04lx: ", p
& 0xffff);
66 for (i
= 0; i
< 8; i
++, p
+= 4) {
69 if (p
< bottom
|| p
>= top
)
72 if (__get_user(val
, (unsigned int __user
*)p
)) {
83 static DEFINE_SPINLOCK(die_lock
);
85 void die(const char * str
, struct pt_regs
* regs
, long err
)
87 static int die_counter
;
92 spin_lock_irq(&die_lock
);
95 printk("%s: %04lx [#%d]\n", str
, err
& 0xffff, ++die_counter
);
97 CHK_REMOTE_DEBUG(regs
);
101 printk("Process: %s (pid: %d, stack limit = %p)\n", current
->comm
,
102 task_pid_nr(current
), task_stack_page(current
) + 1);
104 if (!user_mode(regs
) || in_interrupt())
105 dump_mem("Stack: ", regs
->regs
[15], THREAD_SIZE
+
106 (unsigned long)task_stack_page(current
));
108 notify_die(DIE_OOPS
, str
, regs
, err
, 255, SIGSEGV
);
111 add_taint(TAINT_DIE
);
112 spin_unlock_irq(&die_lock
);
114 if (kexec_should_crash(current
))
118 panic("Fatal exception in interrupt");
121 panic("Fatal exception");
127 static inline void die_if_kernel(const char *str
, struct pt_regs
*regs
,
130 if (!user_mode(regs
))
135 * try and fix up kernelspace address errors
136 * - userspace errors just cause EFAULT to be returned, resulting in SEGV
137 * - kernel/userspace interfaces cause a jump to an appropriate handler
138 * - other kernel errors are bad
139 * - return 0 if fixed-up, -EFAULT if non-fatal (to the kernel) fault
141 static int die_if_no_fixup(const char * str
, struct pt_regs
* regs
, long err
)
143 if (!user_mode(regs
)) {
144 const struct exception_table_entry
*fixup
;
145 fixup
= search_exception_tables(regs
->pc
);
147 regs
->pc
= fixup
->fixup
;
155 static inline void sign_extend(unsigned int count
, unsigned char *dst
)
157 #ifdef __LITTLE_ENDIAN__
158 if ((count
== 1) && dst
[0] & 0x80) {
163 if ((count
== 2) && dst
[1] & 0x80) {
168 if ((count
== 1) && dst
[3] & 0x80) {
173 if ((count
== 2) && dst
[2] & 0x80) {
180 static struct mem_access user_mem_access
= {
186 * handle an instruction that does an unaligned memory access by emulating the
188 * - note that PC _may not_ point to the faulting instruction
189 * (if that instruction is in a branch delay slot)
190 * - return 0 if emulation okay, -EFAULT on existential error
192 static int handle_unaligned_ins(opcode_t instruction
, struct pt_regs
*regs
,
193 struct mem_access
*ma
)
195 int ret
, index
, count
;
196 unsigned long *rm
, *rn
;
197 unsigned char *src
, *dst
;
198 unsigned char __user
*srcu
, *dstu
;
200 index
= (instruction
>>8)&15; /* 0x0F00 */
201 rn
= ®s
->regs
[index
];
203 index
= (instruction
>>4)&15; /* 0x00F0 */
204 rm
= ®s
->regs
[index
];
206 count
= 1<<(instruction
&3);
209 switch (instruction
>>12) {
210 case 0: /* mov.[bwl] to/from memory via r0+rn */
211 if (instruction
& 8) {
213 srcu
= (unsigned char __user
*)*rm
;
214 srcu
+= regs
->regs
[0];
215 dst
= (unsigned char *)rn
;
216 *(unsigned long *)dst
= 0;
218 #if !defined(__LITTLE_ENDIAN__)
221 if (ma
->from(dst
, srcu
, count
))
224 sign_extend(count
, dst
);
227 src
= (unsigned char *)rm
;
228 #if !defined(__LITTLE_ENDIAN__)
231 dstu
= (unsigned char __user
*)*rn
;
232 dstu
+= regs
->regs
[0];
234 if (ma
->to(dstu
, src
, count
))
240 case 1: /* mov.l Rm,@(disp,Rn) */
241 src
= (unsigned char*) rm
;
242 dstu
= (unsigned char __user
*)*rn
;
243 dstu
+= (instruction
&0x000F)<<2;
245 if (ma
->to(dstu
, src
, 4))
250 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
253 src
= (unsigned char*) rm
;
254 dstu
= (unsigned char __user
*)*rn
;
255 #if !defined(__LITTLE_ENDIAN__)
258 if (ma
->to(dstu
, src
, count
))
263 case 5: /* mov.l @(disp,Rm),Rn */
264 srcu
= (unsigned char __user
*)*rm
;
265 srcu
+= (instruction
& 0x000F) << 2;
266 dst
= (unsigned char *)rn
;
267 *(unsigned long *)dst
= 0;
269 if (ma
->from(dst
, srcu
, 4))
274 case 6: /* mov.[bwl] from memory, possibly with post-increment */
275 srcu
= (unsigned char __user
*)*rm
;
278 dst
= (unsigned char*) rn
;
279 *(unsigned long*)dst
= 0;
281 #if !defined(__LITTLE_ENDIAN__)
284 if (ma
->from(dst
, srcu
, count
))
286 sign_extend(count
, dst
);
291 switch ((instruction
&0xFF00)>>8) {
292 case 0x81: /* mov.w R0,@(disp,Rn) */
293 src
= (unsigned char *) ®s
->regs
[0];
294 #if !defined(__LITTLE_ENDIAN__)
297 dstu
= (unsigned char __user
*)*rm
; /* called Rn in the spec */
298 dstu
+= (instruction
& 0x000F) << 1;
300 if (ma
->to(dstu
, src
, 2))
305 case 0x85: /* mov.w @(disp,Rm),R0 */
306 srcu
= (unsigned char __user
*)*rm
;
307 srcu
+= (instruction
& 0x000F) << 1;
308 dst
= (unsigned char *) ®s
->regs
[0];
309 *(unsigned long *)dst
= 0;
311 #if !defined(__LITTLE_ENDIAN__)
314 if (ma
->from(dst
, srcu
, 2))
325 /* Argh. Address not only misaligned but also non-existent.
326 * Raise an EFAULT and see if it's trapped
328 return die_if_no_fixup("Fault in unaligned fixup", regs
, 0);
332 * emulate the instruction in the delay slot
333 * - fetches the instruction from PC+2
335 static inline int handle_delayslot(struct pt_regs
*regs
,
336 opcode_t old_instruction
,
337 struct mem_access
*ma
)
339 opcode_t instruction
;
340 void __user
*addr
= (void __user
*)(regs
->pc
+
341 instruction_size(old_instruction
));
343 if (copy_from_user(&instruction
, addr
, sizeof(instruction
))) {
344 /* the instruction-fetch faulted */
349 die("delay-slot-insn faulting in handle_unaligned_delayslot",
353 return handle_unaligned_ins(instruction
, regs
, ma
);
357 * handle an instruction that does an unaligned memory access
358 * - have to be careful of branch delay-slot instructions that fault
360 * - if the branch would be taken PC points to the branch
361 * - if the branch would not be taken, PC points to delay-slot
363 * - PC always points to delayed branch
364 * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
367 /* Macros to determine offset from current PC for branch instructions */
368 /* Explicit type coercion is used to force sign extension where needed */
369 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
370 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
373 * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit
377 static int handle_unaligned_notify_count
= 10;
379 int handle_unaligned_access(opcode_t instruction
, struct pt_regs
*regs
,
380 struct mem_access
*ma
)
385 index
= (instruction
>>8)&15; /* 0x0F00 */
386 rm
= regs
->regs
[index
];
388 /* shout about the first ten userspace fixups */
389 if (user_mode(regs
) && handle_unaligned_notify_count
>0) {
390 handle_unaligned_notify_count
--;
392 printk(KERN_NOTICE
"Fixing up unaligned userspace access "
393 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
394 current
->comm
, task_pid_nr(current
),
395 (void *)regs
->pc
, instruction
);
399 switch (instruction
&0xF000) {
401 if (instruction
==0x000B) {
403 ret
= handle_delayslot(regs
, instruction
, ma
);
407 else if ((instruction
&0x00FF)==0x0023) {
409 ret
= handle_delayslot(regs
, instruction
, ma
);
413 else if ((instruction
&0x00FF)==0x0003) {
415 ret
= handle_delayslot(regs
, instruction
, ma
);
417 regs
->pr
= regs
->pc
+ 4;
422 /* mov.[bwl] to/from memory via r0+rn */
427 case 0x1000: /* mov.l Rm,@(disp,Rn) */
430 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
434 if ((instruction
&0x00FF)==0x002B) {
436 ret
= handle_delayslot(regs
, instruction
, ma
);
440 else if ((instruction
&0x00FF)==0x000B) {
442 ret
= handle_delayslot(regs
, instruction
, ma
);
444 regs
->pr
= regs
->pc
+ 4;
449 /* mov.[bwl] to/from memory via r0+rn */
454 case 0x5000: /* mov.l @(disp,Rm),Rn */
457 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
460 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
461 switch (instruction
&0x0F00) {
462 case 0x0100: /* mov.w R0,@(disp,Rm) */
464 case 0x0500: /* mov.w @(disp,Rm),R0 */
466 case 0x0B00: /* bf lab - no delayslot*/
468 case 0x0F00: /* bf/s lab */
469 ret
= handle_delayslot(regs
, instruction
, ma
);
471 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
472 if ((regs
->sr
& 0x00000001) != 0)
473 regs
->pc
+= 4; /* next after slot */
476 regs
->pc
+= SH_PC_8BIT_OFFSET(instruction
);
479 case 0x0900: /* bt lab - no delayslot */
481 case 0x0D00: /* bt/s lab */
482 ret
= handle_delayslot(regs
, instruction
, ma
);
484 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
485 if ((regs
->sr
& 0x00000001) == 0)
486 regs
->pc
+= 4; /* next after slot */
489 regs
->pc
+= SH_PC_8BIT_OFFSET(instruction
);
495 case 0xA000: /* bra label */
496 ret
= handle_delayslot(regs
, instruction
, ma
);
498 regs
->pc
+= SH_PC_12BIT_OFFSET(instruction
);
501 case 0xB000: /* bsr label */
502 ret
= handle_delayslot(regs
, instruction
, ma
);
504 regs
->pr
= regs
->pc
+ 4;
505 regs
->pc
+= SH_PC_12BIT_OFFSET(instruction
);
511 /* handle non-delay-slot instruction */
513 ret
= handle_unaligned_ins(instruction
, regs
, ma
);
515 regs
->pc
+= instruction_size(instruction
);
520 * Handle various address error exceptions:
521 * - instruction address error:
523 * PC >= 0x80000000 in user mode
524 * - data address error (read and write)
525 * misaligned data access
526 * access to >= 0x80000000 is user mode
527 * Unfortuntaly we can't distinguish between instruction address error
528 * and data address errors caused by read accesses.
530 asmlinkage
void do_address_error(struct pt_regs
*regs
,
531 unsigned long writeaccess
,
532 unsigned long address
)
534 unsigned long error_code
= 0;
537 opcode_t instruction
;
540 /* Intentional ifdef */
541 #ifdef CONFIG_CPU_HAS_SR_RB
542 error_code
= lookup_exception_vector();
547 if (user_mode(regs
)) {
548 int si_code
= BUS_ADRERR
;
552 /* bad PC is not something we can fix */
554 si_code
= BUS_ADRALN
;
559 if (copy_from_user(&instruction
, (void __user
*)(regs
->pc
),
560 sizeof(instruction
))) {
561 /* Argh. Fault on the instruction itself.
562 This should never happen non-SMP
568 tmp
= handle_unaligned_access(instruction
, regs
,
575 printk(KERN_NOTICE
"Sending SIGBUS to \"%s\" due to unaligned "
576 "access (PC %lx PR %lx)\n", current
->comm
, regs
->pc
,
579 info
.si_signo
= SIGBUS
;
581 info
.si_code
= si_code
;
582 info
.si_addr
= (void __user
*)address
;
583 force_sig_info(SIGBUS
, &info
, current
);
586 die("unaligned program counter", regs
, error_code
);
589 if (copy_from_user(&instruction
, (void __user
*)(regs
->pc
),
590 sizeof(instruction
))) {
591 /* Argh. Fault on the instruction itself.
592 This should never happen non-SMP
595 die("insn faulting in do_address_error", regs
, 0);
598 handle_unaligned_access(instruction
, regs
, &user_mem_access
);
605 * SH-DSP support gerg@snapgear.com.
607 int is_dsp_inst(struct pt_regs
*regs
)
609 unsigned short inst
= 0;
612 * Safe guard if DSP mode is already enabled or we're lacking
613 * the DSP altogether.
615 if (!(current_cpu_data
.flags
& CPU_HAS_DSP
) || (regs
->sr
& SR_DSP
))
618 get_user(inst
, ((unsigned short *) regs
->pc
));
622 /* Check for any type of DSP or support instruction */
623 if ((inst
== 0xf000) || (inst
== 0x4000))
629 #define is_dsp_inst(regs) (0)
630 #endif /* CONFIG_SH_DSP */
632 #ifdef CONFIG_CPU_SH2A
633 asmlinkage
void do_divide_error(unsigned long r4
, unsigned long r5
,
634 unsigned long r6
, unsigned long r7
,
635 struct pt_regs __regs
)
640 case TRAP_DIVZERO_ERROR
:
641 info
.si_code
= FPE_INTDIV
;
643 case TRAP_DIVOVF_ERROR
:
644 info
.si_code
= FPE_INTOVF
;
648 force_sig_info(SIGFPE
, &info
, current
);
652 asmlinkage
void do_reserved_inst(unsigned long r4
, unsigned long r5
,
653 unsigned long r6
, unsigned long r7
,
654 struct pt_regs __regs
)
656 struct pt_regs
*regs
= RELOC_HIDE(&__regs
, 0);
657 unsigned long error_code
;
658 struct task_struct
*tsk
= current
;
660 #ifdef CONFIG_SH_FPU_EMU
661 unsigned short inst
= 0;
664 get_user(inst
, (unsigned short*)regs
->pc
);
666 err
= do_fpu_inst(inst
, regs
);
668 regs
->pc
+= instruction_size(inst
);
671 /* not a FPU inst. */
675 /* Check if it's a DSP instruction */
676 if (is_dsp_inst(regs
)) {
677 /* Enable DSP mode, and restart instruction. */
683 error_code
= lookup_exception_vector();
686 CHK_REMOTE_DEBUG(regs
);
687 force_sig(SIGILL
, tsk
);
688 die_if_no_fixup("reserved instruction", regs
, error_code
);
691 #ifdef CONFIG_SH_FPU_EMU
692 static int emulate_branch(unsigned short inst
, struct pt_regs
* regs
)
695 * bfs: 8fxx: PC+=d*2+4;
696 * bts: 8dxx: PC+=d*2+4;
697 * bra: axxx: PC+=D*2+4;
698 * bsr: bxxx: PC+=D*2+4 after PR=PC+4;
699 * braf:0x23: PC+=Rn*2+4;
700 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
702 * jsr: 4x0b: PC=Rn after PR=PC+4;
705 if ((inst
& 0xfd00) == 0x8d00) {
706 regs
->pc
+= SH_PC_8BIT_OFFSET(inst
);
710 if ((inst
& 0xe000) == 0xa000) {
711 regs
->pc
+= SH_PC_12BIT_OFFSET(inst
);
715 if ((inst
& 0xf0df) == 0x0003) {
716 regs
->pc
+= regs
->regs
[(inst
& 0x0f00) >> 8] + 4;
720 if ((inst
& 0xf0df) == 0x400b) {
721 regs
->pc
= regs
->regs
[(inst
& 0x0f00) >> 8];
725 if ((inst
& 0xffff) == 0x000b) {
734 asmlinkage
void do_illegal_slot_inst(unsigned long r4
, unsigned long r5
,
735 unsigned long r6
, unsigned long r7
,
736 struct pt_regs __regs
)
738 struct pt_regs
*regs
= RELOC_HIDE(&__regs
, 0);
740 struct task_struct
*tsk
= current
;
742 if (kprobe_handle_illslot(regs
->pc
) == 0)
745 #ifdef CONFIG_SH_FPU_EMU
746 get_user(inst
, (unsigned short *)regs
->pc
+ 1);
747 if (!do_fpu_inst(inst
, regs
)) {
748 get_user(inst
, (unsigned short *)regs
->pc
);
749 if (!emulate_branch(inst
, regs
))
751 /* fault in branch.*/
753 /* not a FPU inst. */
756 inst
= lookup_exception_vector();
759 CHK_REMOTE_DEBUG(regs
);
760 force_sig(SIGILL
, tsk
);
761 die_if_no_fixup("illegal slot instruction", regs
, inst
);
764 asmlinkage
void do_exception_error(unsigned long r4
, unsigned long r5
,
765 unsigned long r6
, unsigned long r7
,
766 struct pt_regs __regs
)
768 struct pt_regs
*regs
= RELOC_HIDE(&__regs
, 0);
771 ex
= lookup_exception_vector();
772 die_if_kernel("exception", regs
, ex
);
775 #if defined(CONFIG_SH_STANDARD_BIOS)
776 void *gdb_vbr_vector
;
778 static inline void __init
gdb_vbr_init(void)
780 register unsigned long vbr
;
783 * Read the old value of the VBR register to initialise
784 * the vector through which debug and BIOS traps are
785 * delegated by the Linux trap handler.
787 asm volatile("stc vbr, %0" : "=r" (vbr
));
789 gdb_vbr_vector
= (void *)(vbr
+ 0x100);
790 printk("Setting GDB trap vector to 0x%08lx\n",
791 (unsigned long)gdb_vbr_vector
);
795 void __cpuinit
per_cpu_trap_init(void)
797 extern void *vbr_base
;
799 #ifdef CONFIG_SH_STANDARD_BIOS
800 if (raw_smp_processor_id() == 0)
804 /* NOTE: The VBR value should be at P1
805 (or P2, virtural "fixed" address space).
806 It's definitely should not in physical address. */
808 asm volatile("ldc %0, vbr"
814 void *set_exception_table_vec(unsigned int vec
, void *handler
)
816 extern void *exception_handling_table
[];
819 old_handler
= exception_handling_table
[vec
];
820 exception_handling_table
[vec
] = handler
;
824 void __init
trap_init(void)
826 set_exception_table_vec(TRAP_RESERVED_INST
, do_reserved_inst
);
827 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST
, do_illegal_slot_inst
);
829 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
830 defined(CONFIG_SH_FPU_EMU)
832 * For SH-4 lacking an FPU, treat floating point instructions as
833 * reserved. They'll be handled in the math-emu case, or faulted on
836 set_exception_table_evt(0x800, do_reserved_inst
);
837 set_exception_table_evt(0x820, do_illegal_slot_inst
);
838 #elif defined(CONFIG_SH_FPU)
839 #ifdef CONFIG_CPU_SUBTYPE_SHX3
840 set_exception_table_evt(0xd80, fpu_state_restore_trap_handler
);
841 set_exception_table_evt(0xda0, fpu_state_restore_trap_handler
);
843 set_exception_table_evt(0x800, fpu_state_restore_trap_handler
);
844 set_exception_table_evt(0x820, fpu_state_restore_trap_handler
);
848 #ifdef CONFIG_CPU_SH2
849 set_exception_table_vec(TRAP_ADDRESS_ERROR
, address_error_trap_handler
);
851 #ifdef CONFIG_CPU_SH2A
852 set_exception_table_vec(TRAP_DIVZERO_ERROR
, do_divide_error
);
853 set_exception_table_vec(TRAP_DIVOVF_ERROR
, do_divide_error
);
855 set_exception_table_vec(TRAP_FPU_ERROR
, fpu_error_trap_handler
);
859 /* Setup VBR for boot cpu */
863 void show_trace(struct task_struct
*tsk
, unsigned long *sp
,
864 struct pt_regs
*regs
)
868 if (regs
&& user_mode(regs
))
871 printk("\nCall trace: ");
872 #ifdef CONFIG_KALLSYMS
876 while (!kstack_end(sp
)) {
878 if (kernel_text_address(addr
))
887 debug_show_held_locks(tsk
);
890 void show_stack(struct task_struct
*tsk
, unsigned long *sp
)
897 sp
= (unsigned long *)current_stack_pointer
;
899 sp
= (unsigned long *)tsk
->thread
.sp
;
901 stack
= (unsigned long)sp
;
902 dump_mem("Stack: ", stack
, THREAD_SIZE
+
903 (unsigned long)task_stack_page(tsk
));
904 show_trace(tsk
, sp
, NULL
);
907 void dump_stack(void)
909 show_stack(NULL
, NULL
);
911 EXPORT_SYMBOL(dump_stack
);