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e1000e: Reset 82577/82578 PHY before first PHY register read
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / e1000e / ich8lan.c
blobb8c4dce01a04ece9a4205d4f011823660bf65008
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
55 */
56
57 #include "e1000.h"
58
59 #define ICH_FLASH_GFPREG 0x0000
60 #define ICH_FLASH_HSFSTS 0x0004
61 #define ICH_FLASH_HSFCTL 0x0006
62 #define ICH_FLASH_FADDR 0x0008
63 #define ICH_FLASH_FDATA0 0x0010
64 #define ICH_FLASH_PR0 0x0074
65
66 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
67 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
68 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
69 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
70 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
71
72 #define ICH_CYCLE_READ 0
73 #define ICH_CYCLE_WRITE 2
74 #define ICH_CYCLE_ERASE 3
75
76 #define FLASH_GFPREG_BASE_MASK 0x1FFF
77 #define FLASH_SECTOR_ADDR_SHIFT 12
78
79 #define ICH_FLASH_SEG_SIZE_256 256
80 #define ICH_FLASH_SEG_SIZE_4K 4096
81 #define ICH_FLASH_SEG_SIZE_8K 8192
82 #define ICH_FLASH_SEG_SIZE_64K 65536
83
84
85 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
86 /* FW established a valid mode */
87 #define E1000_ICH_FWSM_FW_VALID 0x00008000
88
89 #define E1000_ICH_MNG_IAMT_MODE 0x2
90
91 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
92 (ID_LED_DEF1_OFF2 << 8) | \
93 (ID_LED_DEF1_ON2 << 4) | \
94 (ID_LED_DEF1_DEF2))
95
96 #define E1000_ICH_NVM_SIG_WORD 0x13
97 #define E1000_ICH_NVM_SIG_MASK 0xC000
98 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
99 #define E1000_ICH_NVM_SIG_VALUE 0x80
100
101 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
102
103 #define E1000_FEXTNVM_SW_CONFIG 1
104 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
105
106 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
107
108 #define E1000_ICH_RAR_ENTRIES 7
109
110 #define PHY_PAGE_SHIFT 5
111 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
112 ((reg) & MAX_PHY_REG_ADDRESS))
113 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
114 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
115
116 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
117 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
118 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
119
120 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
121
122 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
123
124 /* SMBus Address Phy Register */
125 #define HV_SMB_ADDR PHY_REG(768, 26)
126 #define HV_SMB_ADDR_PEC_EN 0x0200
127 #define HV_SMB_ADDR_VALID 0x0080
128
129 /* Strapping Option Register - RO */
130 #define E1000_STRAP 0x0000C
131 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
132 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
133
134 /* OEM Bits Phy Register */
135 #define HV_OEM_BITS PHY_REG(768, 25)
136 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
137 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
138 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
139
140 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
141 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
142
143 /* KMRN Mode Control */
144 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
145 #define HV_KMRN_MDIO_SLOW 0x0400
146
147 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
148 /* Offset 04h HSFSTS */
149 union ich8_hws_flash_status {
150 struct ich8_hsfsts {
151 u16 flcdone :1; /* bit 0 Flash Cycle Done */
152 u16 flcerr :1; /* bit 1 Flash Cycle Error */
153 u16 dael :1; /* bit 2 Direct Access error Log */
154 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
155 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
156 u16 reserved1 :2; /* bit 13:6 Reserved */
157 u16 reserved2 :6; /* bit 13:6 Reserved */
158 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
159 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
160 } hsf_status;
161 u16 regval;
162 };
163
164 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
165 /* Offset 06h FLCTL */
166 union ich8_hws_flash_ctrl {
167 struct ich8_hsflctl {
168 u16 flcgo :1; /* 0 Flash Cycle Go */
169 u16 flcycle :2; /* 2:1 Flash Cycle */
170 u16 reserved :5; /* 7:3 Reserved */
171 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
172 u16 flockdn :6; /* 15:10 Reserved */
173 } hsf_ctrl;
174 u16 regval;
175 };
176
177 /* ICH Flash Region Access Permissions */
178 union ich8_hws_flash_regacc {
179 struct ich8_flracc {
180 u32 grra :8; /* 0:7 GbE region Read Access */
181 u32 grwa :8; /* 8:15 GbE region Write Access */
182 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
183 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
184 } hsf_flregacc;
185 u16 regval;
186 };
187
188 /* ICH Flash Protected Region */
189 union ich8_flash_protected_range {
190 struct ich8_pr {
191 u32 base:13; /* 0:12 Protected Range Base */
192 u32 reserved1:2; /* 13:14 Reserved */
193 u32 rpe:1; /* 15 Read Protection Enable */
194 u32 limit:13; /* 16:28 Protected Range Limit */
195 u32 reserved2:2; /* 29:30 Reserved */
196 u32 wpe:1; /* 31 Write Protection Enable */
197 } range;
198 u32 regval;
199 };
200
201 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
202 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
203 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
204 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
205 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
206 u32 offset, u8 byte);
207 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
208 u8 *data);
209 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
210 u16 *data);
211 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
212 u8 size, u16 *data);
213 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
214 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
215 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
216 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
217 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
218 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
219 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
220 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
221 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
222 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
223 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
224 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
225 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
226 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
227 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
228 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
229
230 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
231 {
232 return readw(hw->flash_address + reg);
233 }
234
235 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
236 {
237 return readl(hw->flash_address + reg);
238 }
239
240 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
241 {
242 writew(val, hw->flash_address + reg);
243 }
244
245 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
246 {
247 writel(val, hw->flash_address + reg);
248 }
249
250 #define er16flash(reg) __er16flash(hw, (reg))
251 #define er32flash(reg) __er32flash(hw, (reg))
252 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
253 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
254
255 /**
256 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
257 * @hw: pointer to the HW structure
258 *
259 * Initialize family-specific PHY parameters and function pointers.
260 **/
261 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
262 {
263 struct e1000_phy_info *phy = &hw->phy;
264 u32 ctrl;
265 s32 ret_val = 0;
266
267 phy->addr = 1;
268 phy->reset_delay_us = 100;
269
270 phy->ops.read_reg = e1000_read_phy_reg_hv;
271 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
272 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
273 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
274 phy->ops.write_reg = e1000_write_phy_reg_hv;
275 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
276 phy->ops.power_up = e1000_power_up_phy_copper;
277 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
278 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
279
280 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
281 /*
282 * The MAC-PHY interconnect may still be in SMBus mode
283 * after Sx->S0. Toggle the LANPHYPC Value bit to force
284 * the interconnect to PCIe mode, but only if there is no
285 * firmware present otherwise firmware will have done it.
286 */
287 ctrl = er32(CTRL);
288 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
289 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
290 ew32(CTRL, ctrl);
291 udelay(10);
292 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
293 ew32(CTRL, ctrl);
294 msleep(50);
295 }
296
297 /*
298 * Reset the PHY before any acccess to it. Doing so, ensures that
299 * the PHY is in a known good state before we read/write PHY registers.
300 * The generic reset is sufficient here, because we haven't determined
301 * the PHY type yet.
302 */
303 ret_val = e1000e_phy_hw_reset_generic(hw);
304 if (ret_val)
305 goto out;
306
307 phy->id = e1000_phy_unknown;
308 ret_val = e1000e_get_phy_id(hw);
309 if (ret_val)
310 goto out;
311 if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {
312 /*
313 * In case the PHY needs to be in mdio slow mode (eg. 82577),
314 * set slow mode and try to get the PHY id again.
315 */
316 ret_val = e1000_set_mdio_slow_mode_hv(hw);
317 if (ret_val)
318 goto out;
319 ret_val = e1000e_get_phy_id(hw);
320 if (ret_val)
321 goto out;
322 }
323 phy->type = e1000e_get_phy_type_from_id(phy->id);
324
325 switch (phy->type) {
326 case e1000_phy_82577:
327 phy->ops.check_polarity = e1000_check_polarity_82577;
328 phy->ops.force_speed_duplex =
329 e1000_phy_force_speed_duplex_82577;
330 phy->ops.get_cable_length = e1000_get_cable_length_82577;
331 phy->ops.get_info = e1000_get_phy_info_82577;
332 phy->ops.commit = e1000e_phy_sw_reset;
333 case e1000_phy_82578:
334 phy->ops.check_polarity = e1000_check_polarity_m88;
335 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
336 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
337 phy->ops.get_info = e1000e_get_phy_info_m88;
338 break;
339 default:
340 ret_val = -E1000_ERR_PHY;
341 break;
342 }
343
344 out:
345 return ret_val;
346 }
347
348 /**
349 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
350 * @hw: pointer to the HW structure
351 *
352 * Initialize family-specific PHY parameters and function pointers.
353 **/
354 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
355 {
356 struct e1000_phy_info *phy = &hw->phy;
357 s32 ret_val;
358 u16 i = 0;
359
360 phy->addr = 1;
361 phy->reset_delay_us = 100;
362
363 phy->ops.power_up = e1000_power_up_phy_copper;
364 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
365
366 /*
367 * We may need to do this twice - once for IGP and if that fails,
368 * we'll set BM func pointers and try again
369 */
370 ret_val = e1000e_determine_phy_address(hw);
371 if (ret_val) {
372 phy->ops.write_reg = e1000e_write_phy_reg_bm;
373 phy->ops.read_reg = e1000e_read_phy_reg_bm;
374 ret_val = e1000e_determine_phy_address(hw);
375 if (ret_val) {
376 e_dbg("Cannot determine PHY addr. Erroring out\n");
377 return ret_val;
378 }
379 }
380
381 phy->id = 0;
382 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
383 (i++ < 100)) {
384 msleep(1);
385 ret_val = e1000e_get_phy_id(hw);
386 if (ret_val)
387 return ret_val;
388 }
389
390 /* Verify phy id */
391 switch (phy->id) {
392 case IGP03E1000_E_PHY_ID:
393 phy->type = e1000_phy_igp_3;
394 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
395 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
396 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
397 phy->ops.get_info = e1000e_get_phy_info_igp;
398 phy->ops.check_polarity = e1000_check_polarity_igp;
399 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
400 break;
401 case IFE_E_PHY_ID:
402 case IFE_PLUS_E_PHY_ID:
403 case IFE_C_E_PHY_ID:
404 phy->type = e1000_phy_ife;
405 phy->autoneg_mask = E1000_ALL_NOT_GIG;
406 phy->ops.get_info = e1000_get_phy_info_ife;
407 phy->ops.check_polarity = e1000_check_polarity_ife;
408 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
409 break;
410 case BME1000_E_PHY_ID:
411 phy->type = e1000_phy_bm;
412 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
413 phy->ops.read_reg = e1000e_read_phy_reg_bm;
414 phy->ops.write_reg = e1000e_write_phy_reg_bm;
415 phy->ops.commit = e1000e_phy_sw_reset;
416 phy->ops.get_info = e1000e_get_phy_info_m88;
417 phy->ops.check_polarity = e1000_check_polarity_m88;
418 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
419 break;
420 default:
421 return -E1000_ERR_PHY;
422 break;
423 }
424
425 return 0;
426 }
427
428 /**
429 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
430 * @hw: pointer to the HW structure
431 *
432 * Initialize family-specific NVM parameters and function
433 * pointers.
434 **/
435 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
436 {
437 struct e1000_nvm_info *nvm = &hw->nvm;
438 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
439 u32 gfpreg, sector_base_addr, sector_end_addr;
440 u16 i;
441
442 /* Can't read flash registers if the register set isn't mapped. */
443 if (!hw->flash_address) {
444 e_dbg("ERROR: Flash registers not mapped\n");
445 return -E1000_ERR_CONFIG;
446 }
447
448 nvm->type = e1000_nvm_flash_sw;
449
450 gfpreg = er32flash(ICH_FLASH_GFPREG);
451
452 /*
453 * sector_X_addr is a "sector"-aligned address (4096 bytes)
454 * Add 1 to sector_end_addr since this sector is included in
455 * the overall size.
456 */
457 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
458 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
459
460 /* flash_base_addr is byte-aligned */
461 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
462
463 /*
464 * find total size of the NVM, then cut in half since the total
465 * size represents two separate NVM banks.
466 */
467 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
468 << FLASH_SECTOR_ADDR_SHIFT;
469 nvm->flash_bank_size /= 2;
470 /* Adjust to word count */
471 nvm->flash_bank_size /= sizeof(u16);
472
473 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
474
475 /* Clear shadow ram */
476 for (i = 0; i < nvm->word_size; i++) {
477 dev_spec->shadow_ram[i].modified = false;
478 dev_spec->shadow_ram[i].value = 0xFFFF;
479 }
480
481 return 0;
482 }
483
484 /**
485 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
486 * @hw: pointer to the HW structure
487 *
488 * Initialize family-specific MAC parameters and function
489 * pointers.
490 **/
491 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
492 {
493 struct e1000_hw *hw = &adapter->hw;
494 struct e1000_mac_info *mac = &hw->mac;
495
496 /* Set media type function pointer */
497 hw->phy.media_type = e1000_media_type_copper;
498
499 /* Set mta register count */
500 mac->mta_reg_count = 32;
501 /* Set rar entry count */
502 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
503 if (mac->type == e1000_ich8lan)
504 mac->rar_entry_count--;
505 /* Set if manageability features are enabled. */
506 mac->arc_subsystem_valid = true;
507 /* Adaptive IFS supported */
508 mac->adaptive_ifs = true;
509
510 /* LED operations */
511 switch (mac->type) {
512 case e1000_ich8lan:
513 case e1000_ich9lan:
514 case e1000_ich10lan:
515 /* ID LED init */
516 mac->ops.id_led_init = e1000e_id_led_init;
517 /* setup LED */
518 mac->ops.setup_led = e1000e_setup_led_generic;
519 /* cleanup LED */
520 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
521 /* turn on/off LED */
522 mac->ops.led_on = e1000_led_on_ich8lan;
523 mac->ops.led_off = e1000_led_off_ich8lan;
524 break;
525 case e1000_pchlan:
526 /* ID LED init */
527 mac->ops.id_led_init = e1000_id_led_init_pchlan;
528 /* setup LED */
529 mac->ops.setup_led = e1000_setup_led_pchlan;
530 /* cleanup LED */
531 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
532 /* turn on/off LED */
533 mac->ops.led_on = e1000_led_on_pchlan;
534 mac->ops.led_off = e1000_led_off_pchlan;
535 break;
536 default:
537 break;
538 }
539
540 /* Enable PCS Lock-loss workaround for ICH8 */
541 if (mac->type == e1000_ich8lan)
542 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
543
544 return 0;
545 }
546
547 /**
548 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
549 * @hw: pointer to the HW structure
550 *
551 * Checks to see of the link status of the hardware has changed. If a
552 * change in link status has been detected, then we read the PHY registers
553 * to get the current speed/duplex if link exists.
554 **/
555 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
556 {
557 struct e1000_mac_info *mac = &hw->mac;
558 s32 ret_val;
559 bool link;
560
561 /*
562 * We only want to go out to the PHY registers to see if Auto-Neg
563 * has completed and/or if our link status has changed. The
564 * get_link_status flag is set upon receiving a Link Status
565 * Change or Rx Sequence Error interrupt.
566 */
567 if (!mac->get_link_status) {
568 ret_val = 0;
569 goto out;
570 }
571
572 /*
573 * First we want to see if the MII Status Register reports
574 * link. If so, then we want to get the current speed/duplex
575 * of the PHY.
576 */
577 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
578 if (ret_val)
579 goto out;
580
581 if (hw->mac.type == e1000_pchlan) {
582 ret_val = e1000_k1_gig_workaround_hv(hw, link);
583 if (ret_val)
584 goto out;
585 }
586
587 if (!link)
588 goto out; /* No link detected */
589
590 mac->get_link_status = false;
591
592 if (hw->phy.type == e1000_phy_82578) {
593 ret_val = e1000_link_stall_workaround_hv(hw);
594 if (ret_val)
595 goto out;
596 }
597
598 /*
599 * Check if there was DownShift, must be checked
600 * immediately after link-up
601 */
602 e1000e_check_downshift(hw);
603
604 /*
605 * If we are forcing speed/duplex, then we simply return since
606 * we have already determined whether we have link or not.
607 */
608 if (!mac->autoneg) {
609 ret_val = -E1000_ERR_CONFIG;
610 goto out;
611 }
612
613 /*
614 * Auto-Neg is enabled. Auto Speed Detection takes care
615 * of MAC speed/duplex configuration. So we only need to
616 * configure Collision Distance in the MAC.
617 */
618 e1000e_config_collision_dist(hw);
619
620 /*
621 * Configure Flow Control now that Auto-Neg has completed.
622 * First, we need to restore the desired flow control
623 * settings because we may have had to re-autoneg with a
624 * different link partner.
625 */
626 ret_val = e1000e_config_fc_after_link_up(hw);
627 if (ret_val)
628 e_dbg("Error configuring flow control\n");
629
630 out:
631 return ret_val;
632 }
633
634 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
635 {
636 struct e1000_hw *hw = &adapter->hw;
637 s32 rc;
638
639 rc = e1000_init_mac_params_ich8lan(adapter);
640 if (rc)
641 return rc;
642
643 rc = e1000_init_nvm_params_ich8lan(hw);
644 if (rc)
645 return rc;
646
647 if (hw->mac.type == e1000_pchlan)
648 rc = e1000_init_phy_params_pchlan(hw);
649 else
650 rc = e1000_init_phy_params_ich8lan(hw);
651 if (rc)
652 return rc;
653
654 if (adapter->hw.phy.type == e1000_phy_ife) {
655 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
656 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
657 }
658
659 if ((adapter->hw.mac.type == e1000_ich8lan) &&
660 (adapter->hw.phy.type == e1000_phy_igp_3))
661 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
662
663 return 0;
664 }
665
666 static DEFINE_MUTEX(nvm_mutex);
667
668 /**
669 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
670 * @hw: pointer to the HW structure
671 *
672 * Acquires the mutex for performing NVM operations.
673 **/
674 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
675 {
676 mutex_lock(&nvm_mutex);
677
678 return 0;
679 }
680
681 /**
682 * e1000_release_nvm_ich8lan - Release NVM mutex
683 * @hw: pointer to the HW structure
684 *
685 * Releases the mutex used while performing NVM operations.
686 **/
687 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
688 {
689 mutex_unlock(&nvm_mutex);
690
691 return;
692 }
693
694 static DEFINE_MUTEX(swflag_mutex);
695
696 /**
697 * e1000_acquire_swflag_ich8lan - Acquire software control flag
698 * @hw: pointer to the HW structure
699 *
700 * Acquires the software control flag for performing PHY and select
701 * MAC CSR accesses.
702 **/
703 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
704 {
705 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
706 s32 ret_val = 0;
707
708 mutex_lock(&swflag_mutex);
709
710 while (timeout) {
711 extcnf_ctrl = er32(EXTCNF_CTRL);
712 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
713 break;
714
715 mdelay(1);
716 timeout--;
717 }
718
719 if (!timeout) {
720 e_dbg("SW/FW/HW has locked the resource for too long.\n");
721 ret_val = -E1000_ERR_CONFIG;
722 goto out;
723 }
724
725 timeout = SW_FLAG_TIMEOUT;
726
727 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
728 ew32(EXTCNF_CTRL, extcnf_ctrl);
729
730 while (timeout) {
731 extcnf_ctrl = er32(EXTCNF_CTRL);
732 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
733 break;
734
735 mdelay(1);
736 timeout--;
737 }
738
739 if (!timeout) {
740 e_dbg("Failed to acquire the semaphore.\n");
741 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
742 ew32(EXTCNF_CTRL, extcnf_ctrl);
743 ret_val = -E1000_ERR_CONFIG;
744 goto out;
745 }
746
747 out:
748 if (ret_val)
749 mutex_unlock(&swflag_mutex);
750
751 return ret_val;
752 }
753
754 /**
755 * e1000_release_swflag_ich8lan - Release software control flag
756 * @hw: pointer to the HW structure
757 *
758 * Releases the software control flag for performing PHY and select
759 * MAC CSR accesses.
760 **/
761 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
762 {
763 u32 extcnf_ctrl;
764
765 extcnf_ctrl = er32(EXTCNF_CTRL);
766 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
767 ew32(EXTCNF_CTRL, extcnf_ctrl);
768
769 mutex_unlock(&swflag_mutex);
770
771 return;
772 }
773
774 /**
775 * e1000_check_mng_mode_ich8lan - Checks management mode
776 * @hw: pointer to the HW structure
777 *
778 * This checks if the adapter has manageability enabled.
779 * This is a function pointer entry point only called by read/write
780 * routines for the PHY and NVM parts.
781 **/
782 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
783 {
784 u32 fwsm;
785
786 fwsm = er32(FWSM);
787
788 return (fwsm & E1000_FWSM_MODE_MASK) ==
789 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
790 }
791
792 /**
793 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
794 * @hw: pointer to the HW structure
795 *
796 * Checks if firmware is blocking the reset of the PHY.
797 * This is a function pointer entry point only called by
798 * reset routines.
799 **/
800 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
801 {
802 u32 fwsm;
803
804 fwsm = er32(FWSM);
805
806 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
807 }
808
809 /**
810 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
811 * @hw: pointer to the HW structure
812 *
813 * SW should configure the LCD from the NVM extended configuration region
814 * as a workaround for certain parts.
815 **/
816 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
817 {
818 struct e1000_phy_info *phy = &hw->phy;
819 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
820 s32 ret_val;
821 u16 word_addr, reg_data, reg_addr, phy_page = 0;
822
823 ret_val = hw->phy.ops.acquire(hw);
824 if (ret_val)
825 return ret_val;
826
827 /*
828 * Initialize the PHY from the NVM on ICH platforms. This
829 * is needed due to an issue where the NVM configuration is
830 * not properly autoloaded after power transitions.
831 * Therefore, after each PHY reset, we will load the
832 * configuration data out of the NVM manually.
833 */
834 if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
835 (hw->mac.type == e1000_pchlan)) {
836 struct e1000_adapter *adapter = hw->adapter;
837
838 /* Check if SW needs to configure the PHY */
839 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
840 (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
841 (hw->mac.type == e1000_pchlan))
842 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
843 else
844 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
845
846 data = er32(FEXTNVM);
847 if (!(data & sw_cfg_mask))
848 goto out;
849
850 /* Wait for basic configuration completes before proceeding */
851 e1000_lan_init_done_ich8lan(hw);
852
853 /*
854 * Make sure HW does not configure LCD from PHY
855 * extended configuration before SW configuration
856 */
857 data = er32(EXTCNF_CTRL);
858 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
859 goto out;
860
861 cnf_size = er32(EXTCNF_SIZE);
862 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
863 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
864 if (!cnf_size)
865 goto out;
866
867 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
868 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
869
870 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
871 (hw->mac.type == e1000_pchlan)) {
872 /*
873 * HW configures the SMBus address and LEDs when the
874 * OEM and LCD Write Enable bits are set in the NVM.
875 * When both NVM bits are cleared, SW will configure
876 * them instead.
877 */
878 data = er32(STRAP);
879 data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
880 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
881 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
882 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
883 reg_data);
884 if (ret_val)
885 goto out;
886
887 data = er32(LEDCTL);
888 ret_val = e1000_write_phy_reg_hv_locked(hw,
889 HV_LED_CONFIG,
890 (u16)data);
891 if (ret_val)
892 goto out;
893 }
894 /* Configure LCD from extended configuration region. */
895
896 /* cnf_base_addr is in DWORD */
897 word_addr = (u16)(cnf_base_addr << 1);
898
899 for (i = 0; i < cnf_size; i++) {
900 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
901 &reg_data);
902 if (ret_val)
903 goto out;
904
905 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
906 1, &reg_addr);
907 if (ret_val)
908 goto out;
909
910 /* Save off the PHY page for future writes. */
911 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
912 phy_page = reg_data;
913 continue;
914 }
915
916 reg_addr &= PHY_REG_MASK;
917 reg_addr |= phy_page;
918
919 ret_val = phy->ops.write_reg_locked(hw,
920 (u32)reg_addr,
921 reg_data);
922 if (ret_val)
923 goto out;
924 }
925 }
926
927 out:
928 hw->phy.ops.release(hw);
929 return ret_val;
930 }
931
932 /**
933 * e1000_k1_gig_workaround_hv - K1 Si workaround
934 * @hw: pointer to the HW structure
935 * @link: link up bool flag
936 *
937 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
938 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
939 * If link is down, the function will restore the default K1 setting located
940 * in the NVM.
941 **/
942 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
943 {
944 s32 ret_val = 0;
945 u16 status_reg = 0;
946 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
947
948 if (hw->mac.type != e1000_pchlan)
949 goto out;
950
951 /* Wrap the whole flow with the sw flag */
952 ret_val = hw->phy.ops.acquire(hw);
953 if (ret_val)
954 goto out;
955
956 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
957 if (link) {
958 if (hw->phy.type == e1000_phy_82578) {
959 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
960 &status_reg);
961 if (ret_val)
962 goto release;
963
964 status_reg &= BM_CS_STATUS_LINK_UP |
965 BM_CS_STATUS_RESOLVED |
966 BM_CS_STATUS_SPEED_MASK;
967
968 if (status_reg == (BM_CS_STATUS_LINK_UP |
969 BM_CS_STATUS_RESOLVED |
970 BM_CS_STATUS_SPEED_1000))
971 k1_enable = false;
972 }
973
974 if (hw->phy.type == e1000_phy_82577) {
975 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
976 &status_reg);
977 if (ret_val)
978 goto release;
979
980 status_reg &= HV_M_STATUS_LINK_UP |
981 HV_M_STATUS_AUTONEG_COMPLETE |
982 HV_M_STATUS_SPEED_MASK;
983
984 if (status_reg == (HV_M_STATUS_LINK_UP |
985 HV_M_STATUS_AUTONEG_COMPLETE |
986 HV_M_STATUS_SPEED_1000))
987 k1_enable = false;
988 }
989
990 /* Link stall fix for link up */
991 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
992 0x0100);
993 if (ret_val)
994 goto release;
995
996 } else {
997 /* Link stall fix for link down */
998 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
999 0x4100);
1000 if (ret_val)
1001 goto release;
1002 }
1003
1004 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1005
1006 release:
1007 hw->phy.ops.release(hw);
1008 out:
1009 return ret_val;
1010 }
1011
1012 /**
1013 * e1000_configure_k1_ich8lan - Configure K1 power state
1014 * @hw: pointer to the HW structure
1015 * @enable: K1 state to configure
1016 *
1017 * Configure the K1 power state based on the provided parameter.
1018 * Assumes semaphore already acquired.
1019 *
1020 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1021 **/
1022 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1023 {
1024 s32 ret_val = 0;
1025 u32 ctrl_reg = 0;
1026 u32 ctrl_ext = 0;
1027 u32 reg = 0;
1028 u16 kmrn_reg = 0;
1029
1030 ret_val = e1000e_read_kmrn_reg_locked(hw,
1031 E1000_KMRNCTRLSTA_K1_CONFIG,
1032 &kmrn_reg);
1033 if (ret_val)
1034 goto out;
1035
1036 if (k1_enable)
1037 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1038 else
1039 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1040
1041 ret_val = e1000e_write_kmrn_reg_locked(hw,
1042 E1000_KMRNCTRLSTA_K1_CONFIG,
1043 kmrn_reg);
1044 if (ret_val)
1045 goto out;
1046
1047 udelay(20);
1048 ctrl_ext = er32(CTRL_EXT);
1049 ctrl_reg = er32(CTRL);
1050
1051 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1052 reg |= E1000_CTRL_FRCSPD;
1053 ew32(CTRL, reg);
1054
1055 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1056 udelay(20);
1057 ew32(CTRL, ctrl_reg);
1058 ew32(CTRL_EXT, ctrl_ext);
1059 udelay(20);
1060
1061 out:
1062 return ret_val;
1063 }
1064
1065 /**
1066 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1067 * @hw: pointer to the HW structure
1068 * @d0_state: boolean if entering d0 or d3 device state
1069 *
1070 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1071 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1072 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1073 **/
1074 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1075 {
1076 s32 ret_val = 0;
1077 u32 mac_reg;
1078 u16 oem_reg;
1079
1080 if (hw->mac.type != e1000_pchlan)
1081 return ret_val;
1082
1083 ret_val = hw->phy.ops.acquire(hw);
1084 if (ret_val)
1085 return ret_val;
1086
1087 mac_reg = er32(EXTCNF_CTRL);
1088 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1089 goto out;
1090
1091 mac_reg = er32(FEXTNVM);
1092 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1093 goto out;
1094
1095 mac_reg = er32(PHY_CTRL);
1096
1097 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1098 if (ret_val)
1099 goto out;
1100
1101 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1102
1103 if (d0_state) {
1104 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1105 oem_reg |= HV_OEM_BITS_GBE_DIS;
1106
1107 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1108 oem_reg |= HV_OEM_BITS_LPLU;
1109 } else {
1110 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1111 oem_reg |= HV_OEM_BITS_GBE_DIS;
1112
1113 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1114 oem_reg |= HV_OEM_BITS_LPLU;
1115 }
1116 /* Restart auto-neg to activate the bits */
1117 if (!e1000_check_reset_block(hw))
1118 oem_reg |= HV_OEM_BITS_RESTART_AN;
1119 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1120
1121 out:
1122 hw->phy.ops.release(hw);
1123
1124 return ret_val;
1125 }
1126
1127
1128 /**
1129 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1130 * @hw: pointer to the HW structure
1131 **/
1132 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1133 {
1134 s32 ret_val;
1135 u16 data;
1136
1137 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1138 if (ret_val)
1139 return ret_val;
1140
1141 data |= HV_KMRN_MDIO_SLOW;
1142
1143 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1144
1145 return ret_val;
1146 }
1147
1148 /**
1149 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1150 * done after every PHY reset.
1151 **/
1152 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1153 {
1154 s32 ret_val = 0;
1155 u16 phy_data;
1156
1157 if (hw->mac.type != e1000_pchlan)
1158 return ret_val;
1159
1160 /* Set MDIO slow mode before any other MDIO access */
1161 if (hw->phy.type == e1000_phy_82577) {
1162 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1163 if (ret_val)
1164 goto out;
1165 }
1166
1167 if (((hw->phy.type == e1000_phy_82577) &&
1168 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1169 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1170 /* Disable generation of early preamble */
1171 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1172 if (ret_val)
1173 return ret_val;
1174
1175 /* Preamble tuning for SSC */
1176 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1177 if (ret_val)
1178 return ret_val;
1179 }
1180
1181 if (hw->phy.type == e1000_phy_82578) {
1182 /*
1183 * Return registers to default by doing a soft reset then
1184 * writing 0x3140 to the control register.
1185 */
1186 if (hw->phy.revision < 2) {
1187 e1000e_phy_sw_reset(hw);
1188 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1189 }
1190 }
1191
1192 /* Select page 0 */
1193 ret_val = hw->phy.ops.acquire(hw);
1194 if (ret_val)
1195 return ret_val;
1196
1197 hw->phy.addr = 1;
1198 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1199 hw->phy.ops.release(hw);
1200 if (ret_val)
1201 goto out;
1202
1203 /*
1204 * Configure the K1 Si workaround during phy reset assuming there is
1205 * link so that it disables K1 if link is in 1Gbps.
1206 */
1207 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1208 if (ret_val)
1209 goto out;
1210
1211 /* Workaround for link disconnects on a busy hub in half duplex */
1212 ret_val = hw->phy.ops.acquire(hw);
1213 if (ret_val)
1214 goto out;
1215 ret_val = hw->phy.ops.read_reg_locked(hw,
1216 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1217 &phy_data);
1218 if (ret_val)
1219 goto release;
1220 ret_val = hw->phy.ops.write_reg_locked(hw,
1221 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1222 phy_data & 0x00FF);
1223 release:
1224 hw->phy.ops.release(hw);
1225 out:
1226 return ret_val;
1227 }
1228
1229 /**
1230 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1231 * @hw: pointer to the HW structure
1232 *
1233 * Check the appropriate indication the MAC has finished configuring the
1234 * PHY after a software reset.
1235 **/
1236 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1237 {
1238 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1239
1240 /* Wait for basic configuration completes before proceeding */
1241 do {
1242 data = er32(STATUS);
1243 data &= E1000_STATUS_LAN_INIT_DONE;
1244 udelay(100);
1245 } while ((!data) && --loop);
1246
1247 /*
1248 * If basic configuration is incomplete before the above loop
1249 * count reaches 0, loading the configuration from NVM will
1250 * leave the PHY in a bad state possibly resulting in no link.
1251 */
1252 if (loop == 0)
1253 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1254
1255 /* Clear the Init Done bit for the next init event */
1256 data = er32(STATUS);
1257 data &= ~E1000_STATUS_LAN_INIT_DONE;
1258 ew32(STATUS, data);
1259 }
1260
1261 /**
1262 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1263 * @hw: pointer to the HW structure
1264 *
1265 * Resets the PHY
1266 * This is a function pointer entry point called by drivers
1267 * or other shared routines.
1268 **/
1269 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1270 {
1271 s32 ret_val = 0;
1272 u16 reg;
1273
1274 ret_val = e1000e_phy_hw_reset_generic(hw);
1275 if (ret_val)
1276 return ret_val;
1277
1278 /* Allow time for h/w to get to a quiescent state after reset */
1279 mdelay(10);
1280
1281 /* Perform any necessary post-reset workarounds */
1282 if (hw->mac.type == e1000_pchlan) {
1283 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1284 if (ret_val)
1285 return ret_val;
1286 }
1287
1288 /* Dummy read to clear the phy wakeup bit after lcd reset */
1289 if (hw->mac.type == e1000_pchlan)
1290 e1e_rphy(hw, BM_WUC, &reg);
1291
1292 /* Configure the LCD with the extended configuration region in NVM */
1293 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1294 if (ret_val)
1295 goto out;
1296
1297 /* Configure the LCD with the OEM bits in NVM */
1298 if (hw->mac.type == e1000_pchlan)
1299 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1300
1301 out:
1302 return 0;
1303 }
1304
1305 /**
1306 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1307 * @hw: pointer to the HW structure
1308 * @active: true to enable LPLU, false to disable
1309 *
1310 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1311 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1312 * the phy speed. This function will manually set the LPLU bit and restart
1313 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1314 * since it configures the same bit.
1315 **/
1316 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1317 {
1318 s32 ret_val = 0;
1319 u16 oem_reg;
1320
1321 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1322 if (ret_val)
1323 goto out;
1324
1325 if (active)
1326 oem_reg |= HV_OEM_BITS_LPLU;
1327 else
1328 oem_reg &= ~HV_OEM_BITS_LPLU;
1329
1330 oem_reg |= HV_OEM_BITS_RESTART_AN;
1331 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1332
1333 out:
1334 return ret_val;
1335 }
1336
1337 /**
1338 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1339 * @hw: pointer to the HW structure
1340 * @active: true to enable LPLU, false to disable
1341 *
1342 * Sets the LPLU D0 state according to the active flag. When
1343 * activating LPLU this function also disables smart speed
1344 * and vice versa. LPLU will not be activated unless the
1345 * device autonegotiation advertisement meets standards of
1346 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1347 * This is a function pointer entry point only called by
1348 * PHY setup routines.
1349 **/
1350 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1351 {
1352 struct e1000_phy_info *phy = &hw->phy;
1353 u32 phy_ctrl;
1354 s32 ret_val = 0;
1355 u16 data;
1356
1357 if (phy->type == e1000_phy_ife)
1358 return ret_val;
1359
1360 phy_ctrl = er32(PHY_CTRL);
1361
1362 if (active) {
1363 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1364 ew32(PHY_CTRL, phy_ctrl);
1365
1366 if (phy->type != e1000_phy_igp_3)
1367 return 0;
1368
1369 /*
1370 * Call gig speed drop workaround on LPLU before accessing
1371 * any PHY registers
1372 */
1373 if (hw->mac.type == e1000_ich8lan)
1374 e1000e_gig_downshift_workaround_ich8lan(hw);
1375
1376 /* When LPLU is enabled, we should disable SmartSpeed */
1377 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1378 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1379 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1380 if (ret_val)
1381 return ret_val;
1382 } else {
1383 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1384 ew32(PHY_CTRL, phy_ctrl);
1385
1386 if (phy->type != e1000_phy_igp_3)
1387 return 0;
1388
1389 /*
1390 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1391 * during Dx states where the power conservation is most
1392 * important. During driver activity we should enable
1393 * SmartSpeed, so performance is maintained.
1394 */
1395 if (phy->smart_speed == e1000_smart_speed_on) {
1396 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1397 &data);
1398 if (ret_val)
1399 return ret_val;
1400
1401 data |= IGP01E1000_PSCFR_SMART_SPEED;
1402 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1403 data);
1404 if (ret_val)
1405 return ret_val;
1406 } else if (phy->smart_speed == e1000_smart_speed_off) {
1407 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1408 &data);
1409 if (ret_val)
1410 return ret_val;
1411
1412 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1413 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1414 data);
1415 if (ret_val)
1416 return ret_val;
1417 }
1418 }
1419
1420 return 0;
1421 }
1422
1423 /**
1424 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1425 * @hw: pointer to the HW structure
1426 * @active: true to enable LPLU, false to disable
1427 *
1428 * Sets the LPLU D3 state according to the active flag. When
1429 * activating LPLU this function also disables smart speed
1430 * and vice versa. LPLU will not be activated unless the
1431 * device autonegotiation advertisement meets standards of
1432 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1433 * This is a function pointer entry point only called by
1434 * PHY setup routines.
1435 **/
1436 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1437 {
1438 struct e1000_phy_info *phy = &hw->phy;
1439 u32 phy_ctrl;
1440 s32 ret_val;
1441 u16 data;
1442
1443 phy_ctrl = er32(PHY_CTRL);
1444
1445 if (!active) {
1446 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1447 ew32(PHY_CTRL, phy_ctrl);
1448
1449 if (phy->type != e1000_phy_igp_3)
1450 return 0;
1451
1452 /*
1453 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1454 * during Dx states where the power conservation is most
1455 * important. During driver activity we should enable
1456 * SmartSpeed, so performance is maintained.
1457 */
1458 if (phy->smart_speed == e1000_smart_speed_on) {
1459 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1460 &data);
1461 if (ret_val)
1462 return ret_val;
1463
1464 data |= IGP01E1000_PSCFR_SMART_SPEED;
1465 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1466 data);
1467 if (ret_val)
1468 return ret_val;
1469 } else if (phy->smart_speed == e1000_smart_speed_off) {
1470 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1471 &data);
1472 if (ret_val)
1473 return ret_val;
1474
1475 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1476 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1477 data);
1478 if (ret_val)
1479 return ret_val;
1480 }
1481 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1482 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1483 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1484 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1485 ew32(PHY_CTRL, phy_ctrl);
1486
1487 if (phy->type != e1000_phy_igp_3)
1488 return 0;
1489
1490 /*
1491 * Call gig speed drop workaround on LPLU before accessing
1492 * any PHY registers
1493 */
1494 if (hw->mac.type == e1000_ich8lan)
1495 e1000e_gig_downshift_workaround_ich8lan(hw);
1496
1497 /* When LPLU is enabled, we should disable SmartSpeed */
1498 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1499 if (ret_val)
1500 return ret_val;
1501
1502 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1503 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1504 }
1505
1506 return 0;
1507 }
1508
1509 /**
1510 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1511 * @hw: pointer to the HW structure
1512 * @bank: pointer to the variable that returns the active bank
1513 *
1514 * Reads signature byte from the NVM using the flash access registers.
1515 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1516 **/
1517 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1518 {
1519 u32 eecd;
1520 struct e1000_nvm_info *nvm = &hw->nvm;
1521 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1522 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1523 u8 sig_byte = 0;
1524 s32 ret_val = 0;
1525
1526 switch (hw->mac.type) {
1527 case e1000_ich8lan:
1528 case e1000_ich9lan:
1529 eecd = er32(EECD);
1530 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1531 E1000_EECD_SEC1VAL_VALID_MASK) {
1532 if (eecd & E1000_EECD_SEC1VAL)
1533 *bank = 1;
1534 else
1535 *bank = 0;
1536
1537 return 0;
1538 }
1539 e_dbg("Unable to determine valid NVM bank via EEC - "
1540 "reading flash signature\n");
1541 /* fall-thru */
1542 default:
1543 /* set bank to 0 in case flash read fails */
1544 *bank = 0;
1545
1546 /* Check bank 0 */
1547 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1548 &sig_byte);
1549 if (ret_val)
1550 return ret_val;
1551 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1552 E1000_ICH_NVM_SIG_VALUE) {
1553 *bank = 0;
1554 return 0;
1555 }
1556
1557 /* Check bank 1 */
1558 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1559 bank1_offset,
1560 &sig_byte);
1561 if (ret_val)
1562 return ret_val;
1563 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1564 E1000_ICH_NVM_SIG_VALUE) {
1565 *bank = 1;
1566 return 0;
1567 }
1568
1569 e_dbg("ERROR: No valid NVM bank present\n");
1570 return -E1000_ERR_NVM;
1571 }
1572
1573 return 0;
1574 }
1575
1576 /**
1577 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1578 * @hw: pointer to the HW structure
1579 * @offset: The offset (in bytes) of the word(s) to read.
1580 * @words: Size of data to read in words
1581 * @data: Pointer to the word(s) to read at offset.
1582 *
1583 * Reads a word(s) from the NVM using the flash access registers.
1584 **/
1585 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1586 u16 *data)
1587 {
1588 struct e1000_nvm_info *nvm = &hw->nvm;
1589 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1590 u32 act_offset;
1591 s32 ret_val = 0;
1592 u32 bank = 0;
1593 u16 i, word;
1594
1595 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1596 (words == 0)) {
1597 e_dbg("nvm parameter(s) out of bounds\n");
1598 ret_val = -E1000_ERR_NVM;
1599 goto out;
1600 }
1601
1602 nvm->ops.acquire(hw);
1603
1604 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1605 if (ret_val) {
1606 e_dbg("Could not detect valid bank, assuming bank 0\n");
1607 bank = 0;
1608 }
1609
1610 act_offset = (bank) ? nvm->flash_bank_size : 0;
1611 act_offset += offset;
1612
1613 ret_val = 0;
1614 for (i = 0; i < words; i++) {
1615 if ((dev_spec->shadow_ram) &&
1616 (dev_spec->shadow_ram[offset+i].modified)) {
1617 data[i] = dev_spec->shadow_ram[offset+i].value;
1618 } else {
1619 ret_val = e1000_read_flash_word_ich8lan(hw,
1620 act_offset + i,
1621 &word);
1622 if (ret_val)
1623 break;
1624 data[i] = word;
1625 }
1626 }
1627
1628 nvm->ops.release(hw);
1629
1630 out:
1631 if (ret_val)
1632 e_dbg("NVM read error: %d\n", ret_val);
1633
1634 return ret_val;
1635 }
1636
1637 /**
1638 * e1000_flash_cycle_init_ich8lan - Initialize flash
1639 * @hw: pointer to the HW structure
1640 *
1641 * This function does initial flash setup so that a new read/write/erase cycle
1642 * can be started.
1643 **/
1644 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1645 {
1646 union ich8_hws_flash_status hsfsts;
1647 s32 ret_val = -E1000_ERR_NVM;
1648 s32 i = 0;
1649
1650 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1651
1652 /* Check if the flash descriptor is valid */
1653 if (hsfsts.hsf_status.fldesvalid == 0) {
1654 e_dbg("Flash descriptor invalid. "
1655 "SW Sequencing must be used.\n");
1656 return -E1000_ERR_NVM;
1657 }
1658
1659 /* Clear FCERR and DAEL in hw status by writing 1 */
1660 hsfsts.hsf_status.flcerr = 1;
1661 hsfsts.hsf_status.dael = 1;
1662
1663 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1664
1665 /*
1666 * Either we should have a hardware SPI cycle in progress
1667 * bit to check against, in order to start a new cycle or
1668 * FDONE bit should be changed in the hardware so that it
1669 * is 1 after hardware reset, which can then be used as an
1670 * indication whether a cycle is in progress or has been
1671 * completed.
1672 */
1673
1674 if (hsfsts.hsf_status.flcinprog == 0) {
1675 /*
1676 * There is no cycle running at present,
1677 * so we can start a cycle.
1678 * Begin by setting Flash Cycle Done.
1679 */
1680 hsfsts.hsf_status.flcdone = 1;
1681 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1682 ret_val = 0;
1683 } else {
1684 /*
1685 * Otherwise poll for sometime so the current
1686 * cycle has a chance to end before giving up.
1687 */
1688 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1689 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1690 if (hsfsts.hsf_status.flcinprog == 0) {
1691 ret_val = 0;
1692 break;
1693 }
1694 udelay(1);
1695 }
1696 if (ret_val == 0) {
1697 /*
1698 * Successful in waiting for previous cycle to timeout,
1699 * now set the Flash Cycle Done.
1700 */
1701 hsfsts.hsf_status.flcdone = 1;
1702 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1703 } else {
1704 e_dbg("Flash controller busy, cannot get access\n");
1705 }
1706 }
1707
1708 return ret_val;
1709 }
1710
1711 /**
1712 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1713 * @hw: pointer to the HW structure
1714 * @timeout: maximum time to wait for completion
1715 *
1716 * This function starts a flash cycle and waits for its completion.
1717 **/
1718 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1719 {
1720 union ich8_hws_flash_ctrl hsflctl;
1721 union ich8_hws_flash_status hsfsts;
1722 s32 ret_val = -E1000_ERR_NVM;
1723 u32 i = 0;
1724
1725 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1726 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1727 hsflctl.hsf_ctrl.flcgo = 1;
1728 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1729
1730 /* wait till FDONE bit is set to 1 */
1731 do {
1732 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1733 if (hsfsts.hsf_status.flcdone == 1)
1734 break;
1735 udelay(1);
1736 } while (i++ < timeout);
1737
1738 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1739 return 0;
1740
1741 return ret_val;
1742 }
1743
1744 /**
1745 * e1000_read_flash_word_ich8lan - Read word from flash
1746 * @hw: pointer to the HW structure
1747 * @offset: offset to data location
1748 * @data: pointer to the location for storing the data
1749 *
1750 * Reads the flash word at offset into data. Offset is converted
1751 * to bytes before read.
1752 **/
1753 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1754 u16 *data)
1755 {
1756 /* Must convert offset into bytes. */
1757 offset <<= 1;
1758
1759 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1760 }
1761
1762 /**
1763 * e1000_read_flash_byte_ich8lan - Read byte from flash
1764 * @hw: pointer to the HW structure
1765 * @offset: The offset of the byte to read.
1766 * @data: Pointer to a byte to store the value read.
1767 *
1768 * Reads a single byte from the NVM using the flash access registers.
1769 **/
1770 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1771 u8 *data)
1772 {
1773 s32 ret_val;
1774 u16 word = 0;
1775
1776 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1777 if (ret_val)
1778 return ret_val;
1779
1780 *data = (u8)word;
1781
1782 return 0;
1783 }
1784
1785 /**
1786 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1787 * @hw: pointer to the HW structure
1788 * @offset: The offset (in bytes) of the byte or word to read.
1789 * @size: Size of data to read, 1=byte 2=word
1790 * @data: Pointer to the word to store the value read.
1791 *
1792 * Reads a byte or word from the NVM using the flash access registers.
1793 **/
1794 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1795 u8 size, u16 *data)
1796 {
1797 union ich8_hws_flash_status hsfsts;
1798 union ich8_hws_flash_ctrl hsflctl;
1799 u32 flash_linear_addr;
1800 u32 flash_data = 0;
1801 s32 ret_val = -E1000_ERR_NVM;
1802 u8 count = 0;
1803
1804 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1805 return -E1000_ERR_NVM;
1806
1807 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1808 hw->nvm.flash_base_addr;
1809
1810 do {
1811 udelay(1);
1812 /* Steps */
1813 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1814 if (ret_val != 0)
1815 break;
1816
1817 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1818 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1819 hsflctl.hsf_ctrl.fldbcount = size - 1;
1820 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1821 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1822
1823 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1824
1825 ret_val = e1000_flash_cycle_ich8lan(hw,
1826 ICH_FLASH_READ_COMMAND_TIMEOUT);
1827
1828 /*
1829 * Check if FCERR is set to 1, if set to 1, clear it
1830 * and try the whole sequence a few more times, else
1831 * read in (shift in) the Flash Data0, the order is
1832 * least significant byte first msb to lsb
1833 */
1834 if (ret_val == 0) {
1835 flash_data = er32flash(ICH_FLASH_FDATA0);
1836 if (size == 1) {
1837 *data = (u8)(flash_data & 0x000000FF);
1838 } else if (size == 2) {
1839 *data = (u16)(flash_data & 0x0000FFFF);
1840 }
1841 break;
1842 } else {
1843 /*
1844 * If we've gotten here, then things are probably
1845 * completely hosed, but if the error condition is
1846 * detected, it won't hurt to give it another try...
1847 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1848 */
1849 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1850 if (hsfsts.hsf_status.flcerr == 1) {
1851 /* Repeat for some time before giving up. */
1852 continue;
1853 } else if (hsfsts.hsf_status.flcdone == 0) {
1854 e_dbg("Timeout error - flash cycle "
1855 "did not complete.\n");
1856 break;
1857 }
1858 }
1859 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1860
1861 return ret_val;
1862 }
1863
1864 /**
1865 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1866 * @hw: pointer to the HW structure
1867 * @offset: The offset (in bytes) of the word(s) to write.
1868 * @words: Size of data to write in words
1869 * @data: Pointer to the word(s) to write at offset.
1870 *
1871 * Writes a byte or word to the NVM using the flash access registers.
1872 **/
1873 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1874 u16 *data)
1875 {
1876 struct e1000_nvm_info *nvm = &hw->nvm;
1877 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1878 u16 i;
1879
1880 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1881 (words == 0)) {
1882 e_dbg("nvm parameter(s) out of bounds\n");
1883 return -E1000_ERR_NVM;
1884 }
1885
1886 nvm->ops.acquire(hw);
1887
1888 for (i = 0; i < words; i++) {
1889 dev_spec->shadow_ram[offset+i].modified = true;
1890 dev_spec->shadow_ram[offset+i].value = data[i];
1891 }
1892
1893 nvm->ops.release(hw);
1894
1895 return 0;
1896 }
1897
1898 /**
1899 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1900 * @hw: pointer to the HW structure
1901 *
1902 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1903 * which writes the checksum to the shadow ram. The changes in the shadow
1904 * ram are then committed to the EEPROM by processing each bank at a time
1905 * checking for the modified bit and writing only the pending changes.
1906 * After a successful commit, the shadow ram is cleared and is ready for
1907 * future writes.
1908 **/
1909 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1910 {
1911 struct e1000_nvm_info *nvm = &hw->nvm;
1912 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1913 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1914 s32 ret_val;
1915 u16 data;
1916
1917 ret_val = e1000e_update_nvm_checksum_generic(hw);
1918 if (ret_val)
1919 goto out;
1920
1921 if (nvm->type != e1000_nvm_flash_sw)
1922 goto out;
1923
1924 nvm->ops.acquire(hw);
1925
1926 /*
1927 * We're writing to the opposite bank so if we're on bank 1,
1928 * write to bank 0 etc. We also need to erase the segment that
1929 * is going to be written
1930 */
1931 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1932 if (ret_val) {
1933 e_dbg("Could not detect valid bank, assuming bank 0\n");
1934 bank = 0;
1935 }
1936
1937 if (bank == 0) {
1938 new_bank_offset = nvm->flash_bank_size;
1939 old_bank_offset = 0;
1940 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1941 if (ret_val) {
1942 nvm->ops.release(hw);
1943 goto out;
1944 }
1945 } else {
1946 old_bank_offset = nvm->flash_bank_size;
1947 new_bank_offset = 0;
1948 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1949 if (ret_val) {
1950 nvm->ops.release(hw);
1951 goto out;
1952 }
1953 }
1954
1955 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1956 /*
1957 * Determine whether to write the value stored
1958 * in the other NVM bank or a modified value stored
1959 * in the shadow RAM
1960 */
1961 if (dev_spec->shadow_ram[i].modified) {
1962 data = dev_spec->shadow_ram[i].value;
1963 } else {
1964 ret_val = e1000_read_flash_word_ich8lan(hw, i +
1965 old_bank_offset,
1966 &data);
1967 if (ret_val)
1968 break;
1969 }
1970
1971 /*
1972 * If the word is 0x13, then make sure the signature bits
1973 * (15:14) are 11b until the commit has completed.
1974 * This will allow us to write 10b which indicates the
1975 * signature is valid. We want to do this after the write
1976 * has completed so that we don't mark the segment valid
1977 * while the write is still in progress
1978 */
1979 if (i == E1000_ICH_NVM_SIG_WORD)
1980 data |= E1000_ICH_NVM_SIG_MASK;
1981
1982 /* Convert offset to bytes. */
1983 act_offset = (i + new_bank_offset) << 1;
1984
1985 udelay(100);
1986 /* Write the bytes to the new bank. */
1987 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1988 act_offset,
1989 (u8)data);
1990 if (ret_val)
1991 break;
1992
1993 udelay(100);
1994 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1995 act_offset + 1,
1996 (u8)(data >> 8));
1997 if (ret_val)
1998 break;
1999 }
2000
2001 /*
2002 * Don't bother writing the segment valid bits if sector
2003 * programming failed.
2004 */
2005 if (ret_val) {
2006 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2007 e_dbg("Flash commit failed.\n");
2008 nvm->ops.release(hw);
2009 goto out;
2010 }
2011
2012 /*
2013 * Finally validate the new segment by setting bit 15:14
2014 * to 10b in word 0x13 , this can be done without an
2015 * erase as well since these bits are 11 to start with
2016 * and we need to change bit 14 to 0b
2017 */
2018 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2019 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2020 if (ret_val) {
2021 nvm->ops.release(hw);
2022 goto out;
2023 }
2024 data &= 0xBFFF;
2025 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2026 act_offset * 2 + 1,
2027 (u8)(data >> 8));
2028 if (ret_val) {
2029 nvm->ops.release(hw);
2030 goto out;
2031 }
2032
2033 /*
2034 * And invalidate the previously valid segment by setting
2035 * its signature word (0x13) high_byte to 0b. This can be
2036 * done without an erase because flash erase sets all bits
2037 * to 1's. We can write 1's to 0's without an erase
2038 */
2039 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2040 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2041 if (ret_val) {
2042 nvm->ops.release(hw);
2043 goto out;
2044 }
2045
2046 /* Great! Everything worked, we can now clear the cached entries. */
2047 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2048 dev_spec->shadow_ram[i].modified = false;
2049 dev_spec->shadow_ram[i].value = 0xFFFF;
2050 }
2051
2052 nvm->ops.release(hw);
2053
2054 /*
2055 * Reload the EEPROM, or else modifications will not appear
2056 * until after the next adapter reset.
2057 */
2058 e1000e_reload_nvm(hw);
2059 msleep(10);
2060
2061 out:
2062 if (ret_val)
2063 e_dbg("NVM update error: %d\n", ret_val);
2064
2065 return ret_val;
2066 }
2067
2068 /**
2069 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2070 * @hw: pointer to the HW structure
2071 *
2072 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2073 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2074 * calculated, in which case we need to calculate the checksum and set bit 6.
2075 **/
2076 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2077 {
2078 s32 ret_val;
2079 u16 data;
2080
2081 /*
2082 * Read 0x19 and check bit 6. If this bit is 0, the checksum
2083 * needs to be fixed. This bit is an indication that the NVM
2084 * was prepared by OEM software and did not calculate the
2085 * checksum...a likely scenario.
2086 */
2087 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2088 if (ret_val)
2089 return ret_val;
2090
2091 if ((data & 0x40) == 0) {
2092 data |= 0x40;
2093 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2094 if (ret_val)
2095 return ret_val;
2096 ret_val = e1000e_update_nvm_checksum(hw);
2097 if (ret_val)
2098 return ret_val;
2099 }
2100
2101 return e1000e_validate_nvm_checksum_generic(hw);
2102 }
2103
2104 /**
2105 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2106 * @hw: pointer to the HW structure
2107 *
2108 * To prevent malicious write/erase of the NVM, set it to be read-only
2109 * so that the hardware ignores all write/erase cycles of the NVM via
2110 * the flash control registers. The shadow-ram copy of the NVM will
2111 * still be updated, however any updates to this copy will not stick
2112 * across driver reloads.
2113 **/
2114 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2115 {
2116 struct e1000_nvm_info *nvm = &hw->nvm;
2117 union ich8_flash_protected_range pr0;
2118 union ich8_hws_flash_status hsfsts;
2119 u32 gfpreg;
2120
2121 nvm->ops.acquire(hw);
2122
2123 gfpreg = er32flash(ICH_FLASH_GFPREG);
2124
2125 /* Write-protect GbE Sector of NVM */
2126 pr0.regval = er32flash(ICH_FLASH_PR0);
2127 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2128 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2129 pr0.range.wpe = true;
2130 ew32flash(ICH_FLASH_PR0, pr0.regval);
2131
2132 /*
2133 * Lock down a subset of GbE Flash Control Registers, e.g.
2134 * PR0 to prevent the write-protection from being lifted.
2135 * Once FLOCKDN is set, the registers protected by it cannot
2136 * be written until FLOCKDN is cleared by a hardware reset.
2137 */
2138 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2139 hsfsts.hsf_status.flockdn = true;
2140 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2141
2142 nvm->ops.release(hw);
2143 }
2144
2145 /**
2146 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2147 * @hw: pointer to the HW structure
2148 * @offset: The offset (in bytes) of the byte/word to read.
2149 * @size: Size of data to read, 1=byte 2=word
2150 * @data: The byte(s) to write to the NVM.
2151 *
2152 * Writes one/two bytes to the NVM using the flash access registers.
2153 **/
2154 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2155 u8 size, u16 data)
2156 {
2157 union ich8_hws_flash_status hsfsts;
2158 union ich8_hws_flash_ctrl hsflctl;
2159 u32 flash_linear_addr;
2160 u32 flash_data = 0;
2161 s32 ret_val;
2162 u8 count = 0;
2163
2164 if (size < 1 || size > 2 || data > size * 0xff ||
2165 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2166 return -E1000_ERR_NVM;
2167
2168 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2169 hw->nvm.flash_base_addr;
2170
2171 do {
2172 udelay(1);
2173 /* Steps */
2174 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2175 if (ret_val)
2176 break;
2177
2178 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2179 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2180 hsflctl.hsf_ctrl.fldbcount = size -1;
2181 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2182 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2183
2184 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2185
2186 if (size == 1)
2187 flash_data = (u32)data & 0x00FF;
2188 else
2189 flash_data = (u32)data;
2190
2191 ew32flash(ICH_FLASH_FDATA0, flash_data);
2192
2193 /*
2194 * check if FCERR is set to 1 , if set to 1, clear it
2195 * and try the whole sequence a few more times else done
2196 */
2197 ret_val = e1000_flash_cycle_ich8lan(hw,
2198 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2199 if (!ret_val)
2200 break;
2201
2202 /*
2203 * If we're here, then things are most likely
2204 * completely hosed, but if the error condition
2205 * is detected, it won't hurt to give it another
2206 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2207 */
2208 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2209 if (hsfsts.hsf_status.flcerr == 1)
2210 /* Repeat for some time before giving up. */
2211 continue;
2212 if (hsfsts.hsf_status.flcdone == 0) {
2213 e_dbg("Timeout error - flash cycle "
2214 "did not complete.");
2215 break;
2216 }
2217 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2218
2219 return ret_val;
2220 }
2221
2222 /**
2223 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2224 * @hw: pointer to the HW structure
2225 * @offset: The index of the byte to read.
2226 * @data: The byte to write to the NVM.
2227 *
2228 * Writes a single byte to the NVM using the flash access registers.
2229 **/
2230 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2231 u8 data)
2232 {
2233 u16 word = (u16)data;
2234
2235 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2236 }
2237
2238 /**
2239 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2240 * @hw: pointer to the HW structure
2241 * @offset: The offset of the byte to write.
2242 * @byte: The byte to write to the NVM.
2243 *
2244 * Writes a single byte to the NVM using the flash access registers.
2245 * Goes through a retry algorithm before giving up.
2246 **/
2247 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2248 u32 offset, u8 byte)
2249 {
2250 s32 ret_val;
2251 u16 program_retries;
2252
2253 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2254 if (!ret_val)
2255 return ret_val;
2256
2257 for (program_retries = 0; program_retries < 100; program_retries++) {
2258 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2259 udelay(100);
2260 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2261 if (!ret_val)
2262 break;
2263 }
2264 if (program_retries == 100)
2265 return -E1000_ERR_NVM;
2266
2267 return 0;
2268 }
2269
2270 /**
2271 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2272 * @hw: pointer to the HW structure
2273 * @bank: 0 for first bank, 1 for second bank, etc.
2274 *
2275 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2276 * bank N is 4096 * N + flash_reg_addr.
2277 **/
2278 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2279 {
2280 struct e1000_nvm_info *nvm = &hw->nvm;
2281 union ich8_hws_flash_status hsfsts;
2282 union ich8_hws_flash_ctrl hsflctl;
2283 u32 flash_linear_addr;
2284 /* bank size is in 16bit words - adjust to bytes */
2285 u32 flash_bank_size = nvm->flash_bank_size * 2;
2286 s32 ret_val;
2287 s32 count = 0;
2288 s32 j, iteration, sector_size;
2289
2290 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2291
2292 /*
2293 * Determine HW Sector size: Read BERASE bits of hw flash status
2294 * register
2295 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2296 * consecutive sectors. The start index for the nth Hw sector
2297 * can be calculated as = bank * 4096 + n * 256
2298 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2299 * The start index for the nth Hw sector can be calculated
2300 * as = bank * 4096
2301 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2302 * (ich9 only, otherwise error condition)
2303 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2304 */
2305 switch (hsfsts.hsf_status.berasesz) {
2306 case 0:
2307 /* Hw sector size 256 */
2308 sector_size = ICH_FLASH_SEG_SIZE_256;
2309 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2310 break;
2311 case 1:
2312 sector_size = ICH_FLASH_SEG_SIZE_4K;
2313 iteration = 1;
2314 break;
2315 case 2:
2316 sector_size = ICH_FLASH_SEG_SIZE_8K;
2317 iteration = 1;
2318 break;
2319 case 3:
2320 sector_size = ICH_FLASH_SEG_SIZE_64K;
2321 iteration = 1;
2322 break;
2323 default:
2324 return -E1000_ERR_NVM;
2325 }
2326
2327 /* Start with the base address, then add the sector offset. */
2328 flash_linear_addr = hw->nvm.flash_base_addr;
2329 flash_linear_addr += (bank) ? flash_bank_size : 0;
2330
2331 for (j = 0; j < iteration ; j++) {
2332 do {
2333 /* Steps */
2334 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2335 if (ret_val)
2336 return ret_val;
2337
2338 /*
2339 * Write a value 11 (block Erase) in Flash
2340 * Cycle field in hw flash control
2341 */
2342 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2343 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2344 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2345
2346 /*
2347 * Write the last 24 bits of an index within the
2348 * block into Flash Linear address field in Flash
2349 * Address.
2350 */
2351 flash_linear_addr += (j * sector_size);
2352 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2353
2354 ret_val = e1000_flash_cycle_ich8lan(hw,
2355 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2356 if (ret_val == 0)
2357 break;
2358
2359 /*
2360 * Check if FCERR is set to 1. If 1,
2361 * clear it and try the whole sequence
2362 * a few more times else Done
2363 */
2364 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2365 if (hsfsts.hsf_status.flcerr == 1)
2366 /* repeat for some time before giving up */
2367 continue;
2368 else if (hsfsts.hsf_status.flcdone == 0)
2369 return ret_val;
2370 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2371 }
2372
2373 return 0;
2374 }
2375
2376 /**
2377 * e1000_valid_led_default_ich8lan - Set the default LED settings
2378 * @hw: pointer to the HW structure
2379 * @data: Pointer to the LED settings
2380 *
2381 * Reads the LED default settings from the NVM to data. If the NVM LED
2382 * settings is all 0's or F's, set the LED default to a valid LED default
2383 * setting.
2384 **/
2385 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2386 {
2387 s32 ret_val;
2388
2389 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2390 if (ret_val) {
2391 e_dbg("NVM Read Error\n");
2392 return ret_val;
2393 }
2394
2395 if (*data == ID_LED_RESERVED_0000 ||
2396 *data == ID_LED_RESERVED_FFFF)
2397 *data = ID_LED_DEFAULT_ICH8LAN;
2398
2399 return 0;
2400 }
2401
2402 /**
2403 * e1000_id_led_init_pchlan - store LED configurations
2404 * @hw: pointer to the HW structure
2405 *
2406 * PCH does not control LEDs via the LEDCTL register, rather it uses
2407 * the PHY LED configuration register.
2408 *
2409 * PCH also does not have an "always on" or "always off" mode which
2410 * complicates the ID feature. Instead of using the "on" mode to indicate
2411 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2412 * use "link_up" mode. The LEDs will still ID on request if there is no
2413 * link based on logic in e1000_led_[on|off]_pchlan().
2414 **/
2415 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2416 {
2417 struct e1000_mac_info *mac = &hw->mac;
2418 s32 ret_val;
2419 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2420 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2421 u16 data, i, temp, shift;
2422
2423 /* Get default ID LED modes */
2424 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2425 if (ret_val)
2426 goto out;
2427
2428 mac->ledctl_default = er32(LEDCTL);
2429 mac->ledctl_mode1 = mac->ledctl_default;
2430 mac->ledctl_mode2 = mac->ledctl_default;
2431
2432 for (i = 0; i < 4; i++) {
2433 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2434 shift = (i * 5);
2435 switch (temp) {
2436 case ID_LED_ON1_DEF2:
2437 case ID_LED_ON1_ON2:
2438 case ID_LED_ON1_OFF2:
2439 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2440 mac->ledctl_mode1 |= (ledctl_on << shift);
2441 break;
2442 case ID_LED_OFF1_DEF2:
2443 case ID_LED_OFF1_ON2:
2444 case ID_LED_OFF1_OFF2:
2445 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2446 mac->ledctl_mode1 |= (ledctl_off << shift);
2447 break;
2448 default:
2449 /* Do nothing */
2450 break;
2451 }
2452 switch (temp) {
2453 case ID_LED_DEF1_ON2:
2454 case ID_LED_ON1_ON2:
2455 case ID_LED_OFF1_ON2:
2456 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2457 mac->ledctl_mode2 |= (ledctl_on << shift);
2458 break;
2459 case ID_LED_DEF1_OFF2:
2460 case ID_LED_ON1_OFF2:
2461 case ID_LED_OFF1_OFF2:
2462 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2463 mac->ledctl_mode2 |= (ledctl_off << shift);
2464 break;
2465 default:
2466 /* Do nothing */
2467 break;
2468 }
2469 }
2470
2471 out:
2472 return ret_val;
2473 }
2474
2475 /**
2476 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2477 * @hw: pointer to the HW structure
2478 *
2479 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2480 * register, so the the bus width is hard coded.
2481 **/
2482 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2483 {
2484 struct e1000_bus_info *bus = &hw->bus;
2485 s32 ret_val;
2486
2487 ret_val = e1000e_get_bus_info_pcie(hw);
2488
2489 /*
2490 * ICH devices are "PCI Express"-ish. They have
2491 * a configuration space, but do not contain
2492 * PCI Express Capability registers, so bus width
2493 * must be hardcoded.
2494 */
2495 if (bus->width == e1000_bus_width_unknown)
2496 bus->width = e1000_bus_width_pcie_x1;
2497
2498 return ret_val;
2499 }
2500
2501 /**
2502 * e1000_reset_hw_ich8lan - Reset the hardware
2503 * @hw: pointer to the HW structure
2504 *
2505 * Does a full reset of the hardware which includes a reset of the PHY and
2506 * MAC.
2507 **/
2508 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2509 {
2510 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2511 u16 reg;
2512 u32 ctrl, icr, kab;
2513 s32 ret_val;
2514
2515 /*
2516 * Prevent the PCI-E bus from sticking if there is no TLP connection
2517 * on the last TLP read/write transaction when MAC is reset.
2518 */
2519 ret_val = e1000e_disable_pcie_master(hw);
2520 if (ret_val) {
2521 e_dbg("PCI-E Master disable polling has failed.\n");
2522 }
2523
2524 e_dbg("Masking off all interrupts\n");
2525 ew32(IMC, 0xffffffff);
2526
2527 /*
2528 * Disable the Transmit and Receive units. Then delay to allow
2529 * any pending transactions to complete before we hit the MAC
2530 * with the global reset.
2531 */
2532 ew32(RCTL, 0);
2533 ew32(TCTL, E1000_TCTL_PSP);
2534 e1e_flush();
2535
2536 msleep(10);
2537
2538 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2539 if (hw->mac.type == e1000_ich8lan) {
2540 /* Set Tx and Rx buffer allocation to 8k apiece. */
2541 ew32(PBA, E1000_PBA_8K);
2542 /* Set Packet Buffer Size to 16k. */
2543 ew32(PBS, E1000_PBS_16K);
2544 }
2545
2546 if (hw->mac.type == e1000_pchlan) {
2547 /* Save the NVM K1 bit setting*/
2548 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2549 if (ret_val)
2550 return ret_val;
2551
2552 if (reg & E1000_NVM_K1_ENABLE)
2553 dev_spec->nvm_k1_enabled = true;
2554 else
2555 dev_spec->nvm_k1_enabled = false;
2556 }
2557
2558 ctrl = er32(CTRL);
2559
2560 if (!e1000_check_reset_block(hw)) {
2561 /* Clear PHY Reset Asserted bit */
2562 if (hw->mac.type >= e1000_pchlan) {
2563 u32 status = er32(STATUS);
2564 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2565 }
2566
2567 /*
2568 * PHY HW reset requires MAC CORE reset at the same
2569 * time to make sure the interface between MAC and the
2570 * external PHY is reset.
2571 */
2572 ctrl |= E1000_CTRL_PHY_RST;
2573 }
2574 ret_val = e1000_acquire_swflag_ich8lan(hw);
2575 e_dbg("Issuing a global reset to ich8lan\n");
2576 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2577 msleep(20);
2578
2579 if (!ret_val)
2580 e1000_release_swflag_ich8lan(hw);
2581
2582 /* Perform any necessary post-reset workarounds */
2583 if (hw->mac.type == e1000_pchlan)
2584 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2585
2586 if (ctrl & E1000_CTRL_PHY_RST)
2587 ret_val = hw->phy.ops.get_cfg_done(hw);
2588
2589 if (hw->mac.type >= e1000_ich10lan) {
2590 e1000_lan_init_done_ich8lan(hw);
2591 } else {
2592 ret_val = e1000e_get_auto_rd_done(hw);
2593 if (ret_val) {
2594 /*
2595 * When auto config read does not complete, do not
2596 * return with an error. This can happen in situations
2597 * where there is no eeprom and prevents getting link.
2598 */
2599 e_dbg("Auto Read Done did not complete\n");
2600 }
2601 }
2602 /* Dummy read to clear the phy wakeup bit after lcd reset */
2603 if (hw->mac.type == e1000_pchlan)
2604 e1e_rphy(hw, BM_WUC, &reg);
2605
2606 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2607 if (ret_val)
2608 goto out;
2609
2610 if (hw->mac.type == e1000_pchlan) {
2611 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2612 if (ret_val)
2613 goto out;
2614 }
2615 /*
2616 * For PCH, this write will make sure that any noise
2617 * will be detected as a CRC error and be dropped rather than show up
2618 * as a bad packet to the DMA engine.
2619 */
2620 if (hw->mac.type == e1000_pchlan)
2621 ew32(CRC_OFFSET, 0x65656565);
2622
2623 ew32(IMC, 0xffffffff);
2624 icr = er32(ICR);
2625
2626 kab = er32(KABGTXD);
2627 kab |= E1000_KABGTXD_BGSQLBIAS;
2628 ew32(KABGTXD, kab);
2629
2630 out:
2631 return ret_val;
2632 }
2633
2634 /**
2635 * e1000_init_hw_ich8lan - Initialize the hardware
2636 * @hw: pointer to the HW structure
2637 *
2638 * Prepares the hardware for transmit and receive by doing the following:
2639 * - initialize hardware bits
2640 * - initialize LED identification
2641 * - setup receive address registers
2642 * - setup flow control
2643 * - setup transmit descriptors
2644 * - clear statistics
2645 **/
2646 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2647 {
2648 struct e1000_mac_info *mac = &hw->mac;
2649 u32 ctrl_ext, txdctl, snoop;
2650 s32 ret_val;
2651 u16 i;
2652
2653 e1000_initialize_hw_bits_ich8lan(hw);
2654
2655 /* Initialize identification LED */
2656 ret_val = mac->ops.id_led_init(hw);
2657 if (ret_val)
2658 e_dbg("Error initializing identification LED\n");
2659 /* This is not fatal and we should not stop init due to this */
2660
2661 /* Setup the receive address. */
2662 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2663
2664 /* Zero out the Multicast HASH table */
2665 e_dbg("Zeroing the MTA\n");
2666 for (i = 0; i < mac->mta_reg_count; i++)
2667 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2668
2669 /*
2670 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2671 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2672 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2673 */
2674 if (hw->phy.type == e1000_phy_82578) {
2675 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2676 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2677 if (ret_val)
2678 return ret_val;
2679 }
2680
2681 /* Setup link and flow control */
2682 ret_val = e1000_setup_link_ich8lan(hw);
2683
2684 /* Set the transmit descriptor write-back policy for both queues */
2685 txdctl = er32(TXDCTL(0));
2686 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2687 E1000_TXDCTL_FULL_TX_DESC_WB;
2688 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2689 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2690 ew32(TXDCTL(0), txdctl);
2691 txdctl = er32(TXDCTL(1));
2692 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2693 E1000_TXDCTL_FULL_TX_DESC_WB;
2694 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2695 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2696 ew32(TXDCTL(1), txdctl);
2697
2698 /*
2699 * ICH8 has opposite polarity of no_snoop bits.
2700 * By default, we should use snoop behavior.
2701 */
2702 if (mac->type == e1000_ich8lan)
2703 snoop = PCIE_ICH8_SNOOP_ALL;
2704 else
2705 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2706 e1000e_set_pcie_no_snoop(hw, snoop);
2707
2708 ctrl_ext = er32(CTRL_EXT);
2709 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2710 ew32(CTRL_EXT, ctrl_ext);
2711
2712 /*
2713 * Clear all of the statistics registers (clear on read). It is
2714 * important that we do this after we have tried to establish link
2715 * because the symbol error count will increment wildly if there
2716 * is no link.
2717 */
2718 e1000_clear_hw_cntrs_ich8lan(hw);
2719
2720 return 0;
2721 }
2722 /**
2723 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2724 * @hw: pointer to the HW structure
2725 *
2726 * Sets/Clears required hardware bits necessary for correctly setting up the
2727 * hardware for transmit and receive.
2728 **/
2729 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2730 {
2731 u32 reg;
2732
2733 /* Extended Device Control */
2734 reg = er32(CTRL_EXT);
2735 reg |= (1 << 22);
2736 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2737 if (hw->mac.type >= e1000_pchlan)
2738 reg |= E1000_CTRL_EXT_PHYPDEN;
2739 ew32(CTRL_EXT, reg);
2740
2741 /* Transmit Descriptor Control 0 */
2742 reg = er32(TXDCTL(0));
2743 reg |= (1 << 22);
2744 ew32(TXDCTL(0), reg);
2745
2746 /* Transmit Descriptor Control 1 */
2747 reg = er32(TXDCTL(1));
2748 reg |= (1 << 22);
2749 ew32(TXDCTL(1), reg);
2750
2751 /* Transmit Arbitration Control 0 */
2752 reg = er32(TARC(0));
2753 if (hw->mac.type == e1000_ich8lan)
2754 reg |= (1 << 28) | (1 << 29);
2755 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2756 ew32(TARC(0), reg);
2757
2758 /* Transmit Arbitration Control 1 */
2759 reg = er32(TARC(1));
2760 if (er32(TCTL) & E1000_TCTL_MULR)
2761 reg &= ~(1 << 28);
2762 else
2763 reg |= (1 << 28);
2764 reg |= (1 << 24) | (1 << 26) | (1 << 30);
2765 ew32(TARC(1), reg);
2766
2767 /* Device Status */
2768 if (hw->mac.type == e1000_ich8lan) {
2769 reg = er32(STATUS);
2770 reg &= ~(1 << 31);
2771 ew32(STATUS, reg);
2772 }
2773
2774 /*
2775 * work-around descriptor data corruption issue during nfs v2 udp
2776 * traffic, just disable the nfs filtering capability
2777 */
2778 reg = er32(RFCTL);
2779 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
2780 ew32(RFCTL, reg);
2781
2782 return;
2783 }
2784
2785 /**
2786 * e1000_setup_link_ich8lan - Setup flow control and link settings
2787 * @hw: pointer to the HW structure
2788 *
2789 * Determines which flow control settings to use, then configures flow
2790 * control. Calls the appropriate media-specific link configuration
2791 * function. Assuming the adapter has a valid link partner, a valid link
2792 * should be established. Assumes the hardware has previously been reset
2793 * and the transmitter and receiver are not enabled.
2794 **/
2795 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2796 {
2797 s32 ret_val;
2798
2799 if (e1000_check_reset_block(hw))
2800 return 0;
2801
2802 /*
2803 * ICH parts do not have a word in the NVM to determine
2804 * the default flow control setting, so we explicitly
2805 * set it to full.
2806 */
2807 if (hw->fc.requested_mode == e1000_fc_default) {
2808 /* Workaround h/w hang when Tx flow control enabled */
2809 if (hw->mac.type == e1000_pchlan)
2810 hw->fc.requested_mode = e1000_fc_rx_pause;
2811 else
2812 hw->fc.requested_mode = e1000_fc_full;
2813 }
2814
2815 /*
2816 * Save off the requested flow control mode for use later. Depending
2817 * on the link partner's capabilities, we may or may not use this mode.
2818 */
2819 hw->fc.current_mode = hw->fc.requested_mode;
2820
2821 e_dbg("After fix-ups FlowControl is now = %x\n",
2822 hw->fc.current_mode);
2823
2824 /* Continue to configure the copper link. */
2825 ret_val = e1000_setup_copper_link_ich8lan(hw);
2826 if (ret_val)
2827 return ret_val;
2828
2829 ew32(FCTTV, hw->fc.pause_time);
2830 if ((hw->phy.type == e1000_phy_82578) ||
2831 (hw->phy.type == e1000_phy_82577)) {
2832 ret_val = hw->phy.ops.write_reg(hw,
2833 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2834 hw->fc.pause_time);
2835 if (ret_val)
2836 return ret_val;
2837 }
2838
2839 return e1000e_set_fc_watermarks(hw);
2840 }
2841
2842 /**
2843 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2844 * @hw: pointer to the HW structure
2845 *
2846 * Configures the kumeran interface to the PHY to wait the appropriate time
2847 * when polling the PHY, then call the generic setup_copper_link to finish
2848 * configuring the copper link.
2849 **/
2850 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2851 {
2852 u32 ctrl;
2853 s32 ret_val;
2854 u16 reg_data;
2855
2856 ctrl = er32(CTRL);
2857 ctrl |= E1000_CTRL_SLU;
2858 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2859 ew32(CTRL, ctrl);
2860
2861 /*
2862 * Set the mac to wait the maximum time between each iteration
2863 * and increase the max iterations when polling the phy;
2864 * this fixes erroneous timeouts at 10Mbps.
2865 */
2866 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
2867 if (ret_val)
2868 return ret_val;
2869 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2870 &reg_data);
2871 if (ret_val)
2872 return ret_val;
2873 reg_data |= 0x3F;
2874 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2875 reg_data);
2876 if (ret_val)
2877 return ret_val;
2878
2879 switch (hw->phy.type) {
2880 case e1000_phy_igp_3:
2881 ret_val = e1000e_copper_link_setup_igp(hw);
2882 if (ret_val)
2883 return ret_val;
2884 break;
2885 case e1000_phy_bm:
2886 case e1000_phy_82578:
2887 ret_val = e1000e_copper_link_setup_m88(hw);
2888 if (ret_val)
2889 return ret_val;
2890 break;
2891 case e1000_phy_82577:
2892 ret_val = e1000_copper_link_setup_82577(hw);
2893 if (ret_val)
2894 return ret_val;
2895 break;
2896 case e1000_phy_ife:
2897 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
2898 &reg_data);
2899 if (ret_val)
2900 return ret_val;
2901
2902 reg_data &= ~IFE_PMC_AUTO_MDIX;
2903
2904 switch (hw->phy.mdix) {
2905 case 1:
2906 reg_data &= ~IFE_PMC_FORCE_MDIX;
2907 break;
2908 case 2:
2909 reg_data |= IFE_PMC_FORCE_MDIX;
2910 break;
2911 case 0:
2912 default:
2913 reg_data |= IFE_PMC_AUTO_MDIX;
2914 break;
2915 }
2916 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
2917 reg_data);
2918 if (ret_val)
2919 return ret_val;
2920 break;
2921 default:
2922 break;
2923 }
2924 return e1000e_setup_copper_link(hw);
2925 }
2926
2927 /**
2928 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2929 * @hw: pointer to the HW structure
2930 * @speed: pointer to store current link speed
2931 * @duplex: pointer to store the current link duplex
2932 *
2933 * Calls the generic get_speed_and_duplex to retrieve the current link
2934 * information and then calls the Kumeran lock loss workaround for links at
2935 * gigabit speeds.
2936 **/
2937 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2938 u16 *duplex)
2939 {
2940 s32 ret_val;
2941
2942 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2943 if (ret_val)
2944 return ret_val;
2945
2946 if ((hw->mac.type == e1000_ich8lan) &&
2947 (hw->phy.type == e1000_phy_igp_3) &&
2948 (*speed == SPEED_1000)) {
2949 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2950 }
2951
2952 return ret_val;
2953 }
2954
2955 /**
2956 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2957 * @hw: pointer to the HW structure
2958 *
2959 * Work-around for 82566 Kumeran PCS lock loss:
2960 * On link status change (i.e. PCI reset, speed change) and link is up and
2961 * speed is gigabit-
2962 * 0) if workaround is optionally disabled do nothing
2963 * 1) wait 1ms for Kumeran link to come up
2964 * 2) check Kumeran Diagnostic register PCS lock loss bit
2965 * 3) if not set the link is locked (all is good), otherwise...
2966 * 4) reset the PHY
2967 * 5) repeat up to 10 times
2968 * Note: this is only called for IGP3 copper when speed is 1gb.
2969 **/
2970 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2971 {
2972 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2973 u32 phy_ctrl;
2974 s32 ret_val;
2975 u16 i, data;
2976 bool link;
2977
2978 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2979 return 0;
2980
2981 /*
2982 * Make sure link is up before proceeding. If not just return.
2983 * Attempting this while link is negotiating fouled up link
2984 * stability
2985 */
2986 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2987 if (!link)
2988 return 0;
2989
2990 for (i = 0; i < 10; i++) {
2991 /* read once to clear */
2992 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2993 if (ret_val)
2994 return ret_val;
2995 /* and again to get new status */
2996 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2997 if (ret_val)
2998 return ret_val;
2999
3000 /* check for PCS lock */
3001 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3002 return 0;
3003
3004 /* Issue PHY reset */
3005 e1000_phy_hw_reset(hw);
3006 mdelay(5);
3007 }
3008 /* Disable GigE link negotiation */
3009 phy_ctrl = er32(PHY_CTRL);
3010 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3011 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3012 ew32(PHY_CTRL, phy_ctrl);
3013
3014 /*
3015 * Call gig speed drop workaround on Gig disable before accessing
3016 * any PHY registers
3017 */
3018 e1000e_gig_downshift_workaround_ich8lan(hw);
3019
3020 /* unable to acquire PCS lock */
3021 return -E1000_ERR_PHY;
3022 }
3023
3024 /**
3025 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3026 * @hw: pointer to the HW structure
3027 * @state: boolean value used to set the current Kumeran workaround state
3028 *
3029 * If ICH8, set the current Kumeran workaround state (enabled - true
3030 * /disabled - false).
3031 **/
3032 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3033 bool state)
3034 {
3035 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3036
3037 if (hw->mac.type != e1000_ich8lan) {
3038 e_dbg("Workaround applies to ICH8 only.\n");
3039 return;
3040 }
3041
3042 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3043 }
3044
3045 /**
3046 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3047 * @hw: pointer to the HW structure
3048 *
3049 * Workaround for 82566 power-down on D3 entry:
3050 * 1) disable gigabit link
3051 * 2) write VR power-down enable
3052 * 3) read it back
3053 * Continue if successful, else issue LCD reset and repeat
3054 **/
3055 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3056 {
3057 u32 reg;
3058 u16 data;
3059 u8 retry = 0;
3060
3061 if (hw->phy.type != e1000_phy_igp_3)
3062 return;
3063
3064 /* Try the workaround twice (if needed) */
3065 do {
3066 /* Disable link */
3067 reg = er32(PHY_CTRL);
3068 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3069 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3070 ew32(PHY_CTRL, reg);
3071
3072 /*
3073 * Call gig speed drop workaround on Gig disable before
3074 * accessing any PHY registers
3075 */
3076 if (hw->mac.type == e1000_ich8lan)
3077 e1000e_gig_downshift_workaround_ich8lan(hw);
3078
3079 /* Write VR power-down enable */
3080 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3081 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3082 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3083
3084 /* Read it back and test */
3085 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3086 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3087 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3088 break;
3089
3090 /* Issue PHY reset and repeat at most one more time */
3091 reg = er32(CTRL);
3092 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3093 retry++;
3094 } while (retry);
3095 }
3096
3097 /**
3098 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3099 * @hw: pointer to the HW structure
3100 *
3101 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3102 * LPLU, Gig disable, MDIC PHY reset):
3103 * 1) Set Kumeran Near-end loopback
3104 * 2) Clear Kumeran Near-end loopback
3105 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3106 **/
3107 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3108 {
3109 s32 ret_val;
3110 u16 reg_data;
3111
3112 if ((hw->mac.type != e1000_ich8lan) ||
3113 (hw->phy.type != e1000_phy_igp_3))
3114 return;
3115
3116 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3117 &reg_data);
3118 if (ret_val)
3119 return;
3120 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3121 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3122 reg_data);
3123 if (ret_val)
3124 return;
3125 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3126 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3127 reg_data);
3128 }
3129
3130 /**
3131 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3132 * @hw: pointer to the HW structure
3133 *
3134 * During S0 to Sx transition, it is possible the link remains at gig
3135 * instead of negotiating to a lower speed. Before going to Sx, set
3136 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3137 * to a lower speed.
3138 *
3139 * Should only be called for applicable parts.
3140 **/
3141 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3142 {
3143 u32 phy_ctrl;
3144
3145 switch (hw->mac.type) {
3146 case e1000_ich8lan:
3147 case e1000_ich9lan:
3148 case e1000_ich10lan:
3149 case e1000_pchlan:
3150 phy_ctrl = er32(PHY_CTRL);
3151 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3152 E1000_PHY_CTRL_GBE_DISABLE;
3153 ew32(PHY_CTRL, phy_ctrl);
3154
3155 if (hw->mac.type == e1000_pchlan)
3156 e1000_phy_hw_reset_ich8lan(hw);
3157 default:
3158 break;
3159 }
3160
3161 return;
3162 }
3163
3164 /**
3165 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3166 * @hw: pointer to the HW structure
3167 *
3168 * Return the LED back to the default configuration.
3169 **/
3170 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3171 {
3172 if (hw->phy.type == e1000_phy_ife)
3173 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3174
3175 ew32(LEDCTL, hw->mac.ledctl_default);
3176 return 0;
3177 }
3178
3179 /**
3180 * e1000_led_on_ich8lan - Turn LEDs on
3181 * @hw: pointer to the HW structure
3182 *
3183 * Turn on the LEDs.
3184 **/
3185 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3186 {
3187 if (hw->phy.type == e1000_phy_ife)
3188 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3189 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3190
3191 ew32(LEDCTL, hw->mac.ledctl_mode2);
3192 return 0;
3193 }
3194
3195 /**
3196 * e1000_led_off_ich8lan - Turn LEDs off
3197 * @hw: pointer to the HW structure
3198 *
3199 * Turn off the LEDs.
3200 **/
3201 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3202 {
3203 if (hw->phy.type == e1000_phy_ife)
3204 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3205 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3206
3207 ew32(LEDCTL, hw->mac.ledctl_mode1);
3208 return 0;
3209 }
3210
3211 /**
3212 * e1000_setup_led_pchlan - Configures SW controllable LED
3213 * @hw: pointer to the HW structure
3214 *
3215 * This prepares the SW controllable LED for use.
3216 **/
3217 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3218 {
3219 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3220 (u16)hw->mac.ledctl_mode1);
3221 }
3222
3223 /**
3224 * e1000_cleanup_led_pchlan - Restore the default LED operation
3225 * @hw: pointer to the HW structure
3226 *
3227 * Return the LED back to the default configuration.
3228 **/
3229 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3230 {
3231 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3232 (u16)hw->mac.ledctl_default);
3233 }
3234
3235 /**
3236 * e1000_led_on_pchlan - Turn LEDs on
3237 * @hw: pointer to the HW structure
3238 *
3239 * Turn on the LEDs.
3240 **/
3241 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3242 {
3243 u16 data = (u16)hw->mac.ledctl_mode2;
3244 u32 i, led;
3245
3246 /*
3247 * If no link, then turn LED on by setting the invert bit
3248 * for each LED that's mode is "link_up" in ledctl_mode2.
3249 */
3250 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3251 for (i = 0; i < 3; i++) {
3252 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3253 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3254 E1000_LEDCTL_MODE_LINK_UP)
3255 continue;
3256 if (led & E1000_PHY_LED0_IVRT)
3257 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3258 else
3259 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3260 }
3261 }
3262
3263 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3264 }
3265
3266 /**
3267 * e1000_led_off_pchlan - Turn LEDs off
3268 * @hw: pointer to the HW structure
3269 *
3270 * Turn off the LEDs.
3271 **/
3272 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3273 {
3274 u16 data = (u16)hw->mac.ledctl_mode1;
3275 u32 i, led;
3276
3277 /*
3278 * If no link, then turn LED off by clearing the invert bit
3279 * for each LED that's mode is "link_up" in ledctl_mode1.
3280 */
3281 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3282 for (i = 0; i < 3; i++) {
3283 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3284 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3285 E1000_LEDCTL_MODE_LINK_UP)
3286 continue;
3287 if (led & E1000_PHY_LED0_IVRT)
3288 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3289 else
3290 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3291 }
3292 }
3293
3294 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3295 }
3296
3297 /**
3298 * e1000_get_cfg_done_ich8lan - Read config done bit
3299 * @hw: pointer to the HW structure
3300 *
3301 * Read the management control register for the config done bit for
3302 * completion status. NOTE: silicon which is EEPROM-less will fail trying
3303 * to read the config done bit, so an error is *ONLY* logged and returns
3304 * 0. If we were to return with error, EEPROM-less silicon
3305 * would not be able to be reset or change link.
3306 **/
3307 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3308 {
3309 u32 bank = 0;
3310
3311 if (hw->mac.type >= e1000_pchlan) {
3312 u32 status = er32(STATUS);
3313
3314 if (status & E1000_STATUS_PHYRA)
3315 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3316 else
3317 e_dbg("PHY Reset Asserted not set - needs delay\n");
3318 }
3319
3320 e1000e_get_cfg_done(hw);
3321
3322 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3323 if ((hw->mac.type != e1000_ich10lan) &&
3324 (hw->mac.type != e1000_pchlan)) {
3325 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3326 (hw->phy.type == e1000_phy_igp_3)) {
3327 e1000e_phy_init_script_igp3(hw);
3328 }
3329 } else {
3330 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3331 /* Maybe we should do a basic PHY config */
3332 e_dbg("EEPROM not present\n");
3333 return -E1000_ERR_CONFIG;
3334 }
3335 }
3336
3337 return 0;
3338 }
3339
3340 /**
3341 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3342 * @hw: pointer to the HW structure
3343 *
3344 * In the case of a PHY power down to save power, or to turn off link during a
3345 * driver unload, or wake on lan is not enabled, remove the link.
3346 **/
3347 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3348 {
3349 /* If the management interface is not enabled, then power down */
3350 if (!(hw->mac.ops.check_mng_mode(hw) ||
3351 hw->phy.ops.check_reset_block(hw)))
3352 e1000_power_down_phy_copper(hw);
3353
3354 return;
3355 }
3356
3357 /**
3358 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3359 * @hw: pointer to the HW structure
3360 *
3361 * Clears hardware counters specific to the silicon family and calls
3362 * clear_hw_cntrs_generic to clear all general purpose counters.
3363 **/
3364 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3365 {
3366 u16 phy_data;
3367
3368 e1000e_clear_hw_cntrs_base(hw);
3369
3370 er32(ALGNERRC);
3371 er32(RXERRC);
3372 er32(TNCRS);
3373 er32(CEXTERR);
3374 er32(TSCTC);
3375 er32(TSCTFC);
3376
3377 er32(MGTPRC);
3378 er32(MGTPDC);
3379 er32(MGTPTC);
3380
3381 er32(IAC);
3382 er32(ICRXOC);
3383
3384 /* Clear PHY statistics registers */
3385 if ((hw->phy.type == e1000_phy_82578) ||
3386 (hw->phy.type == e1000_phy_82577)) {
3387 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3388 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3389 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3390 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3391 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3392 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3393 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3394 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3395 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3396 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3397 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3398 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3399 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3400 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3401 }
3402 }
3403
3404 static struct e1000_mac_operations ich8_mac_ops = {
3405 .id_led_init = e1000e_id_led_init,
3406 .check_mng_mode = e1000_check_mng_mode_ich8lan,
3407 .check_for_link = e1000_check_for_copper_link_ich8lan,
3408 /* cleanup_led dependent on mac type */
3409 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3410 .get_bus_info = e1000_get_bus_info_ich8lan,
3411 .set_lan_id = e1000_set_lan_id_single_port,
3412 .get_link_up_info = e1000_get_link_up_info_ich8lan,
3413 /* led_on dependent on mac type */
3414 /* led_off dependent on mac type */
3415 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
3416 .reset_hw = e1000_reset_hw_ich8lan,
3417 .init_hw = e1000_init_hw_ich8lan,
3418 .setup_link = e1000_setup_link_ich8lan,
3419 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3420 /* id_led_init dependent on mac type */
3421 };
3422
3423 static struct e1000_phy_operations ich8_phy_ops = {
3424 .acquire = e1000_acquire_swflag_ich8lan,
3425 .check_reset_block = e1000_check_reset_block_ich8lan,
3426 .commit = NULL,
3427 .get_cfg_done = e1000_get_cfg_done_ich8lan,
3428 .get_cable_length = e1000e_get_cable_length_igp_2,
3429 .read_reg = e1000e_read_phy_reg_igp,
3430 .release = e1000_release_swflag_ich8lan,
3431 .reset = e1000_phy_hw_reset_ich8lan,
3432 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3433 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
3434 .write_reg = e1000e_write_phy_reg_igp,
3435 };
3436
3437 static struct e1000_nvm_operations ich8_nvm_ops = {
3438 .acquire = e1000_acquire_nvm_ich8lan,
3439 .read = e1000_read_nvm_ich8lan,
3440 .release = e1000_release_nvm_ich8lan,
3441 .update = e1000_update_nvm_checksum_ich8lan,
3442 .valid_led_default = e1000_valid_led_default_ich8lan,
3443 .validate = e1000_validate_nvm_checksum_ich8lan,
3444 .write = e1000_write_nvm_ich8lan,
3445 };
3446
3447 struct e1000_info e1000_ich8_info = {
3448 .mac = e1000_ich8lan,
3449 .flags = FLAG_HAS_WOL
3450 | FLAG_IS_ICH
3451 | FLAG_RX_CSUM_ENABLED
3452 | FLAG_HAS_CTRLEXT_ON_LOAD
3453 | FLAG_HAS_AMT
3454 | FLAG_HAS_FLASH
3455 | FLAG_APME_IN_WUC,
3456 .pba = 8,
3457 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
3458 .get_variants = e1000_get_variants_ich8lan,
3459 .mac_ops = &ich8_mac_ops,
3460 .phy_ops = &ich8_phy_ops,
3461 .nvm_ops = &ich8_nvm_ops,
3462 };
3463
3464 struct e1000_info e1000_ich9_info = {
3465 .mac = e1000_ich9lan,
3466 .flags = FLAG_HAS_JUMBO_FRAMES
3467 | FLAG_IS_ICH
3468 | FLAG_HAS_WOL
3469 | FLAG_RX_CSUM_ENABLED
3470 | FLAG_HAS_CTRLEXT_ON_LOAD
3471 | FLAG_HAS_AMT
3472 | FLAG_HAS_ERT
3473 | FLAG_HAS_FLASH
3474 | FLAG_APME_IN_WUC,
3475 .pba = 10,
3476 .max_hw_frame_size = DEFAULT_JUMBO,
3477 .get_variants = e1000_get_variants_ich8lan,
3478 .mac_ops = &ich8_mac_ops,
3479 .phy_ops = &ich8_phy_ops,
3480 .nvm_ops = &ich8_nvm_ops,
3481 };
3482
3483 struct e1000_info e1000_ich10_info = {
3484 .mac = e1000_ich10lan,
3485 .flags = FLAG_HAS_JUMBO_FRAMES
3486 | FLAG_IS_ICH
3487 | FLAG_HAS_WOL
3488 | FLAG_RX_CSUM_ENABLED
3489 | FLAG_HAS_CTRLEXT_ON_LOAD
3490 | FLAG_HAS_AMT
3491 | FLAG_HAS_ERT
3492 | FLAG_HAS_FLASH
3493 | FLAG_APME_IN_WUC,
3494 .pba = 10,
3495 .max_hw_frame_size = DEFAULT_JUMBO,
3496 .get_variants = e1000_get_variants_ich8lan,
3497 .mac_ops = &ich8_mac_ops,
3498 .phy_ops = &ich8_phy_ops,
3499 .nvm_ops = &ich8_nvm_ops,
3500 };
3501
3502 struct e1000_info e1000_pch_info = {
3503 .mac = e1000_pchlan,
3504 .flags = FLAG_IS_ICH
3505 | FLAG_HAS_WOL
3506 | FLAG_RX_CSUM_ENABLED
3507 | FLAG_HAS_CTRLEXT_ON_LOAD
3508 | FLAG_HAS_AMT
3509 | FLAG_HAS_FLASH
3510 | FLAG_HAS_JUMBO_FRAMES
3511 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3512 | FLAG_APME_IN_WUC,
3513 .pba = 26,
3514 .max_hw_frame_size = 4096,
3515 .get_variants = e1000_get_variants_ich8lan,
3516 .mac_ops = &ich8_mac_ops,
3517 .phy_ops = &ich8_phy_ops,
3518 .nvm_ops = &ich8_nvm_ops,
3519 };
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree