2 * libahci.c - Common AHCI SATA low-level routines
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
49 static int ahci_skip_host_reset
;
51 EXPORT_SYMBOL_GPL(ahci_ignore_sss
);
53 module_param_named(skip_host_reset
, ahci_skip_host_reset
, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset
, "skip global host reset (0=don't skip, 1=skip)");
56 module_param_named(ignore_sss
, ahci_ignore_sss
, int, 0444);
57 MODULE_PARM_DESC(ignore_sss
, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
59 static int ahci_enable_alpm(struct ata_port
*ap
,
61 static void ahci_disable_alpm(struct ata_port
*ap
);
62 static ssize_t
ahci_led_show(struct ata_port
*ap
, char *buf
);
63 static ssize_t
ahci_led_store(struct ata_port
*ap
, const char *buf
,
65 static ssize_t
ahci_transmit_led_message(struct ata_port
*ap
, u32 state
,
70 static int ahci_scr_read(struct ata_link
*link
, unsigned int sc_reg
, u32
*val
);
71 static int ahci_scr_write(struct ata_link
*link
, unsigned int sc_reg
, u32 val
);
72 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
);
73 static bool ahci_qc_fill_rtf(struct ata_queued_cmd
*qc
);
74 static int ahci_port_start(struct ata_port
*ap
);
75 static void ahci_port_stop(struct ata_port
*ap
);
76 static void ahci_qc_prep(struct ata_queued_cmd
*qc
);
77 static int ahci_pmp_qc_defer(struct ata_queued_cmd
*qc
);
78 static void ahci_freeze(struct ata_port
*ap
);
79 static void ahci_thaw(struct ata_port
*ap
);
80 static void ahci_enable_fbs(struct ata_port
*ap
);
81 static void ahci_disable_fbs(struct ata_port
*ap
);
82 static void ahci_pmp_attach(struct ata_port
*ap
);
83 static void ahci_pmp_detach(struct ata_port
*ap
);
84 static int ahci_softreset(struct ata_link
*link
, unsigned int *class,
85 unsigned long deadline
);
86 static int ahci_hardreset(struct ata_link
*link
, unsigned int *class,
87 unsigned long deadline
);
88 static void ahci_postreset(struct ata_link
*link
, unsigned int *class);
89 static void ahci_error_handler(struct ata_port
*ap
);
90 static void ahci_post_internal_cmd(struct ata_queued_cmd
*qc
);
91 static int ahci_port_resume(struct ata_port
*ap
);
92 static void ahci_dev_config(struct ata_device
*dev
);
93 static void ahci_fill_cmd_slot(struct ahci_port_priv
*pp
, unsigned int tag
,
96 static int ahci_port_suspend(struct ata_port
*ap
, pm_message_t mesg
);
98 static ssize_t
ahci_activity_show(struct ata_device
*dev
, char *buf
);
99 static ssize_t
ahci_activity_store(struct ata_device
*dev
,
100 enum sw_activity val
);
101 static void ahci_init_sw_activity(struct ata_link
*link
);
103 static ssize_t
ahci_show_host_caps(struct device
*dev
,
104 struct device_attribute
*attr
, char *buf
);
105 static ssize_t
ahci_show_host_cap2(struct device
*dev
,
106 struct device_attribute
*attr
, char *buf
);
107 static ssize_t
ahci_show_host_version(struct device
*dev
,
108 struct device_attribute
*attr
, char *buf
);
109 static ssize_t
ahci_show_port_cmd(struct device
*dev
,
110 struct device_attribute
*attr
, char *buf
);
111 static ssize_t
ahci_read_em_buffer(struct device
*dev
,
112 struct device_attribute
*attr
, char *buf
);
113 static ssize_t
ahci_store_em_buffer(struct device
*dev
,
114 struct device_attribute
*attr
,
115 const char *buf
, size_t size
);
117 static DEVICE_ATTR(ahci_host_caps
, S_IRUGO
, ahci_show_host_caps
, NULL
);
118 static DEVICE_ATTR(ahci_host_cap2
, S_IRUGO
, ahci_show_host_cap2
, NULL
);
119 static DEVICE_ATTR(ahci_host_version
, S_IRUGO
, ahci_show_host_version
, NULL
);
120 static DEVICE_ATTR(ahci_port_cmd
, S_IRUGO
, ahci_show_port_cmd
, NULL
);
121 static DEVICE_ATTR(em_buffer
, S_IWUSR
| S_IRUGO
,
122 ahci_read_em_buffer
, ahci_store_em_buffer
);
124 static struct device_attribute
*ahci_shost_attrs
[] = {
125 &dev_attr_link_power_management_policy
,
126 &dev_attr_em_message_type
,
127 &dev_attr_em_message
,
128 &dev_attr_ahci_host_caps
,
129 &dev_attr_ahci_host_cap2
,
130 &dev_attr_ahci_host_version
,
131 &dev_attr_ahci_port_cmd
,
136 static struct device_attribute
*ahci_sdev_attrs
[] = {
137 &dev_attr_sw_activity
,
138 &dev_attr_unload_heads
,
142 struct scsi_host_template ahci_sht
= {
144 .can_queue
= AHCI_MAX_CMDS
- 1,
145 .sg_tablesize
= AHCI_MAX_SG
,
146 .dma_boundary
= AHCI_DMA_BOUNDARY
,
147 .shost_attrs
= ahci_shost_attrs
,
148 .sdev_attrs
= ahci_sdev_attrs
,
150 EXPORT_SYMBOL_GPL(ahci_sht
);
152 struct ata_port_operations ahci_ops
= {
153 .inherits
= &sata_pmp_port_ops
,
155 .qc_defer
= ahci_pmp_qc_defer
,
156 .qc_prep
= ahci_qc_prep
,
157 .qc_issue
= ahci_qc_issue
,
158 .qc_fill_rtf
= ahci_qc_fill_rtf
,
160 .freeze
= ahci_freeze
,
162 .softreset
= ahci_softreset
,
163 .hardreset
= ahci_hardreset
,
164 .postreset
= ahci_postreset
,
165 .pmp_softreset
= ahci_softreset
,
166 .error_handler
= ahci_error_handler
,
167 .post_internal_cmd
= ahci_post_internal_cmd
,
168 .dev_config
= ahci_dev_config
,
170 .scr_read
= ahci_scr_read
,
171 .scr_write
= ahci_scr_write
,
172 .pmp_attach
= ahci_pmp_attach
,
173 .pmp_detach
= ahci_pmp_detach
,
175 .enable_pm
= ahci_enable_alpm
,
176 .disable_pm
= ahci_disable_alpm
,
177 .em_show
= ahci_led_show
,
178 .em_store
= ahci_led_store
,
179 .sw_activity_show
= ahci_activity_show
,
180 .sw_activity_store
= ahci_activity_store
,
182 .port_suspend
= ahci_port_suspend
,
183 .port_resume
= ahci_port_resume
,
185 .port_start
= ahci_port_start
,
186 .port_stop
= ahci_port_stop
,
188 EXPORT_SYMBOL_GPL(ahci_ops
);
190 int ahci_em_messages
= 1;
191 EXPORT_SYMBOL_GPL(ahci_em_messages
);
192 module_param(ahci_em_messages
, int, 0444);
193 /* add other LED protocol types when they become supported */
194 MODULE_PARM_DESC(ahci_em_messages
,
195 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
197 static void ahci_enable_ahci(void __iomem
*mmio
)
202 /* turn on AHCI_EN */
203 tmp
= readl(mmio
+ HOST_CTL
);
204 if (tmp
& HOST_AHCI_EN
)
207 /* Some controllers need AHCI_EN to be written multiple times.
208 * Try a few times before giving up.
210 for (i
= 0; i
< 5; i
++) {
212 writel(tmp
, mmio
+ HOST_CTL
);
213 tmp
= readl(mmio
+ HOST_CTL
); /* flush && sanity check */
214 if (tmp
& HOST_AHCI_EN
)
222 static ssize_t
ahci_show_host_caps(struct device
*dev
,
223 struct device_attribute
*attr
, char *buf
)
225 struct Scsi_Host
*shost
= class_to_shost(dev
);
226 struct ata_port
*ap
= ata_shost_to_port(shost
);
227 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
229 return sprintf(buf
, "%x\n", hpriv
->cap
);
232 static ssize_t
ahci_show_host_cap2(struct device
*dev
,
233 struct device_attribute
*attr
, char *buf
)
235 struct Scsi_Host
*shost
= class_to_shost(dev
);
236 struct ata_port
*ap
= ata_shost_to_port(shost
);
237 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
239 return sprintf(buf
, "%x\n", hpriv
->cap2
);
242 static ssize_t
ahci_show_host_version(struct device
*dev
,
243 struct device_attribute
*attr
, char *buf
)
245 struct Scsi_Host
*shost
= class_to_shost(dev
);
246 struct ata_port
*ap
= ata_shost_to_port(shost
);
247 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
248 void __iomem
*mmio
= hpriv
->mmio
;
250 return sprintf(buf
, "%x\n", readl(mmio
+ HOST_VERSION
));
253 static ssize_t
ahci_show_port_cmd(struct device
*dev
,
254 struct device_attribute
*attr
, char *buf
)
256 struct Scsi_Host
*shost
= class_to_shost(dev
);
257 struct ata_port
*ap
= ata_shost_to_port(shost
);
258 void __iomem
*port_mmio
= ahci_port_base(ap
);
260 return sprintf(buf
, "%x\n", readl(port_mmio
+ PORT_CMD
));
263 static ssize_t
ahci_read_em_buffer(struct device
*dev
,
264 struct device_attribute
*attr
, char *buf
)
266 struct Scsi_Host
*shost
= class_to_shost(dev
);
267 struct ata_port
*ap
= ata_shost_to_port(shost
);
268 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
269 void __iomem
*mmio
= hpriv
->mmio
;
270 void __iomem
*em_mmio
= mmio
+ hpriv
->em_loc
;
276 spin_lock_irqsave(ap
->lock
, flags
);
278 em_ctl
= readl(mmio
+ HOST_EM_CTL
);
279 if (!(ap
->flags
& ATA_FLAG_EM
) || em_ctl
& EM_CTL_XMT
||
280 !(hpriv
->em_msg_type
& EM_MSG_TYPE_SGPIO
)) {
281 spin_unlock_irqrestore(ap
->lock
, flags
);
285 if (!(em_ctl
& EM_CTL_MR
)) {
286 spin_unlock_irqrestore(ap
->lock
, flags
);
290 if (!(em_ctl
& EM_CTL_SMB
))
291 em_mmio
+= hpriv
->em_buf_sz
;
293 count
= hpriv
->em_buf_sz
;
295 /* the count should not be larger than PAGE_SIZE */
296 if (count
> PAGE_SIZE
) {
297 if (printk_ratelimit())
298 ata_port_printk(ap
, KERN_WARNING
,
299 "EM read buffer size too large: "
300 "buffer size %u, page size %lu\n",
301 hpriv
->em_buf_sz
, PAGE_SIZE
);
305 for (i
= 0; i
< count
; i
+= 4) {
306 msg
= readl(em_mmio
+ i
);
308 buf
[i
+ 1] = (msg
>> 8) & 0xff;
309 buf
[i
+ 2] = (msg
>> 16) & 0xff;
310 buf
[i
+ 3] = (msg
>> 24) & 0xff;
313 spin_unlock_irqrestore(ap
->lock
, flags
);
318 static ssize_t
ahci_store_em_buffer(struct device
*dev
,
319 struct device_attribute
*attr
,
320 const char *buf
, size_t size
)
322 struct Scsi_Host
*shost
= class_to_shost(dev
);
323 struct ata_port
*ap
= ata_shost_to_port(shost
);
324 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
325 void __iomem
*mmio
= hpriv
->mmio
;
326 void __iomem
*em_mmio
= mmio
+ hpriv
->em_loc
;
331 /* check size validity */
332 if (!(ap
->flags
& ATA_FLAG_EM
) ||
333 !(hpriv
->em_msg_type
& EM_MSG_TYPE_SGPIO
) ||
334 size
% 4 || size
> hpriv
->em_buf_sz
)
337 spin_lock_irqsave(ap
->lock
, flags
);
339 em_ctl
= readl(mmio
+ HOST_EM_CTL
);
340 if (em_ctl
& EM_CTL_TM
) {
341 spin_unlock_irqrestore(ap
->lock
, flags
);
345 for (i
= 0; i
< size
; i
+= 4) {
346 msg
= buf
[i
] | buf
[i
+ 1] << 8 |
347 buf
[i
+ 2] << 16 | buf
[i
+ 3] << 24;
348 writel(msg
, em_mmio
+ i
);
351 writel(em_ctl
| EM_CTL_TM
, mmio
+ HOST_EM_CTL
);
353 spin_unlock_irqrestore(ap
->lock
, flags
);
359 * ahci_save_initial_config - Save and fixup initial config values
360 * @dev: target AHCI device
361 * @hpriv: host private area to store config values
362 * @force_port_map: force port map to a specified value
363 * @mask_port_map: mask out particular bits from port map
365 * Some registers containing configuration info might be setup by
366 * BIOS and might be cleared on reset. This function saves the
367 * initial values of those registers into @hpriv such that they
368 * can be restored after controller reset.
370 * If inconsistent, config values are fixed up by this function.
375 void ahci_save_initial_config(struct device
*dev
,
376 struct ahci_host_priv
*hpriv
,
377 unsigned int force_port_map
,
378 unsigned int mask_port_map
)
380 void __iomem
*mmio
= hpriv
->mmio
;
381 u32 cap
, cap2
, vers
, port_map
;
384 /* make sure AHCI mode is enabled before accessing CAP */
385 ahci_enable_ahci(mmio
);
387 /* Values prefixed with saved_ are written back to host after
388 * reset. Values without are used for driver operation.
390 hpriv
->saved_cap
= cap
= readl(mmio
+ HOST_CAP
);
391 hpriv
->saved_port_map
= port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
393 /* CAP2 register is only defined for AHCI 1.2 and later */
394 vers
= readl(mmio
+ HOST_VERSION
);
395 if ((vers
>> 16) > 1 ||
396 ((vers
>> 16) == 1 && (vers
& 0xFFFF) >= 0x200))
397 hpriv
->saved_cap2
= cap2
= readl(mmio
+ HOST_CAP2
);
399 hpriv
->saved_cap2
= cap2
= 0;
401 /* some chips have errata preventing 64bit use */
402 if ((cap
& HOST_CAP_64
) && (hpriv
->flags
& AHCI_HFLAG_32BIT_ONLY
)) {
403 dev_printk(KERN_INFO
, dev
,
404 "controller can't do 64bit DMA, forcing 32bit\n");
408 if ((cap
& HOST_CAP_NCQ
) && (hpriv
->flags
& AHCI_HFLAG_NO_NCQ
)) {
409 dev_printk(KERN_INFO
, dev
,
410 "controller can't do NCQ, turning off CAP_NCQ\n");
411 cap
&= ~HOST_CAP_NCQ
;
414 if (!(cap
& HOST_CAP_NCQ
) && (hpriv
->flags
& AHCI_HFLAG_YES_NCQ
)) {
415 dev_printk(KERN_INFO
, dev
,
416 "controller can do NCQ, turning on CAP_NCQ\n");
420 if ((cap
& HOST_CAP_PMP
) && (hpriv
->flags
& AHCI_HFLAG_NO_PMP
)) {
421 dev_printk(KERN_INFO
, dev
,
422 "controller can't do PMP, turning off CAP_PMP\n");
423 cap
&= ~HOST_CAP_PMP
;
426 if ((cap
& HOST_CAP_SNTF
) && (hpriv
->flags
& AHCI_HFLAG_NO_SNTF
)) {
427 dev_printk(KERN_INFO
, dev
,
428 "controller can't do SNTF, turning off CAP_SNTF\n");
429 cap
&= ~HOST_CAP_SNTF
;
432 if (force_port_map
&& port_map
!= force_port_map
) {
433 dev_printk(KERN_INFO
, dev
, "forcing port_map 0x%x -> 0x%x\n",
434 port_map
, force_port_map
);
435 port_map
= force_port_map
;
439 dev_printk(KERN_ERR
, dev
, "masking port_map 0x%x -> 0x%x\n",
441 port_map
& mask_port_map
);
442 port_map
&= mask_port_map
;
445 /* cross check port_map and cap.n_ports */
449 for (i
= 0; i
< AHCI_MAX_PORTS
; i
++)
450 if (port_map
& (1 << i
))
453 /* If PI has more ports than n_ports, whine, clear
454 * port_map and let it be generated from n_ports.
456 if (map_ports
> ahci_nr_ports(cap
)) {
457 dev_printk(KERN_WARNING
, dev
,
458 "implemented port map (0x%x) contains more "
459 "ports than nr_ports (%u), using nr_ports\n",
460 port_map
, ahci_nr_ports(cap
));
465 /* fabricate port_map from cap.nr_ports */
467 port_map
= (1 << ahci_nr_ports(cap
)) - 1;
468 dev_printk(KERN_WARNING
, dev
,
469 "forcing PORTS_IMPL to 0x%x\n", port_map
);
471 /* write the fixed up value to the PI register */
472 hpriv
->saved_port_map
= port_map
;
475 /* record values to use during operation */
478 hpriv
->port_map
= port_map
;
480 EXPORT_SYMBOL_GPL(ahci_save_initial_config
);
483 * ahci_restore_initial_config - Restore initial config
484 * @host: target ATA host
486 * Restore initial config stored by ahci_save_initial_config().
491 static void ahci_restore_initial_config(struct ata_host
*host
)
493 struct ahci_host_priv
*hpriv
= host
->private_data
;
494 void __iomem
*mmio
= hpriv
->mmio
;
496 writel(hpriv
->saved_cap
, mmio
+ HOST_CAP
);
497 if (hpriv
->saved_cap2
)
498 writel(hpriv
->saved_cap2
, mmio
+ HOST_CAP2
);
499 writel(hpriv
->saved_port_map
, mmio
+ HOST_PORTS_IMPL
);
500 (void) readl(mmio
+ HOST_PORTS_IMPL
); /* flush */
503 static unsigned ahci_scr_offset(struct ata_port
*ap
, unsigned int sc_reg
)
505 static const int offset
[] = {
506 [SCR_STATUS
] = PORT_SCR_STAT
,
507 [SCR_CONTROL
] = PORT_SCR_CTL
,
508 [SCR_ERROR
] = PORT_SCR_ERR
,
509 [SCR_ACTIVE
] = PORT_SCR_ACT
,
510 [SCR_NOTIFICATION
] = PORT_SCR_NTF
,
512 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
514 if (sc_reg
< ARRAY_SIZE(offset
) &&
515 (sc_reg
!= SCR_NOTIFICATION
|| (hpriv
->cap
& HOST_CAP_SNTF
)))
516 return offset
[sc_reg
];
520 static int ahci_scr_read(struct ata_link
*link
, unsigned int sc_reg
, u32
*val
)
522 void __iomem
*port_mmio
= ahci_port_base(link
->ap
);
523 int offset
= ahci_scr_offset(link
->ap
, sc_reg
);
526 *val
= readl(port_mmio
+ offset
);
532 static int ahci_scr_write(struct ata_link
*link
, unsigned int sc_reg
, u32 val
)
534 void __iomem
*port_mmio
= ahci_port_base(link
->ap
);
535 int offset
= ahci_scr_offset(link
->ap
, sc_reg
);
538 writel(val
, port_mmio
+ offset
);
544 static int ahci_is_device_present(void __iomem
*port_mmio
)
546 u8 status
= readl(port_mmio
+ PORT_TFDATA
) & 0xff;
548 /* Make sure PxTFD.STS.BSY and PxTFD.STS.DRQ are 0 */
549 if (status
& (ATA_BUSY
| ATA_DRQ
))
552 /* Make sure PxSSTS.DET is 3h */
553 status
= readl(port_mmio
+ PORT_SCR_STAT
) & 0xf;
559 void ahci_start_engine(struct ata_port
*ap
)
561 void __iomem
*port_mmio
= ahci_port_base(ap
);
564 if (!ahci_is_device_present(port_mmio
))
568 tmp
= readl(port_mmio
+ PORT_CMD
);
569 tmp
|= PORT_CMD_START
;
570 writel(tmp
, port_mmio
+ PORT_CMD
);
571 readl(port_mmio
+ PORT_CMD
); /* flush */
573 EXPORT_SYMBOL_GPL(ahci_start_engine
);
575 int ahci_stop_engine(struct ata_port
*ap
)
577 void __iomem
*port_mmio
= ahci_port_base(ap
);
580 tmp
= readl(port_mmio
+ PORT_CMD
);
582 /* check if the HBA is idle */
583 if ((tmp
& (PORT_CMD_START
| PORT_CMD_LIST_ON
)) == 0)
586 /* setting HBA to idle */
587 tmp
&= ~PORT_CMD_START
;
588 writel(tmp
, port_mmio
+ PORT_CMD
);
590 /* wait for engine to stop. This could be as long as 500 msec */
591 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
,
592 PORT_CMD_LIST_ON
, PORT_CMD_LIST_ON
, 1, 500);
593 if (tmp
& PORT_CMD_LIST_ON
)
598 EXPORT_SYMBOL_GPL(ahci_stop_engine
);
600 static void ahci_start_fis_rx(struct ata_port
*ap
)
602 void __iomem
*port_mmio
= ahci_port_base(ap
);
603 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
604 struct ahci_port_priv
*pp
= ap
->private_data
;
607 /* set FIS registers */
608 if (hpriv
->cap
& HOST_CAP_64
)
609 writel((pp
->cmd_slot_dma
>> 16) >> 16,
610 port_mmio
+ PORT_LST_ADDR_HI
);
611 writel(pp
->cmd_slot_dma
& 0xffffffff, port_mmio
+ PORT_LST_ADDR
);
613 if (hpriv
->cap
& HOST_CAP_64
)
614 writel((pp
->rx_fis_dma
>> 16) >> 16,
615 port_mmio
+ PORT_FIS_ADDR_HI
);
616 writel(pp
->rx_fis_dma
& 0xffffffff, port_mmio
+ PORT_FIS_ADDR
);
618 /* enable FIS reception */
619 tmp
= readl(port_mmio
+ PORT_CMD
);
620 tmp
|= PORT_CMD_FIS_RX
;
621 writel(tmp
, port_mmio
+ PORT_CMD
);
624 readl(port_mmio
+ PORT_CMD
);
627 static int ahci_stop_fis_rx(struct ata_port
*ap
)
629 void __iomem
*port_mmio
= ahci_port_base(ap
);
632 /* disable FIS reception */
633 tmp
= readl(port_mmio
+ PORT_CMD
);
634 tmp
&= ~PORT_CMD_FIS_RX
;
635 writel(tmp
, port_mmio
+ PORT_CMD
);
637 /* wait for completion, spec says 500ms, give it 1000 */
638 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
, PORT_CMD_FIS_ON
,
639 PORT_CMD_FIS_ON
, 10, 1000);
640 if (tmp
& PORT_CMD_FIS_ON
)
646 static void ahci_power_up(struct ata_port
*ap
)
648 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
649 void __iomem
*port_mmio
= ahci_port_base(ap
);
652 cmd
= readl(port_mmio
+ PORT_CMD
) & ~PORT_CMD_ICC_MASK
;
655 if (hpriv
->cap
& HOST_CAP_SSS
) {
656 cmd
|= PORT_CMD_SPIN_UP
;
657 writel(cmd
, port_mmio
+ PORT_CMD
);
661 writel(cmd
| PORT_CMD_ICC_ACTIVE
, port_mmio
+ PORT_CMD
);
664 static void ahci_disable_alpm(struct ata_port
*ap
)
666 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
667 void __iomem
*port_mmio
= ahci_port_base(ap
);
669 struct ahci_port_priv
*pp
= ap
->private_data
;
671 /* IPM bits should be disabled by libata-core */
672 /* get the existing command bits */
673 cmd
= readl(port_mmio
+ PORT_CMD
);
675 /* disable ALPM and ASP */
676 cmd
&= ~PORT_CMD_ASP
;
677 cmd
&= ~PORT_CMD_ALPE
;
679 /* force the interface back to active */
680 cmd
|= PORT_CMD_ICC_ACTIVE
;
682 /* write out new cmd value */
683 writel(cmd
, port_mmio
+ PORT_CMD
);
684 cmd
= readl(port_mmio
+ PORT_CMD
);
686 /* wait 10ms to be sure we've come out of any low power state */
689 /* clear out any PhyRdy stuff from interrupt status */
690 writel(PORT_IRQ_PHYRDY
, port_mmio
+ PORT_IRQ_STAT
);
692 /* go ahead and clean out PhyRdy Change from Serror too */
693 ahci_scr_write(&ap
->link
, SCR_ERROR
, ((1 << 16) | (1 << 18)));
696 * Clear flag to indicate that we should ignore all PhyRdy
699 hpriv
->flags
&= ~AHCI_HFLAG_NO_HOTPLUG
;
702 * Enable interrupts on Phy Ready.
704 pp
->intr_mask
|= PORT_IRQ_PHYRDY
;
705 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
708 * don't change the link pm policy - we can be called
709 * just to turn of link pm temporarily
713 static int ahci_enable_alpm(struct ata_port
*ap
,
716 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
717 void __iomem
*port_mmio
= ahci_port_base(ap
);
719 struct ahci_port_priv
*pp
= ap
->private_data
;
722 /* Make sure the host is capable of link power management */
723 if (!(hpriv
->cap
& HOST_CAP_ALPM
))
727 case MAX_PERFORMANCE
:
730 * if we came here with NOT_AVAILABLE,
731 * it just means this is the first time we
732 * have tried to enable - default to max performance,
733 * and let the user go to lower power modes on request.
735 ahci_disable_alpm(ap
);
738 /* configure HBA to enter SLUMBER */
742 /* configure HBA to enter PARTIAL */
750 * Disable interrupts on Phy Ready. This keeps us from
751 * getting woken up due to spurious phy ready interrupts
752 * TBD - Hot plug should be done via polling now, is
753 * that even supported?
755 pp
->intr_mask
&= ~PORT_IRQ_PHYRDY
;
756 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
759 * Set a flag to indicate that we should ignore all PhyRdy
760 * state changes since these can happen now whenever we
763 hpriv
->flags
|= AHCI_HFLAG_NO_HOTPLUG
;
765 /* get the existing command bits */
766 cmd
= readl(port_mmio
+ PORT_CMD
);
769 * Set ASP based on Policy
774 * Setting this bit will instruct the HBA to aggressively
775 * enter a lower power link state when it's appropriate and
776 * based on the value set above for ASP
778 cmd
|= PORT_CMD_ALPE
;
780 /* write out new cmd value */
781 writel(cmd
, port_mmio
+ PORT_CMD
);
782 cmd
= readl(port_mmio
+ PORT_CMD
);
784 /* IPM bits should be set by libata-core */
789 static void ahci_power_down(struct ata_port
*ap
)
791 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
792 void __iomem
*port_mmio
= ahci_port_base(ap
);
795 if (!(hpriv
->cap
& HOST_CAP_SSS
))
798 /* put device into listen mode, first set PxSCTL.DET to 0 */
799 scontrol
= readl(port_mmio
+ PORT_SCR_CTL
);
801 writel(scontrol
, port_mmio
+ PORT_SCR_CTL
);
803 /* then set PxCMD.SUD to 0 */
804 cmd
= readl(port_mmio
+ PORT_CMD
) & ~PORT_CMD_ICC_MASK
;
805 cmd
&= ~PORT_CMD_SPIN_UP
;
806 writel(cmd
, port_mmio
+ PORT_CMD
);
810 static void ahci_start_port(struct ata_port
*ap
)
812 struct ahci_port_priv
*pp
= ap
->private_data
;
813 struct ata_link
*link
;
814 struct ahci_em_priv
*emp
;
818 /* enable FIS reception */
819 ahci_start_fis_rx(ap
);
822 ahci_start_engine(ap
);
825 if (ap
->flags
& ATA_FLAG_EM
) {
826 ata_for_each_link(link
, ap
, EDGE
) {
827 emp
= &pp
->em_priv
[link
->pmp
];
829 /* EM Transmit bit maybe busy during init */
830 for (i
= 0; i
< EM_MAX_RETRY
; i
++) {
831 rc
= ahci_transmit_led_message(ap
,
842 if (ap
->flags
& ATA_FLAG_SW_ACTIVITY
)
843 ata_for_each_link(link
, ap
, EDGE
)
844 ahci_init_sw_activity(link
);
848 static int ahci_deinit_port(struct ata_port
*ap
, const char **emsg
)
853 rc
= ahci_stop_engine(ap
);
855 *emsg
= "failed to stop engine";
859 /* disable FIS reception */
860 rc
= ahci_stop_fis_rx(ap
);
862 *emsg
= "failed stop FIS RX";
869 int ahci_reset_controller(struct ata_host
*host
)
871 struct ahci_host_priv
*hpriv
= host
->private_data
;
872 void __iomem
*mmio
= hpriv
->mmio
;
875 /* we must be in AHCI mode, before using anything
876 * AHCI-specific, such as HOST_RESET.
878 ahci_enable_ahci(mmio
);
880 /* global controller reset */
881 if (!ahci_skip_host_reset
) {
882 tmp
= readl(mmio
+ HOST_CTL
);
883 if ((tmp
& HOST_RESET
) == 0) {
884 writel(tmp
| HOST_RESET
, mmio
+ HOST_CTL
);
885 readl(mmio
+ HOST_CTL
); /* flush */
889 * to perform host reset, OS should set HOST_RESET
890 * and poll until this bit is read to be "0".
891 * reset must complete within 1 second, or
892 * the hardware should be considered fried.
894 tmp
= ata_wait_register(mmio
+ HOST_CTL
, HOST_RESET
,
895 HOST_RESET
, 10, 1000);
897 if (tmp
& HOST_RESET
) {
898 dev_printk(KERN_ERR
, host
->dev
,
899 "controller reset failed (0x%x)\n", tmp
);
903 /* turn on AHCI mode */
904 ahci_enable_ahci(mmio
);
906 /* Some registers might be cleared on reset. Restore
909 ahci_restore_initial_config(host
);
911 dev_printk(KERN_INFO
, host
->dev
,
912 "skipping global host reset\n");
916 EXPORT_SYMBOL_GPL(ahci_reset_controller
);
918 static void ahci_sw_activity(struct ata_link
*link
)
920 struct ata_port
*ap
= link
->ap
;
921 struct ahci_port_priv
*pp
= ap
->private_data
;
922 struct ahci_em_priv
*emp
= &pp
->em_priv
[link
->pmp
];
924 if (!(link
->flags
& ATA_LFLAG_SW_ACTIVITY
))
928 if (!timer_pending(&emp
->timer
))
929 mod_timer(&emp
->timer
, jiffies
+ msecs_to_jiffies(10));
932 static void ahci_sw_activity_blink(unsigned long arg
)
934 struct ata_link
*link
= (struct ata_link
*)arg
;
935 struct ata_port
*ap
= link
->ap
;
936 struct ahci_port_priv
*pp
= ap
->private_data
;
937 struct ahci_em_priv
*emp
= &pp
->em_priv
[link
->pmp
];
938 unsigned long led_message
= emp
->led_state
;
939 u32 activity_led_state
;
942 led_message
&= EM_MSG_LED_VALUE
;
943 led_message
|= ap
->port_no
| (link
->pmp
<< 8);
945 /* check to see if we've had activity. If so,
946 * toggle state of LED and reset timer. If not,
947 * turn LED to desired idle state.
949 spin_lock_irqsave(ap
->lock
, flags
);
950 if (emp
->saved_activity
!= emp
->activity
) {
951 emp
->saved_activity
= emp
->activity
;
952 /* get the current LED state */
953 activity_led_state
= led_message
& EM_MSG_LED_VALUE_ON
;
955 if (activity_led_state
)
956 activity_led_state
= 0;
958 activity_led_state
= 1;
960 /* clear old state */
961 led_message
&= ~EM_MSG_LED_VALUE_ACTIVITY
;
964 led_message
|= (activity_led_state
<< 16);
965 mod_timer(&emp
->timer
, jiffies
+ msecs_to_jiffies(100));
968 led_message
&= ~EM_MSG_LED_VALUE_ACTIVITY
;
969 if (emp
->blink_policy
== BLINK_OFF
)
970 led_message
|= (1 << 16);
972 spin_unlock_irqrestore(ap
->lock
, flags
);
973 ahci_transmit_led_message(ap
, led_message
, 4);
976 static void ahci_init_sw_activity(struct ata_link
*link
)
978 struct ata_port
*ap
= link
->ap
;
979 struct ahci_port_priv
*pp
= ap
->private_data
;
980 struct ahci_em_priv
*emp
= &pp
->em_priv
[link
->pmp
];
982 /* init activity stats, setup timer */
983 emp
->saved_activity
= emp
->activity
= 0;
984 setup_timer(&emp
->timer
, ahci_sw_activity_blink
, (unsigned long)link
);
986 /* check our blink policy and set flag for link if it's enabled */
987 if (emp
->blink_policy
)
988 link
->flags
|= ATA_LFLAG_SW_ACTIVITY
;
991 int ahci_reset_em(struct ata_host
*host
)
993 struct ahci_host_priv
*hpriv
= host
->private_data
;
994 void __iomem
*mmio
= hpriv
->mmio
;
997 em_ctl
= readl(mmio
+ HOST_EM_CTL
);
998 if ((em_ctl
& EM_CTL_TM
) || (em_ctl
& EM_CTL_RST
))
1001 writel(em_ctl
| EM_CTL_RST
, mmio
+ HOST_EM_CTL
);
1004 EXPORT_SYMBOL_GPL(ahci_reset_em
);
1006 static ssize_t
ahci_transmit_led_message(struct ata_port
*ap
, u32 state
,
1009 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1010 struct ahci_port_priv
*pp
= ap
->private_data
;
1011 void __iomem
*mmio
= hpriv
->mmio
;
1013 u32 message
[] = {0, 0};
1014 unsigned long flags
;
1016 struct ahci_em_priv
*emp
;
1018 /* get the slot number from the message */
1019 pmp
= (state
& EM_MSG_LED_PMP_SLOT
) >> 8;
1020 if (pmp
< EM_MAX_SLOTS
)
1021 emp
= &pp
->em_priv
[pmp
];
1025 spin_lock_irqsave(ap
->lock
, flags
);
1028 * if we are still busy transmitting a previous message,
1031 em_ctl
= readl(mmio
+ HOST_EM_CTL
);
1032 if (em_ctl
& EM_CTL_TM
) {
1033 spin_unlock_irqrestore(ap
->lock
, flags
);
1037 if (hpriv
->em_msg_type
& EM_MSG_TYPE_LED
) {
1039 * create message header - this is all zero except for
1040 * the message size, which is 4 bytes.
1042 message
[0] |= (4 << 8);
1044 /* ignore 0:4 of byte zero, fill in port info yourself */
1045 message
[1] = ((state
& ~EM_MSG_LED_HBA_PORT
) | ap
->port_no
);
1047 /* write message to EM_LOC */
1048 writel(message
[0], mmio
+ hpriv
->em_loc
);
1049 writel(message
[1], mmio
+ hpriv
->em_loc
+4);
1052 * tell hardware to transmit the message
1054 writel(em_ctl
| EM_CTL_TM
, mmio
+ HOST_EM_CTL
);
1057 /* save off new led state for port/slot */
1058 emp
->led_state
= state
;
1060 spin_unlock_irqrestore(ap
->lock
, flags
);
1064 static ssize_t
ahci_led_show(struct ata_port
*ap
, char *buf
)
1066 struct ahci_port_priv
*pp
= ap
->private_data
;
1067 struct ata_link
*link
;
1068 struct ahci_em_priv
*emp
;
1071 ata_for_each_link(link
, ap
, EDGE
) {
1072 emp
= &pp
->em_priv
[link
->pmp
];
1073 rc
+= sprintf(buf
, "%lx\n", emp
->led_state
);
1078 static ssize_t
ahci_led_store(struct ata_port
*ap
, const char *buf
,
1083 struct ahci_port_priv
*pp
= ap
->private_data
;
1084 struct ahci_em_priv
*emp
;
1086 state
= simple_strtoul(buf
, NULL
, 0);
1088 /* get the slot number from the message */
1089 pmp
= (state
& EM_MSG_LED_PMP_SLOT
) >> 8;
1090 if (pmp
< EM_MAX_SLOTS
)
1091 emp
= &pp
->em_priv
[pmp
];
1095 /* mask off the activity bits if we are in sw_activity
1096 * mode, user should turn off sw_activity before setting
1097 * activity led through em_message
1099 if (emp
->blink_policy
)
1100 state
&= ~EM_MSG_LED_VALUE_ACTIVITY
;
1102 return ahci_transmit_led_message(ap
, state
, size
);
1105 static ssize_t
ahci_activity_store(struct ata_device
*dev
, enum sw_activity val
)
1107 struct ata_link
*link
= dev
->link
;
1108 struct ata_port
*ap
= link
->ap
;
1109 struct ahci_port_priv
*pp
= ap
->private_data
;
1110 struct ahci_em_priv
*emp
= &pp
->em_priv
[link
->pmp
];
1111 u32 port_led_state
= emp
->led_state
;
1113 /* save the desired Activity LED behavior */
1116 link
->flags
&= ~(ATA_LFLAG_SW_ACTIVITY
);
1118 /* set the LED to OFF */
1119 port_led_state
&= EM_MSG_LED_VALUE_OFF
;
1120 port_led_state
|= (ap
->port_no
| (link
->pmp
<< 8));
1121 ahci_transmit_led_message(ap
, port_led_state
, 4);
1123 link
->flags
|= ATA_LFLAG_SW_ACTIVITY
;
1124 if (val
== BLINK_OFF
) {
1125 /* set LED to ON for idle */
1126 port_led_state
&= EM_MSG_LED_VALUE_OFF
;
1127 port_led_state
|= (ap
->port_no
| (link
->pmp
<< 8));
1128 port_led_state
|= EM_MSG_LED_VALUE_ON
; /* check this */
1129 ahci_transmit_led_message(ap
, port_led_state
, 4);
1132 emp
->blink_policy
= val
;
1136 static ssize_t
ahci_activity_show(struct ata_device
*dev
, char *buf
)
1138 struct ata_link
*link
= dev
->link
;
1139 struct ata_port
*ap
= link
->ap
;
1140 struct ahci_port_priv
*pp
= ap
->private_data
;
1141 struct ahci_em_priv
*emp
= &pp
->em_priv
[link
->pmp
];
1143 /* display the saved value of activity behavior for this
1146 return sprintf(buf
, "%d\n", emp
->blink_policy
);
1149 static void ahci_port_init(struct device
*dev
, struct ata_port
*ap
,
1150 int port_no
, void __iomem
*mmio
,
1151 void __iomem
*port_mmio
)
1153 const char *emsg
= NULL
;
1157 /* make sure port is not active */
1158 rc
= ahci_deinit_port(ap
, &emsg
);
1160 dev_warn(dev
, "%s (%d)\n", emsg
, rc
);
1163 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
1164 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp
);
1165 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
1167 /* clear port IRQ */
1168 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
1169 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp
);
1171 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
1173 writel(1 << port_no
, mmio
+ HOST_IRQ_STAT
);
1176 void ahci_init_controller(struct ata_host
*host
)
1178 struct ahci_host_priv
*hpriv
= host
->private_data
;
1179 void __iomem
*mmio
= hpriv
->mmio
;
1181 void __iomem
*port_mmio
;
1184 for (i
= 0; i
< host
->n_ports
; i
++) {
1185 struct ata_port
*ap
= host
->ports
[i
];
1187 port_mmio
= ahci_port_base(ap
);
1188 if (ata_port_is_dummy(ap
))
1191 ahci_port_init(host
->dev
, ap
, i
, mmio
, port_mmio
);
1194 tmp
= readl(mmio
+ HOST_CTL
);
1195 VPRINTK("HOST_CTL 0x%x\n", tmp
);
1196 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
1197 tmp
= readl(mmio
+ HOST_CTL
);
1198 VPRINTK("HOST_CTL 0x%x\n", tmp
);
1200 EXPORT_SYMBOL_GPL(ahci_init_controller
);
1202 static void ahci_dev_config(struct ata_device
*dev
)
1204 struct ahci_host_priv
*hpriv
= dev
->link
->ap
->host
->private_data
;
1206 if (hpriv
->flags
& AHCI_HFLAG_SECT255
) {
1207 dev
->max_sectors
= 255;
1208 ata_dev_printk(dev
, KERN_INFO
,
1209 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1213 static unsigned int ahci_dev_classify(struct ata_port
*ap
)
1215 void __iomem
*port_mmio
= ahci_port_base(ap
);
1216 struct ata_taskfile tf
;
1219 tmp
= readl(port_mmio
+ PORT_SIG
);
1220 tf
.lbah
= (tmp
>> 24) & 0xff;
1221 tf
.lbam
= (tmp
>> 16) & 0xff;
1222 tf
.lbal
= (tmp
>> 8) & 0xff;
1223 tf
.nsect
= (tmp
) & 0xff;
1225 return ata_dev_classify(&tf
);
1228 static void ahci_fill_cmd_slot(struct ahci_port_priv
*pp
, unsigned int tag
,
1231 dma_addr_t cmd_tbl_dma
;
1233 cmd_tbl_dma
= pp
->cmd_tbl_dma
+ tag
* AHCI_CMD_TBL_SZ
;
1235 pp
->cmd_slot
[tag
].opts
= cpu_to_le32(opts
);
1236 pp
->cmd_slot
[tag
].status
= 0;
1237 pp
->cmd_slot
[tag
].tbl_addr
= cpu_to_le32(cmd_tbl_dma
& 0xffffffff);
1238 pp
->cmd_slot
[tag
].tbl_addr_hi
= cpu_to_le32((cmd_tbl_dma
>> 16) >> 16);
1241 int ahci_kick_engine(struct ata_port
*ap
)
1243 void __iomem
*port_mmio
= ahci_port_base(ap
);
1244 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1245 u8 status
= readl(port_mmio
+ PORT_TFDATA
) & 0xFF;
1250 rc
= ahci_stop_engine(ap
);
1255 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1257 busy
= status
& (ATA_BUSY
| ATA_DRQ
);
1258 if (!busy
&& !sata_pmp_attached(ap
)) {
1263 if (!(hpriv
->cap
& HOST_CAP_CLO
)) {
1269 tmp
= readl(port_mmio
+ PORT_CMD
);
1270 tmp
|= PORT_CMD_CLO
;
1271 writel(tmp
, port_mmio
+ PORT_CMD
);
1274 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
,
1275 PORT_CMD_CLO
, PORT_CMD_CLO
, 1, 500);
1276 if (tmp
& PORT_CMD_CLO
)
1279 /* restart engine */
1281 ahci_start_engine(ap
);
1284 EXPORT_SYMBOL_GPL(ahci_kick_engine
);
1286 static int ahci_exec_polled_cmd(struct ata_port
*ap
, int pmp
,
1287 struct ata_taskfile
*tf
, int is_cmd
, u16 flags
,
1288 unsigned long timeout_msec
)
1290 const u32 cmd_fis_len
= 5; /* five dwords */
1291 struct ahci_port_priv
*pp
= ap
->private_data
;
1292 void __iomem
*port_mmio
= ahci_port_base(ap
);
1293 u8
*fis
= pp
->cmd_tbl
;
1296 /* prep the command */
1297 ata_tf_to_fis(tf
, pmp
, is_cmd
, fis
);
1298 ahci_fill_cmd_slot(pp
, 0, cmd_fis_len
| flags
| (pmp
<< 12));
1301 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
1304 tmp
= ata_wait_register(port_mmio
+ PORT_CMD_ISSUE
, 0x1, 0x1,
1307 ahci_kick_engine(ap
);
1311 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
1316 int ahci_do_softreset(struct ata_link
*link
, unsigned int *class,
1317 int pmp
, unsigned long deadline
,
1318 int (*check_ready
)(struct ata_link
*link
))
1320 struct ata_port
*ap
= link
->ap
;
1321 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1322 const char *reason
= NULL
;
1323 unsigned long now
, msecs
;
1324 struct ata_taskfile tf
;
1329 /* prepare for SRST (AHCI-1.1 10.4.1) */
1330 rc
= ahci_kick_engine(ap
);
1331 if (rc
&& rc
!= -EOPNOTSUPP
)
1332 ata_link_printk(link
, KERN_WARNING
,
1333 "failed to reset engine (errno=%d)\n", rc
);
1335 ata_tf_init(link
->device
, &tf
);
1337 /* issue the first D2H Register FIS */
1340 if (time_after(now
, deadline
))
1341 msecs
= jiffies_to_msecs(deadline
- now
);
1344 if (ahci_exec_polled_cmd(ap
, pmp
, &tf
, 0,
1345 AHCI_CMD_RESET
| AHCI_CMD_CLR_BUSY
, msecs
)) {
1347 reason
= "1st FIS failed";
1351 /* spec says at least 5us, but be generous and sleep for 1ms */
1354 /* issue the second D2H Register FIS */
1355 tf
.ctl
&= ~ATA_SRST
;
1356 ahci_exec_polled_cmd(ap
, pmp
, &tf
, 0, 0, 0);
1358 /* wait for link to become ready */
1359 rc
= ata_wait_after_reset(link
, deadline
, check_ready
);
1360 if (rc
== -EBUSY
&& hpriv
->flags
& AHCI_HFLAG_SRST_TOUT_IS_OFFLINE
) {
1362 * Workaround for cases where link online status can't
1363 * be trusted. Treat device readiness timeout as link
1366 ata_link_printk(link
, KERN_INFO
,
1367 "device not ready, treating as offline\n");
1368 *class = ATA_DEV_NONE
;
1370 /* link occupied, -ENODEV too is an error */
1371 reason
= "device not ready";
1374 *class = ahci_dev_classify(ap
);
1376 DPRINTK("EXIT, class=%u\n", *class);
1380 ata_link_printk(link
, KERN_ERR
, "softreset failed (%s)\n", reason
);
1384 int ahci_check_ready(struct ata_link
*link
)
1386 void __iomem
*port_mmio
= ahci_port_base(link
->ap
);
1387 u8 status
= readl(port_mmio
+ PORT_TFDATA
) & 0xFF;
1389 return ata_check_ready(status
);
1391 EXPORT_SYMBOL_GPL(ahci_check_ready
);
1393 static int ahci_softreset(struct ata_link
*link
, unsigned int *class,
1394 unsigned long deadline
)
1396 int pmp
= sata_srst_pmp(link
);
1400 return ahci_do_softreset(link
, class, pmp
, deadline
, ahci_check_ready
);
1402 EXPORT_SYMBOL_GPL(ahci_do_softreset
);
1404 static int ahci_hardreset(struct ata_link
*link
, unsigned int *class,
1405 unsigned long deadline
)
1407 const unsigned long *timing
= sata_ehc_deb_timing(&link
->eh_context
);
1408 struct ata_port
*ap
= link
->ap
;
1409 struct ahci_port_priv
*pp
= ap
->private_data
;
1410 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
1411 struct ata_taskfile tf
;
1417 ahci_stop_engine(ap
);
1419 /* clear D2H reception area to properly wait for D2H FIS */
1420 ata_tf_init(link
->device
, &tf
);
1422 ata_tf_to_fis(&tf
, 0, 0, d2h_fis
);
1424 rc
= sata_link_hardreset(link
, timing
, deadline
, &online
,
1427 ahci_start_engine(ap
);
1430 *class = ahci_dev_classify(ap
);
1432 DPRINTK("EXIT, rc=%d, class=%u\n", rc
, *class);
1436 static void ahci_postreset(struct ata_link
*link
, unsigned int *class)
1438 struct ata_port
*ap
= link
->ap
;
1439 void __iomem
*port_mmio
= ahci_port_base(ap
);
1442 ata_std_postreset(link
, class);
1444 /* Make sure port's ATAPI bit is set appropriately */
1445 new_tmp
= tmp
= readl(port_mmio
+ PORT_CMD
);
1446 if (*class == ATA_DEV_ATAPI
)
1447 new_tmp
|= PORT_CMD_ATAPI
;
1449 new_tmp
&= ~PORT_CMD_ATAPI
;
1450 if (new_tmp
!= tmp
) {
1451 writel(new_tmp
, port_mmio
+ PORT_CMD
);
1452 readl(port_mmio
+ PORT_CMD
); /* flush */
1456 static unsigned int ahci_fill_sg(struct ata_queued_cmd
*qc
, void *cmd_tbl
)
1458 struct scatterlist
*sg
;
1459 struct ahci_sg
*ahci_sg
= cmd_tbl
+ AHCI_CMD_TBL_HDR_SZ
;
1465 * Next, the S/G list.
1467 for_each_sg(qc
->sg
, sg
, qc
->n_elem
, si
) {
1468 dma_addr_t addr
= sg_dma_address(sg
);
1469 u32 sg_len
= sg_dma_len(sg
);
1471 ahci_sg
[si
].addr
= cpu_to_le32(addr
& 0xffffffff);
1472 ahci_sg
[si
].addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
1473 ahci_sg
[si
].flags_size
= cpu_to_le32(sg_len
- 1);
1479 static int ahci_pmp_qc_defer(struct ata_queued_cmd
*qc
)
1481 struct ata_port
*ap
= qc
->ap
;
1482 struct ahci_port_priv
*pp
= ap
->private_data
;
1484 if (!sata_pmp_attached(ap
) || pp
->fbs_enabled
)
1485 return ata_std_qc_defer(qc
);
1487 return sata_pmp_qc_defer_cmd_switch(qc
);
1490 static void ahci_qc_prep(struct ata_queued_cmd
*qc
)
1492 struct ata_port
*ap
= qc
->ap
;
1493 struct ahci_port_priv
*pp
= ap
->private_data
;
1494 int is_atapi
= ata_is_atapi(qc
->tf
.protocol
);
1497 const u32 cmd_fis_len
= 5; /* five dwords */
1498 unsigned int n_elem
;
1501 * Fill in command table information. First, the header,
1502 * a SATA Register - Host to Device command FIS.
1504 cmd_tbl
= pp
->cmd_tbl
+ qc
->tag
* AHCI_CMD_TBL_SZ
;
1506 ata_tf_to_fis(&qc
->tf
, qc
->dev
->link
->pmp
, 1, cmd_tbl
);
1508 memset(cmd_tbl
+ AHCI_CMD_TBL_CDB
, 0, 32);
1509 memcpy(cmd_tbl
+ AHCI_CMD_TBL_CDB
, qc
->cdb
, qc
->dev
->cdb_len
);
1513 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
1514 n_elem
= ahci_fill_sg(qc
, cmd_tbl
);
1517 * Fill in command slot information.
1519 opts
= cmd_fis_len
| n_elem
<< 16 | (qc
->dev
->link
->pmp
<< 12);
1520 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
1521 opts
|= AHCI_CMD_WRITE
;
1523 opts
|= AHCI_CMD_ATAPI
| AHCI_CMD_PREFETCH
;
1525 ahci_fill_cmd_slot(pp
, qc
->tag
, opts
);
1528 static void ahci_fbs_dec_intr(struct ata_port
*ap
)
1530 struct ahci_port_priv
*pp
= ap
->private_data
;
1531 void __iomem
*port_mmio
= ahci_port_base(ap
);
1532 u32 fbs
= readl(port_mmio
+ PORT_FBS
);
1536 BUG_ON(!pp
->fbs_enabled
);
1538 /* time to wait for DEC is not specified by AHCI spec,
1539 * add a retry loop for safety.
1541 writel(fbs
| PORT_FBS_DEC
, port_mmio
+ PORT_FBS
);
1542 fbs
= readl(port_mmio
+ PORT_FBS
);
1543 while ((fbs
& PORT_FBS_DEC
) && retries
--) {
1545 fbs
= readl(port_mmio
+ PORT_FBS
);
1548 if (fbs
& PORT_FBS_DEC
)
1549 dev_printk(KERN_ERR
, ap
->host
->dev
,
1550 "failed to clear device error\n");
1553 static void ahci_error_intr(struct ata_port
*ap
, u32 irq_stat
)
1555 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1556 struct ahci_port_priv
*pp
= ap
->private_data
;
1557 struct ata_eh_info
*host_ehi
= &ap
->link
.eh_info
;
1558 struct ata_link
*link
= NULL
;
1559 struct ata_queued_cmd
*active_qc
;
1560 struct ata_eh_info
*active_ehi
;
1561 bool fbs_need_dec
= false;
1564 /* determine active link with error */
1565 if (pp
->fbs_enabled
) {
1566 void __iomem
*port_mmio
= ahci_port_base(ap
);
1567 u32 fbs
= readl(port_mmio
+ PORT_FBS
);
1568 int pmp
= fbs
>> PORT_FBS_DWE_OFFSET
;
1570 if ((fbs
& PORT_FBS_SDE
) && (pmp
< ap
->nr_pmp_links
) &&
1571 ata_link_online(&ap
->pmp_link
[pmp
])) {
1572 link
= &ap
->pmp_link
[pmp
];
1573 fbs_need_dec
= true;
1577 ata_for_each_link(link
, ap
, EDGE
)
1578 if (ata_link_active(link
))
1584 active_qc
= ata_qc_from_tag(ap
, link
->active_tag
);
1585 active_ehi
= &link
->eh_info
;
1587 /* record irq stat */
1588 ata_ehi_clear_desc(host_ehi
);
1589 ata_ehi_push_desc(host_ehi
, "irq_stat 0x%08x", irq_stat
);
1591 /* AHCI needs SError cleared; otherwise, it might lock up */
1592 ahci_scr_read(&ap
->link
, SCR_ERROR
, &serror
);
1593 ahci_scr_write(&ap
->link
, SCR_ERROR
, serror
);
1594 host_ehi
->serror
|= serror
;
1596 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1597 if (hpriv
->flags
& AHCI_HFLAG_IGN_IRQ_IF_ERR
)
1598 irq_stat
&= ~PORT_IRQ_IF_ERR
;
1600 if (irq_stat
& PORT_IRQ_TF_ERR
) {
1601 /* If qc is active, charge it; otherwise, the active
1602 * link. There's no active qc on NCQ errors. It will
1603 * be determined by EH by reading log page 10h.
1606 active_qc
->err_mask
|= AC_ERR_DEV
;
1608 active_ehi
->err_mask
|= AC_ERR_DEV
;
1610 if (hpriv
->flags
& AHCI_HFLAG_IGN_SERR_INTERNAL
)
1611 host_ehi
->serror
&= ~SERR_INTERNAL
;
1614 if (irq_stat
& PORT_IRQ_UNK_FIS
) {
1615 u32
*unk
= (u32
*)(pp
->rx_fis
+ RX_FIS_UNK
);
1617 active_ehi
->err_mask
|= AC_ERR_HSM
;
1618 active_ehi
->action
|= ATA_EH_RESET
;
1619 ata_ehi_push_desc(active_ehi
,
1620 "unknown FIS %08x %08x %08x %08x" ,
1621 unk
[0], unk
[1], unk
[2], unk
[3]);
1624 if (sata_pmp_attached(ap
) && (irq_stat
& PORT_IRQ_BAD_PMP
)) {
1625 active_ehi
->err_mask
|= AC_ERR_HSM
;
1626 active_ehi
->action
|= ATA_EH_RESET
;
1627 ata_ehi_push_desc(active_ehi
, "incorrect PMP");
1630 if (irq_stat
& (PORT_IRQ_HBUS_ERR
| PORT_IRQ_HBUS_DATA_ERR
)) {
1631 host_ehi
->err_mask
|= AC_ERR_HOST_BUS
;
1632 host_ehi
->action
|= ATA_EH_RESET
;
1633 ata_ehi_push_desc(host_ehi
, "host bus error");
1636 if (irq_stat
& PORT_IRQ_IF_ERR
) {
1638 active_ehi
->err_mask
|= AC_ERR_DEV
;
1640 host_ehi
->err_mask
|= AC_ERR_ATA_BUS
;
1641 host_ehi
->action
|= ATA_EH_RESET
;
1644 ata_ehi_push_desc(host_ehi
, "interface fatal error");
1647 if (irq_stat
& (PORT_IRQ_CONNECT
| PORT_IRQ_PHYRDY
)) {
1648 ata_ehi_hotplugged(host_ehi
);
1649 ata_ehi_push_desc(host_ehi
, "%s",
1650 irq_stat
& PORT_IRQ_CONNECT
?
1651 "connection status changed" : "PHY RDY changed");
1654 /* okay, let's hand over to EH */
1656 if (irq_stat
& PORT_IRQ_FREEZE
)
1657 ata_port_freeze(ap
);
1658 else if (fbs_need_dec
) {
1659 ata_link_abort(link
);
1660 ahci_fbs_dec_intr(ap
);
1665 static void ahci_port_intr(struct ata_port
*ap
)
1667 void __iomem
*port_mmio
= ahci_port_base(ap
);
1668 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
1669 struct ahci_port_priv
*pp
= ap
->private_data
;
1670 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1671 int resetting
= !!(ap
->pflags
& ATA_PFLAG_RESETTING
);
1672 u32 status
, qc_active
= 0;
1675 status
= readl(port_mmio
+ PORT_IRQ_STAT
);
1676 writel(status
, port_mmio
+ PORT_IRQ_STAT
);
1678 /* ignore BAD_PMP while resetting */
1679 if (unlikely(resetting
))
1680 status
&= ~PORT_IRQ_BAD_PMP
;
1682 /* If we are getting PhyRdy, this is
1683 * just a power state change, we should
1684 * clear out this, plus the PhyRdy/Comm
1685 * Wake bits from Serror
1687 if ((hpriv
->flags
& AHCI_HFLAG_NO_HOTPLUG
) &&
1688 (status
& PORT_IRQ_PHYRDY
)) {
1689 status
&= ~PORT_IRQ_PHYRDY
;
1690 ahci_scr_write(&ap
->link
, SCR_ERROR
, ((1 << 16) | (1 << 18)));
1693 if (unlikely(status
& PORT_IRQ_ERROR
)) {
1694 ahci_error_intr(ap
, status
);
1698 if (status
& PORT_IRQ_SDB_FIS
) {
1699 /* If SNotification is available, leave notification
1700 * handling to sata_async_notification(). If not,
1701 * emulate it by snooping SDB FIS RX area.
1703 * Snooping FIS RX area is probably cheaper than
1704 * poking SNotification but some constrollers which
1705 * implement SNotification, ICH9 for example, don't
1706 * store AN SDB FIS into receive area.
1708 if (hpriv
->cap
& HOST_CAP_SNTF
)
1709 sata_async_notification(ap
);
1711 /* If the 'N' bit in word 0 of the FIS is set,
1712 * we just received asynchronous notification.
1713 * Tell libata about it.
1715 * Lack of SNotification should not appear in
1716 * ahci 1.2, so the workaround is unnecessary
1717 * when FBS is enabled.
1719 if (pp
->fbs_enabled
)
1722 const __le32
*f
= pp
->rx_fis
+ RX_FIS_SDB
;
1723 u32 f0
= le32_to_cpu(f
[0]);
1725 sata_async_notification(ap
);
1730 /* pp->active_link is not reliable once FBS is enabled, both
1731 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1732 * NCQ and non-NCQ commands may be in flight at the same time.
1734 if (pp
->fbs_enabled
) {
1735 if (ap
->qc_active
) {
1736 qc_active
= readl(port_mmio
+ PORT_SCR_ACT
);
1737 qc_active
|= readl(port_mmio
+ PORT_CMD_ISSUE
);
1740 /* pp->active_link is valid iff any command is in flight */
1741 if (ap
->qc_active
&& pp
->active_link
->sactive
)
1742 qc_active
= readl(port_mmio
+ PORT_SCR_ACT
);
1744 qc_active
= readl(port_mmio
+ PORT_CMD_ISSUE
);
1748 rc
= ata_qc_complete_multiple(ap
, qc_active
);
1750 /* while resetting, invalid completions are expected */
1751 if (unlikely(rc
< 0 && !resetting
)) {
1752 ehi
->err_mask
|= AC_ERR_HSM
;
1753 ehi
->action
|= ATA_EH_RESET
;
1754 ata_port_freeze(ap
);
1758 irqreturn_t
ahci_interrupt(int irq
, void *dev_instance
)
1760 struct ata_host
*host
= dev_instance
;
1761 struct ahci_host_priv
*hpriv
;
1762 unsigned int i
, handled
= 0;
1764 u32 irq_stat
, irq_masked
;
1768 hpriv
= host
->private_data
;
1771 /* sigh. 0xffffffff is a valid return from h/w */
1772 irq_stat
= readl(mmio
+ HOST_IRQ_STAT
);
1776 irq_masked
= irq_stat
& hpriv
->port_map
;
1778 spin_lock(&host
->lock
);
1780 for (i
= 0; i
< host
->n_ports
; i
++) {
1781 struct ata_port
*ap
;
1783 if (!(irq_masked
& (1 << i
)))
1786 ap
= host
->ports
[i
];
1789 VPRINTK("port %u\n", i
);
1791 VPRINTK("port %u (no irq)\n", i
);
1792 if (ata_ratelimit())
1793 dev_printk(KERN_WARNING
, host
->dev
,
1794 "interrupt on disabled port %u\n", i
);
1800 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1801 * it should be cleared after all the port events are cleared;
1802 * otherwise, it will raise a spurious interrupt after each
1803 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1806 * Also, use the unmasked value to clear interrupt as spurious
1807 * pending event on a dummy port might cause screaming IRQ.
1809 writel(irq_stat
, mmio
+ HOST_IRQ_STAT
);
1811 spin_unlock(&host
->lock
);
1815 return IRQ_RETVAL(handled
);
1817 EXPORT_SYMBOL_GPL(ahci_interrupt
);
1819 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
)
1821 struct ata_port
*ap
= qc
->ap
;
1822 void __iomem
*port_mmio
= ahci_port_base(ap
);
1823 struct ahci_port_priv
*pp
= ap
->private_data
;
1825 /* Keep track of the currently active link. It will be used
1826 * in completion path to determine whether NCQ phase is in
1829 pp
->active_link
= qc
->dev
->link
;
1831 if (qc
->tf
.protocol
== ATA_PROT_NCQ
)
1832 writel(1 << qc
->tag
, port_mmio
+ PORT_SCR_ACT
);
1834 if (pp
->fbs_enabled
&& pp
->fbs_last_dev
!= qc
->dev
->link
->pmp
) {
1835 u32 fbs
= readl(port_mmio
+ PORT_FBS
);
1836 fbs
&= ~(PORT_FBS_DEV_MASK
| PORT_FBS_DEC
);
1837 fbs
|= qc
->dev
->link
->pmp
<< PORT_FBS_DEV_OFFSET
;
1838 writel(fbs
, port_mmio
+ PORT_FBS
);
1839 pp
->fbs_last_dev
= qc
->dev
->link
->pmp
;
1842 writel(1 << qc
->tag
, port_mmio
+ PORT_CMD_ISSUE
);
1844 ahci_sw_activity(qc
->dev
->link
);
1849 static bool ahci_qc_fill_rtf(struct ata_queued_cmd
*qc
)
1851 struct ahci_port_priv
*pp
= qc
->ap
->private_data
;
1852 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
1854 if (pp
->fbs_enabled
)
1855 d2h_fis
+= qc
->dev
->link
->pmp
* AHCI_RX_FIS_SZ
;
1857 ata_tf_from_fis(d2h_fis
, &qc
->result_tf
);
1861 static void ahci_freeze(struct ata_port
*ap
)
1863 void __iomem
*port_mmio
= ahci_port_base(ap
);
1866 writel(0, port_mmio
+ PORT_IRQ_MASK
);
1869 static void ahci_thaw(struct ata_port
*ap
)
1871 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1872 void __iomem
*mmio
= hpriv
->mmio
;
1873 void __iomem
*port_mmio
= ahci_port_base(ap
);
1875 struct ahci_port_priv
*pp
= ap
->private_data
;
1878 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
1879 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
1880 writel(1 << ap
->port_no
, mmio
+ HOST_IRQ_STAT
);
1882 /* turn IRQ back on */
1883 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
1886 static void ahci_error_handler(struct ata_port
*ap
)
1888 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
)) {
1889 /* restart engine */
1890 ahci_stop_engine(ap
);
1891 ahci_start_engine(ap
);
1894 sata_pmp_error_handler(ap
);
1897 static void ahci_post_internal_cmd(struct ata_queued_cmd
*qc
)
1899 struct ata_port
*ap
= qc
->ap
;
1901 /* make DMA engine forget about the failed command */
1902 if (qc
->flags
& ATA_QCFLAG_FAILED
)
1903 ahci_kick_engine(ap
);
1906 static void ahci_enable_fbs(struct ata_port
*ap
)
1908 struct ahci_port_priv
*pp
= ap
->private_data
;
1909 void __iomem
*port_mmio
= ahci_port_base(ap
);
1913 if (!pp
->fbs_supported
)
1916 fbs
= readl(port_mmio
+ PORT_FBS
);
1917 if (fbs
& PORT_FBS_EN
) {
1918 pp
->fbs_enabled
= true;
1919 pp
->fbs_last_dev
= -1; /* initialization */
1923 rc
= ahci_stop_engine(ap
);
1927 writel(fbs
| PORT_FBS_EN
, port_mmio
+ PORT_FBS
);
1928 fbs
= readl(port_mmio
+ PORT_FBS
);
1929 if (fbs
& PORT_FBS_EN
) {
1930 dev_printk(KERN_INFO
, ap
->host
->dev
, "FBS is enabled.\n");
1931 pp
->fbs_enabled
= true;
1932 pp
->fbs_last_dev
= -1; /* initialization */
1934 dev_printk(KERN_ERR
, ap
->host
->dev
, "Failed to enable FBS\n");
1936 ahci_start_engine(ap
);
1939 static void ahci_disable_fbs(struct ata_port
*ap
)
1941 struct ahci_port_priv
*pp
= ap
->private_data
;
1942 void __iomem
*port_mmio
= ahci_port_base(ap
);
1946 if (!pp
->fbs_supported
)
1949 fbs
= readl(port_mmio
+ PORT_FBS
);
1950 if ((fbs
& PORT_FBS_EN
) == 0) {
1951 pp
->fbs_enabled
= false;
1955 rc
= ahci_stop_engine(ap
);
1959 writel(fbs
& ~PORT_FBS_EN
, port_mmio
+ PORT_FBS
);
1960 fbs
= readl(port_mmio
+ PORT_FBS
);
1961 if (fbs
& PORT_FBS_EN
)
1962 dev_printk(KERN_ERR
, ap
->host
->dev
, "Failed to disable FBS\n");
1964 dev_printk(KERN_INFO
, ap
->host
->dev
, "FBS is disabled.\n");
1965 pp
->fbs_enabled
= false;
1968 ahci_start_engine(ap
);
1971 static void ahci_pmp_attach(struct ata_port
*ap
)
1973 void __iomem
*port_mmio
= ahci_port_base(ap
);
1974 struct ahci_port_priv
*pp
= ap
->private_data
;
1977 cmd
= readl(port_mmio
+ PORT_CMD
);
1978 cmd
|= PORT_CMD_PMP
;
1979 writel(cmd
, port_mmio
+ PORT_CMD
);
1981 ahci_enable_fbs(ap
);
1983 pp
->intr_mask
|= PORT_IRQ_BAD_PMP
;
1984 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
1987 static void ahci_pmp_detach(struct ata_port
*ap
)
1989 void __iomem
*port_mmio
= ahci_port_base(ap
);
1990 struct ahci_port_priv
*pp
= ap
->private_data
;
1993 ahci_disable_fbs(ap
);
1995 cmd
= readl(port_mmio
+ PORT_CMD
);
1996 cmd
&= ~PORT_CMD_PMP
;
1997 writel(cmd
, port_mmio
+ PORT_CMD
);
1999 pp
->intr_mask
&= ~PORT_IRQ_BAD_PMP
;
2000 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
2003 static int ahci_port_resume(struct ata_port
*ap
)
2006 ahci_start_port(ap
);
2008 if (sata_pmp_attached(ap
))
2009 ahci_pmp_attach(ap
);
2011 ahci_pmp_detach(ap
);
2017 static int ahci_port_suspend(struct ata_port
*ap
, pm_message_t mesg
)
2019 const char *emsg
= NULL
;
2022 rc
= ahci_deinit_port(ap
, &emsg
);
2024 ahci_power_down(ap
);
2026 ata_port_printk(ap
, KERN_ERR
, "%s (%d)\n", emsg
, rc
);
2027 ahci_start_port(ap
);
2034 static int ahci_port_start(struct ata_port
*ap
)
2036 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
2037 struct device
*dev
= ap
->host
->dev
;
2038 struct ahci_port_priv
*pp
;
2041 size_t dma_sz
, rx_fis_sz
;
2043 pp
= devm_kzalloc(dev
, sizeof(*pp
), GFP_KERNEL
);
2047 /* check FBS capability */
2048 if ((hpriv
->cap
& HOST_CAP_FBS
) && sata_pmp_supported(ap
)) {
2049 void __iomem
*port_mmio
= ahci_port_base(ap
);
2050 u32 cmd
= readl(port_mmio
+ PORT_CMD
);
2051 if (cmd
& PORT_CMD_FBSCP
)
2052 pp
->fbs_supported
= true;
2054 dev_printk(KERN_WARNING
, dev
,
2055 "The port is not capable of FBS\n");
2058 if (pp
->fbs_supported
) {
2059 dma_sz
= AHCI_PORT_PRIV_FBS_DMA_SZ
;
2060 rx_fis_sz
= AHCI_RX_FIS_SZ
* 16;
2062 dma_sz
= AHCI_PORT_PRIV_DMA_SZ
;
2063 rx_fis_sz
= AHCI_RX_FIS_SZ
;
2066 mem
= dmam_alloc_coherent(dev
, dma_sz
, &mem_dma
, GFP_KERNEL
);
2069 memset(mem
, 0, dma_sz
);
2072 * First item in chunk of DMA memory: 32-slot command table,
2073 * 32 bytes each in size
2076 pp
->cmd_slot_dma
= mem_dma
;
2078 mem
+= AHCI_CMD_SLOT_SZ
;
2079 mem_dma
+= AHCI_CMD_SLOT_SZ
;
2082 * Second item: Received-FIS area
2085 pp
->rx_fis_dma
= mem_dma
;
2088 mem_dma
+= rx_fis_sz
;
2091 * Third item: data area for storing a single command
2092 * and its scatter-gather table
2095 pp
->cmd_tbl_dma
= mem_dma
;
2098 * Save off initial list of interrupts to be enabled.
2099 * This could be changed later
2101 pp
->intr_mask
= DEF_PORT_IRQ
;
2103 ap
->private_data
= pp
;
2105 /* engage engines, captain */
2106 return ahci_port_resume(ap
);
2109 static void ahci_port_stop(struct ata_port
*ap
)
2111 const char *emsg
= NULL
;
2114 /* de-initialize port */
2115 rc
= ahci_deinit_port(ap
, &emsg
);
2117 ata_port_printk(ap
, KERN_WARNING
, "%s (%d)\n", emsg
, rc
);
2120 void ahci_print_info(struct ata_host
*host
, const char *scc_s
)
2122 struct ahci_host_priv
*hpriv
= host
->private_data
;
2123 void __iomem
*mmio
= hpriv
->mmio
;
2124 u32 vers
, cap
, cap2
, impl
, speed
;
2125 const char *speed_s
;
2127 vers
= readl(mmio
+ HOST_VERSION
);
2130 impl
= hpriv
->port_map
;
2132 speed
= (cap
>> 20) & 0xf;
2135 else if (speed
== 2)
2137 else if (speed
== 3)
2143 "AHCI %02x%02x.%02x%02x "
2144 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2147 (vers
>> 24) & 0xff,
2148 (vers
>> 16) & 0xff,
2152 ((cap
>> 8) & 0x1f) + 1,
2165 cap
& HOST_CAP_64
? "64bit " : "",
2166 cap
& HOST_CAP_NCQ
? "ncq " : "",
2167 cap
& HOST_CAP_SNTF
? "sntf " : "",
2168 cap
& HOST_CAP_MPS
? "ilck " : "",
2169 cap
& HOST_CAP_SSS
? "stag " : "",
2170 cap
& HOST_CAP_ALPM
? "pm " : "",
2171 cap
& HOST_CAP_LED
? "led " : "",
2172 cap
& HOST_CAP_CLO
? "clo " : "",
2173 cap
& HOST_CAP_ONLY
? "only " : "",
2174 cap
& HOST_CAP_PMP
? "pmp " : "",
2175 cap
& HOST_CAP_FBS
? "fbs " : "",
2176 cap
& HOST_CAP_PIO_MULTI
? "pio " : "",
2177 cap
& HOST_CAP_SSC
? "slum " : "",
2178 cap
& HOST_CAP_PART
? "part " : "",
2179 cap
& HOST_CAP_CCC
? "ccc " : "",
2180 cap
& HOST_CAP_EMS
? "ems " : "",
2181 cap
& HOST_CAP_SXS
? "sxs " : "",
2182 cap2
& HOST_CAP2_APST
? "apst " : "",
2183 cap2
& HOST_CAP2_NVMHCI
? "nvmp " : "",
2184 cap2
& HOST_CAP2_BOH
? "boh " : ""
2187 EXPORT_SYMBOL_GPL(ahci_print_info
);
2189 void ahci_set_em_messages(struct ahci_host_priv
*hpriv
,
2190 struct ata_port_info
*pi
)
2193 void __iomem
*mmio
= hpriv
->mmio
;
2194 u32 em_loc
= readl(mmio
+ HOST_EM_LOC
);
2195 u32 em_ctl
= readl(mmio
+ HOST_EM_CTL
);
2197 if (!ahci_em_messages
|| !(hpriv
->cap
& HOST_CAP_EMS
))
2200 messages
= (em_ctl
& EM_CTRL_MSG_TYPE
) >> 16;
2204 hpriv
->em_loc
= ((em_loc
>> 16) * 4);
2205 hpriv
->em_buf_sz
= ((em_loc
& 0xff) * 4);
2206 hpriv
->em_msg_type
= messages
;
2207 pi
->flags
|= ATA_FLAG_EM
;
2208 if (!(em_ctl
& EM_CTL_ALHD
))
2209 pi
->flags
|= ATA_FLAG_SW_ACTIVITY
;
2212 EXPORT_SYMBOL_GPL(ahci_set_em_messages
);
2214 MODULE_AUTHOR("Jeff Garzik");
2215 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2216 MODULE_LICENSE("GPL");