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seqno mask of THM_ITV register is 16bit
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / mmc / host / sdhci.c
blob401527d273b5811e7a1981af12751ba099b490a8
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/scatterlist.h>
22 #include <linux/regulator/consumer.h>
23
24 #include <linux/leds.h>
25
26 #include <linux/mmc/host.h>
27
28 #include "sdhci.h"
29
30 #define DRIVER_NAME "sdhci"
31
32 #define DBG(f, x...) \
33 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
34
35 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
36 defined(CONFIG_MMC_SDHCI_MODULE))
37 #define SDHCI_USE_LEDS_CLASS
38 #endif
39
40 static unsigned int debug_quirks = 0;
41
42 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
43 static void sdhci_finish_data(struct sdhci_host *);
44
45 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
46 static void sdhci_finish_command(struct sdhci_host *);
47
48 static void sdhci_dumpregs(struct sdhci_host *host)
49 {
50 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
51
52 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
53 sdhci_readl(host, SDHCI_DMA_ADDRESS),
54 sdhci_readw(host, SDHCI_HOST_VERSION));
55 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
56 sdhci_readw(host, SDHCI_BLOCK_SIZE),
57 sdhci_readw(host, SDHCI_BLOCK_COUNT));
58 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
59 sdhci_readl(host, SDHCI_ARGUMENT),
60 sdhci_readw(host, SDHCI_TRANSFER_MODE));
61 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
62 sdhci_readl(host, SDHCI_PRESENT_STATE),
63 sdhci_readb(host, SDHCI_HOST_CONTROL));
64 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
65 sdhci_readb(host, SDHCI_POWER_CONTROL),
66 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
67 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
68 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
69 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
70 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
71 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
72 sdhci_readl(host, SDHCI_INT_STATUS));
73 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
74 sdhci_readl(host, SDHCI_INT_ENABLE),
75 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
76 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
77 sdhci_readw(host, SDHCI_ACMD12_ERR),
78 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
79 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
80 sdhci_readl(host, SDHCI_CAPABILITIES),
81 sdhci_readl(host, SDHCI_MAX_CURRENT));
82
83 if (host->flags & SDHCI_USE_ADMA)
84 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
85 readl(host->ioaddr + SDHCI_ADMA_ERROR),
86 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
87
88 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
89 }
90
91 /*****************************************************************************\
92 * *
93 * Low level functions *
94 * *
95 \*****************************************************************************/
96
97 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
98 {
99 u32 ier;
100
101 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
102 ier &= ~clear;
103 ier |= set;
104 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
105 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
106 }
107
108 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
109 {
110 sdhci_clear_set_irqs(host, 0, irqs);
111 }
112
113 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
114 {
115 sdhci_clear_set_irqs(host, irqs, 0);
116 }
117
118 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
119 {
120 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
121
122 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
123 return;
124
125 if (enable)
126 sdhci_unmask_irqs(host, irqs);
127 else
128 sdhci_mask_irqs(host, irqs);
129 }
130
131 static void sdhci_enable_card_detection(struct sdhci_host *host)
132 {
133 sdhci_set_card_detection(host, true);
134 }
135
136 static void sdhci_disable_card_detection(struct sdhci_host *host)
137 {
138 sdhci_set_card_detection(host, false);
139 }
140
141 static void sdhci_reset(struct sdhci_host *host, u8 mask)
142 {
143 unsigned long timeout;
144 u32 uninitialized_var(ier);
145
146 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
147 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
148 SDHCI_CARD_PRESENT))
149 return;
150 }
151
152 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
153 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
154
155 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
156
157 if (mask & SDHCI_RESET_ALL)
158 host->clock = 0;
159
160 /* Wait max 100 ms */
161 timeout = 100;
162
163 /* hw clears the bit when it's done */
164 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
165 if (timeout == 0) {
166 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
167 mmc_hostname(host->mmc), (int)mask);
168 sdhci_dumpregs(host);
169 return;
170 }
171 timeout--;
172 mdelay(1);
173 }
174
175 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
176 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
177 }
178
179 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
180
181 static void sdhci_init(struct sdhci_host *host, int soft)
182 {
183 if (soft)
184 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
185 else
186 sdhci_reset(host, SDHCI_RESET_ALL);
187
188 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
189 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
190 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
191 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
192 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
193
194 if (soft) {
195 /* force clock reconfiguration */
196 host->clock = 0;
197 sdhci_set_ios(host->mmc, &host->mmc->ios);
198 }
199 }
200
201 static void sdhci_reinit(struct sdhci_host *host)
202 {
203 sdhci_init(host, 0);
204 sdhci_enable_card_detection(host);
205 }
206
207 static void sdhci_activate_led(struct sdhci_host *host)
208 {
209 u8 ctrl;
210
211 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
212 ctrl |= SDHCI_CTRL_LED;
213 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
214 }
215
216 static void sdhci_deactivate_led(struct sdhci_host *host)
217 {
218 u8 ctrl;
219
220 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
221 ctrl &= ~SDHCI_CTRL_LED;
222 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
223 }
224
225 #ifdef SDHCI_USE_LEDS_CLASS
226 static void sdhci_led_control(struct led_classdev *led,
227 enum led_brightness brightness)
228 {
229 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
230 unsigned long flags;
231
232 spin_lock_irqsave(&host->lock, flags);
233
234 if (brightness == LED_OFF)
235 sdhci_deactivate_led(host);
236 else
237 sdhci_activate_led(host);
238
239 spin_unlock_irqrestore(&host->lock, flags);
240 }
241 #endif
242
243 /*****************************************************************************\
244 * *
245 * Core functions *
246 * *
247 \*****************************************************************************/
248
249 static void sdhci_read_block_pio(struct sdhci_host *host)
250 {
251 unsigned long flags;
252 size_t blksize, len, chunk;
253 u32 uninitialized_var(scratch);
254 u8 *buf;
255
256 DBG("PIO reading\n");
257
258 blksize = host->data->blksz;
259 chunk = 0;
260
261 local_irq_save(flags);
262
263 while (blksize) {
264 if (!sg_miter_next(&host->sg_miter))
265 BUG();
266
267 len = min(host->sg_miter.length, blksize);
268
269 blksize -= len;
270 host->sg_miter.consumed = len;
271
272 buf = host->sg_miter.addr;
273
274 while (len) {
275 if (chunk == 0) {
276 scratch = sdhci_readl(host, SDHCI_BUFFER);
277 chunk = 4;
278 }
279
280 *buf = scratch & 0xFF;
281
282 buf++;
283 scratch >>= 8;
284 chunk--;
285 len--;
286 }
287 }
288
289 sg_miter_stop(&host->sg_miter);
290
291 local_irq_restore(flags);
292 }
293
294 static void sdhci_write_block_pio(struct sdhci_host *host)
295 {
296 unsigned long flags;
297 size_t blksize, len, chunk;
298 u32 scratch;
299 u8 *buf;
300
301 DBG("PIO writing\n");
302
303 blksize = host->data->blksz;
304 chunk = 0;
305 scratch = 0;
306
307 local_irq_save(flags);
308
309 while (blksize) {
310 if (!sg_miter_next(&host->sg_miter))
311 BUG();
312
313 len = min(host->sg_miter.length, blksize);
314
315 blksize -= len;
316 host->sg_miter.consumed = len;
317
318 buf = host->sg_miter.addr;
319
320 while (len) {
321 scratch |= (u32)*buf << (chunk * 8);
322
323 buf++;
324 chunk++;
325 len--;
326
327 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
328 sdhci_writel(host, scratch, SDHCI_BUFFER);
329 chunk = 0;
330 scratch = 0;
331 }
332 }
333 }
334
335 sg_miter_stop(&host->sg_miter);
336
337 local_irq_restore(flags);
338 }
339
340 static void sdhci_transfer_pio(struct sdhci_host *host)
341 {
342 u32 mask;
343
344 BUG_ON(!host->data);
345
346 if (host->blocks == 0)
347 return;
348
349 if (host->data->flags & MMC_DATA_READ)
350 mask = SDHCI_DATA_AVAILABLE;
351 else
352 mask = SDHCI_SPACE_AVAILABLE;
353
354 /*
355 * Some controllers (JMicron JMB38x) mess up the buffer bits
356 * for transfers < 4 bytes. As long as it is just one block,
357 * we can ignore the bits.
358 */
359 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
360 (host->data->blocks == 1))
361 mask = ~0;
362
363 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
364 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
365 udelay(100);
366
367 if (host->data->flags & MMC_DATA_READ)
368 sdhci_read_block_pio(host);
369 else
370 sdhci_write_block_pio(host);
371
372 host->blocks--;
373 if (host->blocks == 0)
374 break;
375 }
376
377 DBG("PIO transfer complete.\n");
378 }
379
380 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
381 {
382 local_irq_save(*flags);
383 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
384 }
385
386 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
387 {
388 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
389 local_irq_restore(*flags);
390 }
391
392 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
393 {
394 __le32 *dataddr = (__le32 __force *)(desc + 4);
395 __le16 *cmdlen = (__le16 __force *)desc;
396
397 /* SDHCI specification says ADMA descriptors should be 4 byte
398 * aligned, so using 16 or 32bit operations should be safe. */
399
400 cmdlen[0] = cpu_to_le16(cmd);
401 cmdlen[1] = cpu_to_le16(len);
402
403 dataddr[0] = cpu_to_le32(addr);
404 }
405
406 static int sdhci_adma_table_pre(struct sdhci_host *host,
407 struct mmc_data *data)
408 {
409 int direction;
410
411 u8 *desc;
412 u8 *align;
413 dma_addr_t addr;
414 dma_addr_t align_addr;
415 int len, offset;
416
417 struct scatterlist *sg;
418 int i;
419 char *buffer;
420 unsigned long flags;
421
422 /*
423 * The spec does not specify endianness of descriptor table.
424 * We currently guess that it is LE.
425 */
426
427 if (data->flags & MMC_DATA_READ)
428 direction = DMA_FROM_DEVICE;
429 else
430 direction = DMA_TO_DEVICE;
431
432 /*
433 * The ADMA descriptor table is mapped further down as we
434 * need to fill it with data first.
435 */
436
437 host->align_addr = dma_map_single(mmc_dev(host->mmc),
438 host->align_buffer, 128 * 4, direction);
439 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
440 goto fail;
441 BUG_ON(host->align_addr & 0x3);
442
443 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
444 data->sg, data->sg_len, direction);
445 if (host->sg_count == 0)
446 goto unmap_align;
447
448 desc = host->adma_desc;
449 align = host->align_buffer;
450
451 align_addr = host->align_addr;
452
453 for_each_sg(data->sg, sg, host->sg_count, i) {
454 addr = sg_dma_address(sg);
455 len = sg_dma_len(sg);
456
457 /*
458 * The SDHCI specification states that ADMA
459 * addresses must be 32-bit aligned. If they
460 * aren't, then we use a bounce buffer for
461 * the (up to three) bytes that screw up the
462 * alignment.
463 */
464 offset = (4 - (addr & 0x3)) & 0x3;
465 if (offset) {
466 if (data->flags & MMC_DATA_WRITE) {
467 buffer = sdhci_kmap_atomic(sg, &flags);
468 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
469 memcpy(align, buffer, offset);
470 sdhci_kunmap_atomic(buffer, &flags);
471 }
472
473 /* tran, valid */
474 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
475
476 BUG_ON(offset > 65536);
477
478 align += 4;
479 align_addr += 4;
480
481 desc += 8;
482
483 addr += offset;
484 len -= offset;
485 }
486
487 BUG_ON(len > 65536);
488
489 /* tran, valid */
490 sdhci_set_adma_desc(desc, addr, len, 0x21);
491 desc += 8;
492
493 /*
494 * If this triggers then we have a calculation bug
495 * somewhere. :/
496 */
497 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
498 }
499
500 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
501 /*
502 * Mark the last descriptor as the terminating descriptor
503 */
504 if (desc != host->adma_desc) {
505 desc -= 8;
506 desc[0] |= 0x2; /* end */
507 }
508 } else {
509 /*
510 * Add a terminating entry.
511 */
512
513 /* nop, end, valid */
514 sdhci_set_adma_desc(desc, 0, 0, 0x3);
515 }
516
517 /*
518 * Resync align buffer as we might have changed it.
519 */
520 if (data->flags & MMC_DATA_WRITE) {
521 dma_sync_single_for_device(mmc_dev(host->mmc),
522 host->align_addr, 128 * 4, direction);
523 }
524
525 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
526 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
527 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
528 goto unmap_entries;
529 BUG_ON(host->adma_addr & 0x3);
530
531 return 0;
532
533 unmap_entries:
534 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
535 data->sg_len, direction);
536 unmap_align:
537 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
538 128 * 4, direction);
539 fail:
540 return -EINVAL;
541 }
542
543 static void sdhci_adma_table_post(struct sdhci_host *host,
544 struct mmc_data *data)
545 {
546 int direction;
547
548 struct scatterlist *sg;
549 int i, size;
550 u8 *align;
551 char *buffer;
552 unsigned long flags;
553
554 if (data->flags & MMC_DATA_READ)
555 direction = DMA_FROM_DEVICE;
556 else
557 direction = DMA_TO_DEVICE;
558
559 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
560 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
561
562 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
563 128 * 4, direction);
564
565 if (data->flags & MMC_DATA_READ) {
566 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
567 data->sg_len, direction);
568
569 align = host->align_buffer;
570
571 for_each_sg(data->sg, sg, host->sg_count, i) {
572 if (sg_dma_address(sg) & 0x3) {
573 size = 4 - (sg_dma_address(sg) & 0x3);
574
575 buffer = sdhci_kmap_atomic(sg, &flags);
576 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
577 memcpy(buffer, align, size);
578 sdhci_kunmap_atomic(buffer, &flags);
579
580 align += 4;
581 }
582 }
583 }
584
585 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
586 data->sg_len, direction);
587 }
588
589 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
590 {
591 u8 count;
592 unsigned target_timeout, current_timeout;
593
594 /*
595 * If the host controller provides us with an incorrect timeout
596 * value, just skip the check and use 0xE. The hardware may take
597 * longer to time out, but that's much better than having a too-short
598 * timeout value.
599 */
600 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
601 return 0xE;
602
603 /* timeout in us */
604 target_timeout = data->timeout_ns / 1000 +
605 data->timeout_clks / host->clock;
606
607 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
608 host->timeout_clk = host->clock / 1000;
609
610 /*
611 * Figure out needed cycles.
612 * We do this in steps in order to fit inside a 32 bit int.
613 * The first step is the minimum timeout, which will have a
614 * minimum resolution of 6 bits:
615 * (1) 2^13*1000 > 2^22,
616 * (2) host->timeout_clk < 2^16
617 * =>
618 * (1) / (2) > 2^6
619 */
620 count = 0;
621 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
622 while (current_timeout < target_timeout) {
623 count++;
624 current_timeout <<= 1;
625 if (count >= 0xF)
626 break;
627 }
628
629 if (count >= 0xF) {
630 printk(KERN_WARNING "%s: Too large timeout requested!\n",
631 mmc_hostname(host->mmc));
632 count = 0xE;
633 }
634
635 return count;
636 }
637
638 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
639 {
640 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
641 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
642
643 if (host->flags & SDHCI_REQ_USE_DMA)
644 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
645 else
646 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
647 }
648
649 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
650 {
651 u8 count;
652 u8 ctrl;
653 int ret;
654
655 WARN_ON(host->data);
656
657 if (data == NULL)
658 return;
659
660 /* Sanity checks */
661 BUG_ON(data->blksz * data->blocks > 524288);
662 BUG_ON(data->blksz > host->mmc->max_blk_size);
663 BUG_ON(data->blocks > 65535);
664
665 host->data = data;
666 host->data_early = 0;
667
668 count = sdhci_calc_timeout(host, data);
669 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
670
671 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
672 host->flags |= SDHCI_REQ_USE_DMA;
673
674 /*
675 * FIXME: This doesn't account for merging when mapping the
676 * scatterlist.
677 */
678 if (host->flags & SDHCI_REQ_USE_DMA) {
679 int broken, i;
680 struct scatterlist *sg;
681
682 broken = 0;
683 if (host->flags & SDHCI_USE_ADMA) {
684 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
685 broken = 1;
686 } else {
687 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
688 broken = 1;
689 }
690
691 if (unlikely(broken)) {
692 for_each_sg(data->sg, sg, data->sg_len, i) {
693 if (sg->length & 0x3) {
694 DBG("Reverting to PIO because of "
695 "transfer size (%d)\n",
696 sg->length);
697 host->flags &= ~SDHCI_REQ_USE_DMA;
698 break;
699 }
700 }
701 }
702 }
703
704 /*
705 * The assumption here being that alignment is the same after
706 * translation to device address space.
707 */
708 if (host->flags & SDHCI_REQ_USE_DMA) {
709 int broken, i;
710 struct scatterlist *sg;
711
712 broken = 0;
713 if (host->flags & SDHCI_USE_ADMA) {
714 /*
715 * As we use 3 byte chunks to work around
716 * alignment problems, we need to check this
717 * quirk.
718 */
719 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
720 broken = 1;
721 } else {
722 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
723 broken = 1;
724 }
725
726 if (unlikely(broken)) {
727 for_each_sg(data->sg, sg, data->sg_len, i) {
728 if (sg->offset & 0x3) {
729 DBG("Reverting to PIO because of "
730 "bad alignment\n");
731 host->flags &= ~SDHCI_REQ_USE_DMA;
732 break;
733 }
734 }
735 }
736 }
737
738 if (host->flags & SDHCI_REQ_USE_DMA) {
739 if (host->flags & SDHCI_USE_ADMA) {
740 ret = sdhci_adma_table_pre(host, data);
741 if (ret) {
742 /*
743 * This only happens when someone fed
744 * us an invalid request.
745 */
746 WARN_ON(1);
747 host->flags &= ~SDHCI_REQ_USE_DMA;
748 } else {
749 sdhci_writel(host, host->adma_addr,
750 SDHCI_ADMA_ADDRESS);
751 }
752 } else {
753 int sg_cnt;
754
755 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
756 data->sg, data->sg_len,
757 (data->flags & MMC_DATA_READ) ?
758 DMA_FROM_DEVICE :
759 DMA_TO_DEVICE);
760 if (sg_cnt == 0) {
761 /*
762 * This only happens when someone fed
763 * us an invalid request.
764 */
765 WARN_ON(1);
766 host->flags &= ~SDHCI_REQ_USE_DMA;
767 } else {
768 WARN_ON(sg_cnt != 1);
769 sdhci_writel(host, sg_dma_address(data->sg),
770 SDHCI_DMA_ADDRESS);
771 }
772 }
773 }
774
775 /*
776 * Always adjust the DMA selection as some controllers
777 * (e.g. JMicron) can't do PIO properly when the selection
778 * is ADMA.
779 */
780 if (host->version >= SDHCI_SPEC_200) {
781 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
782 ctrl &= ~SDHCI_CTRL_DMA_MASK;
783 if ((host->flags & SDHCI_REQ_USE_DMA) &&
784 (host->flags & SDHCI_USE_ADMA))
785 ctrl |= SDHCI_CTRL_ADMA32;
786 else
787 ctrl |= SDHCI_CTRL_SDMA;
788 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
789 }
790
791 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
792 int flags;
793
794 flags = SG_MITER_ATOMIC;
795 if (host->data->flags & MMC_DATA_READ)
796 flags |= SG_MITER_TO_SG;
797 else
798 flags |= SG_MITER_FROM_SG;
799 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
800 host->blocks = data->blocks;
801 }
802
803 sdhci_set_transfer_irqs(host);
804
805 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
806 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
807 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
808 }
809
810 static void sdhci_set_transfer_mode(struct sdhci_host *host,
811 struct mmc_data *data)
812 {
813 u16 mode;
814
815 if (data == NULL)
816 return;
817
818 WARN_ON(!host->data);
819
820 mode = SDHCI_TRNS_BLK_CNT_EN;
821 if (data->blocks > 1) {
822 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
823 mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
824 else
825 mode |= SDHCI_TRNS_MULTI;
826 }
827 if (data->flags & MMC_DATA_READ)
828 mode |= SDHCI_TRNS_READ;
829 if (host->flags & SDHCI_REQ_USE_DMA)
830 mode |= SDHCI_TRNS_DMA;
831
832 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
833 }
834
835 static void sdhci_finish_data(struct sdhci_host *host)
836 {
837 struct mmc_data *data;
838
839 BUG_ON(!host->data);
840
841 data = host->data;
842 host->data = NULL;
843
844 if (host->flags & SDHCI_REQ_USE_DMA) {
845 if (host->flags & SDHCI_USE_ADMA)
846 sdhci_adma_table_post(host, data);
847 else {
848 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
849 data->sg_len, (data->flags & MMC_DATA_READ) ?
850 DMA_FROM_DEVICE : DMA_TO_DEVICE);
851 }
852 }
853
854 /*
855 * The specification states that the block count register must
856 * be updated, but it does not specify at what point in the
857 * data flow. That makes the register entirely useless to read
858 * back so we have to assume that nothing made it to the card
859 * in the event of an error.
860 */
861 if (data->error)
862 data->bytes_xfered = 0;
863 else
864 data->bytes_xfered = data->blksz * data->blocks;
865
866 if (data->stop) {
867 /*
868 * The controller needs a reset of internal state machines
869 * upon error conditions.
870 */
871 if (data->error) {
872 sdhci_reset(host, SDHCI_RESET_CMD);
873 sdhci_reset(host, SDHCI_RESET_DATA);
874 }
875
876 sdhci_send_command(host, data->stop);
877 } else
878 tasklet_schedule(&host->finish_tasklet);
879 }
880
881 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
882 {
883 int flags;
884 u32 mask;
885 unsigned long timeout;
886
887 WARN_ON(host->cmd);
888
889 /* Wait max 10 ms */
890 timeout = 10;
891
892 mask = SDHCI_CMD_INHIBIT;
893 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
894 mask |= SDHCI_DATA_INHIBIT;
895
896 /* We shouldn't wait for data inihibit for stop commands, even
897 though they might use busy signaling */
898 if (host->mrq->data && (cmd == host->mrq->data->stop))
899 mask &= ~SDHCI_DATA_INHIBIT;
900
901 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
902 if (timeout == 0) {
903 printk(KERN_ERR "%s: Controller never released "
904 "inhibit bit(s).\n", mmc_hostname(host->mmc));
905 sdhci_dumpregs(host);
906 cmd->error = -EIO;
907 tasklet_schedule(&host->finish_tasklet);
908 return;
909 }
910 timeout--;
911 mdelay(1);
912 }
913
914 mod_timer(&host->timer, jiffies + 10 * HZ);
915
916 host->cmd = cmd;
917
918 sdhci_prepare_data(host, cmd->data);
919
920 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
921
922 sdhci_set_transfer_mode(host, cmd->data);
923
924 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
925 printk(KERN_ERR "%s: Unsupported response type!\n",
926 mmc_hostname(host->mmc));
927 cmd->error = -EINVAL;
928 tasklet_schedule(&host->finish_tasklet);
929 return;
930 }
931
932 if (!(cmd->flags & MMC_RSP_PRESENT))
933 flags = SDHCI_CMD_RESP_NONE;
934 else if (cmd->flags & MMC_RSP_136)
935 flags = SDHCI_CMD_RESP_LONG;
936 else if (cmd->flags & MMC_RSP_BUSY)
937 flags = SDHCI_CMD_RESP_SHORT_BUSY;
938 else
939 flags = SDHCI_CMD_RESP_SHORT;
940
941 if (cmd->flags & MMC_RSP_CRC)
942 flags |= SDHCI_CMD_CRC;
943 if (cmd->flags & MMC_RSP_OPCODE)
944 flags |= SDHCI_CMD_INDEX;
945 if (cmd->data)
946 flags |= SDHCI_CMD_DATA;
947
948 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
949 }
950
951 static void sdhci_finish_command(struct sdhci_host *host)
952 {
953 int i;
954
955 BUG_ON(host->cmd == NULL);
956
957 if (host->cmd->flags & MMC_RSP_PRESENT) {
958 if (host->cmd->flags & MMC_RSP_136) {
959 /* CRC is stripped so we need to do some shifting. */
960 for (i = 0;i < 4;i++) {
961 host->cmd->resp[i] = sdhci_readl(host,
962 SDHCI_RESPONSE + (3-i)*4) << 8;
963 if (i != 3)
964 host->cmd->resp[i] |=
965 sdhci_readb(host,
966 SDHCI_RESPONSE + (3-i)*4-1);
967 }
968 } else {
969 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
970 }
971 }
972
973 host->cmd->error = 0;
974
975 if (host->data && host->data_early)
976 sdhci_finish_data(host);
977
978 if (!host->cmd->data)
979 tasklet_schedule(&host->finish_tasklet);
980
981 host->cmd = NULL;
982 }
983
984 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
985 {
986 int div;
987 u16 clk;
988 unsigned long timeout;
989
990 if (clock == host->clock)
991 return;
992
993 if (host->ops->set_clock) {
994 host->ops->set_clock(host, clock);
995 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
996 return;
997 }
998
999 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1000
1001 if (clock == 0)
1002 goto out;
1003
1004 for (div = 1;div < 256;div *= 2) {
1005 if ((host->max_clk / div) <= clock)
1006 break;
1007 }
1008 div >>= 1;
1009
1010 clk = div << SDHCI_DIVIDER_SHIFT;
1011 clk |= SDHCI_CLOCK_INT_EN;
1012 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1013
1014 /* Wait max 20 ms */
1015 timeout = 20;
1016 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1017 & SDHCI_CLOCK_INT_STABLE)) {
1018 if (timeout == 0) {
1019 printk(KERN_ERR "%s: Internal clock never "
1020 "stabilised.\n", mmc_hostname(host->mmc));
1021 sdhci_dumpregs(host);
1022 return;
1023 }
1024 timeout--;
1025 mdelay(1);
1026 }
1027
1028 clk |= SDHCI_CLOCK_CARD_EN;
1029 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1030
1031 out:
1032 host->clock = clock;
1033 }
1034
1035 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1036 {
1037 u8 pwr;
1038
1039 if (power == (unsigned short)-1)
1040 pwr = 0;
1041 else {
1042 switch (1 << power) {
1043 case MMC_VDD_165_195:
1044 pwr = SDHCI_POWER_180;
1045 break;
1046 case MMC_VDD_29_30:
1047 case MMC_VDD_30_31:
1048 pwr = SDHCI_POWER_300;
1049 break;
1050 case MMC_VDD_32_33:
1051 case MMC_VDD_33_34:
1052 pwr = SDHCI_POWER_330;
1053 break;
1054 default:
1055 BUG();
1056 }
1057 }
1058
1059 if (host->pwr == pwr)
1060 return;
1061
1062 host->pwr = pwr;
1063
1064 if (pwr == 0) {
1065 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1066 return;
1067 }
1068
1069 /*
1070 * Spec says that we should clear the power reg before setting
1071 * a new value. Some controllers don't seem to like this though.
1072 */
1073 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1074 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1075
1076 /*
1077 * At least the Marvell CaFe chip gets confused if we set the voltage
1078 * and set turn on power at the same time, so set the voltage first.
1079 */
1080 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1081 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1082
1083 pwr |= SDHCI_POWER_ON;
1084
1085 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1086
1087 /*
1088 * Some controllers need an extra 10ms delay of 10ms before they
1089 * can apply clock after applying power
1090 */
1091 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1092 mdelay(10);
1093 }
1094
1095 /*****************************************************************************\
1096 * *
1097 * MMC callbacks *
1098 * *
1099 \*****************************************************************************/
1100
1101 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1102 {
1103 struct sdhci_host *host;
1104 bool present;
1105 unsigned long flags;
1106
1107 host = mmc_priv(mmc);
1108
1109 spin_lock_irqsave(&host->lock, flags);
1110
1111 WARN_ON(host->mrq != NULL);
1112
1113 #ifndef SDHCI_USE_LEDS_CLASS
1114 sdhci_activate_led(host);
1115 #endif
1116 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) {
1117 if (mrq->stop) {
1118 mrq->data->stop = NULL;
1119 mrq->stop = NULL;
1120 }
1121 }
1122
1123 host->mrq = mrq;
1124
1125 /* If polling, assume that the card is always present. */
1126 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1127 present = true;
1128 else
1129 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1130 SDHCI_CARD_PRESENT;
1131
1132 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1133 host->mrq->cmd->error = -ENOMEDIUM;
1134 tasklet_schedule(&host->finish_tasklet);
1135 } else
1136 sdhci_send_command(host, mrq->cmd);
1137
1138 mmiowb();
1139 spin_unlock_irqrestore(&host->lock, flags);
1140 }
1141
1142 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1143 {
1144 struct sdhci_host *host;
1145 unsigned long flags;
1146 u8 ctrl;
1147
1148 host = mmc_priv(mmc);
1149
1150 spin_lock_irqsave(&host->lock, flags);
1151
1152 if (host->flags & SDHCI_DEVICE_DEAD)
1153 goto out;
1154
1155 /*
1156 * Reset the chip on each power off.
1157 * Should clear out any weird states.
1158 */
1159 if (ios->power_mode == MMC_POWER_OFF) {
1160 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1161 sdhci_reinit(host);
1162 }
1163
1164 sdhci_set_clock(host, ios->clock);
1165
1166 if (ios->power_mode == MMC_POWER_OFF)
1167 sdhci_set_power(host, -1);
1168 else
1169 sdhci_set_power(host, ios->vdd);
1170
1171 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1172
1173 if (ios->bus_width == MMC_BUS_WIDTH_8)
1174 ctrl |= SDHCI_CTRL_8BITBUS;
1175 else
1176 ctrl &= ~SDHCI_CTRL_8BITBUS;
1177
1178 if (ios->bus_width == MMC_BUS_WIDTH_4)
1179 ctrl |= SDHCI_CTRL_4BITBUS;
1180 else
1181 ctrl &= ~SDHCI_CTRL_4BITBUS;
1182
1183 if (ios->timing == MMC_TIMING_SD_HS &&
1184 !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1185 ctrl |= SDHCI_CTRL_HISPD;
1186 else
1187 ctrl &= ~SDHCI_CTRL_HISPD;
1188
1189 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1190
1191 /*
1192 * Some (ENE) controllers go apeshit on some ios operation,
1193 * signalling timeout and CRC errors even on CMD0. Resetting
1194 * it on each ios seems to solve the problem.
1195 */
1196 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1197 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1198
1199 out:
1200 mmiowb();
1201 spin_unlock_irqrestore(&host->lock, flags);
1202 }
1203
1204 static int sdhci_get_ro(struct mmc_host *mmc)
1205 {
1206 struct sdhci_host *host;
1207 unsigned long flags;
1208 int present;
1209
1210 host = mmc_priv(mmc);
1211
1212 spin_lock_irqsave(&host->lock, flags);
1213
1214 if (host->flags & SDHCI_DEVICE_DEAD)
1215 present = 0;
1216 else
1217 present = sdhci_readl(host, SDHCI_PRESENT_STATE);
1218
1219 spin_unlock_irqrestore(&host->lock, flags);
1220
1221 if (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT)
1222 return !!(present & SDHCI_WRITE_PROTECT);
1223 return !(present & SDHCI_WRITE_PROTECT);
1224 }
1225
1226 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1227 {
1228 struct sdhci_host *host;
1229 unsigned long flags;
1230
1231 host = mmc_priv(mmc);
1232
1233 spin_lock_irqsave(&host->lock, flags);
1234
1235 if (host->flags & SDHCI_DEVICE_DEAD)
1236 goto out;
1237
1238 if (enable)
1239 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1240 else
1241 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1242 out:
1243 mmiowb();
1244
1245 spin_unlock_irqrestore(&host->lock, flags);
1246 }
1247
1248 static const struct mmc_host_ops sdhci_ops = {
1249 .request = sdhci_request,
1250 .set_ios = sdhci_set_ios,
1251 .get_ro = sdhci_get_ro,
1252 .enable_sdio_irq = sdhci_enable_sdio_irq,
1253 };
1254
1255 /*****************************************************************************\
1256 * *
1257 * Tasklets *
1258 * *
1259 \*****************************************************************************/
1260
1261 static void sdhci_tasklet_card(unsigned long param)
1262 {
1263 struct sdhci_host *host;
1264 unsigned long flags;
1265
1266 host = (struct sdhci_host*)param;
1267
1268 spin_lock_irqsave(&host->lock, flags);
1269
1270 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1271 if (host->mrq) {
1272 printk(KERN_ERR "%s: Card removed during transfer!\n",
1273 mmc_hostname(host->mmc));
1274 printk(KERN_ERR "%s: Resetting controller.\n",
1275 mmc_hostname(host->mmc));
1276
1277 sdhci_reset(host, SDHCI_RESET_CMD);
1278 sdhci_reset(host, SDHCI_RESET_DATA);
1279
1280 host->mrq->cmd->error = -ENOMEDIUM;
1281 tasklet_schedule(&host->finish_tasklet);
1282 }
1283 }
1284
1285 spin_unlock_irqrestore(&host->lock, flags);
1286
1287 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1288 }
1289
1290 static void sdhci_tasklet_finish(unsigned long param)
1291 {
1292 struct sdhci_host *host;
1293 unsigned long flags;
1294 struct mmc_request *mrq;
1295
1296 host = (struct sdhci_host*)param;
1297
1298 spin_lock_irqsave(&host->lock, flags);
1299
1300 del_timer(&host->timer);
1301
1302 mrq = host->mrq;
1303
1304 /*
1305 * The controller needs a reset of internal state machines
1306 * upon error conditions.
1307 */
1308 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1309 (mrq->cmd->error ||
1310 (mrq->data && (mrq->data->error ||
1311 (mrq->data->stop && mrq->data->stop->error))) ||
1312 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1313
1314 /* Some controllers need this kick or reset won't work here */
1315 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1316 unsigned int clock;
1317
1318 /* This is to force an update */
1319 clock = host->clock;
1320 host->clock = 0;
1321 sdhci_set_clock(host, clock);
1322 }
1323
1324 /* Spec says we should do both at the same time, but Ricoh
1325 controllers do not like that. */
1326 sdhci_reset(host, SDHCI_RESET_CMD);
1327 sdhci_reset(host, SDHCI_RESET_DATA);
1328 }
1329
1330 host->mrq = NULL;
1331 host->cmd = NULL;
1332 host->data = NULL;
1333
1334 #ifndef SDHCI_USE_LEDS_CLASS
1335 sdhci_deactivate_led(host);
1336 #endif
1337
1338 mmiowb();
1339 spin_unlock_irqrestore(&host->lock, flags);
1340
1341 mmc_request_done(host->mmc, mrq);
1342 }
1343
1344 static void sdhci_timeout_timer(unsigned long data)
1345 {
1346 struct sdhci_host *host;
1347 unsigned long flags;
1348
1349 host = (struct sdhci_host*)data;
1350
1351 spin_lock_irqsave(&host->lock, flags);
1352
1353 if (host->mrq) {
1354 printk(KERN_ERR "%s: Timeout waiting for hardware "
1355 "interrupt.\n", mmc_hostname(host->mmc));
1356 sdhci_dumpregs(host);
1357
1358 if (host->data) {
1359 host->data->error = -ETIMEDOUT;
1360 sdhci_finish_data(host);
1361 } else {
1362 if (host->cmd)
1363 host->cmd->error = -ETIMEDOUT;
1364 else
1365 host->mrq->cmd->error = -ETIMEDOUT;
1366
1367 tasklet_schedule(&host->finish_tasklet);
1368 }
1369 }
1370
1371 mmiowb();
1372 spin_unlock_irqrestore(&host->lock, flags);
1373 }
1374
1375 /*****************************************************************************\
1376 * *
1377 * Interrupt handling *
1378 * *
1379 \*****************************************************************************/
1380
1381 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1382 {
1383 BUG_ON(intmask == 0);
1384
1385 if (!host->cmd) {
1386 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1387 "though no command operation was in progress.\n",
1388 mmc_hostname(host->mmc), (unsigned)intmask);
1389 sdhci_dumpregs(host);
1390 return;
1391 }
1392
1393 if (intmask & SDHCI_INT_TIMEOUT)
1394 host->cmd->error = -ETIMEDOUT;
1395 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1396 SDHCI_INT_INDEX))
1397 host->cmd->error = -EILSEQ;
1398
1399 if (host->cmd->error) {
1400 tasklet_schedule(&host->finish_tasklet);
1401 return;
1402 }
1403
1404 /*
1405 * The host can send and interrupt when the busy state has
1406 * ended, allowing us to wait without wasting CPU cycles.
1407 * Unfortunately this is overloaded on the "data complete"
1408 * interrupt, so we need to take some care when handling
1409 * it.
1410 *
1411 * Note: The 1.0 specification is a bit ambiguous about this
1412 * feature so there might be some problems with older
1413 * controllers.
1414 */
1415 if (host->cmd->flags & MMC_RSP_BUSY) {
1416 if (host->cmd->data)
1417 DBG("Cannot wait for busy signal when also "
1418 "doing a data transfer");
1419 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
1420 return;
1421
1422 /* The controller does not support the end-of-busy IRQ,
1423 * fall through and take the SDHCI_INT_RESPONSE */
1424 }
1425
1426 if (intmask & SDHCI_INT_RESPONSE)
1427 sdhci_finish_command(host);
1428 }
1429
1430 #ifdef DEBUG
1431 static void sdhci_show_adma_error(struct sdhci_host *host)
1432 {
1433 const char *name = mmc_hostname(host->mmc);
1434 u8 *desc = host->adma_desc;
1435 __le32 *dma;
1436 __le16 *len;
1437 u8 attr;
1438
1439 sdhci_dumpregs(host);
1440
1441 while (true) {
1442 dma = (__le32 *)(desc + 4);
1443 len = (__le16 *)(desc + 2);
1444 attr = *desc;
1445
1446 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1447 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1448
1449 desc += 8;
1450
1451 if (attr & 2)
1452 break;
1453 }
1454 }
1455 #else
1456 static void sdhci_show_adma_error(struct sdhci_host *host) { }
1457 #endif
1458
1459 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1460 {
1461 BUG_ON(intmask == 0);
1462
1463 if (!host->data) {
1464 /*
1465 * The "data complete" interrupt is also used to
1466 * indicate that a busy state has ended. See comment
1467 * above in sdhci_cmd_irq().
1468 */
1469 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1470 if (intmask & SDHCI_INT_DATA_END) {
1471 sdhci_finish_command(host);
1472 return;
1473 }
1474 }
1475
1476 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1477 "though no data operation was in progress.\n",
1478 mmc_hostname(host->mmc), (unsigned)intmask);
1479 sdhci_dumpregs(host);
1480
1481 return;
1482 }
1483
1484 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1485 host->data->error = -ETIMEDOUT;
1486 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1487 host->data->error = -EILSEQ;
1488 else if (intmask & SDHCI_INT_ADMA_ERROR) {
1489 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1490 sdhci_show_adma_error(host);
1491 host->data->error = -EIO;
1492 }
1493
1494 if (host->data->error)
1495 sdhci_finish_data(host);
1496 else {
1497 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1498 sdhci_transfer_pio(host);
1499
1500 /*
1501 * We currently don't do anything fancy with DMA
1502 * boundaries, but as we can't disable the feature
1503 * we need to at least restart the transfer.
1504 */
1505 if (intmask & SDHCI_INT_DMA_END)
1506 sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1507 SDHCI_DMA_ADDRESS);
1508
1509 if (intmask & SDHCI_INT_DATA_END) {
1510 if (host->cmd) {
1511 /*
1512 * Data managed to finish before the
1513 * command completed. Make sure we do
1514 * things in the proper order.
1515 */
1516 host->data_early = 1;
1517 } else {
1518 sdhci_finish_data(host);
1519 }
1520 }
1521 }
1522 }
1523
1524 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1525 {
1526 irqreturn_t result;
1527 struct sdhci_host* host = dev_id;
1528 u32 intmask;
1529 int cardint = 0;
1530
1531 spin_lock(&host->lock);
1532
1533 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
1534
1535 if (!intmask || intmask == 0xffffffff) {
1536 result = IRQ_NONE;
1537 goto out;
1538 }
1539
1540 DBG("*** %s got interrupt: 0x%08x\n",
1541 mmc_hostname(host->mmc), intmask);
1542
1543 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1544 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1545 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
1546 tasklet_schedule(&host->card_tasklet);
1547 }
1548
1549 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1550
1551 if (intmask & SDHCI_INT_CMD_MASK) {
1552 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1553 SDHCI_INT_STATUS);
1554 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1555 }
1556
1557 if (intmask & SDHCI_INT_DATA_MASK) {
1558 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1559 SDHCI_INT_STATUS);
1560 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1561 }
1562
1563 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1564
1565 intmask &= ~SDHCI_INT_ERROR;
1566
1567 if (intmask & SDHCI_INT_BUS_POWER) {
1568 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1569 mmc_hostname(host->mmc));
1570 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
1571 }
1572
1573 intmask &= ~SDHCI_INT_BUS_POWER;
1574
1575 if (intmask & SDHCI_INT_CARD_INT)
1576 cardint = 1;
1577
1578 intmask &= ~SDHCI_INT_CARD_INT;
1579
1580 if (intmask) {
1581 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1582 mmc_hostname(host->mmc), intmask);
1583 sdhci_dumpregs(host);
1584
1585 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
1586 }
1587
1588 result = IRQ_HANDLED;
1589
1590 mmiowb();
1591 out:
1592 spin_unlock(&host->lock);
1593
1594 /*
1595 * We have to delay this as it calls back into the driver.
1596 */
1597 if (cardint)
1598 mmc_signal_sdio_irq(host->mmc);
1599
1600 return result;
1601 }
1602
1603 /*****************************************************************************\
1604 * *
1605 * Suspend/resume *
1606 * *
1607 \*****************************************************************************/
1608
1609 #ifdef CONFIG_PM
1610
1611 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1612 {
1613 int ret;
1614
1615 sdhci_disable_card_detection(host);
1616
1617 ret = mmc_suspend_host(host->mmc);
1618 if (ret)
1619 return ret;
1620
1621 free_irq(host->irq, host);
1622
1623 if (host->vmmc)
1624 ret = regulator_disable(host->vmmc);
1625
1626 return ret;
1627 }
1628
1629 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1630
1631 int sdhci_resume_host(struct sdhci_host *host)
1632 {
1633 int ret;
1634
1635 if (host->vmmc) {
1636 int ret = regulator_enable(host->vmmc);
1637 if (ret)
1638 return ret;
1639 }
1640
1641
1642 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1643 if (host->ops->enable_dma)
1644 host->ops->enable_dma(host);
1645 }
1646
1647 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1648 mmc_hostname(host->mmc), host);
1649 if (ret)
1650 return ret;
1651
1652 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
1653 mmiowb();
1654
1655 ret = mmc_resume_host(host->mmc);
1656 sdhci_enable_card_detection(host);
1657
1658 return ret;
1659 }
1660
1661 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1662
1663 #endif /* CONFIG_PM */
1664
1665 /*****************************************************************************\
1666 * *
1667 * Device allocation/registration *
1668 * *
1669 \*****************************************************************************/
1670
1671 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1672 size_t priv_size)
1673 {
1674 struct mmc_host *mmc;
1675 struct sdhci_host *host;
1676
1677 WARN_ON(dev == NULL);
1678
1679 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1680 if (!mmc)
1681 return ERR_PTR(-ENOMEM);
1682
1683 host = mmc_priv(mmc);
1684 host->mmc = mmc;
1685
1686 return host;
1687 }
1688
1689 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1690
1691 int sdhci_add_host(struct sdhci_host *host)
1692 {
1693 struct mmc_host *mmc;
1694 unsigned int caps;
1695 int ret;
1696
1697 WARN_ON(host == NULL);
1698 if (host == NULL)
1699 return -EINVAL;
1700
1701 mmc = host->mmc;
1702
1703 if (debug_quirks)
1704 host->quirks = debug_quirks;
1705
1706 sdhci_reset(host, SDHCI_RESET_ALL);
1707
1708 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
1709 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1710 >> SDHCI_SPEC_VER_SHIFT;
1711 if (host->version > SDHCI_SPEC_200) {
1712 printk(KERN_ERR "%s: Unknown controller version (%d). "
1713 "You may experience problems.\n", mmc_hostname(mmc),
1714 host->version);
1715 }
1716
1717 caps = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
1718 sdhci_readl(host, SDHCI_CAPABILITIES);
1719
1720 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1721 host->flags |= SDHCI_USE_SDMA;
1722 else if (!(caps & SDHCI_CAN_DO_SDMA))
1723 DBG("Controller doesn't have SDMA capability\n");
1724 else
1725 host->flags |= SDHCI_USE_SDMA;
1726
1727 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1728 (host->flags & SDHCI_USE_SDMA)) {
1729 DBG("Disabling DMA as it is marked broken\n");
1730 host->flags &= ~SDHCI_USE_SDMA;
1731 }
1732
1733 if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
1734 host->flags |= SDHCI_USE_ADMA;
1735
1736 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1737 (host->flags & SDHCI_USE_ADMA)) {
1738 DBG("Disabling ADMA as it is marked broken\n");
1739 host->flags &= ~SDHCI_USE_ADMA;
1740 }
1741
1742 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1743 if (host->ops->enable_dma) {
1744 if (host->ops->enable_dma(host)) {
1745 printk(KERN_WARNING "%s: No suitable DMA "
1746 "available. Falling back to PIO.\n",
1747 mmc_hostname(mmc));
1748 host->flags &=
1749 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
1750 }
1751 }
1752 }
1753
1754 if (host->flags & SDHCI_USE_ADMA) {
1755 /*
1756 * We need to allocate descriptors for all sg entries
1757 * (128) and potentially one alignment transfer for
1758 * each of those entries.
1759 */
1760 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1761 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1762 if (!host->adma_desc || !host->align_buffer) {
1763 kfree(host->adma_desc);
1764 kfree(host->align_buffer);
1765 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1766 "buffers. Falling back to standard DMA.\n",
1767 mmc_hostname(mmc));
1768 host->flags &= ~SDHCI_USE_ADMA;
1769 }
1770 }
1771
1772 /*
1773 * If we use DMA, then it's up to the caller to set the DMA
1774 * mask, but PIO does not need the hw shim so we set a new
1775 * mask here in that case.
1776 */
1777 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
1778 host->dma_mask = DMA_BIT_MASK(64);
1779 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1780 }
1781
1782 host->max_clk =
1783 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1784 host->max_clk *= 1000000;
1785 if (host->max_clk == 0 || host->quirks &
1786 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
1787 if (!host->ops->get_max_clock) {
1788 printk(KERN_ERR
1789 "%s: Hardware doesn't specify base clock "
1790 "frequency.\n", mmc_hostname(mmc));
1791 return -ENODEV;
1792 }
1793 host->max_clk = host->ops->get_max_clock(host);
1794 }
1795
1796 host->timeout_clk =
1797 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1798 if (host->timeout_clk == 0) {
1799 if (host->ops->get_timeout_clock) {
1800 host->timeout_clk = host->ops->get_timeout_clock(host);
1801 } else if (!(host->quirks &
1802 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
1803 printk(KERN_ERR
1804 "%s: Hardware doesn't specify timeout clock "
1805 "frequency.\n", mmc_hostname(mmc));
1806 return -ENODEV;
1807 }
1808 }
1809 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1810 host->timeout_clk *= 1000;
1811
1812 /*
1813 * Set host parameters.
1814 */
1815 mmc->ops = &sdhci_ops;
1816 if (host->ops->get_min_clock)
1817 mmc->f_min = host->ops->get_min_clock(host);
1818 else
1819 mmc->f_min = host->max_clk / 256;
1820 mmc->f_max = host->max_clk;
1821 mmc->caps |= MMC_CAP_SDIO_IRQ;
1822
1823 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
1824 mmc->caps |= MMC_CAP_4_BIT_DATA;
1825
1826 if (caps & SDHCI_CAN_DO_HISPD)
1827 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1828
1829 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1830 mmc->caps |= MMC_CAP_NEEDS_POLL;
1831
1832 mmc->ocr_avail = 0;
1833 if (caps & SDHCI_CAN_VDD_330)
1834 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1835 if (caps & SDHCI_CAN_VDD_300)
1836 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1837 if (caps & SDHCI_CAN_VDD_180)
1838 mmc->ocr_avail |= MMC_VDD_165_195;
1839
1840 if (mmc->ocr_avail == 0) {
1841 printk(KERN_ERR "%s: Hardware doesn't report any "
1842 "support voltages.\n", mmc_hostname(mmc));
1843 return -ENODEV;
1844 }
1845
1846 spin_lock_init(&host->lock);
1847
1848 /*
1849 * Maximum number of segments. Depends on if the hardware
1850 * can do scatter/gather or not.
1851 */
1852 if (host->flags & SDHCI_USE_ADMA)
1853 mmc->max_hw_segs = 128;
1854 else if (host->flags & SDHCI_USE_SDMA)
1855 mmc->max_hw_segs = 1;
1856 else /* PIO */
1857 mmc->max_hw_segs = 128;
1858 mmc->max_phys_segs = 128;
1859
1860 /*
1861 * Maximum number of sectors in one transfer. Limited by DMA boundary
1862 * size (512KiB).
1863 */
1864 mmc->max_req_size = 524288;
1865
1866 /*
1867 * Maximum segment size. Could be one segment with the maximum number
1868 * of bytes. When doing hardware scatter/gather, each entry cannot
1869 * be larger than 64 KiB though.
1870 */
1871 if (host->flags & SDHCI_USE_ADMA)
1872 mmc->max_seg_size = 65536;
1873 else
1874 mmc->max_seg_size = mmc->max_req_size;
1875
1876 /*
1877 * Maximum block size. This varies from controller to controller and
1878 * is specified in the capabilities register.
1879 */
1880 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
1881 mmc->max_blk_size = 2;
1882 } else {
1883 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
1884 SDHCI_MAX_BLOCK_SHIFT;
1885 if (mmc->max_blk_size >= 3) {
1886 printk(KERN_WARNING "%s: Invalid maximum block size, "
1887 "assuming 512 bytes\n", mmc_hostname(mmc));
1888 mmc->max_blk_size = 0;
1889 }
1890 }
1891
1892 mmc->max_blk_size = 512 << mmc->max_blk_size;
1893
1894 /*
1895 * Maximum block count.
1896 */
1897 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
1898
1899 /*
1900 * Init tasklets.
1901 */
1902 tasklet_init(&host->card_tasklet,
1903 sdhci_tasklet_card, (unsigned long)host);
1904 tasklet_init(&host->finish_tasklet,
1905 sdhci_tasklet_finish, (unsigned long)host);
1906
1907 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1908
1909 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1910 mmc_hostname(mmc), host);
1911 if (ret)
1912 goto untasklet;
1913
1914 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1915 if (IS_ERR(host->vmmc)) {
1916 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
1917 host->vmmc = NULL;
1918 } else {
1919 regulator_enable(host->vmmc);
1920 }
1921
1922 sdhci_init(host, 0);
1923
1924 #ifdef CONFIG_MMC_DEBUG
1925 sdhci_dumpregs(host);
1926 #endif
1927
1928 #ifdef SDHCI_USE_LEDS_CLASS
1929 snprintf(host->led_name, sizeof(host->led_name),
1930 "%s::", mmc_hostname(mmc));
1931 host->led.name = host->led_name;
1932 host->led.brightness = LED_OFF;
1933 host->led.default_trigger = mmc_hostname(mmc);
1934 host->led.brightness_set = sdhci_led_control;
1935
1936 ret = led_classdev_register(mmc_dev(mmc), &host->led);
1937 if (ret)
1938 goto reset;
1939 #endif
1940
1941 mmiowb();
1942
1943 mmc_add_host(mmc);
1944
1945 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
1946 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
1947 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
1948 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
1949
1950 sdhci_enable_card_detection(host);
1951
1952 return 0;
1953
1954 #ifdef SDHCI_USE_LEDS_CLASS
1955 reset:
1956 sdhci_reset(host, SDHCI_RESET_ALL);
1957 free_irq(host->irq, host);
1958 #endif
1959 untasklet:
1960 tasklet_kill(&host->card_tasklet);
1961 tasklet_kill(&host->finish_tasklet);
1962
1963 return ret;
1964 }
1965
1966 EXPORT_SYMBOL_GPL(sdhci_add_host);
1967
1968 void sdhci_remove_host(struct sdhci_host *host, int dead)
1969 {
1970 unsigned long flags;
1971
1972 if (dead) {
1973 spin_lock_irqsave(&host->lock, flags);
1974
1975 host->flags |= SDHCI_DEVICE_DEAD;
1976
1977 if (host->mrq) {
1978 printk(KERN_ERR "%s: Controller removed during "
1979 " transfer!\n", mmc_hostname(host->mmc));
1980
1981 host->mrq->cmd->error = -ENOMEDIUM;
1982 tasklet_schedule(&host->finish_tasklet);
1983 }
1984
1985 spin_unlock_irqrestore(&host->lock, flags);
1986 }
1987
1988 sdhci_disable_card_detection(host);
1989
1990 mmc_remove_host(host->mmc);
1991
1992 #ifdef SDHCI_USE_LEDS_CLASS
1993 led_classdev_unregister(&host->led);
1994 #endif
1995
1996 if (!dead)
1997 sdhci_reset(host, SDHCI_RESET_ALL);
1998
1999 free_irq(host->irq, host);
2000
2001 del_timer_sync(&host->timer);
2002
2003 tasklet_kill(&host->card_tasklet);
2004 tasklet_kill(&host->finish_tasklet);
2005
2006 if (host->vmmc) {
2007 regulator_disable(host->vmmc);
2008 regulator_put(host->vmmc);
2009 }
2010
2011 kfree(host->adma_desc);
2012 kfree(host->align_buffer);
2013
2014 host->adma_desc = NULL;
2015 host->align_buffer = NULL;
2016 }
2017
2018 EXPORT_SYMBOL_GPL(sdhci_remove_host);
2019
2020 void sdhci_free_host(struct sdhci_host *host)
2021 {
2022 mmc_free_host(host->mmc);
2023 }
2024
2025 EXPORT_SYMBOL_GPL(sdhci_free_host);
2026
2027 /*****************************************************************************\
2028 * *
2029 * Driver init/exit *
2030 * *
2031 \*****************************************************************************/
2032
2033 static int __init sdhci_drv_init(void)
2034 {
2035 printk(KERN_INFO DRIVER_NAME
2036 ": Secure Digital Host Controller Interface driver\n");
2037 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2038
2039 return 0;
2040 }
2041
2042 static void __exit sdhci_drv_exit(void)
2043 {
2044 }
2045
2046 module_init(sdhci_drv_init);
2047 module_exit(sdhci_drv_exit);
2048
2049 module_param(debug_quirks, uint, 0444);
2050
2051 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2052 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2053 MODULE_LICENSE("GPL");
2054
2055 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree