arch/arm/mach-s3c2410/mach-qt2410.c

   1 /* linux/arch/arm/mach-s3c2410/mach-qt2410.c
   2  *
   3  * Copyright (C) 2006 by OpenMoko, Inc.
   4  * Author: Harald Welte <laforge@openmoko.org>
   5  * All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/types.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/list.h>
  28 #include <linux/timer.h>
  29 #include <linux/init.h>
  30 #include <linux/gpio.h>
  31 #include <linux/sysdev.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/serial_core.h>
  34 #include <linux/spi/spi.h>
  35 #include <linux/spi/spi_gpio.h>
  36 #include <linux/io.h>
  37 #include <linux/mtd/mtd.h>
  38 #include <linux/mtd/nand.h>
  39 #include <linux/mtd/nand_ecc.h>
  40 #include <linux/mtd/partitions.h>
  41
  42 #include <asm/mach/arch.h>
  43 #include <asm/mach/map.h>
  44 #include <asm/mach/irq.h>
  45
  46 #include <mach/hardware.h>
  47 #include <asm/irq.h>
  48 #include <asm/mach-types.h>
  49
  50 #include <mach/regs-gpio.h>
  51 #include <mach/leds-gpio.h>
  52 #include <mach/regs-lcd.h>
  53 #include <plat/regs-serial.h>
  54 #include <mach/fb.h>
  55 #include <plat/nand.h>
  56 #include <plat/udc.h>
  57 #include <plat/iic.h>
  58
  59 #include <plat/common-smdk.h>
  60 #include <plat/gpio-cfg.h>
  61 #include <plat/devs.h>
  62 #include <plat/cpu.h>
  63 #include <plat/pm.h>
  64
  65 static struct map_desc qt2410_iodesc[] __initdata = {
  66         { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
  67 };
  68
  69 #define UCON S3C2410_UCON_DEFAULT
  70 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  71 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  72
  73 static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
  74         [0] = {
  75                 .hwport      = 0,
  76                 .flags       = 0,
  77                 .ucon        = UCON,
  78                 .ulcon       = ULCON,
  79                 .ufcon       = UFCON,
  80         },
  81         [1] = {
  82                 .hwport      = 1,
  83                 .flags       = 0,
  84                 .ucon        = UCON,
  85                 .ulcon       = ULCON,
  86                 .ufcon       = UFCON,
  87         },
  88         [2] = {
  89                 .hwport      = 2,
  90                 .flags       = 0,
  91                 .ucon        = UCON,
  92                 .ulcon       = ULCON,
  93                 .ufcon       = UFCON,
  94         }
  95 };
  96
  97 /* LCD driver info */
  98
  99 static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
 100         {
 101                 /* Configuration for 640x480 SHARP LQ080V3DG01 */
 102                 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
 103                            S3C2410_LCDCON5_INVVLINE |
 104                            S3C2410_LCDCON5_INVVFRAME |
 105                            S3C2410_LCDCON5_PWREN |
 106                            S3C2410_LCDCON5_HWSWP,
 107
 108                 .type           = S3C2410_LCDCON1_TFT,
 109                 .width          = 640,
 110                 .height         = 480,
 111
 112                 .pixclock       = 40000, /* HCLK/4 */
 113                 .xres           = 640,
 114                 .yres           = 480,
 115                 .bpp            = 16,
 116                 .left_margin    = 44,
 117                 .right_margin   = 116,
 118                 .hsync_len      = 96,
 119                 .upper_margin   = 19,
 120                 .lower_margin   = 11,
 121                 .vsync_len      = 15,
 122         },
 123         {
 124                 /* Configuration for 480x640 toppoly TD028TTEC1 */
 125                 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
 126                            S3C2410_LCDCON5_INVVLINE |
 127                            S3C2410_LCDCON5_INVVFRAME |
 128                            S3C2410_LCDCON5_PWREN |
 129                            S3C2410_LCDCON5_HWSWP,
 130
 131                 .type           = S3C2410_LCDCON1_TFT,
 132                 .width          = 480,
 133                 .height         = 640,
 134                 .pixclock       = 40000, /* HCLK/4 */
 135                 .xres           = 480,
 136                 .yres           = 640,
 137                 .bpp            = 16,
 138                 .left_margin    = 8,
 139                 .right_margin   = 24,
 140                 .hsync_len      = 8,
 141                 .upper_margin   = 2,
 142                 .lower_margin   = 4,
 143                 .vsync_len      = 2,
 144         },
 145         {
 146                 /* Config for 240x320 LCD */
 147                 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
 148                            S3C2410_LCDCON5_INVVLINE |
 149                            S3C2410_LCDCON5_INVVFRAME |
 150                            S3C2410_LCDCON5_PWREN |
 151                            S3C2410_LCDCON5_HWSWP,
 152
 153                 .type           = S3C2410_LCDCON1_TFT,
 154                 .width          = 240,
 155                 .height         = 320,
 156                 .pixclock       = 100000, /* HCLK/10 */
 157                 .xres           = 240,
 158                 .yres           = 320,
 159                 .bpp            = 16,
 160                 .left_margin    = 13,
 161                 .right_margin   = 8,
 162                 .hsync_len      = 4,
 163                 .upper_margin   = 2,
 164                 .lower_margin   = 7,
 165                 .vsync_len      = 4,
 166         },
 167 };
 168
 169
 170 static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
 171         .displays       = qt2410_lcd_cfg,
 172         .num_displays   = ARRAY_SIZE(qt2410_lcd_cfg),
 173         .default_display = 0,
 174
 175         .lpcsel         = ((0xCE6) & ~7) | 1<<4,
 176 };
 177
 178 /* CS8900 */
 179
 180 static struct resource qt2410_cs89x0_resources[] = {
 181         [0] = {
 182                 .start  = 0x19000000,
 183                 .end    = 0x19000000 + 16,
 184                 .flags  = IORESOURCE_MEM,
 185         },
 186         [1] = {
 187                 .start  = IRQ_EINT9,
 188                 .end    = IRQ_EINT9,
 189                 .flags  = IORESOURCE_IRQ,
 190         },
 191 };
 192
 193 static struct platform_device qt2410_cs89x0 = {
 194         .name           = "cirrus-cs89x0",
 195         .num_resources  = ARRAY_SIZE(qt2410_cs89x0_resources),
 196         .resource       = qt2410_cs89x0_resources,
 197 };
 198
 199 /* LED */
 200
 201 static struct s3c24xx_led_platdata qt2410_pdata_led = {
 202         .gpio           = S3C2410_GPB(0),
 203         .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
 204         .name           = "led",
 205         .def_trigger    = "timer",
 206 };
 207
 208 static struct platform_device qt2410_led = {
 209         .name           = "s3c24xx_led",
 210         .id             = 0,
 211         .dev            = {
 212                 .platform_data = &qt2410_pdata_led,
 213         },
 214 };
 215
 216 /* SPI */
 217
 218 static struct spi_gpio_platform_data spi_gpio_cfg = {
 219         .sck            = S3C2410_GPG(7),
 220         .mosi           = S3C2410_GPG(6),
 221         .miso           = S3C2410_GPG(5),
 222 };
 223
 224 static struct platform_device qt2410_spi = {
 225         .name           = "spi-gpio",
 226         .id             = 1,
 227         .dev.platform_data = &spi_gpio_cfg,
 228 };
 229
 230 /* Board devices */
 231
 232 static struct platform_device *qt2410_devices[] __initdata = {
 233         &s3c_device_ohci,
 234         &s3c_device_lcd,
 235         &s3c_device_wdt,
 236         &s3c_device_i2c0,
 237         &s3c_device_iis,
 238         &s3c_device_sdi,
 239         &s3c_device_usbgadget,
 240         &qt2410_spi,
 241         &qt2410_cs89x0,
 242         &qt2410_led,
 243 };
 244
 245 static struct mtd_partition __initdata qt2410_nand_part[] = {
 246         [0] = {
 247                 .name   = "U-Boot",
 248                 .size   = 0x30000,
 249                 .offset = 0,
 250         },
 251         [1] = {
 252                 .name   = "U-Boot environment",
 253                 .offset = 0x30000,
 254                 .size   = 0x4000,
 255         },
 256         [2] = {
 257                 .name   = "kernel",
 258                 .offset = 0x34000,
 259                 .size   = SZ_2M,
 260         },
 261         [3] = {
 262                 .name   = "initrd",
 263                 .offset = 0x234000,
 264                 .size   = SZ_4M,
 265         },
 266         [4] = {
 267                 .name   = "jffs2",
 268                 .offset = 0x634000,
 269                 .size   = 0x39cc000,
 270         },
 271 };
 272
 273 static struct s3c2410_nand_set __initdata qt2410_nand_sets[] = {
 274         [0] = {
 275                 .name           = "NAND",
 276                 .nr_chips       = 1,
 277                 .nr_partitions  = ARRAY_SIZE(qt2410_nand_part),
 278                 .partitions     = qt2410_nand_part,
 279         },
 280 };
 281
 282 /* choose a set of timings which should suit most 512Mbit
 283  * chips and beyond.
 284  */
 285
 286 static struct s3c2410_platform_nand __initdata qt2410_nand_info = {
 287         .tacls          = 20,
 288         .twrph0         = 60,
 289         .twrph1         = 20,
 290         .nr_sets        = ARRAY_SIZE(qt2410_nand_sets),
 291         .sets           = qt2410_nand_sets,
 292 };
 293
 294 /* UDC */
 295
 296 static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
 297 };
 298
 299 static char tft_type = 's';
 300
 301 static int __init qt2410_tft_setup(char *str)
 302 {
 303         tft_type = str[0];
 304         return 1;
 305 }
 306
 307 __setup("tft=", qt2410_tft_setup);
 308
 309 static void __init qt2410_map_io(void)
 310 {
 311         s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
 312         s3c24xx_init_clocks(12*1000*1000);
 313         s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
 314 }
 315
 316 static void __init qt2410_machine_init(void)
 317 {
 318         s3c_nand_set_platdata(&qt2410_nand_info);
 319
 320         switch (tft_type) {
 321         case 'p': /* production */
 322                 qt2410_fb_info.default_display = 1;
 323                 break;
 324         case 'b': /* big */
 325                 qt2410_fb_info.default_display = 0;
 326                 break;
 327         case 's': /* small */
 328         default:
 329                 qt2410_fb_info.default_display = 2;
 330                 break;
 331         }
 332         s3c24xx_fb_set_platdata(&qt2410_fb_info);
 333
 334         s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
 335         s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
 336
 337         s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
 338         s3c_i2c0_set_platdata(NULL);
 339
 340         WARN_ON(gpio_request(S3C2410_GPB(5), "spi cs"));
 341         gpio_direction_output(S3C2410_GPB(5), 1);
 342
 343         platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
 344         s3c_pm_init();
 345 }
 346
 347 MACHINE_START(QT2410, "QT2410")
 348         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 349         .map_io         = qt2410_map_io,
 350         .init_irq       = s3c24xx_init_irq,
 351         .init_machine   = qt2410_machine_init,
 352         .timer          = &s3c24xx_timer,
 353 MACHINE_END
 354
 355