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neigh: __rcu annotations
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / s2io.c
blob39c17cecb8b98f5258bd9245ad451b14d6b2473b
1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2010 Exar Corp.
4 *
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
26 *
27 * The module loadable parameters that are supported by the driver and a brief
28 * explanation of all the variables.
29 *
30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35 * values are 1, 2.
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_max_pkts: This parameter defines maximum number of packets can be
42 * aggregated as a single large packet
43 * napi: This parameter used to enable/disable NAPI (polling Rx)
44 * Possible values '1' for enable and '0' for disable. Default is '1'
45 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
46 * Possible values '1' for enable and '0' for disable. Default is '0'
47 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
48 * Possible values '1' for enable , '0' for disable.
49 * Default is '2' - which means disable in promisc mode
50 * and enable in non-promiscuous mode.
51 * multiq: This parameter used to enable/disable MULTIQUEUE support.
52 * Possible values '1' for enable and '0' for disable. Default is '0'
53 ************************************************************************/
54
55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/errno.h>
60 #include <linux/ioport.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/kernel.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/mdio.h>
67 #include <linux/skbuff.h>
68 #include <linux/init.h>
69 #include <linux/delay.h>
70 #include <linux/stddef.h>
71 #include <linux/ioctl.h>
72 #include <linux/timex.h>
73 #include <linux/ethtool.h>
74 #include <linux/workqueue.h>
75 #include <linux/if_vlan.h>
76 #include <linux/ip.h>
77 #include <linux/tcp.h>
78 #include <linux/uaccess.h>
79 #include <linux/io.h>
80 #include <linux/slab.h>
81 #include <net/tcp.h>
82
83 #include <asm/system.h>
84 #include <asm/div64.h>
85 #include <asm/irq.h>
86
87 /* local include */
88 #include "s2io.h"
89 #include "s2io-regs.h"
90
91 #define DRV_VERSION "2.0.26.28"
92
93 /* S2io Driver name & version. */
94 static const char s2io_driver_name[] = "Neterion";
95 static const char s2io_driver_version[] = DRV_VERSION;
96
97 static const int rxd_size[2] = {32, 48};
98 static const int rxd_count[2] = {127, 85};
99
100 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
101 {
102 int ret;
103
104 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
105 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
106
107 return ret;
108 }
109
110 /*
111 * Cards with following subsystem_id have a link state indication
112 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
113 * macro below identifies these cards given the subsystem_id.
114 */
115 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
116 (dev_type == XFRAME_I_DEVICE) ? \
117 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
118 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
119
120 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
121 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
122
123 static inline int is_s2io_card_up(const struct s2io_nic *sp)
124 {
125 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
126 }
127
128 /* Ethtool related variables and Macros. */
129 static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
130 "Register test\t(offline)",
131 "Eeprom test\t(offline)",
132 "Link test\t(online)",
133 "RLDRAM test\t(offline)",
134 "BIST Test\t(offline)"
135 };
136
137 static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
138 {"tmac_frms"},
139 {"tmac_data_octets"},
140 {"tmac_drop_frms"},
141 {"tmac_mcst_frms"},
142 {"tmac_bcst_frms"},
143 {"tmac_pause_ctrl_frms"},
144 {"tmac_ttl_octets"},
145 {"tmac_ucst_frms"},
146 {"tmac_nucst_frms"},
147 {"tmac_any_err_frms"},
148 {"tmac_ttl_less_fb_octets"},
149 {"tmac_vld_ip_octets"},
150 {"tmac_vld_ip"},
151 {"tmac_drop_ip"},
152 {"tmac_icmp"},
153 {"tmac_rst_tcp"},
154 {"tmac_tcp"},
155 {"tmac_udp"},
156 {"rmac_vld_frms"},
157 {"rmac_data_octets"},
158 {"rmac_fcs_err_frms"},
159 {"rmac_drop_frms"},
160 {"rmac_vld_mcst_frms"},
161 {"rmac_vld_bcst_frms"},
162 {"rmac_in_rng_len_err_frms"},
163 {"rmac_out_rng_len_err_frms"},
164 {"rmac_long_frms"},
165 {"rmac_pause_ctrl_frms"},
166 {"rmac_unsup_ctrl_frms"},
167 {"rmac_ttl_octets"},
168 {"rmac_accepted_ucst_frms"},
169 {"rmac_accepted_nucst_frms"},
170 {"rmac_discarded_frms"},
171 {"rmac_drop_events"},
172 {"rmac_ttl_less_fb_octets"},
173 {"rmac_ttl_frms"},
174 {"rmac_usized_frms"},
175 {"rmac_osized_frms"},
176 {"rmac_frag_frms"},
177 {"rmac_jabber_frms"},
178 {"rmac_ttl_64_frms"},
179 {"rmac_ttl_65_127_frms"},
180 {"rmac_ttl_128_255_frms"},
181 {"rmac_ttl_256_511_frms"},
182 {"rmac_ttl_512_1023_frms"},
183 {"rmac_ttl_1024_1518_frms"},
184 {"rmac_ip"},
185 {"rmac_ip_octets"},
186 {"rmac_hdr_err_ip"},
187 {"rmac_drop_ip"},
188 {"rmac_icmp"},
189 {"rmac_tcp"},
190 {"rmac_udp"},
191 {"rmac_err_drp_udp"},
192 {"rmac_xgmii_err_sym"},
193 {"rmac_frms_q0"},
194 {"rmac_frms_q1"},
195 {"rmac_frms_q2"},
196 {"rmac_frms_q3"},
197 {"rmac_frms_q4"},
198 {"rmac_frms_q5"},
199 {"rmac_frms_q6"},
200 {"rmac_frms_q7"},
201 {"rmac_full_q0"},
202 {"rmac_full_q1"},
203 {"rmac_full_q2"},
204 {"rmac_full_q3"},
205 {"rmac_full_q4"},
206 {"rmac_full_q5"},
207 {"rmac_full_q6"},
208 {"rmac_full_q7"},
209 {"rmac_pause_cnt"},
210 {"rmac_xgmii_data_err_cnt"},
211 {"rmac_xgmii_ctrl_err_cnt"},
212 {"rmac_accepted_ip"},
213 {"rmac_err_tcp"},
214 {"rd_req_cnt"},
215 {"new_rd_req_cnt"},
216 {"new_rd_req_rtry_cnt"},
217 {"rd_rtry_cnt"},
218 {"wr_rtry_rd_ack_cnt"},
219 {"wr_req_cnt"},
220 {"new_wr_req_cnt"},
221 {"new_wr_req_rtry_cnt"},
222 {"wr_rtry_cnt"},
223 {"wr_disc_cnt"},
224 {"rd_rtry_wr_ack_cnt"},
225 {"txp_wr_cnt"},
226 {"txd_rd_cnt"},
227 {"txd_wr_cnt"},
228 {"rxd_rd_cnt"},
229 {"rxd_wr_cnt"},
230 {"txf_rd_cnt"},
231 {"rxf_wr_cnt"}
232 };
233
234 static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
235 {"rmac_ttl_1519_4095_frms"},
236 {"rmac_ttl_4096_8191_frms"},
237 {"rmac_ttl_8192_max_frms"},
238 {"rmac_ttl_gt_max_frms"},
239 {"rmac_osized_alt_frms"},
240 {"rmac_jabber_alt_frms"},
241 {"rmac_gt_max_alt_frms"},
242 {"rmac_vlan_frms"},
243 {"rmac_len_discard"},
244 {"rmac_fcs_discard"},
245 {"rmac_pf_discard"},
246 {"rmac_da_discard"},
247 {"rmac_red_discard"},
248 {"rmac_rts_discard"},
249 {"rmac_ingm_full_discard"},
250 {"link_fault_cnt"}
251 };
252
253 static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
254 {"\n DRIVER STATISTICS"},
255 {"single_bit_ecc_errs"},
256 {"double_bit_ecc_errs"},
257 {"parity_err_cnt"},
258 {"serious_err_cnt"},
259 {"soft_reset_cnt"},
260 {"fifo_full_cnt"},
261 {"ring_0_full_cnt"},
262 {"ring_1_full_cnt"},
263 {"ring_2_full_cnt"},
264 {"ring_3_full_cnt"},
265 {"ring_4_full_cnt"},
266 {"ring_5_full_cnt"},
267 {"ring_6_full_cnt"},
268 {"ring_7_full_cnt"},
269 {"alarm_transceiver_temp_high"},
270 {"alarm_transceiver_temp_low"},
271 {"alarm_laser_bias_current_high"},
272 {"alarm_laser_bias_current_low"},
273 {"alarm_laser_output_power_high"},
274 {"alarm_laser_output_power_low"},
275 {"warn_transceiver_temp_high"},
276 {"warn_transceiver_temp_low"},
277 {"warn_laser_bias_current_high"},
278 {"warn_laser_bias_current_low"},
279 {"warn_laser_output_power_high"},
280 {"warn_laser_output_power_low"},
281 {"lro_aggregated_pkts"},
282 {"lro_flush_both_count"},
283 {"lro_out_of_sequence_pkts"},
284 {"lro_flush_due_to_max_pkts"},
285 {"lro_avg_aggr_pkts"},
286 {"mem_alloc_fail_cnt"},
287 {"pci_map_fail_cnt"},
288 {"watchdog_timer_cnt"},
289 {"mem_allocated"},
290 {"mem_freed"},
291 {"link_up_cnt"},
292 {"link_down_cnt"},
293 {"link_up_time"},
294 {"link_down_time"},
295 {"tx_tcode_buf_abort_cnt"},
296 {"tx_tcode_desc_abort_cnt"},
297 {"tx_tcode_parity_err_cnt"},
298 {"tx_tcode_link_loss_cnt"},
299 {"tx_tcode_list_proc_err_cnt"},
300 {"rx_tcode_parity_err_cnt"},
301 {"rx_tcode_abort_cnt"},
302 {"rx_tcode_parity_abort_cnt"},
303 {"rx_tcode_rda_fail_cnt"},
304 {"rx_tcode_unkn_prot_cnt"},
305 {"rx_tcode_fcs_err_cnt"},
306 {"rx_tcode_buf_size_err_cnt"},
307 {"rx_tcode_rxd_corrupt_cnt"},
308 {"rx_tcode_unkn_err_cnt"},
309 {"tda_err_cnt"},
310 {"pfc_err_cnt"},
311 {"pcc_err_cnt"},
312 {"tti_err_cnt"},
313 {"tpa_err_cnt"},
314 {"sm_err_cnt"},
315 {"lso_err_cnt"},
316 {"mac_tmac_err_cnt"},
317 {"mac_rmac_err_cnt"},
318 {"xgxs_txgxs_err_cnt"},
319 {"xgxs_rxgxs_err_cnt"},
320 {"rc_err_cnt"},
321 {"prc_pcix_err_cnt"},
322 {"rpa_err_cnt"},
323 {"rda_err_cnt"},
324 {"rti_err_cnt"},
325 {"mc_err_cnt"}
326 };
327
328 #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
329 #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
330 #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
331
332 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
333 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
334
335 #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
336 #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
337
338 #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
339 #define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
340
341 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
342 init_timer(&timer); \
343 timer.function = handle; \
344 timer.data = (unsigned long)arg; \
345 mod_timer(&timer, (jiffies + exp)) \
346
347 /* copy mac addr to def_mac_addr array */
348 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
349 {
350 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
351 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
352 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
353 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
354 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
355 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
356 }
357
358 /* Add the vlan */
359 static void s2io_vlan_rx_register(struct net_device *dev,
360 struct vlan_group *grp)
361 {
362 int i;
363 struct s2io_nic *nic = netdev_priv(dev);
364 unsigned long flags[MAX_TX_FIFOS];
365 struct config_param *config = &nic->config;
366 struct mac_info *mac_control = &nic->mac_control;
367
368 for (i = 0; i < config->tx_fifo_num; i++) {
369 struct fifo_info *fifo = &mac_control->fifos[i];
370
371 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
372 }
373
374 nic->vlgrp = grp;
375
376 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
377 struct fifo_info *fifo = &mac_control->fifos[i];
378
379 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
380 }
381 }
382
383 /* Unregister the vlan */
384 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
385 {
386 int i;
387 struct s2io_nic *nic = netdev_priv(dev);
388 unsigned long flags[MAX_TX_FIFOS];
389 struct config_param *config = &nic->config;
390 struct mac_info *mac_control = &nic->mac_control;
391
392 for (i = 0; i < config->tx_fifo_num; i++) {
393 struct fifo_info *fifo = &mac_control->fifos[i];
394
395 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
396 }
397
398 if (nic->vlgrp)
399 vlan_group_set_device(nic->vlgrp, vid, NULL);
400
401 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
402 struct fifo_info *fifo = &mac_control->fifos[i];
403
404 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
405 }
406 }
407
408 /*
409 * Constants to be programmed into the Xena's registers, to configure
410 * the XAUI.
411 */
412
413 #define END_SIGN 0x0
414 static const u64 herc_act_dtx_cfg[] = {
415 /* Set address */
416 0x8000051536750000ULL, 0x80000515367500E0ULL,
417 /* Write data */
418 0x8000051536750004ULL, 0x80000515367500E4ULL,
419 /* Set address */
420 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
421 /* Write data */
422 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
423 /* Set address */
424 0x801205150D440000ULL, 0x801205150D4400E0ULL,
425 /* Write data */
426 0x801205150D440004ULL, 0x801205150D4400E4ULL,
427 /* Set address */
428 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
429 /* Write data */
430 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
431 /* Done */
432 END_SIGN
433 };
434
435 static const u64 xena_dtx_cfg[] = {
436 /* Set address */
437 0x8000051500000000ULL, 0x80000515000000E0ULL,
438 /* Write data */
439 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
440 /* Set address */
441 0x8001051500000000ULL, 0x80010515000000E0ULL,
442 /* Write data */
443 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
444 /* Set address */
445 0x8002051500000000ULL, 0x80020515000000E0ULL,
446 /* Write data */
447 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
448 END_SIGN
449 };
450
451 /*
452 * Constants for Fixing the MacAddress problem seen mostly on
453 * Alpha machines.
454 */
455 static const u64 fix_mac[] = {
456 0x0060000000000000ULL, 0x0060600000000000ULL,
457 0x0040600000000000ULL, 0x0000600000000000ULL,
458 0x0020600000000000ULL, 0x0060600000000000ULL,
459 0x0020600000000000ULL, 0x0060600000000000ULL,
460 0x0020600000000000ULL, 0x0060600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0060600000000000ULL,
468 0x0020600000000000ULL, 0x0000600000000000ULL,
469 0x0040600000000000ULL, 0x0060600000000000ULL,
470 END_SIGN
471 };
472
473 MODULE_LICENSE("GPL");
474 MODULE_VERSION(DRV_VERSION);
475
476
477 /* Module Loadable parameters. */
478 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
479 S2IO_PARM_INT(rx_ring_num, 1);
480 S2IO_PARM_INT(multiq, 0);
481 S2IO_PARM_INT(rx_ring_mode, 1);
482 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
483 S2IO_PARM_INT(rmac_pause_time, 0x100);
484 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
485 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
486 S2IO_PARM_INT(shared_splits, 0);
487 S2IO_PARM_INT(tmac_util_period, 5);
488 S2IO_PARM_INT(rmac_util_period, 5);
489 S2IO_PARM_INT(l3l4hdr_size, 128);
490 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
491 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
492 /* Frequency of Rx desc syncs expressed as power of 2 */
493 S2IO_PARM_INT(rxsync_frequency, 3);
494 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
495 S2IO_PARM_INT(intr_type, 2);
496 /* Large receive offload feature */
497
498 /* Max pkts to be aggregated by LRO at one time. If not specified,
499 * aggregation happens until we hit max IP pkt size(64K)
500 */
501 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
502 S2IO_PARM_INT(indicate_max_pkts, 0);
503
504 S2IO_PARM_INT(napi, 1);
505 S2IO_PARM_INT(ufo, 0);
506 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
507
508 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
509 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
510 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
511 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
512 static unsigned int rts_frm_len[MAX_RX_RINGS] =
513 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
514
515 module_param_array(tx_fifo_len, uint, NULL, 0);
516 module_param_array(rx_ring_sz, uint, NULL, 0);
517 module_param_array(rts_frm_len, uint, NULL, 0);
518
519 /*
520 * S2IO device table.
521 * This table lists all the devices that this driver supports.
522 */
523 static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = {
524 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
525 PCI_ANY_ID, PCI_ANY_ID},
526 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
527 PCI_ANY_ID, PCI_ANY_ID},
528 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
529 PCI_ANY_ID, PCI_ANY_ID},
530 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
531 PCI_ANY_ID, PCI_ANY_ID},
532 {0,}
533 };
534
535 MODULE_DEVICE_TABLE(pci, s2io_tbl);
536
537 static struct pci_error_handlers s2io_err_handler = {
538 .error_detected = s2io_io_error_detected,
539 .slot_reset = s2io_io_slot_reset,
540 .resume = s2io_io_resume,
541 };
542
543 static struct pci_driver s2io_driver = {
544 .name = "S2IO",
545 .id_table = s2io_tbl,
546 .probe = s2io_init_nic,
547 .remove = __devexit_p(s2io_rem_nic),
548 .err_handler = &s2io_err_handler,
549 };
550
551 /* A simplifier macro used both by init and free shared_mem Fns(). */
552 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
553
554 /* netqueue manipulation helper functions */
555 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
556 {
557 if (!sp->config.multiq) {
558 int i;
559
560 for (i = 0; i < sp->config.tx_fifo_num; i++)
561 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
562 }
563 netif_tx_stop_all_queues(sp->dev);
564 }
565
566 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
567 {
568 if (!sp->config.multiq)
569 sp->mac_control.fifos[fifo_no].queue_state =
570 FIFO_QUEUE_STOP;
571
572 netif_tx_stop_all_queues(sp->dev);
573 }
574
575 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
576 {
577 if (!sp->config.multiq) {
578 int i;
579
580 for (i = 0; i < sp->config.tx_fifo_num; i++)
581 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
582 }
583 netif_tx_start_all_queues(sp->dev);
584 }
585
586 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
587 {
588 if (!sp->config.multiq)
589 sp->mac_control.fifos[fifo_no].queue_state =
590 FIFO_QUEUE_START;
591
592 netif_tx_start_all_queues(sp->dev);
593 }
594
595 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
596 {
597 if (!sp->config.multiq) {
598 int i;
599
600 for (i = 0; i < sp->config.tx_fifo_num; i++)
601 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
602 }
603 netif_tx_wake_all_queues(sp->dev);
604 }
605
606 static inline void s2io_wake_tx_queue(
607 struct fifo_info *fifo, int cnt, u8 multiq)
608 {
609
610 if (multiq) {
611 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
612 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
613 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
614 if (netif_queue_stopped(fifo->dev)) {
615 fifo->queue_state = FIFO_QUEUE_START;
616 netif_wake_queue(fifo->dev);
617 }
618 }
619 }
620
621 /**
622 * init_shared_mem - Allocation and Initialization of Memory
623 * @nic: Device private variable.
624 * Description: The function allocates all the memory areas shared
625 * between the NIC and the driver. This includes Tx descriptors,
626 * Rx descriptors and the statistics block.
627 */
628
629 static int init_shared_mem(struct s2io_nic *nic)
630 {
631 u32 size;
632 void *tmp_v_addr, *tmp_v_addr_next;
633 dma_addr_t tmp_p_addr, tmp_p_addr_next;
634 struct RxD_block *pre_rxd_blk = NULL;
635 int i, j, blk_cnt;
636 int lst_size, lst_per_page;
637 struct net_device *dev = nic->dev;
638 unsigned long tmp;
639 struct buffAdd *ba;
640 struct config_param *config = &nic->config;
641 struct mac_info *mac_control = &nic->mac_control;
642 unsigned long long mem_allocated = 0;
643
644 /* Allocation and initialization of TXDLs in FIFOs */
645 size = 0;
646 for (i = 0; i < config->tx_fifo_num; i++) {
647 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
648
649 size += tx_cfg->fifo_len;
650 }
651 if (size > MAX_AVAILABLE_TXDS) {
652 DBG_PRINT(ERR_DBG,
653 "Too many TxDs requested: %d, max supported: %d\n",
654 size, MAX_AVAILABLE_TXDS);
655 return -EINVAL;
656 }
657
658 size = 0;
659 for (i = 0; i < config->tx_fifo_num; i++) {
660 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
661
662 size = tx_cfg->fifo_len;
663 /*
664 * Legal values are from 2 to 8192
665 */
666 if (size < 2) {
667 DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
668 "Valid lengths are 2 through 8192\n",
669 i, size);
670 return -EINVAL;
671 }
672 }
673
674 lst_size = (sizeof(struct TxD) * config->max_txds);
675 lst_per_page = PAGE_SIZE / lst_size;
676
677 for (i = 0; i < config->tx_fifo_num; i++) {
678 struct fifo_info *fifo = &mac_control->fifos[i];
679 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
680 int fifo_len = tx_cfg->fifo_len;
681 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
682
683 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
684 if (!fifo->list_info) {
685 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
686 return -ENOMEM;
687 }
688 mem_allocated += list_holder_size;
689 }
690 for (i = 0; i < config->tx_fifo_num; i++) {
691 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
692 lst_per_page);
693 struct fifo_info *fifo = &mac_control->fifos[i];
694 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
695
696 fifo->tx_curr_put_info.offset = 0;
697 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
698 fifo->tx_curr_get_info.offset = 0;
699 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
700 fifo->fifo_no = i;
701 fifo->nic = nic;
702 fifo->max_txds = MAX_SKB_FRAGS + 2;
703 fifo->dev = dev;
704
705 for (j = 0; j < page_num; j++) {
706 int k = 0;
707 dma_addr_t tmp_p;
708 void *tmp_v;
709 tmp_v = pci_alloc_consistent(nic->pdev,
710 PAGE_SIZE, &tmp_p);
711 if (!tmp_v) {
712 DBG_PRINT(INFO_DBG,
713 "pci_alloc_consistent failed for TxDL\n");
714 return -ENOMEM;
715 }
716 /* If we got a zero DMA address(can happen on
717 * certain platforms like PPC), reallocate.
718 * Store virtual address of page we don't want,
719 * to be freed later.
720 */
721 if (!tmp_p) {
722 mac_control->zerodma_virt_addr = tmp_v;
723 DBG_PRINT(INIT_DBG,
724 "%s: Zero DMA address for TxDL. "
725 "Virtual address %p\n",
726 dev->name, tmp_v);
727 tmp_v = pci_alloc_consistent(nic->pdev,
728 PAGE_SIZE, &tmp_p);
729 if (!tmp_v) {
730 DBG_PRINT(INFO_DBG,
731 "pci_alloc_consistent failed for TxDL\n");
732 return -ENOMEM;
733 }
734 mem_allocated += PAGE_SIZE;
735 }
736 while (k < lst_per_page) {
737 int l = (j * lst_per_page) + k;
738 if (l == tx_cfg->fifo_len)
739 break;
740 fifo->list_info[l].list_virt_addr =
741 tmp_v + (k * lst_size);
742 fifo->list_info[l].list_phy_addr =
743 tmp_p + (k * lst_size);
744 k++;
745 }
746 }
747 }
748
749 for (i = 0; i < config->tx_fifo_num; i++) {
750 struct fifo_info *fifo = &mac_control->fifos[i];
751 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
752
753 size = tx_cfg->fifo_len;
754 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
755 if (!fifo->ufo_in_band_v)
756 return -ENOMEM;
757 mem_allocated += (size * sizeof(u64));
758 }
759
760 /* Allocation and initialization of RXDs in Rings */
761 size = 0;
762 for (i = 0; i < config->rx_ring_num; i++) {
763 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
764 struct ring_info *ring = &mac_control->rings[i];
765
766 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
767 DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
768 "multiple of RxDs per Block\n",
769 dev->name, i);
770 return FAILURE;
771 }
772 size += rx_cfg->num_rxd;
773 ring->block_count = rx_cfg->num_rxd /
774 (rxd_count[nic->rxd_mode] + 1);
775 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
776 }
777 if (nic->rxd_mode == RXD_MODE_1)
778 size = (size * (sizeof(struct RxD1)));
779 else
780 size = (size * (sizeof(struct RxD3)));
781
782 for (i = 0; i < config->rx_ring_num; i++) {
783 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
784 struct ring_info *ring = &mac_control->rings[i];
785
786 ring->rx_curr_get_info.block_index = 0;
787 ring->rx_curr_get_info.offset = 0;
788 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
789 ring->rx_curr_put_info.block_index = 0;
790 ring->rx_curr_put_info.offset = 0;
791 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
792 ring->nic = nic;
793 ring->ring_no = i;
794
795 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
796 /* Allocating all the Rx blocks */
797 for (j = 0; j < blk_cnt; j++) {
798 struct rx_block_info *rx_blocks;
799 int l;
800
801 rx_blocks = &ring->rx_blocks[j];
802 size = SIZE_OF_BLOCK; /* size is always page size */
803 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
804 &tmp_p_addr);
805 if (tmp_v_addr == NULL) {
806 /*
807 * In case of failure, free_shared_mem()
808 * is called, which should free any
809 * memory that was alloced till the
810 * failure happened.
811 */
812 rx_blocks->block_virt_addr = tmp_v_addr;
813 return -ENOMEM;
814 }
815 mem_allocated += size;
816 memset(tmp_v_addr, 0, size);
817
818 size = sizeof(struct rxd_info) *
819 rxd_count[nic->rxd_mode];
820 rx_blocks->block_virt_addr = tmp_v_addr;
821 rx_blocks->block_dma_addr = tmp_p_addr;
822 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
823 if (!rx_blocks->rxds)
824 return -ENOMEM;
825 mem_allocated += size;
826 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
827 rx_blocks->rxds[l].virt_addr =
828 rx_blocks->block_virt_addr +
829 (rxd_size[nic->rxd_mode] * l);
830 rx_blocks->rxds[l].dma_addr =
831 rx_blocks->block_dma_addr +
832 (rxd_size[nic->rxd_mode] * l);
833 }
834 }
835 /* Interlinking all Rx Blocks */
836 for (j = 0; j < blk_cnt; j++) {
837 int next = (j + 1) % blk_cnt;
838 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
839 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
840 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
841 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
842
843 pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
844 pre_rxd_blk->reserved_2_pNext_RxD_block =
845 (unsigned long)tmp_v_addr_next;
846 pre_rxd_blk->pNext_RxD_Blk_physical =
847 (u64)tmp_p_addr_next;
848 }
849 }
850 if (nic->rxd_mode == RXD_MODE_3B) {
851 /*
852 * Allocation of Storages for buffer addresses in 2BUFF mode
853 * and the buffers as well.
854 */
855 for (i = 0; i < config->rx_ring_num; i++) {
856 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
857 struct ring_info *ring = &mac_control->rings[i];
858
859 blk_cnt = rx_cfg->num_rxd /
860 (rxd_count[nic->rxd_mode] + 1);
861 size = sizeof(struct buffAdd *) * blk_cnt;
862 ring->ba = kmalloc(size, GFP_KERNEL);
863 if (!ring->ba)
864 return -ENOMEM;
865 mem_allocated += size;
866 for (j = 0; j < blk_cnt; j++) {
867 int k = 0;
868
869 size = sizeof(struct buffAdd) *
870 (rxd_count[nic->rxd_mode] + 1);
871 ring->ba[j] = kmalloc(size, GFP_KERNEL);
872 if (!ring->ba[j])
873 return -ENOMEM;
874 mem_allocated += size;
875 while (k != rxd_count[nic->rxd_mode]) {
876 ba = &ring->ba[j][k];
877 size = BUF0_LEN + ALIGN_SIZE;
878 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
879 if (!ba->ba_0_org)
880 return -ENOMEM;
881 mem_allocated += size;
882 tmp = (unsigned long)ba->ba_0_org;
883 tmp += ALIGN_SIZE;
884 tmp &= ~((unsigned long)ALIGN_SIZE);
885 ba->ba_0 = (void *)tmp;
886
887 size = BUF1_LEN + ALIGN_SIZE;
888 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
889 if (!ba->ba_1_org)
890 return -ENOMEM;
891 mem_allocated += size;
892 tmp = (unsigned long)ba->ba_1_org;
893 tmp += ALIGN_SIZE;
894 tmp &= ~((unsigned long)ALIGN_SIZE);
895 ba->ba_1 = (void *)tmp;
896 k++;
897 }
898 }
899 }
900 }
901
902 /* Allocation and initialization of Statistics block */
903 size = sizeof(struct stat_block);
904 mac_control->stats_mem =
905 pci_alloc_consistent(nic->pdev, size,
906 &mac_control->stats_mem_phy);
907
908 if (!mac_control->stats_mem) {
909 /*
910 * In case of failure, free_shared_mem() is called, which
911 * should free any memory that was alloced till the
912 * failure happened.
913 */
914 return -ENOMEM;
915 }
916 mem_allocated += size;
917 mac_control->stats_mem_sz = size;
918
919 tmp_v_addr = mac_control->stats_mem;
920 mac_control->stats_info = (struct stat_block *)tmp_v_addr;
921 memset(tmp_v_addr, 0, size);
922 DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
923 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
924 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
925 return SUCCESS;
926 }
927
928 /**
929 * free_shared_mem - Free the allocated Memory
930 * @nic: Device private variable.
931 * Description: This function is to free all memory locations allocated by
932 * the init_shared_mem() function and return it to the kernel.
933 */
934
935 static void free_shared_mem(struct s2io_nic *nic)
936 {
937 int i, j, blk_cnt, size;
938 void *tmp_v_addr;
939 dma_addr_t tmp_p_addr;
940 int lst_size, lst_per_page;
941 struct net_device *dev;
942 int page_num = 0;
943 struct config_param *config;
944 struct mac_info *mac_control;
945 struct stat_block *stats;
946 struct swStat *swstats;
947
948 if (!nic)
949 return;
950
951 dev = nic->dev;
952
953 config = &nic->config;
954 mac_control = &nic->mac_control;
955 stats = mac_control->stats_info;
956 swstats = &stats->sw_stat;
957
958 lst_size = sizeof(struct TxD) * config->max_txds;
959 lst_per_page = PAGE_SIZE / lst_size;
960
961 for (i = 0; i < config->tx_fifo_num; i++) {
962 struct fifo_info *fifo = &mac_control->fifos[i];
963 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
964
965 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
966 for (j = 0; j < page_num; j++) {
967 int mem_blks = (j * lst_per_page);
968 struct list_info_hold *fli;
969
970 if (!fifo->list_info)
971 return;
972
973 fli = &fifo->list_info[mem_blks];
974 if (!fli->list_virt_addr)
975 break;
976 pci_free_consistent(nic->pdev, PAGE_SIZE,
977 fli->list_virt_addr,
978 fli->list_phy_addr);
979 swstats->mem_freed += PAGE_SIZE;
980 }
981 /* If we got a zero DMA address during allocation,
982 * free the page now
983 */
984 if (mac_control->zerodma_virt_addr) {
985 pci_free_consistent(nic->pdev, PAGE_SIZE,
986 mac_control->zerodma_virt_addr,
987 (dma_addr_t)0);
988 DBG_PRINT(INIT_DBG,
989 "%s: Freeing TxDL with zero DMA address. "
990 "Virtual address %p\n",
991 dev->name, mac_control->zerodma_virt_addr);
992 swstats->mem_freed += PAGE_SIZE;
993 }
994 kfree(fifo->list_info);
995 swstats->mem_freed += tx_cfg->fifo_len *
996 sizeof(struct list_info_hold);
997 }
998
999 size = SIZE_OF_BLOCK;
1000 for (i = 0; i < config->rx_ring_num; i++) {
1001 struct ring_info *ring = &mac_control->rings[i];
1002
1003 blk_cnt = ring->block_count;
1004 for (j = 0; j < blk_cnt; j++) {
1005 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1006 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1007 if (tmp_v_addr == NULL)
1008 break;
1009 pci_free_consistent(nic->pdev, size,
1010 tmp_v_addr, tmp_p_addr);
1011 swstats->mem_freed += size;
1012 kfree(ring->rx_blocks[j].rxds);
1013 swstats->mem_freed += sizeof(struct rxd_info) *
1014 rxd_count[nic->rxd_mode];
1015 }
1016 }
1017
1018 if (nic->rxd_mode == RXD_MODE_3B) {
1019 /* Freeing buffer storage addresses in 2BUFF mode. */
1020 for (i = 0; i < config->rx_ring_num; i++) {
1021 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1022 struct ring_info *ring = &mac_control->rings[i];
1023
1024 blk_cnt = rx_cfg->num_rxd /
1025 (rxd_count[nic->rxd_mode] + 1);
1026 for (j = 0; j < blk_cnt; j++) {
1027 int k = 0;
1028 if (!ring->ba[j])
1029 continue;
1030 while (k != rxd_count[nic->rxd_mode]) {
1031 struct buffAdd *ba = &ring->ba[j][k];
1032 kfree(ba->ba_0_org);
1033 swstats->mem_freed +=
1034 BUF0_LEN + ALIGN_SIZE;
1035 kfree(ba->ba_1_org);
1036 swstats->mem_freed +=
1037 BUF1_LEN + ALIGN_SIZE;
1038 k++;
1039 }
1040 kfree(ring->ba[j]);
1041 swstats->mem_freed += sizeof(struct buffAdd) *
1042 (rxd_count[nic->rxd_mode] + 1);
1043 }
1044 kfree(ring->ba);
1045 swstats->mem_freed += sizeof(struct buffAdd *) *
1046 blk_cnt;
1047 }
1048 }
1049
1050 for (i = 0; i < nic->config.tx_fifo_num; i++) {
1051 struct fifo_info *fifo = &mac_control->fifos[i];
1052 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1053
1054 if (fifo->ufo_in_band_v) {
1055 swstats->mem_freed += tx_cfg->fifo_len *
1056 sizeof(u64);
1057 kfree(fifo->ufo_in_band_v);
1058 }
1059 }
1060
1061 if (mac_control->stats_mem) {
1062 swstats->mem_freed += mac_control->stats_mem_sz;
1063 pci_free_consistent(nic->pdev,
1064 mac_control->stats_mem_sz,
1065 mac_control->stats_mem,
1066 mac_control->stats_mem_phy);
1067 }
1068 }
1069
1070 /**
1071 * s2io_verify_pci_mode -
1072 */
1073
1074 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1075 {
1076 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1077 register u64 val64 = 0;
1078 int mode;
1079
1080 val64 = readq(&bar0->pci_mode);
1081 mode = (u8)GET_PCI_MODE(val64);
1082
1083 if (val64 & PCI_MODE_UNKNOWN_MODE)
1084 return -1; /* Unknown PCI mode */
1085 return mode;
1086 }
1087
1088 #define NEC_VENID 0x1033
1089 #define NEC_DEVID 0x0125
1090 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1091 {
1092 struct pci_dev *tdev = NULL;
1093 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1094 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1095 if (tdev->bus == s2io_pdev->bus->parent) {
1096 pci_dev_put(tdev);
1097 return 1;
1098 }
1099 }
1100 }
1101 return 0;
1102 }
1103
1104 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1105 /**
1106 * s2io_print_pci_mode -
1107 */
1108 static int s2io_print_pci_mode(struct s2io_nic *nic)
1109 {
1110 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1111 register u64 val64 = 0;
1112 int mode;
1113 struct config_param *config = &nic->config;
1114 const char *pcimode;
1115
1116 val64 = readq(&bar0->pci_mode);
1117 mode = (u8)GET_PCI_MODE(val64);
1118
1119 if (val64 & PCI_MODE_UNKNOWN_MODE)
1120 return -1; /* Unknown PCI mode */
1121
1122 config->bus_speed = bus_speed[mode];
1123
1124 if (s2io_on_nec_bridge(nic->pdev)) {
1125 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1126 nic->dev->name);
1127 return mode;
1128 }
1129
1130 switch (mode) {
1131 case PCI_MODE_PCI_33:
1132 pcimode = "33MHz PCI bus";
1133 break;
1134 case PCI_MODE_PCI_66:
1135 pcimode = "66MHz PCI bus";
1136 break;
1137 case PCI_MODE_PCIX_M1_66:
1138 pcimode = "66MHz PCIX(M1) bus";
1139 break;
1140 case PCI_MODE_PCIX_M1_100:
1141 pcimode = "100MHz PCIX(M1) bus";
1142 break;
1143 case PCI_MODE_PCIX_M1_133:
1144 pcimode = "133MHz PCIX(M1) bus";
1145 break;
1146 case PCI_MODE_PCIX_M2_66:
1147 pcimode = "133MHz PCIX(M2) bus";
1148 break;
1149 case PCI_MODE_PCIX_M2_100:
1150 pcimode = "200MHz PCIX(M2) bus";
1151 break;
1152 case PCI_MODE_PCIX_M2_133:
1153 pcimode = "266MHz PCIX(M2) bus";
1154 break;
1155 default:
1156 pcimode = "unsupported bus!";
1157 mode = -1;
1158 }
1159
1160 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1161 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1162
1163 return mode;
1164 }
1165
1166 /**
1167 * init_tti - Initialization transmit traffic interrupt scheme
1168 * @nic: device private variable
1169 * @link: link status (UP/DOWN) used to enable/disable continuous
1170 * transmit interrupts
1171 * Description: The function configures transmit traffic interrupts
1172 * Return Value: SUCCESS on success and
1173 * '-1' on failure
1174 */
1175
1176 static int init_tti(struct s2io_nic *nic, int link)
1177 {
1178 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1179 register u64 val64 = 0;
1180 int i;
1181 struct config_param *config = &nic->config;
1182
1183 for (i = 0; i < config->tx_fifo_num; i++) {
1184 /*
1185 * TTI Initialization. Default Tx timer gets us about
1186 * 250 interrupts per sec. Continuous interrupts are enabled
1187 * by default.
1188 */
1189 if (nic->device_type == XFRAME_II_DEVICE) {
1190 int count = (nic->config.bus_speed * 125)/2;
1191 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1192 } else
1193 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1194
1195 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1196 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1197 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1198 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1199 if (i == 0)
1200 if (use_continuous_tx_intrs && (link == LINK_UP))
1201 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1202 writeq(val64, &bar0->tti_data1_mem);
1203
1204 if (nic->config.intr_type == MSI_X) {
1205 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1206 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1207 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1208 TTI_DATA2_MEM_TX_UFC_D(0x300);
1209 } else {
1210 if ((nic->config.tx_steering_type ==
1211 TX_DEFAULT_STEERING) &&
1212 (config->tx_fifo_num > 1) &&
1213 (i >= nic->udp_fifo_idx) &&
1214 (i < (nic->udp_fifo_idx +
1215 nic->total_udp_fifos)))
1216 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1217 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1218 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1219 TTI_DATA2_MEM_TX_UFC_D(0x120);
1220 else
1221 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1222 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1223 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1224 TTI_DATA2_MEM_TX_UFC_D(0x80);
1225 }
1226
1227 writeq(val64, &bar0->tti_data2_mem);
1228
1229 val64 = TTI_CMD_MEM_WE |
1230 TTI_CMD_MEM_STROBE_NEW_CMD |
1231 TTI_CMD_MEM_OFFSET(i);
1232 writeq(val64, &bar0->tti_command_mem);
1233
1234 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1235 TTI_CMD_MEM_STROBE_NEW_CMD,
1236 S2IO_BIT_RESET) != SUCCESS)
1237 return FAILURE;
1238 }
1239
1240 return SUCCESS;
1241 }
1242
1243 /**
1244 * init_nic - Initialization of hardware
1245 * @nic: device private variable
1246 * Description: The function sequentially configures every block
1247 * of the H/W from their reset values.
1248 * Return Value: SUCCESS on success and
1249 * '-1' on failure (endian settings incorrect).
1250 */
1251
1252 static int init_nic(struct s2io_nic *nic)
1253 {
1254 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1255 struct net_device *dev = nic->dev;
1256 register u64 val64 = 0;
1257 void __iomem *add;
1258 u32 time;
1259 int i, j;
1260 int dtx_cnt = 0;
1261 unsigned long long mem_share;
1262 int mem_size;
1263 struct config_param *config = &nic->config;
1264 struct mac_info *mac_control = &nic->mac_control;
1265
1266 /* to set the swapper controle on the card */
1267 if (s2io_set_swapper(nic)) {
1268 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1269 return -EIO;
1270 }
1271
1272 /*
1273 * Herc requires EOI to be removed from reset before XGXS, so..
1274 */
1275 if (nic->device_type & XFRAME_II_DEVICE) {
1276 val64 = 0xA500000000ULL;
1277 writeq(val64, &bar0->sw_reset);
1278 msleep(500);
1279 val64 = readq(&bar0->sw_reset);
1280 }
1281
1282 /* Remove XGXS from reset state */
1283 val64 = 0;
1284 writeq(val64, &bar0->sw_reset);
1285 msleep(500);
1286 val64 = readq(&bar0->sw_reset);
1287
1288 /* Ensure that it's safe to access registers by checking
1289 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1290 */
1291 if (nic->device_type == XFRAME_II_DEVICE) {
1292 for (i = 0; i < 50; i++) {
1293 val64 = readq(&bar0->adapter_status);
1294 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1295 break;
1296 msleep(10);
1297 }
1298 if (i == 50)
1299 return -ENODEV;
1300 }
1301
1302 /* Enable Receiving broadcasts */
1303 add = &bar0->mac_cfg;
1304 val64 = readq(&bar0->mac_cfg);
1305 val64 |= MAC_RMAC_BCAST_ENABLE;
1306 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1307 writel((u32)val64, add);
1308 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1309 writel((u32) (val64 >> 32), (add + 4));
1310
1311 /* Read registers in all blocks */
1312 val64 = readq(&bar0->mac_int_mask);
1313 val64 = readq(&bar0->mc_int_mask);
1314 val64 = readq(&bar0->xgxs_int_mask);
1315
1316 /* Set MTU */
1317 val64 = dev->mtu;
1318 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1319
1320 if (nic->device_type & XFRAME_II_DEVICE) {
1321 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1322 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1323 &bar0->dtx_control, UF);
1324 if (dtx_cnt & 0x1)
1325 msleep(1); /* Necessary!! */
1326 dtx_cnt++;
1327 }
1328 } else {
1329 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1330 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1331 &bar0->dtx_control, UF);
1332 val64 = readq(&bar0->dtx_control);
1333 dtx_cnt++;
1334 }
1335 }
1336
1337 /* Tx DMA Initialization */
1338 val64 = 0;
1339 writeq(val64, &bar0->tx_fifo_partition_0);
1340 writeq(val64, &bar0->tx_fifo_partition_1);
1341 writeq(val64, &bar0->tx_fifo_partition_2);
1342 writeq(val64, &bar0->tx_fifo_partition_3);
1343
1344 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1345 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1346
1347 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1348 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1349
1350 if (i == (config->tx_fifo_num - 1)) {
1351 if (i % 2 == 0)
1352 i++;
1353 }
1354
1355 switch (i) {
1356 case 1:
1357 writeq(val64, &bar0->tx_fifo_partition_0);
1358 val64 = 0;
1359 j = 0;
1360 break;
1361 case 3:
1362 writeq(val64, &bar0->tx_fifo_partition_1);
1363 val64 = 0;
1364 j = 0;
1365 break;
1366 case 5:
1367 writeq(val64, &bar0->tx_fifo_partition_2);
1368 val64 = 0;
1369 j = 0;
1370 break;
1371 case 7:
1372 writeq(val64, &bar0->tx_fifo_partition_3);
1373 val64 = 0;
1374 j = 0;
1375 break;
1376 default:
1377 j++;
1378 break;
1379 }
1380 }
1381
1382 /*
1383 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1384 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1385 */
1386 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1387 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1388
1389 val64 = readq(&bar0->tx_fifo_partition_0);
1390 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1391 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1392
1393 /*
1394 * Initialization of Tx_PA_CONFIG register to ignore packet
1395 * integrity checking.
1396 */
1397 val64 = readq(&bar0->tx_pa_cfg);
1398 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1399 TX_PA_CFG_IGNORE_SNAP_OUI |
1400 TX_PA_CFG_IGNORE_LLC_CTRL |
1401 TX_PA_CFG_IGNORE_L2_ERR;
1402 writeq(val64, &bar0->tx_pa_cfg);
1403
1404 /* Rx DMA intialization. */
1405 val64 = 0;
1406 for (i = 0; i < config->rx_ring_num; i++) {
1407 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1408
1409 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1410 }
1411 writeq(val64, &bar0->rx_queue_priority);
1412
1413 /*
1414 * Allocating equal share of memory to all the
1415 * configured Rings.
1416 */
1417 val64 = 0;
1418 if (nic->device_type & XFRAME_II_DEVICE)
1419 mem_size = 32;
1420 else
1421 mem_size = 64;
1422
1423 for (i = 0; i < config->rx_ring_num; i++) {
1424 switch (i) {
1425 case 0:
1426 mem_share = (mem_size / config->rx_ring_num +
1427 mem_size % config->rx_ring_num);
1428 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1429 continue;
1430 case 1:
1431 mem_share = (mem_size / config->rx_ring_num);
1432 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1433 continue;
1434 case 2:
1435 mem_share = (mem_size / config->rx_ring_num);
1436 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1437 continue;
1438 case 3:
1439 mem_share = (mem_size / config->rx_ring_num);
1440 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1441 continue;
1442 case 4:
1443 mem_share = (mem_size / config->rx_ring_num);
1444 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1445 continue;
1446 case 5:
1447 mem_share = (mem_size / config->rx_ring_num);
1448 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1449 continue;
1450 case 6:
1451 mem_share = (mem_size / config->rx_ring_num);
1452 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1453 continue;
1454 case 7:
1455 mem_share = (mem_size / config->rx_ring_num);
1456 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1457 continue;
1458 }
1459 }
1460 writeq(val64, &bar0->rx_queue_cfg);
1461
1462 /*
1463 * Filling Tx round robin registers
1464 * as per the number of FIFOs for equal scheduling priority
1465 */
1466 switch (config->tx_fifo_num) {
1467 case 1:
1468 val64 = 0x0;
1469 writeq(val64, &bar0->tx_w_round_robin_0);
1470 writeq(val64, &bar0->tx_w_round_robin_1);
1471 writeq(val64, &bar0->tx_w_round_robin_2);
1472 writeq(val64, &bar0->tx_w_round_robin_3);
1473 writeq(val64, &bar0->tx_w_round_robin_4);
1474 break;
1475 case 2:
1476 val64 = 0x0001000100010001ULL;
1477 writeq(val64, &bar0->tx_w_round_robin_0);
1478 writeq(val64, &bar0->tx_w_round_robin_1);
1479 writeq(val64, &bar0->tx_w_round_robin_2);
1480 writeq(val64, &bar0->tx_w_round_robin_3);
1481 val64 = 0x0001000100000000ULL;
1482 writeq(val64, &bar0->tx_w_round_robin_4);
1483 break;
1484 case 3:
1485 val64 = 0x0001020001020001ULL;
1486 writeq(val64, &bar0->tx_w_round_robin_0);
1487 val64 = 0x0200010200010200ULL;
1488 writeq(val64, &bar0->tx_w_round_robin_1);
1489 val64 = 0x0102000102000102ULL;
1490 writeq(val64, &bar0->tx_w_round_robin_2);
1491 val64 = 0x0001020001020001ULL;
1492 writeq(val64, &bar0->tx_w_round_robin_3);
1493 val64 = 0x0200010200000000ULL;
1494 writeq(val64, &bar0->tx_w_round_robin_4);
1495 break;
1496 case 4:
1497 val64 = 0x0001020300010203ULL;
1498 writeq(val64, &bar0->tx_w_round_robin_0);
1499 writeq(val64, &bar0->tx_w_round_robin_1);
1500 writeq(val64, &bar0->tx_w_round_robin_2);
1501 writeq(val64, &bar0->tx_w_round_robin_3);
1502 val64 = 0x0001020300000000ULL;
1503 writeq(val64, &bar0->tx_w_round_robin_4);
1504 break;
1505 case 5:
1506 val64 = 0x0001020304000102ULL;
1507 writeq(val64, &bar0->tx_w_round_robin_0);
1508 val64 = 0x0304000102030400ULL;
1509 writeq(val64, &bar0->tx_w_round_robin_1);
1510 val64 = 0x0102030400010203ULL;
1511 writeq(val64, &bar0->tx_w_round_robin_2);
1512 val64 = 0x0400010203040001ULL;
1513 writeq(val64, &bar0->tx_w_round_robin_3);
1514 val64 = 0x0203040000000000ULL;
1515 writeq(val64, &bar0->tx_w_round_robin_4);
1516 break;
1517 case 6:
1518 val64 = 0x0001020304050001ULL;
1519 writeq(val64, &bar0->tx_w_round_robin_0);
1520 val64 = 0x0203040500010203ULL;
1521 writeq(val64, &bar0->tx_w_round_robin_1);
1522 val64 = 0x0405000102030405ULL;
1523 writeq(val64, &bar0->tx_w_round_robin_2);
1524 val64 = 0x0001020304050001ULL;
1525 writeq(val64, &bar0->tx_w_round_robin_3);
1526 val64 = 0x0203040500000000ULL;
1527 writeq(val64, &bar0->tx_w_round_robin_4);
1528 break;
1529 case 7:
1530 val64 = 0x0001020304050600ULL;
1531 writeq(val64, &bar0->tx_w_round_robin_0);
1532 val64 = 0x0102030405060001ULL;
1533 writeq(val64, &bar0->tx_w_round_robin_1);
1534 val64 = 0x0203040506000102ULL;
1535 writeq(val64, &bar0->tx_w_round_robin_2);
1536 val64 = 0x0304050600010203ULL;
1537 writeq(val64, &bar0->tx_w_round_robin_3);
1538 val64 = 0x0405060000000000ULL;
1539 writeq(val64, &bar0->tx_w_round_robin_4);
1540 break;
1541 case 8:
1542 val64 = 0x0001020304050607ULL;
1543 writeq(val64, &bar0->tx_w_round_robin_0);
1544 writeq(val64, &bar0->tx_w_round_robin_1);
1545 writeq(val64, &bar0->tx_w_round_robin_2);
1546 writeq(val64, &bar0->tx_w_round_robin_3);
1547 val64 = 0x0001020300000000ULL;
1548 writeq(val64, &bar0->tx_w_round_robin_4);
1549 break;
1550 }
1551
1552 /* Enable all configured Tx FIFO partitions */
1553 val64 = readq(&bar0->tx_fifo_partition_0);
1554 val64 |= (TX_FIFO_PARTITION_EN);
1555 writeq(val64, &bar0->tx_fifo_partition_0);
1556
1557 /* Filling the Rx round robin registers as per the
1558 * number of Rings and steering based on QoS with
1559 * equal priority.
1560 */
1561 switch (config->rx_ring_num) {
1562 case 1:
1563 val64 = 0x0;
1564 writeq(val64, &bar0->rx_w_round_robin_0);
1565 writeq(val64, &bar0->rx_w_round_robin_1);
1566 writeq(val64, &bar0->rx_w_round_robin_2);
1567 writeq(val64, &bar0->rx_w_round_robin_3);
1568 writeq(val64, &bar0->rx_w_round_robin_4);
1569
1570 val64 = 0x8080808080808080ULL;
1571 writeq(val64, &bar0->rts_qos_steering);
1572 break;
1573 case 2:
1574 val64 = 0x0001000100010001ULL;
1575 writeq(val64, &bar0->rx_w_round_robin_0);
1576 writeq(val64, &bar0->rx_w_round_robin_1);
1577 writeq(val64, &bar0->rx_w_round_robin_2);
1578 writeq(val64, &bar0->rx_w_round_robin_3);
1579 val64 = 0x0001000100000000ULL;
1580 writeq(val64, &bar0->rx_w_round_robin_4);
1581
1582 val64 = 0x8080808040404040ULL;
1583 writeq(val64, &bar0->rts_qos_steering);
1584 break;
1585 case 3:
1586 val64 = 0x0001020001020001ULL;
1587 writeq(val64, &bar0->rx_w_round_robin_0);
1588 val64 = 0x0200010200010200ULL;
1589 writeq(val64, &bar0->rx_w_round_robin_1);
1590 val64 = 0x0102000102000102ULL;
1591 writeq(val64, &bar0->rx_w_round_robin_2);
1592 val64 = 0x0001020001020001ULL;
1593 writeq(val64, &bar0->rx_w_round_robin_3);
1594 val64 = 0x0200010200000000ULL;
1595 writeq(val64, &bar0->rx_w_round_robin_4);
1596
1597 val64 = 0x8080804040402020ULL;
1598 writeq(val64, &bar0->rts_qos_steering);
1599 break;
1600 case 4:
1601 val64 = 0x0001020300010203ULL;
1602 writeq(val64, &bar0->rx_w_round_robin_0);
1603 writeq(val64, &bar0->rx_w_round_robin_1);
1604 writeq(val64, &bar0->rx_w_round_robin_2);
1605 writeq(val64, &bar0->rx_w_round_robin_3);
1606 val64 = 0x0001020300000000ULL;
1607 writeq(val64, &bar0->rx_w_round_robin_4);
1608
1609 val64 = 0x8080404020201010ULL;
1610 writeq(val64, &bar0->rts_qos_steering);
1611 break;
1612 case 5:
1613 val64 = 0x0001020304000102ULL;
1614 writeq(val64, &bar0->rx_w_round_robin_0);
1615 val64 = 0x0304000102030400ULL;
1616 writeq(val64, &bar0->rx_w_round_robin_1);
1617 val64 = 0x0102030400010203ULL;
1618 writeq(val64, &bar0->rx_w_round_robin_2);
1619 val64 = 0x0400010203040001ULL;
1620 writeq(val64, &bar0->rx_w_round_robin_3);
1621 val64 = 0x0203040000000000ULL;
1622 writeq(val64, &bar0->rx_w_round_robin_4);
1623
1624 val64 = 0x8080404020201008ULL;
1625 writeq(val64, &bar0->rts_qos_steering);
1626 break;
1627 case 6:
1628 val64 = 0x0001020304050001ULL;
1629 writeq(val64, &bar0->rx_w_round_robin_0);
1630 val64 = 0x0203040500010203ULL;
1631 writeq(val64, &bar0->rx_w_round_robin_1);
1632 val64 = 0x0405000102030405ULL;
1633 writeq(val64, &bar0->rx_w_round_robin_2);
1634 val64 = 0x0001020304050001ULL;
1635 writeq(val64, &bar0->rx_w_round_robin_3);
1636 val64 = 0x0203040500000000ULL;
1637 writeq(val64, &bar0->rx_w_round_robin_4);
1638
1639 val64 = 0x8080404020100804ULL;
1640 writeq(val64, &bar0->rts_qos_steering);
1641 break;
1642 case 7:
1643 val64 = 0x0001020304050600ULL;
1644 writeq(val64, &bar0->rx_w_round_robin_0);
1645 val64 = 0x0102030405060001ULL;
1646 writeq(val64, &bar0->rx_w_round_robin_1);
1647 val64 = 0x0203040506000102ULL;
1648 writeq(val64, &bar0->rx_w_round_robin_2);
1649 val64 = 0x0304050600010203ULL;
1650 writeq(val64, &bar0->rx_w_round_robin_3);
1651 val64 = 0x0405060000000000ULL;
1652 writeq(val64, &bar0->rx_w_round_robin_4);
1653
1654 val64 = 0x8080402010080402ULL;
1655 writeq(val64, &bar0->rts_qos_steering);
1656 break;
1657 case 8:
1658 val64 = 0x0001020304050607ULL;
1659 writeq(val64, &bar0->rx_w_round_robin_0);
1660 writeq(val64, &bar0->rx_w_round_robin_1);
1661 writeq(val64, &bar0->rx_w_round_robin_2);
1662 writeq(val64, &bar0->rx_w_round_robin_3);
1663 val64 = 0x0001020300000000ULL;
1664 writeq(val64, &bar0->rx_w_round_robin_4);
1665
1666 val64 = 0x8040201008040201ULL;
1667 writeq(val64, &bar0->rts_qos_steering);
1668 break;
1669 }
1670
1671 /* UDP Fix */
1672 val64 = 0;
1673 for (i = 0; i < 8; i++)
1674 writeq(val64, &bar0->rts_frm_len_n[i]);
1675
1676 /* Set the default rts frame length for the rings configured */
1677 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1678 for (i = 0 ; i < config->rx_ring_num ; i++)
1679 writeq(val64, &bar0->rts_frm_len_n[i]);
1680
1681 /* Set the frame length for the configured rings
1682 * desired by the user
1683 */
1684 for (i = 0; i < config->rx_ring_num; i++) {
1685 /* If rts_frm_len[i] == 0 then it is assumed that user not
1686 * specified frame length steering.
1687 * If the user provides the frame length then program
1688 * the rts_frm_len register for those values or else
1689 * leave it as it is.
1690 */
1691 if (rts_frm_len[i] != 0) {
1692 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1693 &bar0->rts_frm_len_n[i]);
1694 }
1695 }
1696
1697 /* Disable differentiated services steering logic */
1698 for (i = 0; i < 64; i++) {
1699 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1700 DBG_PRINT(ERR_DBG,
1701 "%s: rts_ds_steer failed on codepoint %d\n",
1702 dev->name, i);
1703 return -ENODEV;
1704 }
1705 }
1706
1707 /* Program statistics memory */
1708 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1709
1710 if (nic->device_type == XFRAME_II_DEVICE) {
1711 val64 = STAT_BC(0x320);
1712 writeq(val64, &bar0->stat_byte_cnt);
1713 }
1714
1715 /*
1716 * Initializing the sampling rate for the device to calculate the
1717 * bandwidth utilization.
1718 */
1719 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1720 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1721 writeq(val64, &bar0->mac_link_util);
1722
1723 /*
1724 * Initializing the Transmit and Receive Traffic Interrupt
1725 * Scheme.
1726 */
1727
1728 /* Initialize TTI */
1729 if (SUCCESS != init_tti(nic, nic->last_link_state))
1730 return -ENODEV;
1731
1732 /* RTI Initialization */
1733 if (nic->device_type == XFRAME_II_DEVICE) {
1734 /*
1735 * Programmed to generate Apprx 500 Intrs per
1736 * second
1737 */
1738 int count = (nic->config.bus_speed * 125)/4;
1739 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1740 } else
1741 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1742 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1743 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1744 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1745 RTI_DATA1_MEM_RX_TIMER_AC_EN;
1746
1747 writeq(val64, &bar0->rti_data1_mem);
1748
1749 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1750 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1751 if (nic->config.intr_type == MSI_X)
1752 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1753 RTI_DATA2_MEM_RX_UFC_D(0x40));
1754 else
1755 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1756 RTI_DATA2_MEM_RX_UFC_D(0x80));
1757 writeq(val64, &bar0->rti_data2_mem);
1758
1759 for (i = 0; i < config->rx_ring_num; i++) {
1760 val64 = RTI_CMD_MEM_WE |
1761 RTI_CMD_MEM_STROBE_NEW_CMD |
1762 RTI_CMD_MEM_OFFSET(i);
1763 writeq(val64, &bar0->rti_command_mem);
1764
1765 /*
1766 * Once the operation completes, the Strobe bit of the
1767 * command register will be reset. We poll for this
1768 * particular condition. We wait for a maximum of 500ms
1769 * for the operation to complete, if it's not complete
1770 * by then we return error.
1771 */
1772 time = 0;
1773 while (true) {
1774 val64 = readq(&bar0->rti_command_mem);
1775 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1776 break;
1777
1778 if (time > 10) {
1779 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
1780 dev->name);
1781 return -ENODEV;
1782 }
1783 time++;
1784 msleep(50);
1785 }
1786 }
1787
1788 /*
1789 * Initializing proper values as Pause threshold into all
1790 * the 8 Queues on Rx side.
1791 */
1792 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1793 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1794
1795 /* Disable RMAC PAD STRIPPING */
1796 add = &bar0->mac_cfg;
1797 val64 = readq(&bar0->mac_cfg);
1798 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1799 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1800 writel((u32) (val64), add);
1801 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1802 writel((u32) (val64 >> 32), (add + 4));
1803 val64 = readq(&bar0->mac_cfg);
1804
1805 /* Enable FCS stripping by adapter */
1806 add = &bar0->mac_cfg;
1807 val64 = readq(&bar0->mac_cfg);
1808 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1809 if (nic->device_type == XFRAME_II_DEVICE)
1810 writeq(val64, &bar0->mac_cfg);
1811 else {
1812 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1813 writel((u32) (val64), add);
1814 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1815 writel((u32) (val64 >> 32), (add + 4));
1816 }
1817
1818 /*
1819 * Set the time value to be inserted in the pause frame
1820 * generated by xena.
1821 */
1822 val64 = readq(&bar0->rmac_pause_cfg);
1823 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1824 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1825 writeq(val64, &bar0->rmac_pause_cfg);
1826
1827 /*
1828 * Set the Threshold Limit for Generating the pause frame
1829 * If the amount of data in any Queue exceeds ratio of
1830 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1831 * pause frame is generated
1832 */
1833 val64 = 0;
1834 for (i = 0; i < 4; i++) {
1835 val64 |= (((u64)0xFF00 |
1836 nic->mac_control.mc_pause_threshold_q0q3)
1837 << (i * 2 * 8));
1838 }
1839 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1840
1841 val64 = 0;
1842 for (i = 0; i < 4; i++) {
1843 val64 |= (((u64)0xFF00 |
1844 nic->mac_control.mc_pause_threshold_q4q7)
1845 << (i * 2 * 8));
1846 }
1847 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1848
1849 /*
1850 * TxDMA will stop Read request if the number of read split has
1851 * exceeded the limit pointed by shared_splits
1852 */
1853 val64 = readq(&bar0->pic_control);
1854 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1855 writeq(val64, &bar0->pic_control);
1856
1857 if (nic->config.bus_speed == 266) {
1858 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1859 writeq(0x0, &bar0->read_retry_delay);
1860 writeq(0x0, &bar0->write_retry_delay);
1861 }
1862
1863 /*
1864 * Programming the Herc to split every write transaction
1865 * that does not start on an ADB to reduce disconnects.
1866 */
1867 if (nic->device_type == XFRAME_II_DEVICE) {
1868 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1869 MISC_LINK_STABILITY_PRD(3);
1870 writeq(val64, &bar0->misc_control);
1871 val64 = readq(&bar0->pic_control2);
1872 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1873 writeq(val64, &bar0->pic_control2);
1874 }
1875 if (strstr(nic->product_name, "CX4")) {
1876 val64 = TMAC_AVG_IPG(0x17);
1877 writeq(val64, &bar0->tmac_avg_ipg);
1878 }
1879
1880 return SUCCESS;
1881 }
1882 #define LINK_UP_DOWN_INTERRUPT 1
1883 #define MAC_RMAC_ERR_TIMER 2
1884
1885 static int s2io_link_fault_indication(struct s2io_nic *nic)
1886 {
1887 if (nic->device_type == XFRAME_II_DEVICE)
1888 return LINK_UP_DOWN_INTERRUPT;
1889 else
1890 return MAC_RMAC_ERR_TIMER;
1891 }
1892
1893 /**
1894 * do_s2io_write_bits - update alarm bits in alarm register
1895 * @value: alarm bits
1896 * @flag: interrupt status
1897 * @addr: address value
1898 * Description: update alarm bits in alarm register
1899 * Return Value:
1900 * NONE.
1901 */
1902 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1903 {
1904 u64 temp64;
1905
1906 temp64 = readq(addr);
1907
1908 if (flag == ENABLE_INTRS)
1909 temp64 &= ~((u64)value);
1910 else
1911 temp64 |= ((u64)value);
1912 writeq(temp64, addr);
1913 }
1914
1915 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1916 {
1917 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1918 register u64 gen_int_mask = 0;
1919 u64 interruptible;
1920
1921 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1922 if (mask & TX_DMA_INTR) {
1923 gen_int_mask |= TXDMA_INT_M;
1924
1925 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1926 TXDMA_PCC_INT | TXDMA_TTI_INT |
1927 TXDMA_LSO_INT | TXDMA_TPA_INT |
1928 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1929
1930 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1931 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1932 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1933 &bar0->pfc_err_mask);
1934
1935 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1936 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1937 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1938
1939 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1940 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1941 PCC_N_SERR | PCC_6_COF_OV_ERR |
1942 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1943 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1944 PCC_TXB_ECC_SG_ERR,
1945 flag, &bar0->pcc_err_mask);
1946
1947 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1948 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1949
1950 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1951 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1952 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1953 flag, &bar0->lso_err_mask);
1954
1955 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1956 flag, &bar0->tpa_err_mask);
1957
1958 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1959 }
1960
1961 if (mask & TX_MAC_INTR) {
1962 gen_int_mask |= TXMAC_INT_M;
1963 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1964 &bar0->mac_int_mask);
1965 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1966 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1967 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1968 flag, &bar0->mac_tmac_err_mask);
1969 }
1970
1971 if (mask & TX_XGXS_INTR) {
1972 gen_int_mask |= TXXGXS_INT_M;
1973 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1974 &bar0->xgxs_int_mask);
1975 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1976 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1977 flag, &bar0->xgxs_txgxs_err_mask);
1978 }
1979
1980 if (mask & RX_DMA_INTR) {
1981 gen_int_mask |= RXDMA_INT_M;
1982 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1983 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1984 flag, &bar0->rxdma_int_mask);
1985 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1986 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1987 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1988 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1989 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1990 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1991 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1992 &bar0->prc_pcix_err_mask);
1993 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1994 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1995 &bar0->rpa_err_mask);
1996 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1997 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1998 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1999 RDA_FRM_ECC_SG_ERR |
2000 RDA_MISC_ERR|RDA_PCIX_ERR,
2001 flag, &bar0->rda_err_mask);
2002 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2003 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2004 flag, &bar0->rti_err_mask);
2005 }
2006
2007 if (mask & RX_MAC_INTR) {
2008 gen_int_mask |= RXMAC_INT_M;
2009 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2010 &bar0->mac_int_mask);
2011 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2012 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2013 RMAC_DOUBLE_ECC_ERR);
2014 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2015 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2016 do_s2io_write_bits(interruptible,
2017 flag, &bar0->mac_rmac_err_mask);
2018 }
2019
2020 if (mask & RX_XGXS_INTR) {
2021 gen_int_mask |= RXXGXS_INT_M;
2022 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2023 &bar0->xgxs_int_mask);
2024 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2025 &bar0->xgxs_rxgxs_err_mask);
2026 }
2027
2028 if (mask & MC_INTR) {
2029 gen_int_mask |= MC_INT_M;
2030 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2031 flag, &bar0->mc_int_mask);
2032 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2033 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2034 &bar0->mc_err_mask);
2035 }
2036 nic->general_int_mask = gen_int_mask;
2037
2038 /* Remove this line when alarm interrupts are enabled */
2039 nic->general_int_mask = 0;
2040 }
2041
2042 /**
2043 * en_dis_able_nic_intrs - Enable or Disable the interrupts
2044 * @nic: device private variable,
2045 * @mask: A mask indicating which Intr block must be modified and,
2046 * @flag: A flag indicating whether to enable or disable the Intrs.
2047 * Description: This function will either disable or enable the interrupts
2048 * depending on the flag argument. The mask argument can be used to
2049 * enable/disable any Intr block.
2050 * Return Value: NONE.
2051 */
2052
2053 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2054 {
2055 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2056 register u64 temp64 = 0, intr_mask = 0;
2057
2058 intr_mask = nic->general_int_mask;
2059
2060 /* Top level interrupt classification */
2061 /* PIC Interrupts */
2062 if (mask & TX_PIC_INTR) {
2063 /* Enable PIC Intrs in the general intr mask register */
2064 intr_mask |= TXPIC_INT_M;
2065 if (flag == ENABLE_INTRS) {
2066 /*
2067 * If Hercules adapter enable GPIO otherwise
2068 * disable all PCIX, Flash, MDIO, IIC and GPIO
2069 * interrupts for now.
2070 * TODO
2071 */
2072 if (s2io_link_fault_indication(nic) ==
2073 LINK_UP_DOWN_INTERRUPT) {
2074 do_s2io_write_bits(PIC_INT_GPIO, flag,
2075 &bar0->pic_int_mask);
2076 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2077 &bar0->gpio_int_mask);
2078 } else
2079 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2080 } else if (flag == DISABLE_INTRS) {
2081 /*
2082 * Disable PIC Intrs in the general
2083 * intr mask register
2084 */
2085 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2086 }
2087 }
2088
2089 /* Tx traffic interrupts */
2090 if (mask & TX_TRAFFIC_INTR) {
2091 intr_mask |= TXTRAFFIC_INT_M;
2092 if (flag == ENABLE_INTRS) {
2093 /*
2094 * Enable all the Tx side interrupts
2095 * writing 0 Enables all 64 TX interrupt levels
2096 */
2097 writeq(0x0, &bar0->tx_traffic_mask);
2098 } else if (flag == DISABLE_INTRS) {
2099 /*
2100 * Disable Tx Traffic Intrs in the general intr mask
2101 * register.
2102 */
2103 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2104 }
2105 }
2106
2107 /* Rx traffic interrupts */
2108 if (mask & RX_TRAFFIC_INTR) {
2109 intr_mask |= RXTRAFFIC_INT_M;
2110 if (flag == ENABLE_INTRS) {
2111 /* writing 0 Enables all 8 RX interrupt levels */
2112 writeq(0x0, &bar0->rx_traffic_mask);
2113 } else if (flag == DISABLE_INTRS) {
2114 /*
2115 * Disable Rx Traffic Intrs in the general intr mask
2116 * register.
2117 */
2118 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2119 }
2120 }
2121
2122 temp64 = readq(&bar0->general_int_mask);
2123 if (flag == ENABLE_INTRS)
2124 temp64 &= ~((u64)intr_mask);
2125 else
2126 temp64 = DISABLE_ALL_INTRS;
2127 writeq(temp64, &bar0->general_int_mask);
2128
2129 nic->general_int_mask = readq(&bar0->general_int_mask);
2130 }
2131
2132 /**
2133 * verify_pcc_quiescent- Checks for PCC quiescent state
2134 * Return: 1 If PCC is quiescence
2135 * 0 If PCC is not quiescence
2136 */
2137 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2138 {
2139 int ret = 0, herc;
2140 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2141 u64 val64 = readq(&bar0->adapter_status);
2142
2143 herc = (sp->device_type == XFRAME_II_DEVICE);
2144
2145 if (flag == false) {
2146 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2147 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2148 ret = 1;
2149 } else {
2150 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2151 ret = 1;
2152 }
2153 } else {
2154 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2155 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2156 ADAPTER_STATUS_RMAC_PCC_IDLE))
2157 ret = 1;
2158 } else {
2159 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2160 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2161 ret = 1;
2162 }
2163 }
2164
2165 return ret;
2166 }
2167 /**
2168 * verify_xena_quiescence - Checks whether the H/W is ready
2169 * Description: Returns whether the H/W is ready to go or not. Depending
2170 * on whether adapter enable bit was written or not the comparison
2171 * differs and the calling function passes the input argument flag to
2172 * indicate this.
2173 * Return: 1 If xena is quiescence
2174 * 0 If Xena is not quiescence
2175 */
2176
2177 static int verify_xena_quiescence(struct s2io_nic *sp)
2178 {
2179 int mode;
2180 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2181 u64 val64 = readq(&bar0->adapter_status);
2182 mode = s2io_verify_pci_mode(sp);
2183
2184 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2185 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
2186 return 0;
2187 }
2188 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2189 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
2190 return 0;
2191 }
2192 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2193 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
2194 return 0;
2195 }
2196 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2197 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
2198 return 0;
2199 }
2200 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2201 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
2202 return 0;
2203 }
2204 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2205 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
2206 return 0;
2207 }
2208 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2209 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
2210 return 0;
2211 }
2212 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2213 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
2214 return 0;
2215 }
2216
2217 /*
2218 * In PCI 33 mode, the P_PLL is not used, and therefore,
2219 * the the P_PLL_LOCK bit in the adapter_status register will
2220 * not be asserted.
2221 */
2222 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2223 sp->device_type == XFRAME_II_DEVICE &&
2224 mode != PCI_MODE_PCI_33) {
2225 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
2226 return 0;
2227 }
2228 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2229 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2230 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
2231 return 0;
2232 }
2233 return 1;
2234 }
2235
2236 /**
2237 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2238 * @sp: Pointer to device specifc structure
2239 * Description :
2240 * New procedure to clear mac address reading problems on Alpha platforms
2241 *
2242 */
2243
2244 static void fix_mac_address(struct s2io_nic *sp)
2245 {
2246 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2247 u64 val64;
2248 int i = 0;
2249
2250 while (fix_mac[i] != END_SIGN) {
2251 writeq(fix_mac[i++], &bar0->gpio_control);
2252 udelay(10);
2253 val64 = readq(&bar0->gpio_control);
2254 }
2255 }
2256
2257 /**
2258 * start_nic - Turns the device on
2259 * @nic : device private variable.
2260 * Description:
2261 * This function actually turns the device on. Before this function is
2262 * called,all Registers are configured from their reset states
2263 * and shared memory is allocated but the NIC is still quiescent. On
2264 * calling this function, the device interrupts are cleared and the NIC is
2265 * literally switched on by writing into the adapter control register.
2266 * Return Value:
2267 * SUCCESS on success and -1 on failure.
2268 */
2269
2270 static int start_nic(struct s2io_nic *nic)
2271 {
2272 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2273 struct net_device *dev = nic->dev;
2274 register u64 val64 = 0;
2275 u16 subid, i;
2276 struct config_param *config = &nic->config;
2277 struct mac_info *mac_control = &nic->mac_control;
2278
2279 /* PRC Initialization and configuration */
2280 for (i = 0; i < config->rx_ring_num; i++) {
2281 struct ring_info *ring = &mac_control->rings[i];
2282
2283 writeq((u64)ring->rx_blocks[0].block_dma_addr,
2284 &bar0->prc_rxd0_n[i]);
2285
2286 val64 = readq(&bar0->prc_ctrl_n[i]);
2287 if (nic->rxd_mode == RXD_MODE_1)
2288 val64 |= PRC_CTRL_RC_ENABLED;
2289 else
2290 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2291 if (nic->device_type == XFRAME_II_DEVICE)
2292 val64 |= PRC_CTRL_GROUP_READS;
2293 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2294 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2295 writeq(val64, &bar0->prc_ctrl_n[i]);
2296 }
2297
2298 if (nic->rxd_mode == RXD_MODE_3B) {
2299 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2300 val64 = readq(&bar0->rx_pa_cfg);
2301 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2302 writeq(val64, &bar0->rx_pa_cfg);
2303 }
2304
2305 if (vlan_tag_strip == 0) {
2306 val64 = readq(&bar0->rx_pa_cfg);
2307 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2308 writeq(val64, &bar0->rx_pa_cfg);
2309 nic->vlan_strip_flag = 0;
2310 }
2311
2312 /*
2313 * Enabling MC-RLDRAM. After enabling the device, we timeout
2314 * for around 100ms, which is approximately the time required
2315 * for the device to be ready for operation.
2316 */
2317 val64 = readq(&bar0->mc_rldram_mrs);
2318 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2319 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2320 val64 = readq(&bar0->mc_rldram_mrs);
2321
2322 msleep(100); /* Delay by around 100 ms. */
2323
2324 /* Enabling ECC Protection. */
2325 val64 = readq(&bar0->adapter_control);
2326 val64 &= ~ADAPTER_ECC_EN;
2327 writeq(val64, &bar0->adapter_control);
2328
2329 /*
2330 * Verify if the device is ready to be enabled, if so enable
2331 * it.
2332 */
2333 val64 = readq(&bar0->adapter_status);
2334 if (!verify_xena_quiescence(nic)) {
2335 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2336 "Adapter status reads: 0x%llx\n",
2337 dev->name, (unsigned long long)val64);
2338 return FAILURE;
2339 }
2340
2341 /*
2342 * With some switches, link might be already up at this point.
2343 * Because of this weird behavior, when we enable laser,
2344 * we may not get link. We need to handle this. We cannot
2345 * figure out which switch is misbehaving. So we are forced to
2346 * make a global change.
2347 */
2348
2349 /* Enabling Laser. */
2350 val64 = readq(&bar0->adapter_control);
2351 val64 |= ADAPTER_EOI_TX_ON;
2352 writeq(val64, &bar0->adapter_control);
2353
2354 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2355 /*
2356 * Dont see link state interrupts initally on some switches,
2357 * so directly scheduling the link state task here.
2358 */
2359 schedule_work(&nic->set_link_task);
2360 }
2361 /* SXE-002: Initialize link and activity LED */
2362 subid = nic->pdev->subsystem_device;
2363 if (((subid & 0xFF) >= 0x07) &&
2364 (nic->device_type == XFRAME_I_DEVICE)) {
2365 val64 = readq(&bar0->gpio_control);
2366 val64 |= 0x0000800000000000ULL;
2367 writeq(val64, &bar0->gpio_control);
2368 val64 = 0x0411040400000000ULL;
2369 writeq(val64, (void __iomem *)bar0 + 0x2700);
2370 }
2371
2372 return SUCCESS;
2373 }
2374 /**
2375 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2376 */
2377 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2378 struct TxD *txdlp, int get_off)
2379 {
2380 struct s2io_nic *nic = fifo_data->nic;
2381 struct sk_buff *skb;
2382 struct TxD *txds;
2383 u16 j, frg_cnt;
2384
2385 txds = txdlp;
2386 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2387 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2388 sizeof(u64), PCI_DMA_TODEVICE);
2389 txds++;
2390 }
2391
2392 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2393 if (!skb) {
2394 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2395 return NULL;
2396 }
2397 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2398 skb_headlen(skb), PCI_DMA_TODEVICE);
2399 frg_cnt = skb_shinfo(skb)->nr_frags;
2400 if (frg_cnt) {
2401 txds++;
2402 for (j = 0; j < frg_cnt; j++, txds++) {
2403 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2404 if (!txds->Buffer_Pointer)
2405 break;
2406 pci_unmap_page(nic->pdev,
2407 (dma_addr_t)txds->Buffer_Pointer,
2408 frag->size, PCI_DMA_TODEVICE);
2409 }
2410 }
2411 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2412 return skb;
2413 }
2414
2415 /**
2416 * free_tx_buffers - Free all queued Tx buffers
2417 * @nic : device private variable.
2418 * Description:
2419 * Free all queued Tx buffers.
2420 * Return Value: void
2421 */
2422
2423 static void free_tx_buffers(struct s2io_nic *nic)
2424 {
2425 struct net_device *dev = nic->dev;
2426 struct sk_buff *skb;
2427 struct TxD *txdp;
2428 int i, j;
2429 int cnt = 0;
2430 struct config_param *config = &nic->config;
2431 struct mac_info *mac_control = &nic->mac_control;
2432 struct stat_block *stats = mac_control->stats_info;
2433 struct swStat *swstats = &stats->sw_stat;
2434
2435 for (i = 0; i < config->tx_fifo_num; i++) {
2436 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2437 struct fifo_info *fifo = &mac_control->fifos[i];
2438 unsigned long flags;
2439
2440 spin_lock_irqsave(&fifo->tx_lock, flags);
2441 for (j = 0; j < tx_cfg->fifo_len; j++) {
2442 txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
2443 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2444 if (skb) {
2445 swstats->mem_freed += skb->truesize;
2446 dev_kfree_skb(skb);
2447 cnt++;
2448 }
2449 }
2450 DBG_PRINT(INTR_DBG,
2451 "%s: forcibly freeing %d skbs on FIFO%d\n",
2452 dev->name, cnt, i);
2453 fifo->tx_curr_get_info.offset = 0;
2454 fifo->tx_curr_put_info.offset = 0;
2455 spin_unlock_irqrestore(&fifo->tx_lock, flags);
2456 }
2457 }
2458
2459 /**
2460 * stop_nic - To stop the nic
2461 * @nic ; device private variable.
2462 * Description:
2463 * This function does exactly the opposite of what the start_nic()
2464 * function does. This function is called to stop the device.
2465 * Return Value:
2466 * void.
2467 */
2468
2469 static void stop_nic(struct s2io_nic *nic)
2470 {
2471 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2472 register u64 val64 = 0;
2473 u16 interruptible;
2474
2475 /* Disable all interrupts */
2476 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2477 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2478 interruptible |= TX_PIC_INTR;
2479 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2480
2481 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2482 val64 = readq(&bar0->adapter_control);
2483 val64 &= ~(ADAPTER_CNTL_EN);
2484 writeq(val64, &bar0->adapter_control);
2485 }
2486
2487 /**
2488 * fill_rx_buffers - Allocates the Rx side skbs
2489 * @ring_info: per ring structure
2490 * @from_card_up: If this is true, we will map the buffer to get
2491 * the dma address for buf0 and buf1 to give it to the card.
2492 * Else we will sync the already mapped buffer to give it to the card.
2493 * Description:
2494 * The function allocates Rx side skbs and puts the physical
2495 * address of these buffers into the RxD buffer pointers, so that the NIC
2496 * can DMA the received frame into these locations.
2497 * The NIC supports 3 receive modes, viz
2498 * 1. single buffer,
2499 * 2. three buffer and
2500 * 3. Five buffer modes.
2501 * Each mode defines how many fragments the received frame will be split
2502 * up into by the NIC. The frame is split into L3 header, L4 Header,
2503 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2504 * is split into 3 fragments. As of now only single buffer mode is
2505 * supported.
2506 * Return Value:
2507 * SUCCESS on success or an appropriate -ve value on failure.
2508 */
2509 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2510 int from_card_up)
2511 {
2512 struct sk_buff *skb;
2513 struct RxD_t *rxdp;
2514 int off, size, block_no, block_no1;
2515 u32 alloc_tab = 0;
2516 u32 alloc_cnt;
2517 u64 tmp;
2518 struct buffAdd *ba;
2519 struct RxD_t *first_rxdp = NULL;
2520 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2521 int rxd_index = 0;
2522 struct RxD1 *rxdp1;
2523 struct RxD3 *rxdp3;
2524 struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
2525
2526 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2527
2528 block_no1 = ring->rx_curr_get_info.block_index;
2529 while (alloc_tab < alloc_cnt) {
2530 block_no = ring->rx_curr_put_info.block_index;
2531
2532 off = ring->rx_curr_put_info.offset;
2533
2534 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2535
2536 rxd_index = off + 1;
2537 if (block_no)
2538 rxd_index += (block_no * ring->rxd_count);
2539
2540 if ((block_no == block_no1) &&
2541 (off == ring->rx_curr_get_info.offset) &&
2542 (rxdp->Host_Control)) {
2543 DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2544 ring->dev->name);
2545 goto end;
2546 }
2547 if (off && (off == ring->rxd_count)) {
2548 ring->rx_curr_put_info.block_index++;
2549 if (ring->rx_curr_put_info.block_index ==
2550 ring->block_count)
2551 ring->rx_curr_put_info.block_index = 0;
2552 block_no = ring->rx_curr_put_info.block_index;
2553 off = 0;
2554 ring->rx_curr_put_info.offset = off;
2555 rxdp = ring->rx_blocks[block_no].block_virt_addr;
2556 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2557 ring->dev->name, rxdp);
2558
2559 }
2560
2561 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2562 ((ring->rxd_mode == RXD_MODE_3B) &&
2563 (rxdp->Control_2 & s2BIT(0)))) {
2564 ring->rx_curr_put_info.offset = off;
2565 goto end;
2566 }
2567 /* calculate size of skb based on ring mode */
2568 size = ring->mtu +
2569 HEADER_ETHERNET_II_802_3_SIZE +
2570 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2571 if (ring->rxd_mode == RXD_MODE_1)
2572 size += NET_IP_ALIGN;
2573 else
2574 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2575
2576 /* allocate skb */
2577 skb = dev_alloc_skb(size);
2578 if (!skb) {
2579 DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2580 ring->dev->name);
2581 if (first_rxdp) {
2582 wmb();
2583 first_rxdp->Control_1 |= RXD_OWN_XENA;
2584 }
2585 swstats->mem_alloc_fail_cnt++;
2586
2587 return -ENOMEM ;
2588 }
2589 swstats->mem_allocated += skb->truesize;
2590
2591 if (ring->rxd_mode == RXD_MODE_1) {
2592 /* 1 buffer mode - normal operation mode */
2593 rxdp1 = (struct RxD1 *)rxdp;
2594 memset(rxdp, 0, sizeof(struct RxD1));
2595 skb_reserve(skb, NET_IP_ALIGN);
2596 rxdp1->Buffer0_ptr =
2597 pci_map_single(ring->pdev, skb->data,
2598 size - NET_IP_ALIGN,
2599 PCI_DMA_FROMDEVICE);
2600 if (pci_dma_mapping_error(nic->pdev,
2601 rxdp1->Buffer0_ptr))
2602 goto pci_map_failed;
2603
2604 rxdp->Control_2 =
2605 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2606 rxdp->Host_Control = (unsigned long)skb;
2607 } else if (ring->rxd_mode == RXD_MODE_3B) {
2608 /*
2609 * 2 buffer mode -
2610 * 2 buffer mode provides 128
2611 * byte aligned receive buffers.
2612 */
2613
2614 rxdp3 = (struct RxD3 *)rxdp;
2615 /* save buffer pointers to avoid frequent dma mapping */
2616 Buffer0_ptr = rxdp3->Buffer0_ptr;
2617 Buffer1_ptr = rxdp3->Buffer1_ptr;
2618 memset(rxdp, 0, sizeof(struct RxD3));
2619 /* restore the buffer pointers for dma sync*/
2620 rxdp3->Buffer0_ptr = Buffer0_ptr;
2621 rxdp3->Buffer1_ptr = Buffer1_ptr;
2622
2623 ba = &ring->ba[block_no][off];
2624 skb_reserve(skb, BUF0_LEN);
2625 tmp = (u64)(unsigned long)skb->data;
2626 tmp += ALIGN_SIZE;
2627 tmp &= ~ALIGN_SIZE;
2628 skb->data = (void *) (unsigned long)tmp;
2629 skb_reset_tail_pointer(skb);
2630
2631 if (from_card_up) {
2632 rxdp3->Buffer0_ptr =
2633 pci_map_single(ring->pdev, ba->ba_0,
2634 BUF0_LEN,
2635 PCI_DMA_FROMDEVICE);
2636 if (pci_dma_mapping_error(nic->pdev,
2637 rxdp3->Buffer0_ptr))
2638 goto pci_map_failed;
2639 } else
2640 pci_dma_sync_single_for_device(ring->pdev,
2641 (dma_addr_t)rxdp3->Buffer0_ptr,
2642 BUF0_LEN,
2643 PCI_DMA_FROMDEVICE);
2644
2645 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2646 if (ring->rxd_mode == RXD_MODE_3B) {
2647 /* Two buffer mode */
2648
2649 /*
2650 * Buffer2 will have L3/L4 header plus
2651 * L4 payload
2652 */
2653 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2654 skb->data,
2655 ring->mtu + 4,
2656 PCI_DMA_FROMDEVICE);
2657
2658 if (pci_dma_mapping_error(nic->pdev,
2659 rxdp3->Buffer2_ptr))
2660 goto pci_map_failed;
2661
2662 if (from_card_up) {
2663 rxdp3->Buffer1_ptr =
2664 pci_map_single(ring->pdev,
2665 ba->ba_1,
2666 BUF1_LEN,
2667 PCI_DMA_FROMDEVICE);
2668
2669 if (pci_dma_mapping_error(nic->pdev,
2670 rxdp3->Buffer1_ptr)) {
2671 pci_unmap_single(ring->pdev,
2672 (dma_addr_t)(unsigned long)
2673 skb->data,
2674 ring->mtu + 4,
2675 PCI_DMA_FROMDEVICE);
2676 goto pci_map_failed;
2677 }
2678 }
2679 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2680 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2681 (ring->mtu + 4);
2682 }
2683 rxdp->Control_2 |= s2BIT(0);
2684 rxdp->Host_Control = (unsigned long) (skb);
2685 }
2686 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2687 rxdp->Control_1 |= RXD_OWN_XENA;
2688 off++;
2689 if (off == (ring->rxd_count + 1))
2690 off = 0;
2691 ring->rx_curr_put_info.offset = off;
2692
2693 rxdp->Control_2 |= SET_RXD_MARKER;
2694 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2695 if (first_rxdp) {
2696 wmb();
2697 first_rxdp->Control_1 |= RXD_OWN_XENA;
2698 }
2699 first_rxdp = rxdp;
2700 }
2701 ring->rx_bufs_left += 1;
2702 alloc_tab++;
2703 }
2704
2705 end:
2706 /* Transfer ownership of first descriptor to adapter just before
2707 * exiting. Before that, use memory barrier so that ownership
2708 * and other fields are seen by adapter correctly.
2709 */
2710 if (first_rxdp) {
2711 wmb();
2712 first_rxdp->Control_1 |= RXD_OWN_XENA;
2713 }
2714
2715 return SUCCESS;
2716
2717 pci_map_failed:
2718 swstats->pci_map_fail_cnt++;
2719 swstats->mem_freed += skb->truesize;
2720 dev_kfree_skb_irq(skb);
2721 return -ENOMEM;
2722 }
2723
2724 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2725 {
2726 struct net_device *dev = sp->dev;
2727 int j;
2728 struct sk_buff *skb;
2729 struct RxD_t *rxdp;
2730 struct buffAdd *ba;
2731 struct RxD1 *rxdp1;
2732 struct RxD3 *rxdp3;
2733 struct mac_info *mac_control = &sp->mac_control;
2734 struct stat_block *stats = mac_control->stats_info;
2735 struct swStat *swstats = &stats->sw_stat;
2736
2737 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2738 rxdp = mac_control->rings[ring_no].
2739 rx_blocks[blk].rxds[j].virt_addr;
2740 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2741 if (!skb)
2742 continue;
2743 if (sp->rxd_mode == RXD_MODE_1) {
2744 rxdp1 = (struct RxD1 *)rxdp;
2745 pci_unmap_single(sp->pdev,
2746 (dma_addr_t)rxdp1->Buffer0_ptr,
2747 dev->mtu +
2748 HEADER_ETHERNET_II_802_3_SIZE +
2749 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2750 PCI_DMA_FROMDEVICE);
2751 memset(rxdp, 0, sizeof(struct RxD1));
2752 } else if (sp->rxd_mode == RXD_MODE_3B) {
2753 rxdp3 = (struct RxD3 *)rxdp;
2754 ba = &mac_control->rings[ring_no].ba[blk][j];
2755 pci_unmap_single(sp->pdev,
2756 (dma_addr_t)rxdp3->Buffer0_ptr,
2757 BUF0_LEN,
2758 PCI_DMA_FROMDEVICE);
2759 pci_unmap_single(sp->pdev,
2760 (dma_addr_t)rxdp3->Buffer1_ptr,
2761 BUF1_LEN,
2762 PCI_DMA_FROMDEVICE);
2763 pci_unmap_single(sp->pdev,
2764 (dma_addr_t)rxdp3->Buffer2_ptr,
2765 dev->mtu + 4,
2766 PCI_DMA_FROMDEVICE);
2767 memset(rxdp, 0, sizeof(struct RxD3));
2768 }
2769 swstats->mem_freed += skb->truesize;
2770 dev_kfree_skb(skb);
2771 mac_control->rings[ring_no].rx_bufs_left -= 1;
2772 }
2773 }
2774
2775 /**
2776 * free_rx_buffers - Frees all Rx buffers
2777 * @sp: device private variable.
2778 * Description:
2779 * This function will free all Rx buffers allocated by host.
2780 * Return Value:
2781 * NONE.
2782 */
2783
2784 static void free_rx_buffers(struct s2io_nic *sp)
2785 {
2786 struct net_device *dev = sp->dev;
2787 int i, blk = 0, buf_cnt = 0;
2788 struct config_param *config = &sp->config;
2789 struct mac_info *mac_control = &sp->mac_control;
2790
2791 for (i = 0; i < config->rx_ring_num; i++) {
2792 struct ring_info *ring = &mac_control->rings[i];
2793
2794 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2795 free_rxd_blk(sp, i, blk);
2796
2797 ring->rx_curr_put_info.block_index = 0;
2798 ring->rx_curr_get_info.block_index = 0;
2799 ring->rx_curr_put_info.offset = 0;
2800 ring->rx_curr_get_info.offset = 0;
2801 ring->rx_bufs_left = 0;
2802 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
2803 dev->name, buf_cnt, i);
2804 }
2805 }
2806
2807 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2808 {
2809 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2810 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2811 ring->dev->name);
2812 }
2813 return 0;
2814 }
2815
2816 /**
2817 * s2io_poll - Rx interrupt handler for NAPI support
2818 * @napi : pointer to the napi structure.
2819 * @budget : The number of packets that were budgeted to be processed
2820 * during one pass through the 'Poll" function.
2821 * Description:
2822 * Comes into picture only if NAPI support has been incorporated. It does
2823 * the same thing that rx_intr_handler does, but not in a interrupt context
2824 * also It will process only a given number of packets.
2825 * Return value:
2826 * 0 on success and 1 if there are No Rx packets to be processed.
2827 */
2828
2829 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2830 {
2831 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2832 struct net_device *dev = ring->dev;
2833 int pkts_processed = 0;
2834 u8 __iomem *addr = NULL;
2835 u8 val8 = 0;
2836 struct s2io_nic *nic = netdev_priv(dev);
2837 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2838 int budget_org = budget;
2839
2840 if (unlikely(!is_s2io_card_up(nic)))
2841 return 0;
2842
2843 pkts_processed = rx_intr_handler(ring, budget);
2844 s2io_chk_rx_buffers(nic, ring);
2845
2846 if (pkts_processed < budget_org) {
2847 napi_complete(napi);
2848 /*Re Enable MSI-Rx Vector*/
2849 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2850 addr += 7 - ring->ring_no;
2851 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2852 writeb(val8, addr);
2853 val8 = readb(addr);
2854 }
2855 return pkts_processed;
2856 }
2857
2858 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2859 {
2860 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2861 int pkts_processed = 0;
2862 int ring_pkts_processed, i;
2863 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2864 int budget_org = budget;
2865 struct config_param *config = &nic->config;
2866 struct mac_info *mac_control = &nic->mac_control;
2867
2868 if (unlikely(!is_s2io_card_up(nic)))
2869 return 0;
2870
2871 for (i = 0; i < config->rx_ring_num; i++) {
2872 struct ring_info *ring = &mac_control->rings[i];
2873 ring_pkts_processed = rx_intr_handler(ring, budget);
2874 s2io_chk_rx_buffers(nic, ring);
2875 pkts_processed += ring_pkts_processed;
2876 budget -= ring_pkts_processed;
2877 if (budget <= 0)
2878 break;
2879 }
2880 if (pkts_processed < budget_org) {
2881 napi_complete(napi);
2882 /* Re enable the Rx interrupts for the ring */
2883 writeq(0, &bar0->rx_traffic_mask);
2884 readl(&bar0->rx_traffic_mask);
2885 }
2886 return pkts_processed;
2887 }
2888
2889 #ifdef CONFIG_NET_POLL_CONTROLLER
2890 /**
2891 * s2io_netpoll - netpoll event handler entry point
2892 * @dev : pointer to the device structure.
2893 * Description:
2894 * This function will be called by upper layer to check for events on the
2895 * interface in situations where interrupts are disabled. It is used for
2896 * specific in-kernel networking tasks, such as remote consoles and kernel
2897 * debugging over the network (example netdump in RedHat).
2898 */
2899 static void s2io_netpoll(struct net_device *dev)
2900 {
2901 struct s2io_nic *nic = netdev_priv(dev);
2902 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2903 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2904 int i;
2905 struct config_param *config = &nic->config;
2906 struct mac_info *mac_control = &nic->mac_control;
2907
2908 if (pci_channel_offline(nic->pdev))
2909 return;
2910
2911 disable_irq(dev->irq);
2912
2913 writeq(val64, &bar0->rx_traffic_int);
2914 writeq(val64, &bar0->tx_traffic_int);
2915
2916 /* we need to free up the transmitted skbufs or else netpoll will
2917 * run out of skbs and will fail and eventually netpoll application such
2918 * as netdump will fail.
2919 */
2920 for (i = 0; i < config->tx_fifo_num; i++)
2921 tx_intr_handler(&mac_control->fifos[i]);
2922
2923 /* check for received packet and indicate up to network */
2924 for (i = 0; i < config->rx_ring_num; i++) {
2925 struct ring_info *ring = &mac_control->rings[i];
2926
2927 rx_intr_handler(ring, 0);
2928 }
2929
2930 for (i = 0; i < config->rx_ring_num; i++) {
2931 struct ring_info *ring = &mac_control->rings[i];
2932
2933 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2934 DBG_PRINT(INFO_DBG,
2935 "%s: Out of memory in Rx Netpoll!!\n",
2936 dev->name);
2937 break;
2938 }
2939 }
2940 enable_irq(dev->irq);
2941 }
2942 #endif
2943
2944 /**
2945 * rx_intr_handler - Rx interrupt handler
2946 * @ring_info: per ring structure.
2947 * @budget: budget for napi processing.
2948 * Description:
2949 * If the interrupt is because of a received frame or if the
2950 * receive ring contains fresh as yet un-processed frames,this function is
2951 * called. It picks out the RxD at which place the last Rx processing had
2952 * stopped and sends the skb to the OSM's Rx handler and then increments
2953 * the offset.
2954 * Return Value:
2955 * No. of napi packets processed.
2956 */
2957 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2958 {
2959 int get_block, put_block;
2960 struct rx_curr_get_info get_info, put_info;
2961 struct RxD_t *rxdp;
2962 struct sk_buff *skb;
2963 int pkt_cnt = 0, napi_pkts = 0;
2964 int i;
2965 struct RxD1 *rxdp1;
2966 struct RxD3 *rxdp3;
2967
2968 get_info = ring_data->rx_curr_get_info;
2969 get_block = get_info.block_index;
2970 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2971 put_block = put_info.block_index;
2972 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2973
2974 while (RXD_IS_UP2DT(rxdp)) {
2975 /*
2976 * If your are next to put index then it's
2977 * FIFO full condition
2978 */
2979 if ((get_block == put_block) &&
2980 (get_info.offset + 1) == put_info.offset) {
2981 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2982 ring_data->dev->name);
2983 break;
2984 }
2985 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2986 if (skb == NULL) {
2987 DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
2988 ring_data->dev->name);
2989 return 0;
2990 }
2991 if (ring_data->rxd_mode == RXD_MODE_1) {
2992 rxdp1 = (struct RxD1 *)rxdp;
2993 pci_unmap_single(ring_data->pdev, (dma_addr_t)
2994 rxdp1->Buffer0_ptr,
2995 ring_data->mtu +
2996 HEADER_ETHERNET_II_802_3_SIZE +
2997 HEADER_802_2_SIZE +
2998 HEADER_SNAP_SIZE,
2999 PCI_DMA_FROMDEVICE);
3000 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
3001 rxdp3 = (struct RxD3 *)rxdp;
3002 pci_dma_sync_single_for_cpu(ring_data->pdev,
3003 (dma_addr_t)rxdp3->Buffer0_ptr,
3004 BUF0_LEN,
3005 PCI_DMA_FROMDEVICE);
3006 pci_unmap_single(ring_data->pdev,
3007 (dma_addr_t)rxdp3->Buffer2_ptr,
3008 ring_data->mtu + 4,
3009 PCI_DMA_FROMDEVICE);
3010 }
3011 prefetch(skb->data);
3012 rx_osm_handler(ring_data, rxdp);
3013 get_info.offset++;
3014 ring_data->rx_curr_get_info.offset = get_info.offset;
3015 rxdp = ring_data->rx_blocks[get_block].
3016 rxds[get_info.offset].virt_addr;
3017 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
3018 get_info.offset = 0;
3019 ring_data->rx_curr_get_info.offset = get_info.offset;
3020 get_block++;
3021 if (get_block == ring_data->block_count)
3022 get_block = 0;
3023 ring_data->rx_curr_get_info.block_index = get_block;
3024 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3025 }
3026
3027 if (ring_data->nic->config.napi) {
3028 budget--;
3029 napi_pkts++;
3030 if (!budget)
3031 break;
3032 }
3033 pkt_cnt++;
3034 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3035 break;
3036 }
3037 if (ring_data->lro) {
3038 /* Clear all LRO sessions before exiting */
3039 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
3040 struct lro *lro = &ring_data->lro0_n[i];
3041 if (lro->in_use) {
3042 update_L3L4_header(ring_data->nic, lro);
3043 queue_rx_frame(lro->parent, lro->vlan_tag);
3044 clear_lro_session(lro);
3045 }
3046 }
3047 }
3048 return napi_pkts;
3049 }
3050
3051 /**
3052 * tx_intr_handler - Transmit interrupt handler
3053 * @nic : device private variable
3054 * Description:
3055 * If an interrupt was raised to indicate DMA complete of the
3056 * Tx packet, this function is called. It identifies the last TxD
3057 * whose buffer was freed and frees all skbs whose data have already
3058 * DMA'ed into the NICs internal memory.
3059 * Return Value:
3060 * NONE
3061 */
3062
3063 static void tx_intr_handler(struct fifo_info *fifo_data)
3064 {
3065 struct s2io_nic *nic = fifo_data->nic;
3066 struct tx_curr_get_info get_info, put_info;
3067 struct sk_buff *skb = NULL;
3068 struct TxD *txdlp;
3069 int pkt_cnt = 0;
3070 unsigned long flags = 0;
3071 u8 err_mask;
3072 struct stat_block *stats = nic->mac_control.stats_info;
3073 struct swStat *swstats = &stats->sw_stat;
3074
3075 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3076 return;
3077
3078 get_info = fifo_data->tx_curr_get_info;
3079 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3080 txdlp = (struct TxD *)
3081 fifo_data->list_info[get_info.offset].list_virt_addr;
3082 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3083 (get_info.offset != put_info.offset) &&
3084 (txdlp->Host_Control)) {
3085 /* Check for TxD errors */
3086 if (txdlp->Control_1 & TXD_T_CODE) {
3087 unsigned long long err;
3088 err = txdlp->Control_1 & TXD_T_CODE;
3089 if (err & 0x1) {
3090 swstats->parity_err_cnt++;
3091 }
3092
3093 /* update t_code statistics */
3094 err_mask = err >> 48;
3095 switch (err_mask) {
3096 case 2:
3097 swstats->tx_buf_abort_cnt++;
3098 break;
3099
3100 case 3:
3101 swstats->tx_desc_abort_cnt++;
3102 break;
3103
3104 case 7:
3105 swstats->tx_parity_err_cnt++;
3106 break;
3107
3108 case 10:
3109 swstats->tx_link_loss_cnt++;
3110 break;
3111
3112 case 15:
3113 swstats->tx_list_proc_err_cnt++;
3114 break;
3115 }
3116 }
3117
3118 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3119 if (skb == NULL) {
3120 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3121 DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3122 __func__);
3123 return;
3124 }
3125 pkt_cnt++;
3126
3127 /* Updating the statistics block */
3128 swstats->mem_freed += skb->truesize;
3129 dev_kfree_skb_irq(skb);
3130
3131 get_info.offset++;
3132 if (get_info.offset == get_info.fifo_len + 1)
3133 get_info.offset = 0;
3134 txdlp = (struct TxD *)
3135 fifo_data->list_info[get_info.offset].list_virt_addr;
3136 fifo_data->tx_curr_get_info.offset = get_info.offset;
3137 }
3138
3139 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3140
3141 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3142 }
3143
3144 /**
3145 * s2io_mdio_write - Function to write in to MDIO registers
3146 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3147 * @addr : address value
3148 * @value : data value
3149 * @dev : pointer to net_device structure
3150 * Description:
3151 * This function is used to write values to the MDIO registers
3152 * NONE
3153 */
3154 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3155 struct net_device *dev)
3156 {
3157 u64 val64;
3158 struct s2io_nic *sp = netdev_priv(dev);
3159 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3160
3161 /* address transaction */
3162 val64 = MDIO_MMD_INDX_ADDR(addr) |
3163 MDIO_MMD_DEV_ADDR(mmd_type) |
3164 MDIO_MMS_PRT_ADDR(0x0);
3165 writeq(val64, &bar0->mdio_control);
3166 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3167 writeq(val64, &bar0->mdio_control);
3168 udelay(100);
3169
3170 /* Data transaction */
3171 val64 = MDIO_MMD_INDX_ADDR(addr) |
3172 MDIO_MMD_DEV_ADDR(mmd_type) |
3173 MDIO_MMS_PRT_ADDR(0x0) |
3174 MDIO_MDIO_DATA(value) |
3175 MDIO_OP(MDIO_OP_WRITE_TRANS);
3176 writeq(val64, &bar0->mdio_control);
3177 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3178 writeq(val64, &bar0->mdio_control);
3179 udelay(100);
3180
3181 val64 = MDIO_MMD_INDX_ADDR(addr) |
3182 MDIO_MMD_DEV_ADDR(mmd_type) |
3183 MDIO_MMS_PRT_ADDR(0x0) |
3184 MDIO_OP(MDIO_OP_READ_TRANS);
3185 writeq(val64, &bar0->mdio_control);
3186 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3187 writeq(val64, &bar0->mdio_control);
3188 udelay(100);
3189 }
3190
3191 /**
3192 * s2io_mdio_read - Function to write in to MDIO registers
3193 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3194 * @addr : address value
3195 * @dev : pointer to net_device structure
3196 * Description:
3197 * This function is used to read values to the MDIO registers
3198 * NONE
3199 */
3200 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3201 {
3202 u64 val64 = 0x0;
3203 u64 rval64 = 0x0;
3204 struct s2io_nic *sp = netdev_priv(dev);
3205 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3206
3207 /* address transaction */
3208 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3209 | MDIO_MMD_DEV_ADDR(mmd_type)
3210 | MDIO_MMS_PRT_ADDR(0x0));
3211 writeq(val64, &bar0->mdio_control);
3212 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3213 writeq(val64, &bar0->mdio_control);
3214 udelay(100);
3215
3216 /* Data transaction */
3217 val64 = MDIO_MMD_INDX_ADDR(addr) |
3218 MDIO_MMD_DEV_ADDR(mmd_type) |
3219 MDIO_MMS_PRT_ADDR(0x0) |
3220 MDIO_OP(MDIO_OP_READ_TRANS);
3221 writeq(val64, &bar0->mdio_control);
3222 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3223 writeq(val64, &bar0->mdio_control);
3224 udelay(100);
3225
3226 /* Read the value from regs */
3227 rval64 = readq(&bar0->mdio_control);
3228 rval64 = rval64 & 0xFFFF0000;
3229 rval64 = rval64 >> 16;
3230 return rval64;
3231 }
3232
3233 /**
3234 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3235 * @counter : counter value to be updated
3236 * @flag : flag to indicate the status
3237 * @type : counter type
3238 * Description:
3239 * This function is to check the status of the xpak counters value
3240 * NONE
3241 */
3242
3243 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3244 u16 flag, u16 type)
3245 {
3246 u64 mask = 0x3;
3247 u64 val64;
3248 int i;
3249 for (i = 0; i < index; i++)
3250 mask = mask << 0x2;
3251
3252 if (flag > 0) {
3253 *counter = *counter + 1;
3254 val64 = *regs_stat & mask;
3255 val64 = val64 >> (index * 0x2);
3256 val64 = val64 + 1;
3257 if (val64 == 3) {
3258 switch (type) {
3259 case 1:
3260 DBG_PRINT(ERR_DBG,
3261 "Take Xframe NIC out of service.\n");
3262 DBG_PRINT(ERR_DBG,
3263 "Excessive temperatures may result in premature transceiver failure.\n");
3264 break;
3265 case 2:
3266 DBG_PRINT(ERR_DBG,
3267 "Take Xframe NIC out of service.\n");
3268 DBG_PRINT(ERR_DBG,
3269 "Excessive bias currents may indicate imminent laser diode failure.\n");
3270 break;
3271 case 3:
3272 DBG_PRINT(ERR_DBG,
3273 "Take Xframe NIC out of service.\n");
3274 DBG_PRINT(ERR_DBG,
3275 "Excessive laser output power may saturate far-end receiver.\n");
3276 break;
3277 default:
3278 DBG_PRINT(ERR_DBG,
3279 "Incorrect XPAK Alarm type\n");
3280 }
3281 val64 = 0x0;
3282 }
3283 val64 = val64 << (index * 0x2);
3284 *regs_stat = (*regs_stat & (~mask)) | (val64);
3285
3286 } else {
3287 *regs_stat = *regs_stat & (~mask);
3288 }
3289 }
3290
3291 /**
3292 * s2io_updt_xpak_counter - Function to update the xpak counters
3293 * @dev : pointer to net_device struct
3294 * Description:
3295 * This function is to upate the status of the xpak counters value
3296 * NONE
3297 */
3298 static void s2io_updt_xpak_counter(struct net_device *dev)
3299 {
3300 u16 flag = 0x0;
3301 u16 type = 0x0;
3302 u16 val16 = 0x0;
3303 u64 val64 = 0x0;
3304 u64 addr = 0x0;
3305
3306 struct s2io_nic *sp = netdev_priv(dev);
3307 struct stat_block *stats = sp->mac_control.stats_info;
3308 struct xpakStat *xstats = &stats->xpak_stat;
3309
3310 /* Check the communication with the MDIO slave */
3311 addr = MDIO_CTRL1;
3312 val64 = 0x0;
3313 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3314 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3315 DBG_PRINT(ERR_DBG,
3316 "ERR: MDIO slave access failed - Returned %llx\n",
3317 (unsigned long long)val64);
3318 return;
3319 }
3320
3321 /* Check for the expected value of control reg 1 */
3322 if (val64 != MDIO_CTRL1_SPEED10G) {
3323 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3324 "Returned: %llx- Expected: 0x%x\n",
3325 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3326 return;
3327 }
3328
3329 /* Loading the DOM register to MDIO register */
3330 addr = 0xA100;
3331 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3332 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3333
3334 /* Reading the Alarm flags */
3335 addr = 0xA070;
3336 val64 = 0x0;
3337 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3338
3339 flag = CHECKBIT(val64, 0x7);
3340 type = 1;
3341 s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3342 &xstats->xpak_regs_stat,
3343 0x0, flag, type);
3344
3345 if (CHECKBIT(val64, 0x6))
3346 xstats->alarm_transceiver_temp_low++;
3347
3348 flag = CHECKBIT(val64, 0x3);
3349 type = 2;
3350 s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3351 &xstats->xpak_regs_stat,
3352 0x2, flag, type);
3353
3354 if (CHECKBIT(val64, 0x2))
3355 xstats->alarm_laser_bias_current_low++;
3356
3357 flag = CHECKBIT(val64, 0x1);
3358 type = 3;
3359 s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3360 &xstats->xpak_regs_stat,
3361 0x4, flag, type);
3362
3363 if (CHECKBIT(val64, 0x0))
3364 xstats->alarm_laser_output_power_low++;
3365
3366 /* Reading the Warning flags */
3367 addr = 0xA074;
3368 val64 = 0x0;
3369 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3370
3371 if (CHECKBIT(val64, 0x7))
3372 xstats->warn_transceiver_temp_high++;
3373
3374 if (CHECKBIT(val64, 0x6))
3375 xstats->warn_transceiver_temp_low++;
3376
3377 if (CHECKBIT(val64, 0x3))
3378 xstats->warn_laser_bias_current_high++;
3379
3380 if (CHECKBIT(val64, 0x2))
3381 xstats->warn_laser_bias_current_low++;
3382
3383 if (CHECKBIT(val64, 0x1))
3384 xstats->warn_laser_output_power_high++;
3385
3386 if (CHECKBIT(val64, 0x0))
3387 xstats->warn_laser_output_power_low++;
3388 }
3389
3390 /**
3391 * wait_for_cmd_complete - waits for a command to complete.
3392 * @sp : private member of the device structure, which is a pointer to the
3393 * s2io_nic structure.
3394 * Description: Function that waits for a command to Write into RMAC
3395 * ADDR DATA registers to be completed and returns either success or
3396 * error depending on whether the command was complete or not.
3397 * Return value:
3398 * SUCCESS on success and FAILURE on failure.
3399 */
3400
3401 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3402 int bit_state)
3403 {
3404 int ret = FAILURE, cnt = 0, delay = 1;
3405 u64 val64;
3406
3407 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3408 return FAILURE;
3409
3410 do {
3411 val64 = readq(addr);
3412 if (bit_state == S2IO_BIT_RESET) {
3413 if (!(val64 & busy_bit)) {
3414 ret = SUCCESS;
3415 break;
3416 }
3417 } else {
3418 if (val64 & busy_bit) {
3419 ret = SUCCESS;
3420 break;
3421 }
3422 }
3423
3424 if (in_interrupt())
3425 mdelay(delay);
3426 else
3427 msleep(delay);
3428
3429 if (++cnt >= 10)
3430 delay = 50;
3431 } while (cnt < 20);
3432 return ret;
3433 }
3434 /*
3435 * check_pci_device_id - Checks if the device id is supported
3436 * @id : device id
3437 * Description: Function to check if the pci device id is supported by driver.
3438 * Return value: Actual device id if supported else PCI_ANY_ID
3439 */
3440 static u16 check_pci_device_id(u16 id)
3441 {
3442 switch (id) {
3443 case PCI_DEVICE_ID_HERC_WIN:
3444 case PCI_DEVICE_ID_HERC_UNI:
3445 return XFRAME_II_DEVICE;
3446 case PCI_DEVICE_ID_S2IO_UNI:
3447 case PCI_DEVICE_ID_S2IO_WIN:
3448 return XFRAME_I_DEVICE;
3449 default:
3450 return PCI_ANY_ID;
3451 }
3452 }
3453
3454 /**
3455 * s2io_reset - Resets the card.
3456 * @sp : private member of the device structure.
3457 * Description: Function to Reset the card. This function then also
3458 * restores the previously saved PCI configuration space registers as
3459 * the card reset also resets the configuration space.
3460 * Return value:
3461 * void.
3462 */
3463
3464 static void s2io_reset(struct s2io_nic *sp)
3465 {
3466 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3467 u64 val64;
3468 u16 subid, pci_cmd;
3469 int i;
3470 u16 val16;
3471 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3472 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3473 struct stat_block *stats;
3474 struct swStat *swstats;
3475
3476 DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3477 __func__, pci_name(sp->pdev));
3478
3479 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3480 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3481
3482 val64 = SW_RESET_ALL;
3483 writeq(val64, &bar0->sw_reset);
3484 if (strstr(sp->product_name, "CX4"))
3485 msleep(750);
3486 msleep(250);
3487 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3488
3489 /* Restore the PCI state saved during initialization. */
3490 pci_restore_state(sp->pdev);
3491 pci_save_state(sp->pdev);
3492 pci_read_config_word(sp->pdev, 0x2, &val16);
3493 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3494 break;
3495 msleep(200);
3496 }
3497
3498 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3499 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3500
3501 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3502
3503 s2io_init_pci(sp);
3504
3505 /* Set swapper to enable I/O register access */
3506 s2io_set_swapper(sp);
3507
3508 /* restore mac_addr entries */
3509 do_s2io_restore_unicast_mc(sp);
3510
3511 /* Restore the MSIX table entries from local variables */
3512 restore_xmsi_data(sp);
3513
3514 /* Clear certain PCI/PCI-X fields after reset */
3515 if (sp->device_type == XFRAME_II_DEVICE) {
3516 /* Clear "detected parity error" bit */
3517 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3518
3519 /* Clearing PCIX Ecc status register */
3520 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3521
3522 /* Clearing PCI_STATUS error reflected here */
3523 writeq(s2BIT(62), &bar0->txpic_int_reg);
3524 }
3525
3526 /* Reset device statistics maintained by OS */
3527 memset(&sp->stats, 0, sizeof(struct net_device_stats));
3528
3529 stats = sp->mac_control.stats_info;
3530 swstats = &stats->sw_stat;
3531
3532 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3533 up_cnt = swstats->link_up_cnt;
3534 down_cnt = swstats->link_down_cnt;
3535 up_time = swstats->link_up_time;
3536 down_time = swstats->link_down_time;
3537 reset_cnt = swstats->soft_reset_cnt;
3538 mem_alloc_cnt = swstats->mem_allocated;
3539 mem_free_cnt = swstats->mem_freed;
3540 watchdog_cnt = swstats->watchdog_timer_cnt;
3541
3542 memset(stats, 0, sizeof(struct stat_block));
3543
3544 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3545 swstats->link_up_cnt = up_cnt;
3546 swstats->link_down_cnt = down_cnt;
3547 swstats->link_up_time = up_time;
3548 swstats->link_down_time = down_time;
3549 swstats->soft_reset_cnt = reset_cnt;
3550 swstats->mem_allocated = mem_alloc_cnt;
3551 swstats->mem_freed = mem_free_cnt;
3552 swstats->watchdog_timer_cnt = watchdog_cnt;
3553
3554 /* SXE-002: Configure link and activity LED to turn it off */
3555 subid = sp->pdev->subsystem_device;
3556 if (((subid & 0xFF) >= 0x07) &&
3557 (sp->device_type == XFRAME_I_DEVICE)) {
3558 val64 = readq(&bar0->gpio_control);
3559 val64 |= 0x0000800000000000ULL;
3560 writeq(val64, &bar0->gpio_control);
3561 val64 = 0x0411040400000000ULL;
3562 writeq(val64, (void __iomem *)bar0 + 0x2700);
3563 }
3564
3565 /*
3566 * Clear spurious ECC interrupts that would have occured on
3567 * XFRAME II cards after reset.
3568 */
3569 if (sp->device_type == XFRAME_II_DEVICE) {
3570 val64 = readq(&bar0->pcc_err_reg);
3571 writeq(val64, &bar0->pcc_err_reg);
3572 }
3573
3574 sp->device_enabled_once = false;
3575 }
3576
3577 /**
3578 * s2io_set_swapper - to set the swapper controle on the card
3579 * @sp : private member of the device structure,
3580 * pointer to the s2io_nic structure.
3581 * Description: Function to set the swapper control on the card
3582 * correctly depending on the 'endianness' of the system.
3583 * Return value:
3584 * SUCCESS on success and FAILURE on failure.
3585 */
3586
3587 static int s2io_set_swapper(struct s2io_nic *sp)
3588 {
3589 struct net_device *dev = sp->dev;
3590 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3591 u64 val64, valt, valr;
3592
3593 /*
3594 * Set proper endian settings and verify the same by reading
3595 * the PIF Feed-back register.
3596 */
3597
3598 val64 = readq(&bar0->pif_rd_swapper_fb);
3599 if (val64 != 0x0123456789ABCDEFULL) {
3600 int i = 0;
3601 static const u64 value[] = {
3602 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3603 0x8100008181000081ULL, /* FE=1, SE=0 */
3604 0x4200004242000042ULL, /* FE=0, SE=1 */
3605 0 /* FE=0, SE=0 */
3606 };
3607
3608 while (i < 4) {
3609 writeq(value[i], &bar0->swapper_ctrl);
3610 val64 = readq(&bar0->pif_rd_swapper_fb);
3611 if (val64 == 0x0123456789ABCDEFULL)
3612 break;
3613 i++;
3614 }
3615 if (i == 4) {
3616 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3617 "feedback read %llx\n",
3618 dev->name, (unsigned long long)val64);
3619 return FAILURE;
3620 }
3621 valr = value[i];
3622 } else {
3623 valr = readq(&bar0->swapper_ctrl);
3624 }
3625
3626 valt = 0x0123456789ABCDEFULL;
3627 writeq(valt, &bar0->xmsi_address);
3628 val64 = readq(&bar0->xmsi_address);
3629
3630 if (val64 != valt) {
3631 int i = 0;
3632 static const u64 value[] = {
3633 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3634 0x0081810000818100ULL, /* FE=1, SE=0 */
3635 0x0042420000424200ULL, /* FE=0, SE=1 */
3636 0 /* FE=0, SE=0 */
3637 };
3638
3639 while (i < 4) {
3640 writeq((value[i] | valr), &bar0->swapper_ctrl);
3641 writeq(valt, &bar0->xmsi_address);
3642 val64 = readq(&bar0->xmsi_address);
3643 if (val64 == valt)
3644 break;
3645 i++;
3646 }
3647 if (i == 4) {
3648 unsigned long long x = val64;
3649 DBG_PRINT(ERR_DBG,
3650 "Write failed, Xmsi_addr reads:0x%llx\n", x);
3651 return FAILURE;
3652 }
3653 }
3654 val64 = readq(&bar0->swapper_ctrl);
3655 val64 &= 0xFFFF000000000000ULL;
3656
3657 #ifdef __BIG_ENDIAN
3658 /*
3659 * The device by default set to a big endian format, so a
3660 * big endian driver need not set anything.
3661 */
3662 val64 |= (SWAPPER_CTRL_TXP_FE |
3663 SWAPPER_CTRL_TXP_SE |
3664 SWAPPER_CTRL_TXD_R_FE |
3665 SWAPPER_CTRL_TXD_W_FE |
3666 SWAPPER_CTRL_TXF_R_FE |
3667 SWAPPER_CTRL_RXD_R_FE |
3668 SWAPPER_CTRL_RXD_W_FE |
3669 SWAPPER_CTRL_RXF_W_FE |
3670 SWAPPER_CTRL_XMSI_FE |
3671 SWAPPER_CTRL_STATS_FE |
3672 SWAPPER_CTRL_STATS_SE);
3673 if (sp->config.intr_type == INTA)
3674 val64 |= SWAPPER_CTRL_XMSI_SE;
3675 writeq(val64, &bar0->swapper_ctrl);
3676 #else
3677 /*
3678 * Initially we enable all bits to make it accessible by the
3679 * driver, then we selectively enable only those bits that
3680 * we want to set.
3681 */
3682 val64 |= (SWAPPER_CTRL_TXP_FE |
3683 SWAPPER_CTRL_TXP_SE |
3684 SWAPPER_CTRL_TXD_R_FE |
3685 SWAPPER_CTRL_TXD_R_SE |
3686 SWAPPER_CTRL_TXD_W_FE |
3687 SWAPPER_CTRL_TXD_W_SE |
3688 SWAPPER_CTRL_TXF_R_FE |
3689 SWAPPER_CTRL_RXD_R_FE |
3690 SWAPPER_CTRL_RXD_R_SE |
3691 SWAPPER_CTRL_RXD_W_FE |
3692 SWAPPER_CTRL_RXD_W_SE |
3693 SWAPPER_CTRL_RXF_W_FE |
3694 SWAPPER_CTRL_XMSI_FE |
3695 SWAPPER_CTRL_STATS_FE |
3696 SWAPPER_CTRL_STATS_SE);
3697 if (sp->config.intr_type == INTA)
3698 val64 |= SWAPPER_CTRL_XMSI_SE;
3699 writeq(val64, &bar0->swapper_ctrl);
3700 #endif
3701 val64 = readq(&bar0->swapper_ctrl);
3702
3703 /*
3704 * Verifying if endian settings are accurate by reading a
3705 * feedback register.
3706 */
3707 val64 = readq(&bar0->pif_rd_swapper_fb);
3708 if (val64 != 0x0123456789ABCDEFULL) {
3709 /* Endian settings are incorrect, calls for another dekko. */
3710 DBG_PRINT(ERR_DBG,
3711 "%s: Endian settings are wrong, feedback read %llx\n",
3712 dev->name, (unsigned long long)val64);
3713 return FAILURE;
3714 }
3715
3716 return SUCCESS;
3717 }
3718
3719 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3720 {
3721 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3722 u64 val64;
3723 int ret = 0, cnt = 0;
3724
3725 do {
3726 val64 = readq(&bar0->xmsi_access);
3727 if (!(val64 & s2BIT(15)))
3728 break;
3729 mdelay(1);
3730 cnt++;
3731 } while (cnt < 5);
3732 if (cnt == 5) {
3733 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3734 ret = 1;
3735 }
3736
3737 return ret;
3738 }
3739
3740 static void restore_xmsi_data(struct s2io_nic *nic)
3741 {
3742 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3743 u64 val64;
3744 int i, msix_index;
3745
3746 if (nic->device_type == XFRAME_I_DEVICE)
3747 return;
3748
3749 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3750 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3751 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3752 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3753 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3754 writeq(val64, &bar0->xmsi_access);
3755 if (wait_for_msix_trans(nic, msix_index)) {
3756 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3757 __func__, msix_index);
3758 continue;
3759 }
3760 }
3761 }
3762
3763 static void store_xmsi_data(struct s2io_nic *nic)
3764 {
3765 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3766 u64 val64, addr, data;
3767 int i, msix_index;
3768
3769 if (nic->device_type == XFRAME_I_DEVICE)
3770 return;
3771
3772 /* Store and display */
3773 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3774 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3775 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3776 writeq(val64, &bar0->xmsi_access);
3777 if (wait_for_msix_trans(nic, msix_index)) {
3778 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3779 __func__, msix_index);
3780 continue;
3781 }
3782 addr = readq(&bar0->xmsi_address);
3783 data = readq(&bar0->xmsi_data);
3784 if (addr && data) {
3785 nic->msix_info[i].addr = addr;
3786 nic->msix_info[i].data = data;
3787 }
3788 }
3789 }
3790
3791 static int s2io_enable_msi_x(struct s2io_nic *nic)
3792 {
3793 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3794 u64 rx_mat;
3795 u16 msi_control; /* Temp variable */
3796 int ret, i, j, msix_indx = 1;
3797 int size;
3798 struct stat_block *stats = nic->mac_control.stats_info;
3799 struct swStat *swstats = &stats->sw_stat;
3800
3801 size = nic->num_entries * sizeof(struct msix_entry);
3802 nic->entries = kzalloc(size, GFP_KERNEL);
3803 if (!nic->entries) {
3804 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3805 __func__);
3806 swstats->mem_alloc_fail_cnt++;
3807 return -ENOMEM;
3808 }
3809 swstats->mem_allocated += size;
3810
3811 size = nic->num_entries * sizeof(struct s2io_msix_entry);
3812 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3813 if (!nic->s2io_entries) {
3814 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3815 __func__);
3816 swstats->mem_alloc_fail_cnt++;
3817 kfree(nic->entries);
3818 swstats->mem_freed
3819 += (nic->num_entries * sizeof(struct msix_entry));
3820 return -ENOMEM;
3821 }
3822 swstats->mem_allocated += size;
3823
3824 nic->entries[0].entry = 0;
3825 nic->s2io_entries[0].entry = 0;
3826 nic->s2io_entries[0].in_use = MSIX_FLG;
3827 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3828 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3829
3830 for (i = 1; i < nic->num_entries; i++) {
3831 nic->entries[i].entry = ((i - 1) * 8) + 1;
3832 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3833 nic->s2io_entries[i].arg = NULL;
3834 nic->s2io_entries[i].in_use = 0;
3835 }
3836
3837 rx_mat = readq(&bar0->rx_mat);
3838 for (j = 0; j < nic->config.rx_ring_num; j++) {
3839 rx_mat |= RX_MAT_SET(j, msix_indx);
3840 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3841 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3842 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3843 msix_indx += 8;
3844 }
3845 writeq(rx_mat, &bar0->rx_mat);
3846 readq(&bar0->rx_mat);
3847
3848 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
3849 /* We fail init if error or we get less vectors than min required */
3850 if (ret) {
3851 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
3852 kfree(nic->entries);
3853 swstats->mem_freed += nic->num_entries *
3854 sizeof(struct msix_entry);
3855 kfree(nic->s2io_entries);
3856 swstats->mem_freed += nic->num_entries *
3857 sizeof(struct s2io_msix_entry);
3858 nic->entries = NULL;
3859 nic->s2io_entries = NULL;
3860 return -ENOMEM;
3861 }
3862
3863 /*
3864 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3865 * in the herc NIC. (Temp change, needs to be removed later)
3866 */
3867 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3868 msi_control |= 0x1; /* Enable MSI */
3869 pci_write_config_word(nic->pdev, 0x42, msi_control);
3870
3871 return 0;
3872 }
3873
3874 /* Handle software interrupt used during MSI(X) test */
3875 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3876 {
3877 struct s2io_nic *sp = dev_id;
3878
3879 sp->msi_detected = 1;
3880 wake_up(&sp->msi_wait);
3881
3882 return IRQ_HANDLED;
3883 }
3884
3885 /* Test interrupt path by forcing a a software IRQ */
3886 static int s2io_test_msi(struct s2io_nic *sp)
3887 {
3888 struct pci_dev *pdev = sp->pdev;
3889 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3890 int err;
3891 u64 val64, saved64;
3892
3893 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3894 sp->name, sp);
3895 if (err) {
3896 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3897 sp->dev->name, pci_name(pdev), pdev->irq);
3898 return err;
3899 }
3900
3901 init_waitqueue_head(&sp->msi_wait);
3902 sp->msi_detected = 0;
3903
3904 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3905 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3906 val64 |= SCHED_INT_CTRL_TIMER_EN;
3907 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3908 writeq(val64, &bar0->scheduled_int_ctrl);
3909
3910 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3911
3912 if (!sp->msi_detected) {
3913 /* MSI(X) test failed, go back to INTx mode */
3914 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3915 "using MSI(X) during test\n",
3916 sp->dev->name, pci_name(pdev));
3917
3918 err = -EOPNOTSUPP;
3919 }
3920
3921 free_irq(sp->entries[1].vector, sp);
3922
3923 writeq(saved64, &bar0->scheduled_int_ctrl);
3924
3925 return err;
3926 }
3927
3928 static void remove_msix_isr(struct s2io_nic *sp)
3929 {
3930 int i;
3931 u16 msi_control;
3932
3933 for (i = 0; i < sp->num_entries; i++) {
3934 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3935 int vector = sp->entries[i].vector;
3936 void *arg = sp->s2io_entries[i].arg;
3937 free_irq(vector, arg);
3938 }
3939 }
3940
3941 kfree(sp->entries);
3942 kfree(sp->s2io_entries);
3943 sp->entries = NULL;
3944 sp->s2io_entries = NULL;
3945
3946 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3947 msi_control &= 0xFFFE; /* Disable MSI */
3948 pci_write_config_word(sp->pdev, 0x42, msi_control);
3949
3950 pci_disable_msix(sp->pdev);
3951 }
3952
3953 static void remove_inta_isr(struct s2io_nic *sp)
3954 {
3955 struct net_device *dev = sp->dev;
3956
3957 free_irq(sp->pdev->irq, dev);
3958 }
3959
3960 /* ********************************************************* *
3961 * Functions defined below concern the OS part of the driver *
3962 * ********************************************************* */
3963
3964 /**
3965 * s2io_open - open entry point of the driver
3966 * @dev : pointer to the device structure.
3967 * Description:
3968 * This function is the open entry point of the driver. It mainly calls a
3969 * function to allocate Rx buffers and inserts them into the buffer
3970 * descriptors and then enables the Rx part of the NIC.
3971 * Return value:
3972 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3973 * file on failure.
3974 */
3975
3976 static int s2io_open(struct net_device *dev)
3977 {
3978 struct s2io_nic *sp = netdev_priv(dev);
3979 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
3980 int err = 0;
3981
3982 /*
3983 * Make sure you have link off by default every time
3984 * Nic is initialized
3985 */
3986 netif_carrier_off(dev);
3987 sp->last_link_state = 0;
3988
3989 /* Initialize H/W and enable interrupts */
3990 err = s2io_card_up(sp);
3991 if (err) {
3992 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3993 dev->name);
3994 goto hw_init_failed;
3995 }
3996
3997 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
3998 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3999 s2io_card_down(sp);
4000 err = -ENODEV;
4001 goto hw_init_failed;
4002 }
4003 s2io_start_all_tx_queue(sp);
4004 return 0;
4005
4006 hw_init_failed:
4007 if (sp->config.intr_type == MSI_X) {
4008 if (sp->entries) {
4009 kfree(sp->entries);
4010 swstats->mem_freed += sp->num_entries *
4011 sizeof(struct msix_entry);
4012 }
4013 if (sp->s2io_entries) {
4014 kfree(sp->s2io_entries);
4015 swstats->mem_freed += sp->num_entries *
4016 sizeof(struct s2io_msix_entry);
4017 }
4018 }
4019 return err;
4020 }
4021
4022 /**
4023 * s2io_close -close entry point of the driver
4024 * @dev : device pointer.
4025 * Description:
4026 * This is the stop entry point of the driver. It needs to undo exactly
4027 * whatever was done by the open entry point,thus it's usually referred to
4028 * as the close function.Among other things this function mainly stops the
4029 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4030 * Return value:
4031 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4032 * file on failure.
4033 */
4034
4035 static int s2io_close(struct net_device *dev)
4036 {
4037 struct s2io_nic *sp = netdev_priv(dev);
4038 struct config_param *config = &sp->config;
4039 u64 tmp64;
4040 int offset;
4041
4042 /* Return if the device is already closed *
4043 * Can happen when s2io_card_up failed in change_mtu *
4044 */
4045 if (!is_s2io_card_up(sp))
4046 return 0;
4047
4048 s2io_stop_all_tx_queue(sp);
4049 /* delete all populated mac entries */
4050 for (offset = 1; offset < config->max_mc_addr; offset++) {
4051 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4052 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4053 do_s2io_delete_unicast_mc(sp, tmp64);
4054 }
4055
4056 s2io_card_down(sp);
4057
4058 return 0;
4059 }
4060
4061 /**
4062 * s2io_xmit - Tx entry point of te driver
4063 * @skb : the socket buffer containing the Tx data.
4064 * @dev : device pointer.
4065 * Description :
4066 * This function is the Tx entry point of the driver. S2IO NIC supports
4067 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4068 * NOTE: when device cant queue the pkt,just the trans_start variable will
4069 * not be upadted.
4070 * Return value:
4071 * 0 on success & 1 on failure.
4072 */
4073
4074 static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4075 {
4076 struct s2io_nic *sp = netdev_priv(dev);
4077 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4078 register u64 val64;
4079 struct TxD *txdp;
4080 struct TxFIFO_element __iomem *tx_fifo;
4081 unsigned long flags = 0;
4082 u16 vlan_tag = 0;
4083 struct fifo_info *fifo = NULL;
4084 int do_spin_lock = 1;
4085 int offload_type;
4086 int enable_per_list_interrupt = 0;
4087 struct config_param *config = &sp->config;
4088 struct mac_info *mac_control = &sp->mac_control;
4089 struct stat_block *stats = mac_control->stats_info;
4090 struct swStat *swstats = &stats->sw_stat;
4091
4092 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4093
4094 if (unlikely(skb->len <= 0)) {
4095 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
4096 dev_kfree_skb_any(skb);
4097 return NETDEV_TX_OK;
4098 }
4099
4100 if (!is_s2io_card_up(sp)) {
4101 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4102 dev->name);
4103 dev_kfree_skb(skb);
4104 return NETDEV_TX_OK;
4105 }
4106
4107 queue = 0;
4108 if (vlan_tx_tag_present(skb))
4109 vlan_tag = vlan_tx_tag_get(skb);
4110 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4111 if (skb->protocol == htons(ETH_P_IP)) {
4112 struct iphdr *ip;
4113 struct tcphdr *th;
4114 ip = ip_hdr(skb);
4115
4116 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4117 th = (struct tcphdr *)(((unsigned char *)ip) +
4118 ip->ihl*4);
4119
4120 if (ip->protocol == IPPROTO_TCP) {
4121 queue_len = sp->total_tcp_fifos;
4122 queue = (ntohs(th->source) +
4123 ntohs(th->dest)) &
4124 sp->fifo_selector[queue_len - 1];
4125 if (queue >= queue_len)
4126 queue = queue_len - 1;
4127 } else if (ip->protocol == IPPROTO_UDP) {
4128 queue_len = sp->total_udp_fifos;
4129 queue = (ntohs(th->source) +
4130 ntohs(th->dest)) &
4131 sp->fifo_selector[queue_len - 1];
4132 if (queue >= queue_len)
4133 queue = queue_len - 1;
4134 queue += sp->udp_fifo_idx;
4135 if (skb->len > 1024)
4136 enable_per_list_interrupt = 1;
4137 do_spin_lock = 0;
4138 }
4139 }
4140 }
4141 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4142 /* get fifo number based on skb->priority value */
4143 queue = config->fifo_mapping
4144 [skb->priority & (MAX_TX_FIFOS - 1)];
4145 fifo = &mac_control->fifos[queue];
4146
4147 if (do_spin_lock)
4148 spin_lock_irqsave(&fifo->tx_lock, flags);
4149 else {
4150 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4151 return NETDEV_TX_LOCKED;
4152 }
4153
4154 if (sp->config.multiq) {
4155 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4156 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4157 return NETDEV_TX_BUSY;
4158 }
4159 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4160 if (netif_queue_stopped(dev)) {
4161 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4162 return NETDEV_TX_BUSY;
4163 }
4164 }
4165
4166 put_off = (u16)fifo->tx_curr_put_info.offset;
4167 get_off = (u16)fifo->tx_curr_get_info.offset;
4168 txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
4169
4170 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4171 /* Avoid "put" pointer going beyond "get" pointer */
4172 if (txdp->Host_Control ||
4173 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4174 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4175 s2io_stop_tx_queue(sp, fifo->fifo_no);
4176 dev_kfree_skb(skb);
4177 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4178 return NETDEV_TX_OK;
4179 }
4180
4181 offload_type = s2io_offload_type(skb);
4182 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4183 txdp->Control_1 |= TXD_TCP_LSO_EN;
4184 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4185 }
4186 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4187 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4188 TXD_TX_CKO_TCP_EN |
4189 TXD_TX_CKO_UDP_EN);
4190 }
4191 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4192 txdp->Control_1 |= TXD_LIST_OWN_XENA;
4193 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4194 if (enable_per_list_interrupt)
4195 if (put_off & (queue_len >> 5))
4196 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4197 if (vlan_tag) {
4198 txdp->Control_2 |= TXD_VLAN_ENABLE;
4199 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4200 }
4201
4202 frg_len = skb_headlen(skb);
4203 if (offload_type == SKB_GSO_UDP) {
4204 int ufo_size;
4205
4206 ufo_size = s2io_udp_mss(skb);
4207 ufo_size &= ~7;
4208 txdp->Control_1 |= TXD_UFO_EN;
4209 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4210 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4211 #ifdef __BIG_ENDIAN
4212 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4213 fifo->ufo_in_band_v[put_off] =
4214 (__force u64)skb_shinfo(skb)->ip6_frag_id;
4215 #else
4216 fifo->ufo_in_band_v[put_off] =
4217 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4218 #endif
4219 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4220 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4221 fifo->ufo_in_band_v,
4222 sizeof(u64),
4223 PCI_DMA_TODEVICE);
4224 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4225 goto pci_map_failed;
4226 txdp++;
4227 }
4228
4229 txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4230 frg_len, PCI_DMA_TODEVICE);
4231 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4232 goto pci_map_failed;
4233
4234 txdp->Host_Control = (unsigned long)skb;
4235 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4236 if (offload_type == SKB_GSO_UDP)
4237 txdp->Control_1 |= TXD_UFO_EN;
4238
4239 frg_cnt = skb_shinfo(skb)->nr_frags;
4240 /* For fragmented SKB. */
4241 for (i = 0; i < frg_cnt; i++) {
4242 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4243 /* A '0' length fragment will be ignored */
4244 if (!frag->size)
4245 continue;
4246 txdp++;
4247 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4248 frag->page_offset,
4249 frag->size,
4250 PCI_DMA_TODEVICE);
4251 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4252 if (offload_type == SKB_GSO_UDP)
4253 txdp->Control_1 |= TXD_UFO_EN;
4254 }
4255 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4256
4257 if (offload_type == SKB_GSO_UDP)
4258 frg_cnt++; /* as Txd0 was used for inband header */
4259
4260 tx_fifo = mac_control->tx_FIFO_start[queue];
4261 val64 = fifo->list_info[put_off].list_phy_addr;
4262 writeq(val64, &tx_fifo->TxDL_Pointer);
4263
4264 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4265 TX_FIFO_LAST_LIST);
4266 if (offload_type)
4267 val64 |= TX_FIFO_SPECIAL_FUNC;
4268
4269 writeq(val64, &tx_fifo->List_Control);
4270
4271 mmiowb();
4272
4273 put_off++;
4274 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4275 put_off = 0;
4276 fifo->tx_curr_put_info.offset = put_off;
4277
4278 /* Avoid "put" pointer going beyond "get" pointer */
4279 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4280 swstats->fifo_full_cnt++;
4281 DBG_PRINT(TX_DBG,
4282 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4283 put_off, get_off);
4284 s2io_stop_tx_queue(sp, fifo->fifo_no);
4285 }
4286 swstats->mem_allocated += skb->truesize;
4287 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4288
4289 if (sp->config.intr_type == MSI_X)
4290 tx_intr_handler(fifo);
4291
4292 return NETDEV_TX_OK;
4293
4294 pci_map_failed:
4295 swstats->pci_map_fail_cnt++;
4296 s2io_stop_tx_queue(sp, fifo->fifo_no);
4297 swstats->mem_freed += skb->truesize;
4298 dev_kfree_skb(skb);
4299 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4300 return NETDEV_TX_OK;
4301 }
4302
4303 static void
4304 s2io_alarm_handle(unsigned long data)
4305 {
4306 struct s2io_nic *sp = (struct s2io_nic *)data;
4307 struct net_device *dev = sp->dev;
4308
4309 s2io_handle_errors(dev);
4310 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4311 }
4312
4313 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4314 {
4315 struct ring_info *ring = (struct ring_info *)dev_id;
4316 struct s2io_nic *sp = ring->nic;
4317 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4318
4319 if (unlikely(!is_s2io_card_up(sp)))
4320 return IRQ_HANDLED;
4321
4322 if (sp->config.napi) {
4323 u8 __iomem *addr = NULL;
4324 u8 val8 = 0;
4325
4326 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4327 addr += (7 - ring->ring_no);
4328 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4329 writeb(val8, addr);
4330 val8 = readb(addr);
4331 napi_schedule(&ring->napi);
4332 } else {
4333 rx_intr_handler(ring, 0);
4334 s2io_chk_rx_buffers(sp, ring);
4335 }
4336
4337 return IRQ_HANDLED;
4338 }
4339
4340 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4341 {
4342 int i;
4343 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4344 struct s2io_nic *sp = fifos->nic;
4345 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4346 struct config_param *config = &sp->config;
4347 u64 reason;
4348
4349 if (unlikely(!is_s2io_card_up(sp)))
4350 return IRQ_NONE;
4351
4352 reason = readq(&bar0->general_int_status);
4353 if (unlikely(reason == S2IO_MINUS_ONE))
4354 /* Nothing much can be done. Get out */
4355 return IRQ_HANDLED;
4356
4357 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4358 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4359
4360 if (reason & GEN_INTR_TXPIC)
4361 s2io_txpic_intr_handle(sp);
4362
4363 if (reason & GEN_INTR_TXTRAFFIC)
4364 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4365
4366 for (i = 0; i < config->tx_fifo_num; i++)
4367 tx_intr_handler(&fifos[i]);
4368
4369 writeq(sp->general_int_mask, &bar0->general_int_mask);
4370 readl(&bar0->general_int_status);
4371 return IRQ_HANDLED;
4372 }
4373 /* The interrupt was not raised by us */
4374 return IRQ_NONE;
4375 }
4376
4377 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4378 {
4379 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4380 u64 val64;
4381
4382 val64 = readq(&bar0->pic_int_status);
4383 if (val64 & PIC_INT_GPIO) {
4384 val64 = readq(&bar0->gpio_int_reg);
4385 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4386 (val64 & GPIO_INT_REG_LINK_UP)) {
4387 /*
4388 * This is unstable state so clear both up/down
4389 * interrupt and adapter to re-evaluate the link state.
4390 */
4391 val64 |= GPIO_INT_REG_LINK_DOWN;
4392 val64 |= GPIO_INT_REG_LINK_UP;
4393 writeq(val64, &bar0->gpio_int_reg);
4394 val64 = readq(&bar0->gpio_int_mask);
4395 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4396 GPIO_INT_MASK_LINK_DOWN);
4397 writeq(val64, &bar0->gpio_int_mask);
4398 } else if (val64 & GPIO_INT_REG_LINK_UP) {
4399 val64 = readq(&bar0->adapter_status);
4400 /* Enable Adapter */
4401 val64 = readq(&bar0->adapter_control);
4402 val64 |= ADAPTER_CNTL_EN;
4403 writeq(val64, &bar0->adapter_control);
4404 val64 |= ADAPTER_LED_ON;
4405 writeq(val64, &bar0->adapter_control);
4406 if (!sp->device_enabled_once)
4407 sp->device_enabled_once = 1;
4408
4409 s2io_link(sp, LINK_UP);
4410 /*
4411 * unmask link down interrupt and mask link-up
4412 * intr
4413 */
4414 val64 = readq(&bar0->gpio_int_mask);
4415 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4416 val64 |= GPIO_INT_MASK_LINK_UP;
4417 writeq(val64, &bar0->gpio_int_mask);
4418
4419 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4420 val64 = readq(&bar0->adapter_status);
4421 s2io_link(sp, LINK_DOWN);
4422 /* Link is down so unmaks link up interrupt */
4423 val64 = readq(&bar0->gpio_int_mask);
4424 val64 &= ~GPIO_INT_MASK_LINK_UP;
4425 val64 |= GPIO_INT_MASK_LINK_DOWN;
4426 writeq(val64, &bar0->gpio_int_mask);
4427
4428 /* turn off LED */
4429 val64 = readq(&bar0->adapter_control);
4430 val64 = val64 & (~ADAPTER_LED_ON);
4431 writeq(val64, &bar0->adapter_control);
4432 }
4433 }
4434 val64 = readq(&bar0->gpio_int_mask);
4435 }
4436
4437 /**
4438 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4439 * @value: alarm bits
4440 * @addr: address value
4441 * @cnt: counter variable
4442 * Description: Check for alarm and increment the counter
4443 * Return Value:
4444 * 1 - if alarm bit set
4445 * 0 - if alarm bit is not set
4446 */
4447 static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4448 unsigned long long *cnt)
4449 {
4450 u64 val64;
4451 val64 = readq(addr);
4452 if (val64 & value) {
4453 writeq(val64, addr);
4454 (*cnt)++;
4455 return 1;
4456 }
4457 return 0;
4458
4459 }
4460
4461 /**
4462 * s2io_handle_errors - Xframe error indication handler
4463 * @nic: device private variable
4464 * Description: Handle alarms such as loss of link, single or
4465 * double ECC errors, critical and serious errors.
4466 * Return Value:
4467 * NONE
4468 */
4469 static void s2io_handle_errors(void *dev_id)
4470 {
4471 struct net_device *dev = (struct net_device *)dev_id;
4472 struct s2io_nic *sp = netdev_priv(dev);
4473 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4474 u64 temp64 = 0, val64 = 0;
4475 int i = 0;
4476
4477 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4478 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4479
4480 if (!is_s2io_card_up(sp))
4481 return;
4482
4483 if (pci_channel_offline(sp->pdev))
4484 return;
4485
4486 memset(&sw_stat->ring_full_cnt, 0,
4487 sizeof(sw_stat->ring_full_cnt));
4488
4489 /* Handling the XPAK counters update */
4490 if (stats->xpak_timer_count < 72000) {
4491 /* waiting for an hour */
4492 stats->xpak_timer_count++;
4493 } else {
4494 s2io_updt_xpak_counter(dev);
4495 /* reset the count to zero */
4496 stats->xpak_timer_count = 0;
4497 }
4498
4499 /* Handling link status change error Intr */
4500 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4501 val64 = readq(&bar0->mac_rmac_err_reg);
4502 writeq(val64, &bar0->mac_rmac_err_reg);
4503 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4504 schedule_work(&sp->set_link_task);
4505 }
4506
4507 /* In case of a serious error, the device will be Reset. */
4508 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4509 &sw_stat->serious_err_cnt))
4510 goto reset;
4511
4512 /* Check for data parity error */
4513 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4514 &sw_stat->parity_err_cnt))
4515 goto reset;
4516
4517 /* Check for ring full counter */
4518 if (sp->device_type == XFRAME_II_DEVICE) {
4519 val64 = readq(&bar0->ring_bump_counter1);
4520 for (i = 0; i < 4; i++) {
4521 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4522 temp64 >>= 64 - ((i+1)*16);
4523 sw_stat->ring_full_cnt[i] += temp64;
4524 }
4525
4526 val64 = readq(&bar0->ring_bump_counter2);
4527 for (i = 0; i < 4; i++) {
4528 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4529 temp64 >>= 64 - ((i+1)*16);
4530 sw_stat->ring_full_cnt[i+4] += temp64;
4531 }
4532 }
4533
4534 val64 = readq(&bar0->txdma_int_status);
4535 /*check for pfc_err*/
4536 if (val64 & TXDMA_PFC_INT) {
4537 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4538 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4539 PFC_PCIX_ERR,
4540 &bar0->pfc_err_reg,
4541 &sw_stat->pfc_err_cnt))
4542 goto reset;
4543 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4544 &bar0->pfc_err_reg,
4545 &sw_stat->pfc_err_cnt);
4546 }
4547
4548 /*check for tda_err*/
4549 if (val64 & TXDMA_TDA_INT) {
4550 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4551 TDA_SM0_ERR_ALARM |
4552 TDA_SM1_ERR_ALARM,
4553 &bar0->tda_err_reg,
4554 &sw_stat->tda_err_cnt))
4555 goto reset;
4556 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4557 &bar0->tda_err_reg,
4558 &sw_stat->tda_err_cnt);
4559 }
4560 /*check for pcc_err*/
4561 if (val64 & TXDMA_PCC_INT) {
4562 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4563 PCC_N_SERR | PCC_6_COF_OV_ERR |
4564 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4565 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4566 PCC_TXB_ECC_DB_ERR,
4567 &bar0->pcc_err_reg,
4568 &sw_stat->pcc_err_cnt))
4569 goto reset;
4570 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4571 &bar0->pcc_err_reg,
4572 &sw_stat->pcc_err_cnt);
4573 }
4574
4575 /*check for tti_err*/
4576 if (val64 & TXDMA_TTI_INT) {
4577 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4578 &bar0->tti_err_reg,
4579 &sw_stat->tti_err_cnt))
4580 goto reset;
4581 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4582 &bar0->tti_err_reg,
4583 &sw_stat->tti_err_cnt);
4584 }
4585
4586 /*check for lso_err*/
4587 if (val64 & TXDMA_LSO_INT) {
4588 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4589 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4590 &bar0->lso_err_reg,
4591 &sw_stat->lso_err_cnt))
4592 goto reset;
4593 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4594 &bar0->lso_err_reg,
4595 &sw_stat->lso_err_cnt);
4596 }
4597
4598 /*check for tpa_err*/
4599 if (val64 & TXDMA_TPA_INT) {
4600 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4601 &bar0->tpa_err_reg,
4602 &sw_stat->tpa_err_cnt))
4603 goto reset;
4604 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4605 &bar0->tpa_err_reg,
4606 &sw_stat->tpa_err_cnt);
4607 }
4608
4609 /*check for sm_err*/
4610 if (val64 & TXDMA_SM_INT) {
4611 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4612 &bar0->sm_err_reg,
4613 &sw_stat->sm_err_cnt))
4614 goto reset;
4615 }
4616
4617 val64 = readq(&bar0->mac_int_status);
4618 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4619 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4620 &bar0->mac_tmac_err_reg,
4621 &sw_stat->mac_tmac_err_cnt))
4622 goto reset;
4623 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4624 TMAC_DESC_ECC_SG_ERR |
4625 TMAC_DESC_ECC_DB_ERR,
4626 &bar0->mac_tmac_err_reg,
4627 &sw_stat->mac_tmac_err_cnt);
4628 }
4629
4630 val64 = readq(&bar0->xgxs_int_status);
4631 if (val64 & XGXS_INT_STATUS_TXGXS) {
4632 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4633 &bar0->xgxs_txgxs_err_reg,
4634 &sw_stat->xgxs_txgxs_err_cnt))
4635 goto reset;
4636 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4637 &bar0->xgxs_txgxs_err_reg,
4638 &sw_stat->xgxs_txgxs_err_cnt);
4639 }
4640
4641 val64 = readq(&bar0->rxdma_int_status);
4642 if (val64 & RXDMA_INT_RC_INT_M) {
4643 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4644 RC_FTC_ECC_DB_ERR |
4645 RC_PRCn_SM_ERR_ALARM |
4646 RC_FTC_SM_ERR_ALARM,
4647 &bar0->rc_err_reg,
4648 &sw_stat->rc_err_cnt))
4649 goto reset;
4650 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4651 RC_FTC_ECC_SG_ERR |
4652 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4653 &sw_stat->rc_err_cnt);
4654 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4655 PRC_PCI_AB_WR_Rn |
4656 PRC_PCI_AB_F_WR_Rn,
4657 &bar0->prc_pcix_err_reg,
4658 &sw_stat->prc_pcix_err_cnt))
4659 goto reset;
4660 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4661 PRC_PCI_DP_WR_Rn |
4662 PRC_PCI_DP_F_WR_Rn,
4663 &bar0->prc_pcix_err_reg,
4664 &sw_stat->prc_pcix_err_cnt);
4665 }
4666
4667 if (val64 & RXDMA_INT_RPA_INT_M) {
4668 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4669 &bar0->rpa_err_reg,
4670 &sw_stat->rpa_err_cnt))
4671 goto reset;
4672 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4673 &bar0->rpa_err_reg,
4674 &sw_stat->rpa_err_cnt);
4675 }
4676
4677 if (val64 & RXDMA_INT_RDA_INT_M) {
4678 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4679 RDA_FRM_ECC_DB_N_AERR |
4680 RDA_SM1_ERR_ALARM |
4681 RDA_SM0_ERR_ALARM |
4682 RDA_RXD_ECC_DB_SERR,
4683 &bar0->rda_err_reg,
4684 &sw_stat->rda_err_cnt))
4685 goto reset;
4686 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4687 RDA_FRM_ECC_SG_ERR |
4688 RDA_MISC_ERR |
4689 RDA_PCIX_ERR,
4690 &bar0->rda_err_reg,
4691 &sw_stat->rda_err_cnt);
4692 }
4693
4694 if (val64 & RXDMA_INT_RTI_INT_M) {
4695 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4696 &bar0->rti_err_reg,
4697 &sw_stat->rti_err_cnt))
4698 goto reset;
4699 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4700 &bar0->rti_err_reg,
4701 &sw_stat->rti_err_cnt);
4702 }
4703
4704 val64 = readq(&bar0->mac_int_status);
4705 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4706 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4707 &bar0->mac_rmac_err_reg,
4708 &sw_stat->mac_rmac_err_cnt))
4709 goto reset;
4710 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4711 RMAC_SINGLE_ECC_ERR |
4712 RMAC_DOUBLE_ECC_ERR,
4713 &bar0->mac_rmac_err_reg,
4714 &sw_stat->mac_rmac_err_cnt);
4715 }
4716
4717 val64 = readq(&bar0->xgxs_int_status);
4718 if (val64 & XGXS_INT_STATUS_RXGXS) {
4719 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4720 &bar0->xgxs_rxgxs_err_reg,
4721 &sw_stat->xgxs_rxgxs_err_cnt))
4722 goto reset;
4723 }
4724
4725 val64 = readq(&bar0->mc_int_status);
4726 if (val64 & MC_INT_STATUS_MC_INT) {
4727 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4728 &bar0->mc_err_reg,
4729 &sw_stat->mc_err_cnt))
4730 goto reset;
4731
4732 /* Handling Ecc errors */
4733 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4734 writeq(val64, &bar0->mc_err_reg);
4735 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4736 sw_stat->double_ecc_errs++;
4737 if (sp->device_type != XFRAME_II_DEVICE) {
4738 /*
4739 * Reset XframeI only if critical error
4740 */
4741 if (val64 &
4742 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4743 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4744 goto reset;
4745 }
4746 } else
4747 sw_stat->single_ecc_errs++;
4748 }
4749 }
4750 return;
4751
4752 reset:
4753 s2io_stop_all_tx_queue(sp);
4754 schedule_work(&sp->rst_timer_task);
4755 sw_stat->soft_reset_cnt++;
4756 }
4757
4758 /**
4759 * s2io_isr - ISR handler of the device .
4760 * @irq: the irq of the device.
4761 * @dev_id: a void pointer to the dev structure of the NIC.
4762 * Description: This function is the ISR handler of the device. It
4763 * identifies the reason for the interrupt and calls the relevant
4764 * service routines. As a contongency measure, this ISR allocates the
4765 * recv buffers, if their numbers are below the panic value which is
4766 * presently set to 25% of the original number of rcv buffers allocated.
4767 * Return value:
4768 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4769 * IRQ_NONE: will be returned if interrupt is not from our device
4770 */
4771 static irqreturn_t s2io_isr(int irq, void *dev_id)
4772 {
4773 struct net_device *dev = (struct net_device *)dev_id;
4774 struct s2io_nic *sp = netdev_priv(dev);
4775 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4776 int i;
4777 u64 reason = 0;
4778 struct mac_info *mac_control;
4779 struct config_param *config;
4780
4781 /* Pretend we handled any irq's from a disconnected card */
4782 if (pci_channel_offline(sp->pdev))
4783 return IRQ_NONE;
4784
4785 if (!is_s2io_card_up(sp))
4786 return IRQ_NONE;
4787
4788 config = &sp->config;
4789 mac_control = &sp->mac_control;
4790
4791 /*
4792 * Identify the cause for interrupt and call the appropriate
4793 * interrupt handler. Causes for the interrupt could be;
4794 * 1. Rx of packet.
4795 * 2. Tx complete.
4796 * 3. Link down.
4797 */
4798 reason = readq(&bar0->general_int_status);
4799
4800 if (unlikely(reason == S2IO_MINUS_ONE))
4801 return IRQ_HANDLED; /* Nothing much can be done. Get out */
4802
4803 if (reason &
4804 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4805 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4806
4807 if (config->napi) {
4808 if (reason & GEN_INTR_RXTRAFFIC) {
4809 napi_schedule(&sp->napi);
4810 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4811 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4812 readl(&bar0->rx_traffic_int);
4813 }
4814 } else {
4815 /*
4816 * rx_traffic_int reg is an R1 register, writing all 1's
4817 * will ensure that the actual interrupt causing bit
4818 * get's cleared and hence a read can be avoided.
4819 */
4820 if (reason & GEN_INTR_RXTRAFFIC)
4821 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4822
4823 for (i = 0; i < config->rx_ring_num; i++) {
4824 struct ring_info *ring = &mac_control->rings[i];
4825
4826 rx_intr_handler(ring, 0);
4827 }
4828 }
4829
4830 /*
4831 * tx_traffic_int reg is an R1 register, writing all 1's
4832 * will ensure that the actual interrupt causing bit get's
4833 * cleared and hence a read can be avoided.
4834 */
4835 if (reason & GEN_INTR_TXTRAFFIC)
4836 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4837
4838 for (i = 0; i < config->tx_fifo_num; i++)
4839 tx_intr_handler(&mac_control->fifos[i]);
4840
4841 if (reason & GEN_INTR_TXPIC)
4842 s2io_txpic_intr_handle(sp);
4843
4844 /*
4845 * Reallocate the buffers from the interrupt handler itself.
4846 */
4847 if (!config->napi) {
4848 for (i = 0; i < config->rx_ring_num; i++) {
4849 struct ring_info *ring = &mac_control->rings[i];
4850
4851 s2io_chk_rx_buffers(sp, ring);
4852 }
4853 }
4854 writeq(sp->general_int_mask, &bar0->general_int_mask);
4855 readl(&bar0->general_int_status);
4856
4857 return IRQ_HANDLED;
4858
4859 } else if (!reason) {
4860 /* The interrupt was not raised by us */
4861 return IRQ_NONE;
4862 }
4863
4864 return IRQ_HANDLED;
4865 }
4866
4867 /**
4868 * s2io_updt_stats -
4869 */
4870 static void s2io_updt_stats(struct s2io_nic *sp)
4871 {
4872 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4873 u64 val64;
4874 int cnt = 0;
4875
4876 if (is_s2io_card_up(sp)) {
4877 /* Apprx 30us on a 133 MHz bus */
4878 val64 = SET_UPDT_CLICKS(10) |
4879 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4880 writeq(val64, &bar0->stat_cfg);
4881 do {
4882 udelay(100);
4883 val64 = readq(&bar0->stat_cfg);
4884 if (!(val64 & s2BIT(0)))
4885 break;
4886 cnt++;
4887 if (cnt == 5)
4888 break; /* Updt failed */
4889 } while (1);
4890 }
4891 }
4892
4893 /**
4894 * s2io_get_stats - Updates the device statistics structure.
4895 * @dev : pointer to the device structure.
4896 * Description:
4897 * This function updates the device statistics structure in the s2io_nic
4898 * structure and returns a pointer to the same.
4899 * Return value:
4900 * pointer to the updated net_device_stats structure.
4901 */
4902 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4903 {
4904 struct s2io_nic *sp = netdev_priv(dev);
4905 struct mac_info *mac_control = &sp->mac_control;
4906 struct stat_block *stats = mac_control->stats_info;
4907 u64 delta;
4908
4909 /* Configure Stats for immediate updt */
4910 s2io_updt_stats(sp);
4911
4912 /* A device reset will cause the on-adapter statistics to be zero'ed.
4913 * This can be done while running by changing the MTU. To prevent the
4914 * system from having the stats zero'ed, the driver keeps a copy of the
4915 * last update to the system (which is also zero'ed on reset). This
4916 * enables the driver to accurately know the delta between the last
4917 * update and the current update.
4918 */
4919 delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
4920 le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets;
4921 sp->stats.rx_packets += delta;
4922 dev->stats.rx_packets += delta;
4923
4924 delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 |
4925 le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets;
4926 sp->stats.tx_packets += delta;
4927 dev->stats.tx_packets += delta;
4928
4929 delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
4930 le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes;
4931 sp->stats.rx_bytes += delta;
4932 dev->stats.rx_bytes += delta;
4933
4934 delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
4935 le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes;
4936 sp->stats.tx_bytes += delta;
4937 dev->stats.tx_bytes += delta;
4938
4939 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors;
4940 sp->stats.rx_errors += delta;
4941 dev->stats.rx_errors += delta;
4942
4943 delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
4944 le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors;
4945 sp->stats.tx_errors += delta;
4946 dev->stats.tx_errors += delta;
4947
4948 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped;
4949 sp->stats.rx_dropped += delta;
4950 dev->stats.rx_dropped += delta;
4951
4952 delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped;
4953 sp->stats.tx_dropped += delta;
4954 dev->stats.tx_dropped += delta;
4955
4956 /* The adapter MAC interprets pause frames as multicast packets, but
4957 * does not pass them up. This erroneously increases the multicast
4958 * packet count and needs to be deducted when the multicast frame count
4959 * is queried.
4960 */
4961 delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
4962 le32_to_cpu(stats->rmac_vld_mcst_frms);
4963 delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms);
4964 delta -= sp->stats.multicast;
4965 sp->stats.multicast += delta;
4966 dev->stats.multicast += delta;
4967
4968 delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
4969 le32_to_cpu(stats->rmac_usized_frms)) +
4970 le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors;
4971 sp->stats.rx_length_errors += delta;
4972 dev->stats.rx_length_errors += delta;
4973
4974 delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors;
4975 sp->stats.rx_crc_errors += delta;
4976 dev->stats.rx_crc_errors += delta;
4977
4978 return &dev->stats;
4979 }
4980
4981 /**
4982 * s2io_set_multicast - entry point for multicast address enable/disable.
4983 * @dev : pointer to the device structure
4984 * Description:
4985 * This function is a driver entry point which gets called by the kernel
4986 * whenever multicast addresses must be enabled/disabled. This also gets
4987 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4988 * determine, if multicast address must be enabled or if promiscuous mode
4989 * is to be disabled etc.
4990 * Return value:
4991 * void.
4992 */
4993
4994 static void s2io_set_multicast(struct net_device *dev)
4995 {
4996 int i, j, prev_cnt;
4997 struct netdev_hw_addr *ha;
4998 struct s2io_nic *sp = netdev_priv(dev);
4999 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5000 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
5001 0xfeffffffffffULL;
5002 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
5003 void __iomem *add;
5004 struct config_param *config = &sp->config;
5005
5006 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
5007 /* Enable all Multicast addresses */
5008 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
5009 &bar0->rmac_addr_data0_mem);
5010 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
5011 &bar0->rmac_addr_data1_mem);
5012 val64 = RMAC_ADDR_CMD_MEM_WE |
5013 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5014 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
5015 writeq(val64, &bar0->rmac_addr_cmd_mem);
5016 /* Wait till command completes */
5017 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5018 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5019 S2IO_BIT_RESET);
5020
5021 sp->m_cast_flg = 1;
5022 sp->all_multi_pos = config->max_mc_addr - 1;
5023 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
5024 /* Disable all Multicast addresses */
5025 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5026 &bar0->rmac_addr_data0_mem);
5027 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
5028 &bar0->rmac_addr_data1_mem);
5029 val64 = RMAC_ADDR_CMD_MEM_WE |
5030 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5031 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
5032 writeq(val64, &bar0->rmac_addr_cmd_mem);
5033 /* Wait till command completes */
5034 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5035 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5036 S2IO_BIT_RESET);
5037
5038 sp->m_cast_flg = 0;
5039 sp->all_multi_pos = 0;
5040 }
5041
5042 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5043 /* Put the NIC into promiscuous mode */
5044 add = &bar0->mac_cfg;
5045 val64 = readq(&bar0->mac_cfg);
5046 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5047
5048 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5049 writel((u32)val64, add);
5050 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5051 writel((u32) (val64 >> 32), (add + 4));
5052
5053 if (vlan_tag_strip != 1) {
5054 val64 = readq(&bar0->rx_pa_cfg);
5055 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5056 writeq(val64, &bar0->rx_pa_cfg);
5057 sp->vlan_strip_flag = 0;
5058 }
5059
5060 val64 = readq(&bar0->mac_cfg);
5061 sp->promisc_flg = 1;
5062 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5063 dev->name);
5064 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5065 /* Remove the NIC from promiscuous mode */
5066 add = &bar0->mac_cfg;
5067 val64 = readq(&bar0->mac_cfg);
5068 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5069
5070 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5071 writel((u32)val64, add);
5072 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5073 writel((u32) (val64 >> 32), (add + 4));
5074
5075 if (vlan_tag_strip != 0) {
5076 val64 = readq(&bar0->rx_pa_cfg);
5077 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5078 writeq(val64, &bar0->rx_pa_cfg);
5079 sp->vlan_strip_flag = 1;
5080 }
5081
5082 val64 = readq(&bar0->mac_cfg);
5083 sp->promisc_flg = 0;
5084 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
5085 }
5086
5087 /* Update individual M_CAST address list */
5088 if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
5089 if (netdev_mc_count(dev) >
5090 (config->max_mc_addr - config->max_mac_addr)) {
5091 DBG_PRINT(ERR_DBG,
5092 "%s: No more Rx filters can be added - "
5093 "please enable ALL_MULTI instead\n",
5094 dev->name);
5095 return;
5096 }
5097
5098 prev_cnt = sp->mc_addr_count;
5099 sp->mc_addr_count = netdev_mc_count(dev);
5100
5101 /* Clear out the previous list of Mc in the H/W. */
5102 for (i = 0; i < prev_cnt; i++) {
5103 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5104 &bar0->rmac_addr_data0_mem);
5105 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5106 &bar0->rmac_addr_data1_mem);
5107 val64 = RMAC_ADDR_CMD_MEM_WE |
5108 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5109 RMAC_ADDR_CMD_MEM_OFFSET
5110 (config->mc_start_offset + i);
5111 writeq(val64, &bar0->rmac_addr_cmd_mem);
5112
5113 /* Wait for command completes */
5114 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5115 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5116 S2IO_BIT_RESET)) {
5117 DBG_PRINT(ERR_DBG,
5118 "%s: Adding Multicasts failed\n",
5119 dev->name);
5120 return;
5121 }
5122 }
5123
5124 /* Create the new Rx filter list and update the same in H/W. */
5125 i = 0;
5126 netdev_for_each_mc_addr(ha, dev) {
5127 mac_addr = 0;
5128 for (j = 0; j < ETH_ALEN; j++) {
5129 mac_addr |= ha->addr[j];
5130 mac_addr <<= 8;
5131 }
5132 mac_addr >>= 8;
5133 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5134 &bar0->rmac_addr_data0_mem);
5135 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5136 &bar0->rmac_addr_data1_mem);
5137 val64 = RMAC_ADDR_CMD_MEM_WE |
5138 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5139 RMAC_ADDR_CMD_MEM_OFFSET
5140 (i + config->mc_start_offset);
5141 writeq(val64, &bar0->rmac_addr_cmd_mem);
5142
5143 /* Wait for command completes */
5144 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5145 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5146 S2IO_BIT_RESET)) {
5147 DBG_PRINT(ERR_DBG,
5148 "%s: Adding Multicasts failed\n",
5149 dev->name);
5150 return;
5151 }
5152 i++;
5153 }
5154 }
5155 }
5156
5157 /* read from CAM unicast & multicast addresses and store it in
5158 * def_mac_addr structure
5159 */
5160 static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5161 {
5162 int offset;
5163 u64 mac_addr = 0x0;
5164 struct config_param *config = &sp->config;
5165
5166 /* store unicast & multicast mac addresses */
5167 for (offset = 0; offset < config->max_mc_addr; offset++) {
5168 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5169 /* if read fails disable the entry */
5170 if (mac_addr == FAILURE)
5171 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5172 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5173 }
5174 }
5175
5176 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5177 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5178 {
5179 int offset;
5180 struct config_param *config = &sp->config;
5181 /* restore unicast mac address */
5182 for (offset = 0; offset < config->max_mac_addr; offset++)
5183 do_s2io_prog_unicast(sp->dev,
5184 sp->def_mac_addr[offset].mac_addr);
5185
5186 /* restore multicast mac address */
5187 for (offset = config->mc_start_offset;
5188 offset < config->max_mc_addr; offset++)
5189 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5190 }
5191
5192 /* add a multicast MAC address to CAM */
5193 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5194 {
5195 int i;
5196 u64 mac_addr = 0;
5197 struct config_param *config = &sp->config;
5198
5199 for (i = 0; i < ETH_ALEN; i++) {
5200 mac_addr <<= 8;
5201 mac_addr |= addr[i];
5202 }
5203 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5204 return SUCCESS;
5205
5206 /* check if the multicast mac already preset in CAM */
5207 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5208 u64 tmp64;
5209 tmp64 = do_s2io_read_unicast_mc(sp, i);
5210 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5211 break;
5212
5213 if (tmp64 == mac_addr)
5214 return SUCCESS;
5215 }
5216 if (i == config->max_mc_addr) {
5217 DBG_PRINT(ERR_DBG,
5218 "CAM full no space left for multicast MAC\n");
5219 return FAILURE;
5220 }
5221 /* Update the internal structure with this new mac address */
5222 do_s2io_copy_mac_addr(sp, i, mac_addr);
5223
5224 return do_s2io_add_mac(sp, mac_addr, i);
5225 }
5226
5227 /* add MAC address to CAM */
5228 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5229 {
5230 u64 val64;
5231 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5232
5233 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5234 &bar0->rmac_addr_data0_mem);
5235
5236 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5237 RMAC_ADDR_CMD_MEM_OFFSET(off);
5238 writeq(val64, &bar0->rmac_addr_cmd_mem);
5239
5240 /* Wait till command completes */
5241 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5242 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5243 S2IO_BIT_RESET)) {
5244 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5245 return FAILURE;
5246 }
5247 return SUCCESS;
5248 }
5249 /* deletes a specified unicast/multicast mac entry from CAM */
5250 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5251 {
5252 int offset;
5253 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5254 struct config_param *config = &sp->config;
5255
5256 for (offset = 1;
5257 offset < config->max_mc_addr; offset++) {
5258 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5259 if (tmp64 == addr) {
5260 /* disable the entry by writing 0xffffffffffffULL */
5261 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5262 return FAILURE;
5263 /* store the new mac list from CAM */
5264 do_s2io_store_unicast_mc(sp);
5265 return SUCCESS;
5266 }
5267 }
5268 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5269 (unsigned long long)addr);
5270 return FAILURE;
5271 }
5272
5273 /* read mac entries from CAM */
5274 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5275 {
5276 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5277 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5278
5279 /* read mac addr */
5280 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5281 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5282 writeq(val64, &bar0->rmac_addr_cmd_mem);
5283
5284 /* Wait till command completes */
5285 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5286 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5287 S2IO_BIT_RESET)) {
5288 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5289 return FAILURE;
5290 }
5291 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5292
5293 return tmp64 >> 16;
5294 }
5295
5296 /**
5297 * s2io_set_mac_addr driver entry point
5298 */
5299
5300 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5301 {
5302 struct sockaddr *addr = p;
5303
5304 if (!is_valid_ether_addr(addr->sa_data))
5305 return -EINVAL;
5306
5307 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5308
5309 /* store the MAC address in CAM */
5310 return do_s2io_prog_unicast(dev, dev->dev_addr);
5311 }
5312 /**
5313 * do_s2io_prog_unicast - Programs the Xframe mac address
5314 * @dev : pointer to the device structure.
5315 * @addr: a uchar pointer to the new mac address which is to be set.
5316 * Description : This procedure will program the Xframe to receive
5317 * frames with new Mac Address
5318 * Return value: SUCCESS on success and an appropriate (-)ve integer
5319 * as defined in errno.h file on failure.
5320 */
5321
5322 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5323 {
5324 struct s2io_nic *sp = netdev_priv(dev);
5325 register u64 mac_addr = 0, perm_addr = 0;
5326 int i;
5327 u64 tmp64;
5328 struct config_param *config = &sp->config;
5329
5330 /*
5331 * Set the new MAC address as the new unicast filter and reflect this
5332 * change on the device address registered with the OS. It will be
5333 * at offset 0.
5334 */
5335 for (i = 0; i < ETH_ALEN; i++) {
5336 mac_addr <<= 8;
5337 mac_addr |= addr[i];
5338 perm_addr <<= 8;
5339 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5340 }
5341
5342 /* check if the dev_addr is different than perm_addr */
5343 if (mac_addr == perm_addr)
5344 return SUCCESS;
5345
5346 /* check if the mac already preset in CAM */
5347 for (i = 1; i < config->max_mac_addr; i++) {
5348 tmp64 = do_s2io_read_unicast_mc(sp, i);
5349 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5350 break;
5351
5352 if (tmp64 == mac_addr) {
5353 DBG_PRINT(INFO_DBG,
5354 "MAC addr:0x%llx already present in CAM\n",
5355 (unsigned long long)mac_addr);
5356 return SUCCESS;
5357 }
5358 }
5359 if (i == config->max_mac_addr) {
5360 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5361 return FAILURE;
5362 }
5363 /* Update the internal structure with this new mac address */
5364 do_s2io_copy_mac_addr(sp, i, mac_addr);
5365
5366 return do_s2io_add_mac(sp, mac_addr, i);
5367 }
5368
5369 /**
5370 * s2io_ethtool_sset - Sets different link parameters.
5371 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5372 * @info: pointer to the structure with parameters given by ethtool to set
5373 * link information.
5374 * Description:
5375 * The function sets different link parameters provided by the user onto
5376 * the NIC.
5377 * Return value:
5378 * 0 on success.
5379 */
5380
5381 static int s2io_ethtool_sset(struct net_device *dev,
5382 struct ethtool_cmd *info)
5383 {
5384 struct s2io_nic *sp = netdev_priv(dev);
5385 if ((info->autoneg == AUTONEG_ENABLE) ||
5386 (info->speed != SPEED_10000) ||
5387 (info->duplex != DUPLEX_FULL))
5388 return -EINVAL;
5389 else {
5390 s2io_close(sp->dev);
5391 s2io_open(sp->dev);
5392 }
5393
5394 return 0;
5395 }
5396
5397 /**
5398 * s2io_ethtol_gset - Return link specific information.
5399 * @sp : private member of the device structure, pointer to the
5400 * s2io_nic structure.
5401 * @info : pointer to the structure with parameters given by ethtool
5402 * to return link information.
5403 * Description:
5404 * Returns link specific information like speed, duplex etc.. to ethtool.
5405 * Return value :
5406 * return 0 on success.
5407 */
5408
5409 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5410 {
5411 struct s2io_nic *sp = netdev_priv(dev);
5412 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5413 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5414 info->port = PORT_FIBRE;
5415
5416 /* info->transceiver */
5417 info->transceiver = XCVR_EXTERNAL;
5418
5419 if (netif_carrier_ok(sp->dev)) {
5420 info->speed = 10000;
5421 info->duplex = DUPLEX_FULL;
5422 } else {
5423 info->speed = -1;
5424 info->duplex = -1;
5425 }
5426
5427 info->autoneg = AUTONEG_DISABLE;
5428 return 0;
5429 }
5430
5431 /**
5432 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5433 * @sp : private member of the device structure, which is a pointer to the
5434 * s2io_nic structure.
5435 * @info : pointer to the structure with parameters given by ethtool to
5436 * return driver information.
5437 * Description:
5438 * Returns driver specefic information like name, version etc.. to ethtool.
5439 * Return value:
5440 * void
5441 */
5442
5443 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5444 struct ethtool_drvinfo *info)
5445 {
5446 struct s2io_nic *sp = netdev_priv(dev);
5447
5448 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5449 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5450 strncpy(info->fw_version, "", sizeof(info->fw_version));
5451 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5452 info->regdump_len = XENA_REG_SPACE;
5453 info->eedump_len = XENA_EEPROM_SPACE;
5454 }
5455
5456 /**
5457 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5458 * @sp: private member of the device structure, which is a pointer to the
5459 * s2io_nic structure.
5460 * @regs : pointer to the structure with parameters given by ethtool for
5461 * dumping the registers.
5462 * @reg_space: The input argumnet into which all the registers are dumped.
5463 * Description:
5464 * Dumps the entire register space of xFrame NIC into the user given
5465 * buffer area.
5466 * Return value :
5467 * void .
5468 */
5469
5470 static void s2io_ethtool_gregs(struct net_device *dev,
5471 struct ethtool_regs *regs, void *space)
5472 {
5473 int i;
5474 u64 reg;
5475 u8 *reg_space = (u8 *)space;
5476 struct s2io_nic *sp = netdev_priv(dev);
5477
5478 regs->len = XENA_REG_SPACE;
5479 regs->version = sp->pdev->subsystem_device;
5480
5481 for (i = 0; i < regs->len; i += 8) {
5482 reg = readq(sp->bar0 + i);
5483 memcpy((reg_space + i), &reg, 8);
5484 }
5485 }
5486
5487 /**
5488 * s2io_phy_id - timer function that alternates adapter LED.
5489 * @data : address of the private member of the device structure, which
5490 * is a pointer to the s2io_nic structure, provided as an u32.
5491 * Description: This is actually the timer function that alternates the
5492 * adapter LED bit of the adapter control bit to set/reset every time on
5493 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5494 * once every second.
5495 */
5496 static void s2io_phy_id(unsigned long data)
5497 {
5498 struct s2io_nic *sp = (struct s2io_nic *)data;
5499 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5500 u64 val64 = 0;
5501 u16 subid;
5502
5503 subid = sp->pdev->subsystem_device;
5504 if ((sp->device_type == XFRAME_II_DEVICE) ||
5505 ((subid & 0xFF) >= 0x07)) {
5506 val64 = readq(&bar0->gpio_control);
5507 val64 ^= GPIO_CTRL_GPIO_0;
5508 writeq(val64, &bar0->gpio_control);
5509 } else {
5510 val64 = readq(&bar0->adapter_control);
5511 val64 ^= ADAPTER_LED_ON;
5512 writeq(val64, &bar0->adapter_control);
5513 }
5514
5515 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5516 }
5517
5518 /**
5519 * s2io_ethtool_idnic - To physically identify the nic on the system.
5520 * @sp : private member of the device structure, which is a pointer to the
5521 * s2io_nic structure.
5522 * @id : pointer to the structure with identification parameters given by
5523 * ethtool.
5524 * Description: Used to physically identify the NIC on the system.
5525 * The Link LED will blink for a time specified by the user for
5526 * identification.
5527 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5528 * identification is possible only if it's link is up.
5529 * Return value:
5530 * int , returns 0 on success
5531 */
5532
5533 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5534 {
5535 u64 val64 = 0, last_gpio_ctrl_val;
5536 struct s2io_nic *sp = netdev_priv(dev);
5537 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5538 u16 subid;
5539
5540 subid = sp->pdev->subsystem_device;
5541 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5542 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
5543 val64 = readq(&bar0->adapter_control);
5544 if (!(val64 & ADAPTER_CNTL_EN)) {
5545 pr_err("Adapter Link down, cannot blink LED\n");
5546 return -EFAULT;
5547 }
5548 }
5549 if (sp->id_timer.function == NULL) {
5550 init_timer(&sp->id_timer);
5551 sp->id_timer.function = s2io_phy_id;
5552 sp->id_timer.data = (unsigned long)sp;
5553 }
5554 mod_timer(&sp->id_timer, jiffies);
5555 if (data)
5556 msleep_interruptible(data * HZ);
5557 else
5558 msleep_interruptible(MAX_FLICKER_TIME);
5559 del_timer_sync(&sp->id_timer);
5560
5561 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
5562 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5563 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5564 }
5565
5566 return 0;
5567 }
5568
5569 static void s2io_ethtool_gringparam(struct net_device *dev,
5570 struct ethtool_ringparam *ering)
5571 {
5572 struct s2io_nic *sp = netdev_priv(dev);
5573 int i, tx_desc_count = 0, rx_desc_count = 0;
5574
5575 if (sp->rxd_mode == RXD_MODE_1) {
5576 ering->rx_max_pending = MAX_RX_DESC_1;
5577 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5578 } else {
5579 ering->rx_max_pending = MAX_RX_DESC_2;
5580 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5581 }
5582
5583 ering->rx_mini_max_pending = 0;
5584 ering->tx_max_pending = MAX_TX_DESC;
5585
5586 for (i = 0; i < sp->config.rx_ring_num; i++)
5587 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5588 ering->rx_pending = rx_desc_count;
5589 ering->rx_jumbo_pending = rx_desc_count;
5590 ering->rx_mini_pending = 0;
5591
5592 for (i = 0; i < sp->config.tx_fifo_num; i++)
5593 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5594 ering->tx_pending = tx_desc_count;
5595 DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
5596 }
5597
5598 /**
5599 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5600 * @sp : private member of the device structure, which is a pointer to the
5601 * s2io_nic structure.
5602 * @ep : pointer to the structure with pause parameters given by ethtool.
5603 * Description:
5604 * Returns the Pause frame generation and reception capability of the NIC.
5605 * Return value:
5606 * void
5607 */
5608 static void s2io_ethtool_getpause_data(struct net_device *dev,
5609 struct ethtool_pauseparam *ep)
5610 {
5611 u64 val64;
5612 struct s2io_nic *sp = netdev_priv(dev);
5613 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5614
5615 val64 = readq(&bar0->rmac_pause_cfg);
5616 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5617 ep->tx_pause = true;
5618 if (val64 & RMAC_PAUSE_RX_ENABLE)
5619 ep->rx_pause = true;
5620 ep->autoneg = false;
5621 }
5622
5623 /**
5624 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5625 * @sp : private member of the device structure, which is a pointer to the
5626 * s2io_nic structure.
5627 * @ep : pointer to the structure with pause parameters given by ethtool.
5628 * Description:
5629 * It can be used to set or reset Pause frame generation or reception
5630 * support of the NIC.
5631 * Return value:
5632 * int, returns 0 on Success
5633 */
5634
5635 static int s2io_ethtool_setpause_data(struct net_device *dev,
5636 struct ethtool_pauseparam *ep)
5637 {
5638 u64 val64;
5639 struct s2io_nic *sp = netdev_priv(dev);
5640 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5641
5642 val64 = readq(&bar0->rmac_pause_cfg);
5643 if (ep->tx_pause)
5644 val64 |= RMAC_PAUSE_GEN_ENABLE;
5645 else
5646 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5647 if (ep->rx_pause)
5648 val64 |= RMAC_PAUSE_RX_ENABLE;
5649 else
5650 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5651 writeq(val64, &bar0->rmac_pause_cfg);
5652 return 0;
5653 }
5654
5655 /**
5656 * read_eeprom - reads 4 bytes of data from user given offset.
5657 * @sp : private member of the device structure, which is a pointer to the
5658 * s2io_nic structure.
5659 * @off : offset at which the data must be written
5660 * @data : Its an output parameter where the data read at the given
5661 * offset is stored.
5662 * Description:
5663 * Will read 4 bytes of data from the user given offset and return the
5664 * read data.
5665 * NOTE: Will allow to read only part of the EEPROM visible through the
5666 * I2C bus.
5667 * Return value:
5668 * -1 on failure and 0 on success.
5669 */
5670
5671 #define S2IO_DEV_ID 5
5672 static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
5673 {
5674 int ret = -1;
5675 u32 exit_cnt = 0;
5676 u64 val64;
5677 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5678
5679 if (sp->device_type == XFRAME_I_DEVICE) {
5680 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5681 I2C_CONTROL_ADDR(off) |
5682 I2C_CONTROL_BYTE_CNT(0x3) |
5683 I2C_CONTROL_READ |
5684 I2C_CONTROL_CNTL_START;
5685 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5686
5687 while (exit_cnt < 5) {
5688 val64 = readq(&bar0->i2c_control);
5689 if (I2C_CONTROL_CNTL_END(val64)) {
5690 *data = I2C_CONTROL_GET_DATA(val64);
5691 ret = 0;
5692 break;
5693 }
5694 msleep(50);
5695 exit_cnt++;
5696 }
5697 }
5698
5699 if (sp->device_type == XFRAME_II_DEVICE) {
5700 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5701 SPI_CONTROL_BYTECNT(0x3) |
5702 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5703 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5704 val64 |= SPI_CONTROL_REQ;
5705 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5706 while (exit_cnt < 5) {
5707 val64 = readq(&bar0->spi_control);
5708 if (val64 & SPI_CONTROL_NACK) {
5709 ret = 1;
5710 break;
5711 } else if (val64 & SPI_CONTROL_DONE) {
5712 *data = readq(&bar0->spi_data);
5713 *data &= 0xffffff;
5714 ret = 0;
5715 break;
5716 }
5717 msleep(50);
5718 exit_cnt++;
5719 }
5720 }
5721 return ret;
5722 }
5723
5724 /**
5725 * write_eeprom - actually writes the relevant part of the data value.
5726 * @sp : private member of the device structure, which is a pointer to the
5727 * s2io_nic structure.
5728 * @off : offset at which the data must be written
5729 * @data : The data that is to be written
5730 * @cnt : Number of bytes of the data that are actually to be written into
5731 * the Eeprom. (max of 3)
5732 * Description:
5733 * Actually writes the relevant part of the data value into the Eeprom
5734 * through the I2C bus.
5735 * Return value:
5736 * 0 on success, -1 on failure.
5737 */
5738
5739 static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
5740 {
5741 int exit_cnt = 0, ret = -1;
5742 u64 val64;
5743 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5744
5745 if (sp->device_type == XFRAME_I_DEVICE) {
5746 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5747 I2C_CONTROL_ADDR(off) |
5748 I2C_CONTROL_BYTE_CNT(cnt) |
5749 I2C_CONTROL_SET_DATA((u32)data) |
5750 I2C_CONTROL_CNTL_START;
5751 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5752
5753 while (exit_cnt < 5) {
5754 val64 = readq(&bar0->i2c_control);
5755 if (I2C_CONTROL_CNTL_END(val64)) {
5756 if (!(val64 & I2C_CONTROL_NACK))
5757 ret = 0;
5758 break;
5759 }
5760 msleep(50);
5761 exit_cnt++;
5762 }
5763 }
5764
5765 if (sp->device_type == XFRAME_II_DEVICE) {
5766 int write_cnt = (cnt == 8) ? 0 : cnt;
5767 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
5768
5769 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5770 SPI_CONTROL_BYTECNT(write_cnt) |
5771 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5772 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5773 val64 |= SPI_CONTROL_REQ;
5774 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5775 while (exit_cnt < 5) {
5776 val64 = readq(&bar0->spi_control);
5777 if (val64 & SPI_CONTROL_NACK) {
5778 ret = 1;
5779 break;
5780 } else if (val64 & SPI_CONTROL_DONE) {
5781 ret = 0;
5782 break;
5783 }
5784 msleep(50);
5785 exit_cnt++;
5786 }
5787 }
5788 return ret;
5789 }
5790 static void s2io_vpd_read(struct s2io_nic *nic)
5791 {
5792 u8 *vpd_data;
5793 u8 data;
5794 int i = 0, cnt, len, fail = 0;
5795 int vpd_addr = 0x80;
5796 struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
5797
5798 if (nic->device_type == XFRAME_II_DEVICE) {
5799 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5800 vpd_addr = 0x80;
5801 } else {
5802 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5803 vpd_addr = 0x50;
5804 }
5805 strcpy(nic->serial_num, "NOT AVAILABLE");
5806
5807 vpd_data = kmalloc(256, GFP_KERNEL);
5808 if (!vpd_data) {
5809 swstats->mem_alloc_fail_cnt++;
5810 return;
5811 }
5812 swstats->mem_allocated += 256;
5813
5814 for (i = 0; i < 256; i += 4) {
5815 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5816 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5817 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5818 for (cnt = 0; cnt < 5; cnt++) {
5819 msleep(2);
5820 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5821 if (data == 0x80)
5822 break;
5823 }
5824 if (cnt >= 5) {
5825 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5826 fail = 1;
5827 break;
5828 }
5829 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5830 (u32 *)&vpd_data[i]);
5831 }
5832
5833 if (!fail) {
5834 /* read serial number of adapter */
5835 for (cnt = 0; cnt < 252; cnt++) {
5836 if ((vpd_data[cnt] == 'S') &&
5837 (vpd_data[cnt+1] == 'N')) {
5838 len = vpd_data[cnt+2];
5839 if (len < min(VPD_STRING_LEN, 256-cnt-2)) {
5840 memcpy(nic->serial_num,
5841 &vpd_data[cnt + 3],
5842 len);
5843 memset(nic->serial_num+len,
5844 0,
5845 VPD_STRING_LEN-len);
5846 break;
5847 }
5848 }
5849 }
5850 }
5851
5852 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5853 len = vpd_data[1];
5854 memcpy(nic->product_name, &vpd_data[3], len);
5855 nic->product_name[len] = 0;
5856 }
5857 kfree(vpd_data);
5858 swstats->mem_freed += 256;
5859 }
5860
5861 /**
5862 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5863 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5864 * @eeprom : pointer to the user level structure provided by ethtool,
5865 * containing all relevant information.
5866 * @data_buf : user defined value to be written into Eeprom.
5867 * Description: Reads the values stored in the Eeprom at given offset
5868 * for a given length. Stores these values int the input argument data
5869 * buffer 'data_buf' and returns these to the caller (ethtool.)
5870 * Return value:
5871 * int 0 on success
5872 */
5873
5874 static int s2io_ethtool_geeprom(struct net_device *dev,
5875 struct ethtool_eeprom *eeprom, u8 * data_buf)
5876 {
5877 u32 i, valid;
5878 u64 data;
5879 struct s2io_nic *sp = netdev_priv(dev);
5880
5881 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5882
5883 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5884 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5885
5886 for (i = 0; i < eeprom->len; i += 4) {
5887 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5888 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5889 return -EFAULT;
5890 }
5891 valid = INV(data);
5892 memcpy((data_buf + i), &valid, 4);
5893 }
5894 return 0;
5895 }
5896
5897 /**
5898 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5899 * @sp : private member of the device structure, which is a pointer to the
5900 * s2io_nic structure.
5901 * @eeprom : pointer to the user level structure provided by ethtool,
5902 * containing all relevant information.
5903 * @data_buf ; user defined value to be written into Eeprom.
5904 * Description:
5905 * Tries to write the user provided value in the Eeprom, at the offset
5906 * given by the user.
5907 * Return value:
5908 * 0 on success, -EFAULT on failure.
5909 */
5910
5911 static int s2io_ethtool_seeprom(struct net_device *dev,
5912 struct ethtool_eeprom *eeprom,
5913 u8 *data_buf)
5914 {
5915 int len = eeprom->len, cnt = 0;
5916 u64 valid = 0, data;
5917 struct s2io_nic *sp = netdev_priv(dev);
5918
5919 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5920 DBG_PRINT(ERR_DBG,
5921 "ETHTOOL_WRITE_EEPROM Err: "
5922 "Magic value is wrong, it is 0x%x should be 0x%x\n",
5923 (sp->pdev->vendor | (sp->pdev->device << 16)),
5924 eeprom->magic);
5925 return -EFAULT;
5926 }
5927
5928 while (len) {
5929 data = (u32)data_buf[cnt] & 0x000000FF;
5930 if (data)
5931 valid = (u32)(data << 24);
5932 else
5933 valid = data;
5934
5935 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5936 DBG_PRINT(ERR_DBG,
5937 "ETHTOOL_WRITE_EEPROM Err: "
5938 "Cannot write into the specified offset\n");
5939 return -EFAULT;
5940 }
5941 cnt++;
5942 len--;
5943 }
5944
5945 return 0;
5946 }
5947
5948 /**
5949 * s2io_register_test - reads and writes into all clock domains.
5950 * @sp : private member of the device structure, which is a pointer to the
5951 * s2io_nic structure.
5952 * @data : variable that returns the result of each of the test conducted b
5953 * by the driver.
5954 * Description:
5955 * Read and write into all clock domains. The NIC has 3 clock domains,
5956 * see that registers in all the three regions are accessible.
5957 * Return value:
5958 * 0 on success.
5959 */
5960
5961 static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
5962 {
5963 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5964 u64 val64 = 0, exp_val;
5965 int fail = 0;
5966
5967 val64 = readq(&bar0->pif_rd_swapper_fb);
5968 if (val64 != 0x123456789abcdefULL) {
5969 fail = 1;
5970 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
5971 }
5972
5973 val64 = readq(&bar0->rmac_pause_cfg);
5974 if (val64 != 0xc000ffff00000000ULL) {
5975 fail = 1;
5976 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
5977 }
5978
5979 val64 = readq(&bar0->rx_queue_cfg);
5980 if (sp->device_type == XFRAME_II_DEVICE)
5981 exp_val = 0x0404040404040404ULL;
5982 else
5983 exp_val = 0x0808080808080808ULL;
5984 if (val64 != exp_val) {
5985 fail = 1;
5986 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
5987 }
5988
5989 val64 = readq(&bar0->xgxs_efifo_cfg);
5990 if (val64 != 0x000000001923141EULL) {
5991 fail = 1;
5992 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
5993 }
5994
5995 val64 = 0x5A5A5A5A5A5A5A5AULL;
5996 writeq(val64, &bar0->xmsi_data);
5997 val64 = readq(&bar0->xmsi_data);
5998 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5999 fail = 1;
6000 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
6001 }
6002
6003 val64 = 0xA5A5A5A5A5A5A5A5ULL;
6004 writeq(val64, &bar0->xmsi_data);
6005 val64 = readq(&bar0->xmsi_data);
6006 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
6007 fail = 1;
6008 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
6009 }
6010
6011 *data = fail;
6012 return fail;
6013 }
6014
6015 /**
6016 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
6017 * @sp : private member of the device structure, which is a pointer to the
6018 * s2io_nic structure.
6019 * @data:variable that returns the result of each of the test conducted by
6020 * the driver.
6021 * Description:
6022 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
6023 * register.
6024 * Return value:
6025 * 0 on success.
6026 */
6027
6028 static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
6029 {
6030 int fail = 0;
6031 u64 ret_data, org_4F0, org_7F0;
6032 u8 saved_4F0 = 0, saved_7F0 = 0;
6033 struct net_device *dev = sp->dev;
6034
6035 /* Test Write Error at offset 0 */
6036 /* Note that SPI interface allows write access to all areas
6037 * of EEPROM. Hence doing all negative testing only for Xframe I.
6038 */
6039 if (sp->device_type == XFRAME_I_DEVICE)
6040 if (!write_eeprom(sp, 0, 0, 3))
6041 fail = 1;
6042
6043 /* Save current values at offsets 0x4F0 and 0x7F0 */
6044 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6045 saved_4F0 = 1;
6046 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6047 saved_7F0 = 1;
6048
6049 /* Test Write at offset 4f0 */
6050 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
6051 fail = 1;
6052 if (read_eeprom(sp, 0x4F0, &ret_data))
6053 fail = 1;
6054
6055 if (ret_data != 0x012345) {
6056 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
6057 "Data written %llx Data read %llx\n",
6058 dev->name, (unsigned long long)0x12345,
6059 (unsigned long long)ret_data);
6060 fail = 1;
6061 }
6062
6063 /* Reset the EEPROM data go FFFF */
6064 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
6065
6066 /* Test Write Request Error at offset 0x7c */
6067 if (sp->device_type == XFRAME_I_DEVICE)
6068 if (!write_eeprom(sp, 0x07C, 0, 3))
6069 fail = 1;
6070
6071 /* Test Write Request at offset 0x7f0 */
6072 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
6073 fail = 1;
6074 if (read_eeprom(sp, 0x7F0, &ret_data))
6075 fail = 1;
6076
6077 if (ret_data != 0x012345) {
6078 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6079 "Data written %llx Data read %llx\n",
6080 dev->name, (unsigned long long)0x12345,
6081 (unsigned long long)ret_data);
6082 fail = 1;
6083 }
6084
6085 /* Reset the EEPROM data go FFFF */
6086 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
6087
6088 if (sp->device_type == XFRAME_I_DEVICE) {
6089 /* Test Write Error at offset 0x80 */
6090 if (!write_eeprom(sp, 0x080, 0, 3))
6091 fail = 1;
6092
6093 /* Test Write Error at offset 0xfc */
6094 if (!write_eeprom(sp, 0x0FC, 0, 3))
6095 fail = 1;
6096
6097 /* Test Write Error at offset 0x100 */
6098 if (!write_eeprom(sp, 0x100, 0, 3))
6099 fail = 1;
6100
6101 /* Test Write Error at offset 4ec */
6102 if (!write_eeprom(sp, 0x4EC, 0, 3))
6103 fail = 1;
6104 }
6105
6106 /* Restore values at offsets 0x4F0 and 0x7F0 */
6107 if (saved_4F0)
6108 write_eeprom(sp, 0x4F0, org_4F0, 3);
6109 if (saved_7F0)
6110 write_eeprom(sp, 0x7F0, org_7F0, 3);
6111
6112 *data = fail;
6113 return fail;
6114 }
6115
6116 /**
6117 * s2io_bist_test - invokes the MemBist test of the card .
6118 * @sp : private member of the device structure, which is a pointer to the
6119 * s2io_nic structure.
6120 * @data:variable that returns the result of each of the test conducted by
6121 * the driver.
6122 * Description:
6123 * This invokes the MemBist test of the card. We give around
6124 * 2 secs time for the Test to complete. If it's still not complete
6125 * within this peiod, we consider that the test failed.
6126 * Return value:
6127 * 0 on success and -1 on failure.
6128 */
6129
6130 static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
6131 {
6132 u8 bist = 0;
6133 int cnt = 0, ret = -1;
6134
6135 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6136 bist |= PCI_BIST_START;
6137 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6138
6139 while (cnt < 20) {
6140 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6141 if (!(bist & PCI_BIST_START)) {
6142 *data = (bist & PCI_BIST_CODE_MASK);
6143 ret = 0;
6144 break;
6145 }
6146 msleep(100);
6147 cnt++;
6148 }
6149
6150 return ret;
6151 }
6152
6153 /**
6154 * s2io-link_test - verifies the link state of the nic
6155 * @sp ; private member of the device structure, which is a pointer to the
6156 * s2io_nic structure.
6157 * @data: variable that returns the result of each of the test conducted by
6158 * the driver.
6159 * Description:
6160 * The function verifies the link state of the NIC and updates the input
6161 * argument 'data' appropriately.
6162 * Return value:
6163 * 0 on success.
6164 */
6165
6166 static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
6167 {
6168 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6169 u64 val64;
6170
6171 val64 = readq(&bar0->adapter_status);
6172 if (!(LINK_IS_UP(val64)))
6173 *data = 1;
6174 else
6175 *data = 0;
6176
6177 return *data;
6178 }
6179
6180 /**
6181 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6182 * @sp - private member of the device structure, which is a pointer to the
6183 * s2io_nic structure.
6184 * @data - variable that returns the result of each of the test
6185 * conducted by the driver.
6186 * Description:
6187 * This is one of the offline test that tests the read and write
6188 * access to the RldRam chip on the NIC.
6189 * Return value:
6190 * 0 on success.
6191 */
6192
6193 static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
6194 {
6195 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6196 u64 val64;
6197 int cnt, iteration = 0, test_fail = 0;
6198
6199 val64 = readq(&bar0->adapter_control);
6200 val64 &= ~ADAPTER_ECC_EN;
6201 writeq(val64, &bar0->adapter_control);
6202
6203 val64 = readq(&bar0->mc_rldram_test_ctrl);
6204 val64 |= MC_RLDRAM_TEST_MODE;
6205 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6206
6207 val64 = readq(&bar0->mc_rldram_mrs);
6208 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6209 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6210
6211 val64 |= MC_RLDRAM_MRS_ENABLE;
6212 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6213
6214 while (iteration < 2) {
6215 val64 = 0x55555555aaaa0000ULL;
6216 if (iteration == 1)
6217 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6218 writeq(val64, &bar0->mc_rldram_test_d0);
6219
6220 val64 = 0xaaaa5a5555550000ULL;
6221 if (iteration == 1)
6222 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6223 writeq(val64, &bar0->mc_rldram_test_d1);
6224
6225 val64 = 0x55aaaaaaaa5a0000ULL;
6226 if (iteration == 1)
6227 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6228 writeq(val64, &bar0->mc_rldram_test_d2);
6229
6230 val64 = (u64) (0x0000003ffffe0100ULL);
6231 writeq(val64, &bar0->mc_rldram_test_add);
6232
6233 val64 = MC_RLDRAM_TEST_MODE |
6234 MC_RLDRAM_TEST_WRITE |
6235 MC_RLDRAM_TEST_GO;
6236 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6237
6238 for (cnt = 0; cnt < 5; cnt++) {
6239 val64 = readq(&bar0->mc_rldram_test_ctrl);
6240 if (val64 & MC_RLDRAM_TEST_DONE)
6241 break;
6242 msleep(200);
6243 }
6244
6245 if (cnt == 5)
6246 break;
6247
6248 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6249 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6250
6251 for (cnt = 0; cnt < 5; cnt++) {
6252 val64 = readq(&bar0->mc_rldram_test_ctrl);
6253 if (val64 & MC_RLDRAM_TEST_DONE)
6254 break;
6255 msleep(500);
6256 }
6257
6258 if (cnt == 5)
6259 break;
6260
6261 val64 = readq(&bar0->mc_rldram_test_ctrl);
6262 if (!(val64 & MC_RLDRAM_TEST_PASS))
6263 test_fail = 1;
6264
6265 iteration++;
6266 }
6267
6268 *data = test_fail;
6269
6270 /* Bring the adapter out of test mode */
6271 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6272
6273 return test_fail;
6274 }
6275
6276 /**
6277 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6278 * @sp : private member of the device structure, which is a pointer to the
6279 * s2io_nic structure.
6280 * @ethtest : pointer to a ethtool command specific structure that will be
6281 * returned to the user.
6282 * @data : variable that returns the result of each of the test
6283 * conducted by the driver.
6284 * Description:
6285 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6286 * the health of the card.
6287 * Return value:
6288 * void
6289 */
6290
6291 static void s2io_ethtool_test(struct net_device *dev,
6292 struct ethtool_test *ethtest,
6293 uint64_t *data)
6294 {
6295 struct s2io_nic *sp = netdev_priv(dev);
6296 int orig_state = netif_running(sp->dev);
6297
6298 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6299 /* Offline Tests. */
6300 if (orig_state)
6301 s2io_close(sp->dev);
6302
6303 if (s2io_register_test(sp, &data[0]))
6304 ethtest->flags |= ETH_TEST_FL_FAILED;
6305
6306 s2io_reset(sp);
6307
6308 if (s2io_rldram_test(sp, &data[3]))
6309 ethtest->flags |= ETH_TEST_FL_FAILED;
6310
6311 s2io_reset(sp);
6312
6313 if (s2io_eeprom_test(sp, &data[1]))
6314 ethtest->flags |= ETH_TEST_FL_FAILED;
6315
6316 if (s2io_bist_test(sp, &data[4]))
6317 ethtest->flags |= ETH_TEST_FL_FAILED;
6318
6319 if (orig_state)
6320 s2io_open(sp->dev);
6321
6322 data[2] = 0;
6323 } else {
6324 /* Online Tests. */
6325 if (!orig_state) {
6326 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
6327 dev->name);
6328 data[0] = -1;
6329 data[1] = -1;
6330 data[2] = -1;
6331 data[3] = -1;
6332 data[4] = -1;
6333 }
6334
6335 if (s2io_link_test(sp, &data[2]))
6336 ethtest->flags |= ETH_TEST_FL_FAILED;
6337
6338 data[0] = 0;
6339 data[1] = 0;
6340 data[3] = 0;
6341 data[4] = 0;
6342 }
6343 }
6344
6345 static void s2io_get_ethtool_stats(struct net_device *dev,
6346 struct ethtool_stats *estats,
6347 u64 *tmp_stats)
6348 {
6349 int i = 0, k;
6350 struct s2io_nic *sp = netdev_priv(dev);
6351 struct stat_block *stats = sp->mac_control.stats_info;
6352 struct swStat *swstats = &stats->sw_stat;
6353 struct xpakStat *xstats = &stats->xpak_stat;
6354
6355 s2io_updt_stats(sp);
6356 tmp_stats[i++] =
6357 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 |
6358 le32_to_cpu(stats->tmac_frms);
6359 tmp_stats[i++] =
6360 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6361 le32_to_cpu(stats->tmac_data_octets);
6362 tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
6363 tmp_stats[i++] =
6364 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6365 le32_to_cpu(stats->tmac_mcst_frms);
6366 tmp_stats[i++] =
6367 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6368 le32_to_cpu(stats->tmac_bcst_frms);
6369 tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
6370 tmp_stats[i++] =
6371 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6372 le32_to_cpu(stats->tmac_ttl_octets);
6373 tmp_stats[i++] =
6374 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6375 le32_to_cpu(stats->tmac_ucst_frms);
6376 tmp_stats[i++] =
6377 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6378 le32_to_cpu(stats->tmac_nucst_frms);
6379 tmp_stats[i++] =
6380 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6381 le32_to_cpu(stats->tmac_any_err_frms);
6382 tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6383 tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
6384 tmp_stats[i++] =
6385 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6386 le32_to_cpu(stats->tmac_vld_ip);
6387 tmp_stats[i++] =
6388 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6389 le32_to_cpu(stats->tmac_drop_ip);
6390 tmp_stats[i++] =
6391 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6392 le32_to_cpu(stats->tmac_icmp);
6393 tmp_stats[i++] =
6394 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6395 le32_to_cpu(stats->tmac_rst_tcp);
6396 tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6397 tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6398 le32_to_cpu(stats->tmac_udp);
6399 tmp_stats[i++] =
6400 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6401 le32_to_cpu(stats->rmac_vld_frms);
6402 tmp_stats[i++] =
6403 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6404 le32_to_cpu(stats->rmac_data_octets);
6405 tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6406 tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
6407 tmp_stats[i++] =
6408 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6409 le32_to_cpu(stats->rmac_vld_mcst_frms);
6410 tmp_stats[i++] =
6411 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6412 le32_to_cpu(stats->rmac_vld_bcst_frms);
6413 tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6414 tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6415 tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6416 tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6417 tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
6418 tmp_stats[i++] =
6419 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6420 le32_to_cpu(stats->rmac_ttl_octets);
6421 tmp_stats[i++] =
6422 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6423 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
6424 tmp_stats[i++] =
6425 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6426 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
6427 tmp_stats[i++] =
6428 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6429 le32_to_cpu(stats->rmac_discarded_frms);
6430 tmp_stats[i++] =
6431 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6432 << 32 | le32_to_cpu(stats->rmac_drop_events);
6433 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6434 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
6435 tmp_stats[i++] =
6436 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6437 le32_to_cpu(stats->rmac_usized_frms);
6438 tmp_stats[i++] =
6439 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6440 le32_to_cpu(stats->rmac_osized_frms);
6441 tmp_stats[i++] =
6442 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6443 le32_to_cpu(stats->rmac_frag_frms);
6444 tmp_stats[i++] =
6445 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6446 le32_to_cpu(stats->rmac_jabber_frms);
6447 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6448 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6449 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6450 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6451 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6452 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
6453 tmp_stats[i++] =
6454 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6455 le32_to_cpu(stats->rmac_ip);
6456 tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6457 tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
6458 tmp_stats[i++] =
6459 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6460 le32_to_cpu(stats->rmac_drop_ip);
6461 tmp_stats[i++] =
6462 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6463 le32_to_cpu(stats->rmac_icmp);
6464 tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
6465 tmp_stats[i++] =
6466 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6467 le32_to_cpu(stats->rmac_udp);
6468 tmp_stats[i++] =
6469 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6470 le32_to_cpu(stats->rmac_err_drp_udp);
6471 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6472 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6473 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6474 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6475 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6476 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6477 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6478 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6479 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6480 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6481 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6482 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6483 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6484 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6485 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6486 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6487 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
6488 tmp_stats[i++] =
6489 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6490 le32_to_cpu(stats->rmac_pause_cnt);
6491 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6492 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
6493 tmp_stats[i++] =
6494 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6495 le32_to_cpu(stats->rmac_accepted_ip);
6496 tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6497 tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6498 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6499 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6500 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6501 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6502 tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6503 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6504 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6505 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6506 tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6507 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6508 tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6509 tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6510 tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6511 tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6512 tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6513 tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6514 tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
6515
6516 /* Enhanced statistics exist only for Hercules */
6517 if (sp->device_type == XFRAME_II_DEVICE) {
6518 tmp_stats[i++] =
6519 le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
6520 tmp_stats[i++] =
6521 le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
6522 tmp_stats[i++] =
6523 le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6524 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6525 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6526 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6527 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6528 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6529 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6530 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6531 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6532 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6533 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6534 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6535 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6536 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
6537 }
6538
6539 tmp_stats[i++] = 0;
6540 tmp_stats[i++] = swstats->single_ecc_errs;
6541 tmp_stats[i++] = swstats->double_ecc_errs;
6542 tmp_stats[i++] = swstats->parity_err_cnt;
6543 tmp_stats[i++] = swstats->serious_err_cnt;
6544 tmp_stats[i++] = swstats->soft_reset_cnt;
6545 tmp_stats[i++] = swstats->fifo_full_cnt;
6546 for (k = 0; k < MAX_RX_RINGS; k++)
6547 tmp_stats[i++] = swstats->ring_full_cnt[k];
6548 tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6549 tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6550 tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6551 tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6552 tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6553 tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6554 tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6555 tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6556 tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6557 tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6558 tmp_stats[i++] = xstats->warn_laser_output_power_high;
6559 tmp_stats[i++] = xstats->warn_laser_output_power_low;
6560 tmp_stats[i++] = swstats->clubbed_frms_cnt;
6561 tmp_stats[i++] = swstats->sending_both;
6562 tmp_stats[i++] = swstats->outof_sequence_pkts;
6563 tmp_stats[i++] = swstats->flush_max_pkts;
6564 if (swstats->num_aggregations) {
6565 u64 tmp = swstats->sum_avg_pkts_aggregated;
6566 int count = 0;
6567 /*
6568 * Since 64-bit divide does not work on all platforms,
6569 * do repeated subtraction.
6570 */
6571 while (tmp >= swstats->num_aggregations) {
6572 tmp -= swstats->num_aggregations;
6573 count++;
6574 }
6575 tmp_stats[i++] = count;
6576 } else
6577 tmp_stats[i++] = 0;
6578 tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6579 tmp_stats[i++] = swstats->pci_map_fail_cnt;
6580 tmp_stats[i++] = swstats->watchdog_timer_cnt;
6581 tmp_stats[i++] = swstats->mem_allocated;
6582 tmp_stats[i++] = swstats->mem_freed;
6583 tmp_stats[i++] = swstats->link_up_cnt;
6584 tmp_stats[i++] = swstats->link_down_cnt;
6585 tmp_stats[i++] = swstats->link_up_time;
6586 tmp_stats[i++] = swstats->link_down_time;
6587
6588 tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6589 tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6590 tmp_stats[i++] = swstats->tx_parity_err_cnt;
6591 tmp_stats[i++] = swstats->tx_link_loss_cnt;
6592 tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6593
6594 tmp_stats[i++] = swstats->rx_parity_err_cnt;
6595 tmp_stats[i++] = swstats->rx_abort_cnt;
6596 tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6597 tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6598 tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6599 tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6600 tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6601 tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6602 tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6603 tmp_stats[i++] = swstats->tda_err_cnt;
6604 tmp_stats[i++] = swstats->pfc_err_cnt;
6605 tmp_stats[i++] = swstats->pcc_err_cnt;
6606 tmp_stats[i++] = swstats->tti_err_cnt;
6607 tmp_stats[i++] = swstats->tpa_err_cnt;
6608 tmp_stats[i++] = swstats->sm_err_cnt;
6609 tmp_stats[i++] = swstats->lso_err_cnt;
6610 tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6611 tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6612 tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6613 tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6614 tmp_stats[i++] = swstats->rc_err_cnt;
6615 tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6616 tmp_stats[i++] = swstats->rpa_err_cnt;
6617 tmp_stats[i++] = swstats->rda_err_cnt;
6618 tmp_stats[i++] = swstats->rti_err_cnt;
6619 tmp_stats[i++] = swstats->mc_err_cnt;
6620 }
6621
6622 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6623 {
6624 return XENA_REG_SPACE;
6625 }
6626
6627
6628 static u32 s2io_ethtool_get_rx_csum(struct net_device *dev)
6629 {
6630 struct s2io_nic *sp = netdev_priv(dev);
6631
6632 return sp->rx_csum;
6633 }
6634
6635 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
6636 {
6637 struct s2io_nic *sp = netdev_priv(dev);
6638
6639 if (data)
6640 sp->rx_csum = 1;
6641 else
6642 sp->rx_csum = 0;
6643
6644 return 0;
6645 }
6646
6647 static int s2io_get_eeprom_len(struct net_device *dev)
6648 {
6649 return XENA_EEPROM_SPACE;
6650 }
6651
6652 static int s2io_get_sset_count(struct net_device *dev, int sset)
6653 {
6654 struct s2io_nic *sp = netdev_priv(dev);
6655
6656 switch (sset) {
6657 case ETH_SS_TEST:
6658 return S2IO_TEST_LEN;
6659 case ETH_SS_STATS:
6660 switch (sp->device_type) {
6661 case XFRAME_I_DEVICE:
6662 return XFRAME_I_STAT_LEN;
6663 case XFRAME_II_DEVICE:
6664 return XFRAME_II_STAT_LEN;
6665 default:
6666 return 0;
6667 }
6668 default:
6669 return -EOPNOTSUPP;
6670 }
6671 }
6672
6673 static void s2io_ethtool_get_strings(struct net_device *dev,
6674 u32 stringset, u8 *data)
6675 {
6676 int stat_size = 0;
6677 struct s2io_nic *sp = netdev_priv(dev);
6678
6679 switch (stringset) {
6680 case ETH_SS_TEST:
6681 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6682 break;
6683 case ETH_SS_STATS:
6684 stat_size = sizeof(ethtool_xena_stats_keys);
6685 memcpy(data, &ethtool_xena_stats_keys, stat_size);
6686 if (sp->device_type == XFRAME_II_DEVICE) {
6687 memcpy(data + stat_size,
6688 &ethtool_enhanced_stats_keys,
6689 sizeof(ethtool_enhanced_stats_keys));
6690 stat_size += sizeof(ethtool_enhanced_stats_keys);
6691 }
6692
6693 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6694 sizeof(ethtool_driver_stats_keys));
6695 }
6696 }
6697
6698 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
6699 {
6700 if (data)
6701 dev->features |= NETIF_F_IP_CSUM;
6702 else
6703 dev->features &= ~NETIF_F_IP_CSUM;
6704
6705 return 0;
6706 }
6707
6708 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6709 {
6710 return (dev->features & NETIF_F_TSO) != 0;
6711 }
6712
6713 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6714 {
6715 if (data)
6716 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6717 else
6718 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6719
6720 return 0;
6721 }
6722
6723 static int s2io_ethtool_set_flags(struct net_device *dev, u32 data)
6724 {
6725 struct s2io_nic *sp = netdev_priv(dev);
6726 int rc = 0;
6727 int changed = 0;
6728
6729 if (data & ~ETH_FLAG_LRO)
6730 return -EINVAL;
6731
6732 if (data & ETH_FLAG_LRO) {
6733 if (!(dev->features & NETIF_F_LRO)) {
6734 dev->features |= NETIF_F_LRO;
6735 changed = 1;
6736 }
6737 } else if (dev->features & NETIF_F_LRO) {
6738 dev->features &= ~NETIF_F_LRO;
6739 changed = 1;
6740 }
6741
6742 if (changed && netif_running(dev)) {
6743 s2io_stop_all_tx_queue(sp);
6744 s2io_card_down(sp);
6745 rc = s2io_card_up(sp);
6746 if (rc)
6747 s2io_reset(sp);
6748 else
6749 s2io_start_all_tx_queue(sp);
6750 }
6751
6752 return rc;
6753 }
6754
6755 static const struct ethtool_ops netdev_ethtool_ops = {
6756 .get_settings = s2io_ethtool_gset,
6757 .set_settings = s2io_ethtool_sset,
6758 .get_drvinfo = s2io_ethtool_gdrvinfo,
6759 .get_regs_len = s2io_ethtool_get_regs_len,
6760 .get_regs = s2io_ethtool_gregs,
6761 .get_link = ethtool_op_get_link,
6762 .get_eeprom_len = s2io_get_eeprom_len,
6763 .get_eeprom = s2io_ethtool_geeprom,
6764 .set_eeprom = s2io_ethtool_seeprom,
6765 .get_ringparam = s2io_ethtool_gringparam,
6766 .get_pauseparam = s2io_ethtool_getpause_data,
6767 .set_pauseparam = s2io_ethtool_setpause_data,
6768 .get_rx_csum = s2io_ethtool_get_rx_csum,
6769 .set_rx_csum = s2io_ethtool_set_rx_csum,
6770 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6771 .set_flags = s2io_ethtool_set_flags,
6772 .get_flags = ethtool_op_get_flags,
6773 .set_sg = ethtool_op_set_sg,
6774 .get_tso = s2io_ethtool_op_get_tso,
6775 .set_tso = s2io_ethtool_op_set_tso,
6776 .set_ufo = ethtool_op_set_ufo,
6777 .self_test = s2io_ethtool_test,
6778 .get_strings = s2io_ethtool_get_strings,
6779 .phys_id = s2io_ethtool_idnic,
6780 .get_ethtool_stats = s2io_get_ethtool_stats,
6781 .get_sset_count = s2io_get_sset_count,
6782 };
6783
6784 /**
6785 * s2io_ioctl - Entry point for the Ioctl
6786 * @dev : Device pointer.
6787 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6788 * a proprietary structure used to pass information to the driver.
6789 * @cmd : This is used to distinguish between the different commands that
6790 * can be passed to the IOCTL functions.
6791 * Description:
6792 * Currently there are no special functionality supported in IOCTL, hence
6793 * function always return EOPNOTSUPPORTED
6794 */
6795
6796 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6797 {
6798 return -EOPNOTSUPP;
6799 }
6800
6801 /**
6802 * s2io_change_mtu - entry point to change MTU size for the device.
6803 * @dev : device pointer.
6804 * @new_mtu : the new MTU size for the device.
6805 * Description: A driver entry point to change MTU size for the device.
6806 * Before changing the MTU the device must be stopped.
6807 * Return value:
6808 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6809 * file on failure.
6810 */
6811
6812 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6813 {
6814 struct s2io_nic *sp = netdev_priv(dev);
6815 int ret = 0;
6816
6817 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6818 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
6819 return -EPERM;
6820 }
6821
6822 dev->mtu = new_mtu;
6823 if (netif_running(dev)) {
6824 s2io_stop_all_tx_queue(sp);
6825 s2io_card_down(sp);
6826 ret = s2io_card_up(sp);
6827 if (ret) {
6828 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6829 __func__);
6830 return ret;
6831 }
6832 s2io_wake_all_tx_queue(sp);
6833 } else { /* Device is down */
6834 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6835 u64 val64 = new_mtu;
6836
6837 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6838 }
6839
6840 return ret;
6841 }
6842
6843 /**
6844 * s2io_set_link - Set the LInk status
6845 * @data: long pointer to device private structue
6846 * Description: Sets the link status for the adapter
6847 */
6848
6849 static void s2io_set_link(struct work_struct *work)
6850 {
6851 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6852 set_link_task);
6853 struct net_device *dev = nic->dev;
6854 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6855 register u64 val64;
6856 u16 subid;
6857
6858 rtnl_lock();
6859
6860 if (!netif_running(dev))
6861 goto out_unlock;
6862
6863 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6864 /* The card is being reset, no point doing anything */
6865 goto out_unlock;
6866 }
6867
6868 subid = nic->pdev->subsystem_device;
6869 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6870 /*
6871 * Allow a small delay for the NICs self initiated
6872 * cleanup to complete.
6873 */
6874 msleep(100);
6875 }
6876
6877 val64 = readq(&bar0->adapter_status);
6878 if (LINK_IS_UP(val64)) {
6879 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6880 if (verify_xena_quiescence(nic)) {
6881 val64 = readq(&bar0->adapter_control);
6882 val64 |= ADAPTER_CNTL_EN;
6883 writeq(val64, &bar0->adapter_control);
6884 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6885 nic->device_type, subid)) {
6886 val64 = readq(&bar0->gpio_control);
6887 val64 |= GPIO_CTRL_GPIO_0;
6888 writeq(val64, &bar0->gpio_control);
6889 val64 = readq(&bar0->gpio_control);
6890 } else {
6891 val64 |= ADAPTER_LED_ON;
6892 writeq(val64, &bar0->adapter_control);
6893 }
6894 nic->device_enabled_once = true;
6895 } else {
6896 DBG_PRINT(ERR_DBG,
6897 "%s: Error: device is not Quiescent\n",
6898 dev->name);
6899 s2io_stop_all_tx_queue(nic);
6900 }
6901 }
6902 val64 = readq(&bar0->adapter_control);
6903 val64 |= ADAPTER_LED_ON;
6904 writeq(val64, &bar0->adapter_control);
6905 s2io_link(nic, LINK_UP);
6906 } else {
6907 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6908 subid)) {
6909 val64 = readq(&bar0->gpio_control);
6910 val64 &= ~GPIO_CTRL_GPIO_0;
6911 writeq(val64, &bar0->gpio_control);
6912 val64 = readq(&bar0->gpio_control);
6913 }
6914 /* turn off LED */
6915 val64 = readq(&bar0->adapter_control);
6916 val64 = val64 & (~ADAPTER_LED_ON);
6917 writeq(val64, &bar0->adapter_control);
6918 s2io_link(nic, LINK_DOWN);
6919 }
6920 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6921
6922 out_unlock:
6923 rtnl_unlock();
6924 }
6925
6926 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6927 struct buffAdd *ba,
6928 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6929 u64 *temp2, int size)
6930 {
6931 struct net_device *dev = sp->dev;
6932 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6933
6934 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6935 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6936 /* allocate skb */
6937 if (*skb) {
6938 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6939 /*
6940 * As Rx frame are not going to be processed,
6941 * using same mapped address for the Rxd
6942 * buffer pointer
6943 */
6944 rxdp1->Buffer0_ptr = *temp0;
6945 } else {
6946 *skb = dev_alloc_skb(size);
6947 if (!(*skb)) {
6948 DBG_PRINT(INFO_DBG,
6949 "%s: Out of memory to allocate %s\n",
6950 dev->name, "1 buf mode SKBs");
6951 stats->mem_alloc_fail_cnt++;
6952 return -ENOMEM ;
6953 }
6954 stats->mem_allocated += (*skb)->truesize;
6955 /* storing the mapped addr in a temp variable
6956 * such it will be used for next rxd whose
6957 * Host Control is NULL
6958 */
6959 rxdp1->Buffer0_ptr = *temp0 =
6960 pci_map_single(sp->pdev, (*skb)->data,
6961 size - NET_IP_ALIGN,
6962 PCI_DMA_FROMDEVICE);
6963 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
6964 goto memalloc_failed;
6965 rxdp->Host_Control = (unsigned long) (*skb);
6966 }
6967 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6968 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6969 /* Two buffer Mode */
6970 if (*skb) {
6971 rxdp3->Buffer2_ptr = *temp2;
6972 rxdp3->Buffer0_ptr = *temp0;
6973 rxdp3->Buffer1_ptr = *temp1;
6974 } else {
6975 *skb = dev_alloc_skb(size);
6976 if (!(*skb)) {
6977 DBG_PRINT(INFO_DBG,
6978 "%s: Out of memory to allocate %s\n",
6979 dev->name,
6980 "2 buf mode SKBs");
6981 stats->mem_alloc_fail_cnt++;
6982 return -ENOMEM;
6983 }
6984 stats->mem_allocated += (*skb)->truesize;
6985 rxdp3->Buffer2_ptr = *temp2 =
6986 pci_map_single(sp->pdev, (*skb)->data,
6987 dev->mtu + 4,
6988 PCI_DMA_FROMDEVICE);
6989 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
6990 goto memalloc_failed;
6991 rxdp3->Buffer0_ptr = *temp0 =
6992 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6993 PCI_DMA_FROMDEVICE);
6994 if (pci_dma_mapping_error(sp->pdev,
6995 rxdp3->Buffer0_ptr)) {
6996 pci_unmap_single(sp->pdev,
6997 (dma_addr_t)rxdp3->Buffer2_ptr,
6998 dev->mtu + 4,
6999 PCI_DMA_FROMDEVICE);
7000 goto memalloc_failed;
7001 }
7002 rxdp->Host_Control = (unsigned long) (*skb);
7003
7004 /* Buffer-1 will be dummy buffer not used */
7005 rxdp3->Buffer1_ptr = *temp1 =
7006 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
7007 PCI_DMA_FROMDEVICE);
7008 if (pci_dma_mapping_error(sp->pdev,
7009 rxdp3->Buffer1_ptr)) {
7010 pci_unmap_single(sp->pdev,
7011 (dma_addr_t)rxdp3->Buffer0_ptr,
7012 BUF0_LEN, PCI_DMA_FROMDEVICE);
7013 pci_unmap_single(sp->pdev,
7014 (dma_addr_t)rxdp3->Buffer2_ptr,
7015 dev->mtu + 4,
7016 PCI_DMA_FROMDEVICE);
7017 goto memalloc_failed;
7018 }
7019 }
7020 }
7021 return 0;
7022
7023 memalloc_failed:
7024 stats->pci_map_fail_cnt++;
7025 stats->mem_freed += (*skb)->truesize;
7026 dev_kfree_skb(*skb);
7027 return -ENOMEM;
7028 }
7029
7030 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
7031 int size)
7032 {
7033 struct net_device *dev = sp->dev;
7034 if (sp->rxd_mode == RXD_MODE_1) {
7035 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
7036 } else if (sp->rxd_mode == RXD_MODE_3B) {
7037 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
7038 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
7039 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
7040 }
7041 }
7042
7043 static int rxd_owner_bit_reset(struct s2io_nic *sp)
7044 {
7045 int i, j, k, blk_cnt = 0, size;
7046 struct config_param *config = &sp->config;
7047 struct mac_info *mac_control = &sp->mac_control;
7048 struct net_device *dev = sp->dev;
7049 struct RxD_t *rxdp = NULL;
7050 struct sk_buff *skb = NULL;
7051 struct buffAdd *ba = NULL;
7052 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
7053
7054 /* Calculate the size based on ring mode */
7055 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
7056 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
7057 if (sp->rxd_mode == RXD_MODE_1)
7058 size += NET_IP_ALIGN;
7059 else if (sp->rxd_mode == RXD_MODE_3B)
7060 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
7061
7062 for (i = 0; i < config->rx_ring_num; i++) {
7063 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7064 struct ring_info *ring = &mac_control->rings[i];
7065
7066 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
7067
7068 for (j = 0; j < blk_cnt; j++) {
7069 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
7070 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
7071 if (sp->rxd_mode == RXD_MODE_3B)
7072 ba = &ring->ba[j][k];
7073 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
7074 (u64 *)&temp0_64,
7075 (u64 *)&temp1_64,
7076 (u64 *)&temp2_64,
7077 size) == -ENOMEM) {
7078 return 0;
7079 }
7080
7081 set_rxd_buffer_size(sp, rxdp, size);
7082 wmb();
7083 /* flip the Ownership bit to Hardware */
7084 rxdp->Control_1 |= RXD_OWN_XENA;
7085 }
7086 }
7087 }
7088 return 0;
7089
7090 }
7091
7092 static int s2io_add_isr(struct s2io_nic *sp)
7093 {
7094 int ret = 0;
7095 struct net_device *dev = sp->dev;
7096 int err = 0;
7097
7098 if (sp->config.intr_type == MSI_X)
7099 ret = s2io_enable_msi_x(sp);
7100 if (ret) {
7101 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
7102 sp->config.intr_type = INTA;
7103 }
7104
7105 /*
7106 * Store the values of the MSIX table in
7107 * the struct s2io_nic structure
7108 */
7109 store_xmsi_data(sp);
7110
7111 /* After proper initialization of H/W, register ISR */
7112 if (sp->config.intr_type == MSI_X) {
7113 int i, msix_rx_cnt = 0;
7114
7115 for (i = 0; i < sp->num_entries; i++) {
7116 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7117 if (sp->s2io_entries[i].type ==
7118 MSIX_RING_TYPE) {
7119 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7120 dev->name, i);
7121 err = request_irq(sp->entries[i].vector,
7122 s2io_msix_ring_handle,
7123 0,
7124 sp->desc[i],
7125 sp->s2io_entries[i].arg);
7126 } else if (sp->s2io_entries[i].type ==
7127 MSIX_ALARM_TYPE) {
7128 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
7129 dev->name, i);
7130 err = request_irq(sp->entries[i].vector,
7131 s2io_msix_fifo_handle,
7132 0,
7133 sp->desc[i],
7134 sp->s2io_entries[i].arg);
7135
7136 }
7137 /* if either data or addr is zero print it. */
7138 if (!(sp->msix_info[i].addr &&
7139 sp->msix_info[i].data)) {
7140 DBG_PRINT(ERR_DBG,
7141 "%s @Addr:0x%llx Data:0x%llx\n",
7142 sp->desc[i],
7143 (unsigned long long)
7144 sp->msix_info[i].addr,
7145 (unsigned long long)
7146 ntohl(sp->msix_info[i].data));
7147 } else
7148 msix_rx_cnt++;
7149 if (err) {
7150 remove_msix_isr(sp);
7151
7152 DBG_PRINT(ERR_DBG,
7153 "%s:MSI-X-%d registration "
7154 "failed\n", dev->name, i);
7155
7156 DBG_PRINT(ERR_DBG,
7157 "%s: Defaulting to INTA\n",
7158 dev->name);
7159 sp->config.intr_type = INTA;
7160 break;
7161 }
7162 sp->s2io_entries[i].in_use =
7163 MSIX_REGISTERED_SUCCESS;
7164 }
7165 }
7166 if (!err) {
7167 pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
7168 DBG_PRINT(INFO_DBG,
7169 "MSI-X-TX entries enabled through alarm vector\n");
7170 }
7171 }
7172 if (sp->config.intr_type == INTA) {
7173 err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED,
7174 sp->name, dev);
7175 if (err) {
7176 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7177 dev->name);
7178 return -1;
7179 }
7180 }
7181 return 0;
7182 }
7183
7184 static void s2io_rem_isr(struct s2io_nic *sp)
7185 {
7186 if (sp->config.intr_type == MSI_X)
7187 remove_msix_isr(sp);
7188 else
7189 remove_inta_isr(sp);
7190 }
7191
7192 static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
7193 {
7194 int cnt = 0;
7195 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7196 register u64 val64 = 0;
7197 struct config_param *config;
7198 config = &sp->config;
7199
7200 if (!is_s2io_card_up(sp))
7201 return;
7202
7203 del_timer_sync(&sp->alarm_timer);
7204 /* If s2io_set_link task is executing, wait till it completes. */
7205 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
7206 msleep(50);
7207 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7208
7209 /* Disable napi */
7210 if (sp->config.napi) {
7211 int off = 0;
7212 if (config->intr_type == MSI_X) {
7213 for (; off < sp->config.rx_ring_num; off++)
7214 napi_disable(&sp->mac_control.rings[off].napi);
7215 }
7216 else
7217 napi_disable(&sp->napi);
7218 }
7219
7220 /* disable Tx and Rx traffic on the NIC */
7221 if (do_io)
7222 stop_nic(sp);
7223
7224 s2io_rem_isr(sp);
7225
7226 /* stop the tx queue, indicate link down */
7227 s2io_link(sp, LINK_DOWN);
7228
7229 /* Check if the device is Quiescent and then Reset the NIC */
7230 while (do_io) {
7231 /* As per the HW requirement we need to replenish the
7232 * receive buffer to avoid the ring bump. Since there is
7233 * no intention of processing the Rx frame at this pointwe are
7234 * just settting the ownership bit of rxd in Each Rx
7235 * ring to HW and set the appropriate buffer size
7236 * based on the ring mode
7237 */
7238 rxd_owner_bit_reset(sp);
7239
7240 val64 = readq(&bar0->adapter_status);
7241 if (verify_xena_quiescence(sp)) {
7242 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7243 break;
7244 }
7245
7246 msleep(50);
7247 cnt++;
7248 if (cnt == 10) {
7249 DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7250 "adapter status reads 0x%llx\n",
7251 (unsigned long long)val64);
7252 break;
7253 }
7254 }
7255 if (do_io)
7256 s2io_reset(sp);
7257
7258 /* Free all Tx buffers */
7259 free_tx_buffers(sp);
7260
7261 /* Free all Rx buffers */
7262 free_rx_buffers(sp);
7263
7264 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7265 }
7266
7267 static void s2io_card_down(struct s2io_nic *sp)
7268 {
7269 do_s2io_card_down(sp, 1);
7270 }
7271
7272 static int s2io_card_up(struct s2io_nic *sp)
7273 {
7274 int i, ret = 0;
7275 struct config_param *config;
7276 struct mac_info *mac_control;
7277 struct net_device *dev = (struct net_device *)sp->dev;
7278 u16 interruptible;
7279
7280 /* Initialize the H/W I/O registers */
7281 ret = init_nic(sp);
7282 if (ret != 0) {
7283 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7284 dev->name);
7285 if (ret != -EIO)
7286 s2io_reset(sp);
7287 return ret;
7288 }
7289
7290 /*
7291 * Initializing the Rx buffers. For now we are considering only 1
7292 * Rx ring and initializing buffers into 30 Rx blocks
7293 */
7294 config = &sp->config;
7295 mac_control = &sp->mac_control;
7296
7297 for (i = 0; i < config->rx_ring_num; i++) {
7298 struct ring_info *ring = &mac_control->rings[i];
7299
7300 ring->mtu = dev->mtu;
7301 ring->lro = !!(dev->features & NETIF_F_LRO);
7302 ret = fill_rx_buffers(sp, ring, 1);
7303 if (ret) {
7304 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7305 dev->name);
7306 s2io_reset(sp);
7307 free_rx_buffers(sp);
7308 return -ENOMEM;
7309 }
7310 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7311 ring->rx_bufs_left);
7312 }
7313
7314 /* Initialise napi */
7315 if (config->napi) {
7316 if (config->intr_type == MSI_X) {
7317 for (i = 0; i < sp->config.rx_ring_num; i++)
7318 napi_enable(&sp->mac_control.rings[i].napi);
7319 } else {
7320 napi_enable(&sp->napi);
7321 }
7322 }
7323
7324 /* Maintain the state prior to the open */
7325 if (sp->promisc_flg)
7326 sp->promisc_flg = 0;
7327 if (sp->m_cast_flg) {
7328 sp->m_cast_flg = 0;
7329 sp->all_multi_pos = 0;
7330 }
7331
7332 /* Setting its receive mode */
7333 s2io_set_multicast(dev);
7334
7335 if (dev->features & NETIF_F_LRO) {
7336 /* Initialize max aggregatable pkts per session based on MTU */
7337 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7338 /* Check if we can use (if specified) user provided value */
7339 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7340 sp->lro_max_aggr_per_sess = lro_max_pkts;
7341 }
7342
7343 /* Enable Rx Traffic and interrupts on the NIC */
7344 if (start_nic(sp)) {
7345 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7346 s2io_reset(sp);
7347 free_rx_buffers(sp);
7348 return -ENODEV;
7349 }
7350
7351 /* Add interrupt service routine */
7352 if (s2io_add_isr(sp) != 0) {
7353 if (sp->config.intr_type == MSI_X)
7354 s2io_rem_isr(sp);
7355 s2io_reset(sp);
7356 free_rx_buffers(sp);
7357 return -ENODEV;
7358 }
7359
7360 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7361
7362 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7363
7364 /* Enable select interrupts */
7365 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7366 if (sp->config.intr_type != INTA) {
7367 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7368 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7369 } else {
7370 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7371 interruptible |= TX_PIC_INTR;
7372 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7373 }
7374
7375 return 0;
7376 }
7377
7378 /**
7379 * s2io_restart_nic - Resets the NIC.
7380 * @data : long pointer to the device private structure
7381 * Description:
7382 * This function is scheduled to be run by the s2io_tx_watchdog
7383 * function after 0.5 secs to reset the NIC. The idea is to reduce
7384 * the run time of the watch dog routine which is run holding a
7385 * spin lock.
7386 */
7387
7388 static void s2io_restart_nic(struct work_struct *work)
7389 {
7390 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7391 struct net_device *dev = sp->dev;
7392
7393 rtnl_lock();
7394
7395 if (!netif_running(dev))
7396 goto out_unlock;
7397
7398 s2io_card_down(sp);
7399 if (s2io_card_up(sp)) {
7400 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
7401 }
7402 s2io_wake_all_tx_queue(sp);
7403 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
7404 out_unlock:
7405 rtnl_unlock();
7406 }
7407
7408 /**
7409 * s2io_tx_watchdog - Watchdog for transmit side.
7410 * @dev : Pointer to net device structure
7411 * Description:
7412 * This function is triggered if the Tx Queue is stopped
7413 * for a pre-defined amount of time when the Interface is still up.
7414 * If the Interface is jammed in such a situation, the hardware is
7415 * reset (by s2io_close) and restarted again (by s2io_open) to
7416 * overcome any problem that might have been caused in the hardware.
7417 * Return value:
7418 * void
7419 */
7420
7421 static void s2io_tx_watchdog(struct net_device *dev)
7422 {
7423 struct s2io_nic *sp = netdev_priv(dev);
7424 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7425
7426 if (netif_carrier_ok(dev)) {
7427 swstats->watchdog_timer_cnt++;
7428 schedule_work(&sp->rst_timer_task);
7429 swstats->soft_reset_cnt++;
7430 }
7431 }
7432
7433 /**
7434 * rx_osm_handler - To perform some OS related operations on SKB.
7435 * @sp: private member of the device structure,pointer to s2io_nic structure.
7436 * @skb : the socket buffer pointer.
7437 * @len : length of the packet
7438 * @cksum : FCS checksum of the frame.
7439 * @ring_no : the ring from which this RxD was extracted.
7440 * Description:
7441 * This function is called by the Rx interrupt serivce routine to perform
7442 * some OS related operations on the SKB before passing it to the upper
7443 * layers. It mainly checks if the checksum is OK, if so adds it to the
7444 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7445 * to the upper layer. If the checksum is wrong, it increments the Rx
7446 * packet error count, frees the SKB and returns error.
7447 * Return value:
7448 * SUCCESS on success and -1 on failure.
7449 */
7450 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7451 {
7452 struct s2io_nic *sp = ring_data->nic;
7453 struct net_device *dev = (struct net_device *)ring_data->dev;
7454 struct sk_buff *skb = (struct sk_buff *)
7455 ((unsigned long)rxdp->Host_Control);
7456 int ring_no = ring_data->ring_no;
7457 u16 l3_csum, l4_csum;
7458 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7459 struct lro *uninitialized_var(lro);
7460 u8 err_mask;
7461 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7462
7463 skb->dev = dev;
7464
7465 if (err) {
7466 /* Check for parity error */
7467 if (err & 0x1)
7468 swstats->parity_err_cnt++;
7469
7470 err_mask = err >> 48;
7471 switch (err_mask) {
7472 case 1:
7473 swstats->rx_parity_err_cnt++;
7474 break;
7475
7476 case 2:
7477 swstats->rx_abort_cnt++;
7478 break;
7479
7480 case 3:
7481 swstats->rx_parity_abort_cnt++;
7482 break;
7483
7484 case 4:
7485 swstats->rx_rda_fail_cnt++;
7486 break;
7487
7488 case 5:
7489 swstats->rx_unkn_prot_cnt++;
7490 break;
7491
7492 case 6:
7493 swstats->rx_fcs_err_cnt++;
7494 break;
7495
7496 case 7:
7497 swstats->rx_buf_size_err_cnt++;
7498 break;
7499
7500 case 8:
7501 swstats->rx_rxd_corrupt_cnt++;
7502 break;
7503
7504 case 15:
7505 swstats->rx_unkn_err_cnt++;
7506 break;
7507 }
7508 /*
7509 * Drop the packet if bad transfer code. Exception being
7510 * 0x5, which could be due to unsupported IPv6 extension header.
7511 * In this case, we let stack handle the packet.
7512 * Note that in this case, since checksum will be incorrect,
7513 * stack will validate the same.
7514 */
7515 if (err_mask != 0x5) {
7516 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7517 dev->name, err_mask);
7518 dev->stats.rx_crc_errors++;
7519 swstats->mem_freed
7520 += skb->truesize;
7521 dev_kfree_skb(skb);
7522 ring_data->rx_bufs_left -= 1;
7523 rxdp->Host_Control = 0;
7524 return 0;
7525 }
7526 }
7527
7528 rxdp->Host_Control = 0;
7529 if (sp->rxd_mode == RXD_MODE_1) {
7530 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7531
7532 skb_put(skb, len);
7533 } else if (sp->rxd_mode == RXD_MODE_3B) {
7534 int get_block = ring_data->rx_curr_get_info.block_index;
7535 int get_off = ring_data->rx_curr_get_info.offset;
7536 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7537 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7538 unsigned char *buff = skb_push(skb, buf0_len);
7539
7540 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7541 memcpy(buff, ba->ba_0, buf0_len);
7542 skb_put(skb, buf2_len);
7543 }
7544
7545 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7546 ((!ring_data->lro) ||
7547 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7548 (sp->rx_csum)) {
7549 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7550 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7551 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7552 /*
7553 * NIC verifies if the Checksum of the received
7554 * frame is Ok or not and accordingly returns
7555 * a flag in the RxD.
7556 */
7557 skb->ip_summed = CHECKSUM_UNNECESSARY;
7558 if (ring_data->lro) {
7559 u32 tcp_len;
7560 u8 *tcp;
7561 int ret = 0;
7562
7563 ret = s2io_club_tcp_session(ring_data,
7564 skb->data, &tcp,
7565 &tcp_len, &lro,
7566 rxdp, sp);
7567 switch (ret) {
7568 case 3: /* Begin anew */
7569 lro->parent = skb;
7570 goto aggregate;
7571 case 1: /* Aggregate */
7572 lro_append_pkt(sp, lro, skb, tcp_len);
7573 goto aggregate;
7574 case 4: /* Flush session */
7575 lro_append_pkt(sp, lro, skb, tcp_len);
7576 queue_rx_frame(lro->parent,
7577 lro->vlan_tag);
7578 clear_lro_session(lro);
7579 swstats->flush_max_pkts++;
7580 goto aggregate;
7581 case 2: /* Flush both */
7582 lro->parent->data_len = lro->frags_len;
7583 swstats->sending_both++;
7584 queue_rx_frame(lro->parent,
7585 lro->vlan_tag);
7586 clear_lro_session(lro);
7587 goto send_up;
7588 case 0: /* sessions exceeded */
7589 case -1: /* non-TCP or not L2 aggregatable */
7590 case 5: /*
7591 * First pkt in session not
7592 * L3/L4 aggregatable
7593 */
7594 break;
7595 default:
7596 DBG_PRINT(ERR_DBG,
7597 "%s: Samadhana!!\n",
7598 __func__);
7599 BUG();
7600 }
7601 }
7602 } else {
7603 /*
7604 * Packet with erroneous checksum, let the
7605 * upper layers deal with it.
7606 */
7607 skb_checksum_none_assert(skb);
7608 }
7609 } else
7610 skb_checksum_none_assert(skb);
7611
7612 swstats->mem_freed += skb->truesize;
7613 send_up:
7614 skb_record_rx_queue(skb, ring_no);
7615 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7616 aggregate:
7617 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7618 return SUCCESS;
7619 }
7620
7621 /**
7622 * s2io_link - stops/starts the Tx queue.
7623 * @sp : private member of the device structure, which is a pointer to the
7624 * s2io_nic structure.
7625 * @link : inidicates whether link is UP/DOWN.
7626 * Description:
7627 * This function stops/starts the Tx queue depending on whether the link
7628 * status of the NIC is is down or up. This is called by the Alarm
7629 * interrupt handler whenever a link change interrupt comes up.
7630 * Return value:
7631 * void.
7632 */
7633
7634 static void s2io_link(struct s2io_nic *sp, int link)
7635 {
7636 struct net_device *dev = (struct net_device *)sp->dev;
7637 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7638
7639 if (link != sp->last_link_state) {
7640 init_tti(sp, link);
7641 if (link == LINK_DOWN) {
7642 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7643 s2io_stop_all_tx_queue(sp);
7644 netif_carrier_off(dev);
7645 if (swstats->link_up_cnt)
7646 swstats->link_up_time =
7647 jiffies - sp->start_time;
7648 swstats->link_down_cnt++;
7649 } else {
7650 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7651 if (swstats->link_down_cnt)
7652 swstats->link_down_time =
7653 jiffies - sp->start_time;
7654 swstats->link_up_cnt++;
7655 netif_carrier_on(dev);
7656 s2io_wake_all_tx_queue(sp);
7657 }
7658 }
7659 sp->last_link_state = link;
7660 sp->start_time = jiffies;
7661 }
7662
7663 /**
7664 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7665 * @sp : private member of the device structure, which is a pointer to the
7666 * s2io_nic structure.
7667 * Description:
7668 * This function initializes a few of the PCI and PCI-X configuration registers
7669 * with recommended values.
7670 * Return value:
7671 * void
7672 */
7673
7674 static void s2io_init_pci(struct s2io_nic *sp)
7675 {
7676 u16 pci_cmd = 0, pcix_cmd = 0;
7677
7678 /* Enable Data Parity Error Recovery in PCI-X command register. */
7679 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7680 &(pcix_cmd));
7681 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7682 (pcix_cmd | 1));
7683 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7684 &(pcix_cmd));
7685
7686 /* Set the PErr Response bit in PCI command register. */
7687 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7688 pci_write_config_word(sp->pdev, PCI_COMMAND,
7689 (pci_cmd | PCI_COMMAND_PARITY));
7690 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7691 }
7692
7693 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7694 u8 *dev_multiq)
7695 {
7696 int i;
7697
7698 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
7699 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
7700 "(%d) not supported\n", tx_fifo_num);
7701
7702 if (tx_fifo_num < 1)
7703 tx_fifo_num = 1;
7704 else
7705 tx_fifo_num = MAX_TX_FIFOS;
7706
7707 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
7708 }
7709
7710 if (multiq)
7711 *dev_multiq = multiq;
7712
7713 if (tx_steering_type && (1 == tx_fifo_num)) {
7714 if (tx_steering_type != TX_DEFAULT_STEERING)
7715 DBG_PRINT(ERR_DBG,
7716 "Tx steering is not supported with "
7717 "one fifo. Disabling Tx steering.\n");
7718 tx_steering_type = NO_STEERING;
7719 }
7720
7721 if ((tx_steering_type < NO_STEERING) ||
7722 (tx_steering_type > TX_DEFAULT_STEERING)) {
7723 DBG_PRINT(ERR_DBG,
7724 "Requested transmit steering not supported\n");
7725 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
7726 tx_steering_type = NO_STEERING;
7727 }
7728
7729 if (rx_ring_num > MAX_RX_RINGS) {
7730 DBG_PRINT(ERR_DBG,
7731 "Requested number of rx rings not supported\n");
7732 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
7733 MAX_RX_RINGS);
7734 rx_ring_num = MAX_RX_RINGS;
7735 }
7736
7737 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7738 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
7739 "Defaulting to INTA\n");
7740 *dev_intr_type = INTA;
7741 }
7742
7743 if ((*dev_intr_type == MSI_X) &&
7744 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7745 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7746 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
7747 "Defaulting to INTA\n");
7748 *dev_intr_type = INTA;
7749 }
7750
7751 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7752 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7753 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
7754 rx_ring_mode = 1;
7755 }
7756
7757 for (i = 0; i < MAX_RX_RINGS; i++)
7758 if (rx_ring_sz[i] > MAX_RX_BLOCKS_PER_RING) {
7759 DBG_PRINT(ERR_DBG, "Requested rx ring size not "
7760 "supported\nDefaulting to %d\n",
7761 MAX_RX_BLOCKS_PER_RING);
7762 rx_ring_sz[i] = MAX_RX_BLOCKS_PER_RING;
7763 }
7764
7765 return SUCCESS;
7766 }
7767
7768 /**
7769 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7770 * or Traffic class respectively.
7771 * @nic: device private variable
7772 * Description: The function configures the receive steering to
7773 * desired receive ring.
7774 * Return Value: SUCCESS on success and
7775 * '-1' on failure (endian settings incorrect).
7776 */
7777 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7778 {
7779 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7780 register u64 val64 = 0;
7781
7782 if (ds_codepoint > 63)
7783 return FAILURE;
7784
7785 val64 = RTS_DS_MEM_DATA(ring);
7786 writeq(val64, &bar0->rts_ds_mem_data);
7787
7788 val64 = RTS_DS_MEM_CTRL_WE |
7789 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7790 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7791
7792 writeq(val64, &bar0->rts_ds_mem_ctrl);
7793
7794 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7795 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7796 S2IO_BIT_RESET);
7797 }
7798
7799 static const struct net_device_ops s2io_netdev_ops = {
7800 .ndo_open = s2io_open,
7801 .ndo_stop = s2io_close,
7802 .ndo_get_stats = s2io_get_stats,
7803 .ndo_start_xmit = s2io_xmit,
7804 .ndo_validate_addr = eth_validate_addr,
7805 .ndo_set_multicast_list = s2io_set_multicast,
7806 .ndo_do_ioctl = s2io_ioctl,
7807 .ndo_set_mac_address = s2io_set_mac_addr,
7808 .ndo_change_mtu = s2io_change_mtu,
7809 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7810 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7811 .ndo_tx_timeout = s2io_tx_watchdog,
7812 #ifdef CONFIG_NET_POLL_CONTROLLER
7813 .ndo_poll_controller = s2io_netpoll,
7814 #endif
7815 };
7816
7817 /**
7818 * s2io_init_nic - Initialization of the adapter .
7819 * @pdev : structure containing the PCI related information of the device.
7820 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7821 * Description:
7822 * The function initializes an adapter identified by the pci_dec structure.
7823 * All OS related initialization including memory and device structure and
7824 * initlaization of the device private variable is done. Also the swapper
7825 * control register is initialized to enable read and write into the I/O
7826 * registers of the device.
7827 * Return value:
7828 * returns 0 on success and negative on failure.
7829 */
7830
7831 static int __devinit
7832 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7833 {
7834 struct s2io_nic *sp;
7835 struct net_device *dev;
7836 int i, j, ret;
7837 int dma_flag = false;
7838 u32 mac_up, mac_down;
7839 u64 val64 = 0, tmp64 = 0;
7840 struct XENA_dev_config __iomem *bar0 = NULL;
7841 u16 subid;
7842 struct config_param *config;
7843 struct mac_info *mac_control;
7844 int mode;
7845 u8 dev_intr_type = intr_type;
7846 u8 dev_multiq = 0;
7847
7848 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7849 if (ret)
7850 return ret;
7851
7852 ret = pci_enable_device(pdev);
7853 if (ret) {
7854 DBG_PRINT(ERR_DBG,
7855 "%s: pci_enable_device failed\n", __func__);
7856 return ret;
7857 }
7858
7859 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
7860 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
7861 dma_flag = true;
7862 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7863 DBG_PRINT(ERR_DBG,
7864 "Unable to obtain 64bit DMA "
7865 "for consistent allocations\n");
7866 pci_disable_device(pdev);
7867 return -ENOMEM;
7868 }
7869 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
7870 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
7871 } else {
7872 pci_disable_device(pdev);
7873 return -ENOMEM;
7874 }
7875 ret = pci_request_regions(pdev, s2io_driver_name);
7876 if (ret) {
7877 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
7878 __func__, ret);
7879 pci_disable_device(pdev);
7880 return -ENODEV;
7881 }
7882 if (dev_multiq)
7883 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7884 else
7885 dev = alloc_etherdev(sizeof(struct s2io_nic));
7886 if (dev == NULL) {
7887 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7888 pci_disable_device(pdev);
7889 pci_release_regions(pdev);
7890 return -ENODEV;
7891 }
7892
7893 pci_set_master(pdev);
7894 pci_set_drvdata(pdev, dev);
7895 SET_NETDEV_DEV(dev, &pdev->dev);
7896
7897 /* Private member variable initialized to s2io NIC structure */
7898 sp = netdev_priv(dev);
7899 sp->dev = dev;
7900 sp->pdev = pdev;
7901 sp->high_dma_flag = dma_flag;
7902 sp->device_enabled_once = false;
7903 if (rx_ring_mode == 1)
7904 sp->rxd_mode = RXD_MODE_1;
7905 if (rx_ring_mode == 2)
7906 sp->rxd_mode = RXD_MODE_3B;
7907
7908 sp->config.intr_type = dev_intr_type;
7909
7910 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7911 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7912 sp->device_type = XFRAME_II_DEVICE;
7913 else
7914 sp->device_type = XFRAME_I_DEVICE;
7915
7916
7917 /* Initialize some PCI/PCI-X fields of the NIC. */
7918 s2io_init_pci(sp);
7919
7920 /*
7921 * Setting the device configuration parameters.
7922 * Most of these parameters can be specified by the user during
7923 * module insertion as they are module loadable parameters. If
7924 * these parameters are not not specified during load time, they
7925 * are initialized with default values.
7926 */
7927 config = &sp->config;
7928 mac_control = &sp->mac_control;
7929
7930 config->napi = napi;
7931 config->tx_steering_type = tx_steering_type;
7932
7933 /* Tx side parameters. */
7934 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7935 config->tx_fifo_num = MAX_TX_FIFOS;
7936 else
7937 config->tx_fifo_num = tx_fifo_num;
7938
7939 /* Initialize the fifos used for tx steering */
7940 if (config->tx_fifo_num < 5) {
7941 if (config->tx_fifo_num == 1)
7942 sp->total_tcp_fifos = 1;
7943 else
7944 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7945 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7946 sp->total_udp_fifos = 1;
7947 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7948 } else {
7949 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7950 FIFO_OTHER_MAX_NUM);
7951 sp->udp_fifo_idx = sp->total_tcp_fifos;
7952 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7953 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7954 }
7955
7956 config->multiq = dev_multiq;
7957 for (i = 0; i < config->tx_fifo_num; i++) {
7958 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7959
7960 tx_cfg->fifo_len = tx_fifo_len[i];
7961 tx_cfg->fifo_priority = i;
7962 }
7963
7964 /* mapping the QoS priority to the configured fifos */
7965 for (i = 0; i < MAX_TX_FIFOS; i++)
7966 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7967
7968 /* map the hashing selector table to the configured fifos */
7969 for (i = 0; i < config->tx_fifo_num; i++)
7970 sp->fifo_selector[i] = fifo_selector[i];
7971
7972
7973 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7974 for (i = 0; i < config->tx_fifo_num; i++) {
7975 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7976
7977 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7978 if (tx_cfg->fifo_len < 65) {
7979 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7980 break;
7981 }
7982 }
7983 /* + 2 because one Txd for skb->data and one Txd for UFO */
7984 config->max_txds = MAX_SKB_FRAGS + 2;
7985
7986 /* Rx side parameters. */
7987 config->rx_ring_num = rx_ring_num;
7988 for (i = 0; i < config->rx_ring_num; i++) {
7989 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7990 struct ring_info *ring = &mac_control->rings[i];
7991
7992 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7993 rx_cfg->ring_priority = i;
7994 ring->rx_bufs_left = 0;
7995 ring->rxd_mode = sp->rxd_mode;
7996 ring->rxd_count = rxd_count[sp->rxd_mode];
7997 ring->pdev = sp->pdev;
7998 ring->dev = sp->dev;
7999 }
8000
8001 for (i = 0; i < rx_ring_num; i++) {
8002 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
8003
8004 rx_cfg->ring_org = RING_ORG_BUFF1;
8005 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
8006 }
8007
8008 /* Setting Mac Control parameters */
8009 mac_control->rmac_pause_time = rmac_pause_time;
8010 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
8011 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
8012
8013
8014 /* initialize the shared memory used by the NIC and the host */
8015 if (init_shared_mem(sp)) {
8016 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
8017 ret = -ENOMEM;
8018 goto mem_alloc_failed;
8019 }
8020
8021 sp->bar0 = pci_ioremap_bar(pdev, 0);
8022 if (!sp->bar0) {
8023 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
8024 dev->name);
8025 ret = -ENOMEM;
8026 goto bar0_remap_failed;
8027 }
8028
8029 sp->bar1 = pci_ioremap_bar(pdev, 2);
8030 if (!sp->bar1) {
8031 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
8032 dev->name);
8033 ret = -ENOMEM;
8034 goto bar1_remap_failed;
8035 }
8036
8037 dev->irq = pdev->irq;
8038 dev->base_addr = (unsigned long)sp->bar0;
8039
8040 /* Initializing the BAR1 address as the start of the FIFO pointer. */
8041 for (j = 0; j < MAX_TX_FIFOS; j++) {
8042 mac_control->tx_FIFO_start[j] =
8043 (struct TxFIFO_element __iomem *)
8044 (sp->bar1 + (j * 0x00020000));
8045 }
8046
8047 /* Driver entry points */
8048 dev->netdev_ops = &s2io_netdev_ops;
8049 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
8050 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8051 dev->features |= NETIF_F_LRO;
8052 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
8053 if (sp->high_dma_flag == true)
8054 dev->features |= NETIF_F_HIGHDMA;
8055 dev->features |= NETIF_F_TSO;
8056 dev->features |= NETIF_F_TSO6;
8057 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
8058 dev->features |= NETIF_F_UFO;
8059 dev->features |= NETIF_F_HW_CSUM;
8060 }
8061 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
8062 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
8063 INIT_WORK(&sp->set_link_task, s2io_set_link);
8064
8065 pci_save_state(sp->pdev);
8066
8067 /* Setting swapper control on the NIC, for proper reset operation */
8068 if (s2io_set_swapper(sp)) {
8069 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
8070 dev->name);
8071 ret = -EAGAIN;
8072 goto set_swap_failed;
8073 }
8074
8075 /* Verify if the Herc works on the slot its placed into */
8076 if (sp->device_type & XFRAME_II_DEVICE) {
8077 mode = s2io_verify_pci_mode(sp);
8078 if (mode < 0) {
8079 DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
8080 __func__);
8081 ret = -EBADSLT;
8082 goto set_swap_failed;
8083 }
8084 }
8085
8086 if (sp->config.intr_type == MSI_X) {
8087 sp->num_entries = config->rx_ring_num + 1;
8088 ret = s2io_enable_msi_x(sp);
8089
8090 if (!ret) {
8091 ret = s2io_test_msi(sp);
8092 /* rollback MSI-X, will re-enable during add_isr() */
8093 remove_msix_isr(sp);
8094 }
8095 if (ret) {
8096
8097 DBG_PRINT(ERR_DBG,
8098 "MSI-X requested but failed to enable\n");
8099 sp->config.intr_type = INTA;
8100 }
8101 }
8102
8103 if (config->intr_type == MSI_X) {
8104 for (i = 0; i < config->rx_ring_num ; i++) {
8105 struct ring_info *ring = &mac_control->rings[i];
8106
8107 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8108 }
8109 } else {
8110 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8111 }
8112
8113 /* Not needed for Herc */
8114 if (sp->device_type & XFRAME_I_DEVICE) {
8115 /*
8116 * Fix for all "FFs" MAC address problems observed on
8117 * Alpha platforms
8118 */
8119 fix_mac_address(sp);
8120 s2io_reset(sp);
8121 }
8122
8123 /*
8124 * MAC address initialization.
8125 * For now only one mac address will be read and used.
8126 */
8127 bar0 = sp->bar0;
8128 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
8129 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
8130 writeq(val64, &bar0->rmac_addr_cmd_mem);
8131 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
8132 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8133 S2IO_BIT_RESET);
8134 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8135 mac_down = (u32)tmp64;
8136 mac_up = (u32) (tmp64 >> 32);
8137
8138 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8139 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8140 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8141 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8142 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8143 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8144
8145 /* Set the factory defined MAC address initially */
8146 dev->addr_len = ETH_ALEN;
8147 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
8148 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
8149
8150 /* initialize number of multicast & unicast MAC entries variables */
8151 if (sp->device_type == XFRAME_I_DEVICE) {
8152 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8153 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8154 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8155 } else if (sp->device_type == XFRAME_II_DEVICE) {
8156 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8157 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8158 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8159 }
8160
8161 /* store mac addresses from CAM to s2io_nic structure */
8162 do_s2io_store_unicast_mc(sp);
8163
8164 /* Configure MSIX vector for number of rings configured plus one */
8165 if ((sp->device_type == XFRAME_II_DEVICE) &&
8166 (config->intr_type == MSI_X))
8167 sp->num_entries = config->rx_ring_num + 1;
8168
8169 /* Store the values of the MSIX table in the s2io_nic structure */
8170 store_xmsi_data(sp);
8171 /* reset Nic and bring it to known state */
8172 s2io_reset(sp);
8173
8174 /*
8175 * Initialize link state flags
8176 * and the card state parameter
8177 */
8178 sp->state = 0;
8179
8180 /* Initialize spinlocks */
8181 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8182 struct fifo_info *fifo = &mac_control->fifos[i];
8183
8184 spin_lock_init(&fifo->tx_lock);
8185 }
8186
8187 /*
8188 * SXE-002: Configure link and activity LED to init state
8189 * on driver load.
8190 */
8191 subid = sp->pdev->subsystem_device;
8192 if ((subid & 0xFF) >= 0x07) {
8193 val64 = readq(&bar0->gpio_control);
8194 val64 |= 0x0000800000000000ULL;
8195 writeq(val64, &bar0->gpio_control);
8196 val64 = 0x0411040400000000ULL;
8197 writeq(val64, (void __iomem *)bar0 + 0x2700);
8198 val64 = readq(&bar0->gpio_control);
8199 }
8200
8201 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8202
8203 if (register_netdev(dev)) {
8204 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8205 ret = -ENODEV;
8206 goto register_failed;
8207 }
8208 s2io_vpd_read(sp);
8209 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2010 Exar Corp.\n");
8210 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
8211 sp->product_name, pdev->revision);
8212 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8213 s2io_driver_version);
8214 DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8215 DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
8216 if (sp->device_type & XFRAME_II_DEVICE) {
8217 mode = s2io_print_pci_mode(sp);
8218 if (mode < 0) {
8219 ret = -EBADSLT;
8220 unregister_netdev(dev);
8221 goto set_swap_failed;
8222 }
8223 }
8224 switch (sp->rxd_mode) {
8225 case RXD_MODE_1:
8226 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8227 dev->name);
8228 break;
8229 case RXD_MODE_3B:
8230 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8231 dev->name);
8232 break;
8233 }
8234
8235 switch (sp->config.napi) {
8236 case 0:
8237 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8238 break;
8239 case 1:
8240 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8241 break;
8242 }
8243
8244 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8245 sp->config.tx_fifo_num);
8246
8247 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8248 sp->config.rx_ring_num);
8249
8250 switch (sp->config.intr_type) {
8251 case INTA:
8252 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8253 break;
8254 case MSI_X:
8255 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8256 break;
8257 }
8258 if (sp->config.multiq) {
8259 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8260 struct fifo_info *fifo = &mac_control->fifos[i];
8261
8262 fifo->multiq = config->multiq;
8263 }
8264 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8265 dev->name);
8266 } else
8267 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8268 dev->name);
8269
8270 switch (sp->config.tx_steering_type) {
8271 case NO_STEERING:
8272 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8273 dev->name);
8274 break;
8275 case TX_PRIORITY_STEERING:
8276 DBG_PRINT(ERR_DBG,
8277 "%s: Priority steering enabled for transmit\n",
8278 dev->name);
8279 break;
8280 case TX_DEFAULT_STEERING:
8281 DBG_PRINT(ERR_DBG,
8282 "%s: Default steering enabled for transmit\n",
8283 dev->name);
8284 }
8285
8286 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8287 dev->name);
8288 if (ufo)
8289 DBG_PRINT(ERR_DBG,
8290 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8291 dev->name);
8292 /* Initialize device name */
8293 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
8294
8295 if (vlan_tag_strip)
8296 sp->vlan_strip_flag = 1;
8297 else
8298 sp->vlan_strip_flag = 0;
8299
8300 /*
8301 * Make Link state as off at this point, when the Link change
8302 * interrupt comes the state will be automatically changed to
8303 * the right state.
8304 */
8305 netif_carrier_off(dev);
8306
8307 return 0;
8308
8309 register_failed:
8310 set_swap_failed:
8311 iounmap(sp->bar1);
8312 bar1_remap_failed:
8313 iounmap(sp->bar0);
8314 bar0_remap_failed:
8315 mem_alloc_failed:
8316 free_shared_mem(sp);
8317 pci_disable_device(pdev);
8318 pci_release_regions(pdev);
8319 pci_set_drvdata(pdev, NULL);
8320 free_netdev(dev);
8321
8322 return ret;
8323 }
8324
8325 /**
8326 * s2io_rem_nic - Free the PCI device
8327 * @pdev: structure containing the PCI related information of the device.
8328 * Description: This function is called by the Pci subsystem to release a
8329 * PCI device and free up all resource held up by the device. This could
8330 * be in response to a Hot plug event or when the driver is to be removed
8331 * from memory.
8332 */
8333
8334 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8335 {
8336 struct net_device *dev = pci_get_drvdata(pdev);
8337 struct s2io_nic *sp;
8338
8339 if (dev == NULL) {
8340 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8341 return;
8342 }
8343
8344 sp = netdev_priv(dev);
8345
8346 cancel_work_sync(&sp->rst_timer_task);
8347 cancel_work_sync(&sp->set_link_task);
8348
8349 unregister_netdev(dev);
8350
8351 free_shared_mem(sp);
8352 iounmap(sp->bar0);
8353 iounmap(sp->bar1);
8354 pci_release_regions(pdev);
8355 pci_set_drvdata(pdev, NULL);
8356 free_netdev(dev);
8357 pci_disable_device(pdev);
8358 }
8359
8360 /**
8361 * s2io_starter - Entry point for the driver
8362 * Description: This function is the entry point for the driver. It verifies
8363 * the module loadable parameters and initializes PCI configuration space.
8364 */
8365
8366 static int __init s2io_starter(void)
8367 {
8368 return pci_register_driver(&s2io_driver);
8369 }
8370
8371 /**
8372 * s2io_closer - Cleanup routine for the driver
8373 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8374 */
8375
8376 static __exit void s2io_closer(void)
8377 {
8378 pci_unregister_driver(&s2io_driver);
8379 DBG_PRINT(INIT_DBG, "cleanup done\n");
8380 }
8381
8382 module_init(s2io_starter);
8383 module_exit(s2io_closer);
8384
8385 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8386 struct tcphdr **tcp, struct RxD_t *rxdp,
8387 struct s2io_nic *sp)
8388 {
8389 int ip_off;
8390 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8391
8392 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8393 DBG_PRINT(INIT_DBG,
8394 "%s: Non-TCP frames not supported for LRO\n",
8395 __func__);
8396 return -1;
8397 }
8398
8399 /* Checking for DIX type or DIX type with VLAN */
8400 if ((l2_type == 0) || (l2_type == 4)) {
8401 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8402 /*
8403 * If vlan stripping is disabled and the frame is VLAN tagged,
8404 * shift the offset by the VLAN header size bytes.
8405 */
8406 if ((!sp->vlan_strip_flag) &&
8407 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8408 ip_off += HEADER_VLAN_SIZE;
8409 } else {
8410 /* LLC, SNAP etc are considered non-mergeable */
8411 return -1;
8412 }
8413
8414 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8415 ip_len = (u8)((*ip)->ihl);
8416 ip_len <<= 2;
8417 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8418
8419 return 0;
8420 }
8421
8422 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8423 struct tcphdr *tcp)
8424 {
8425 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8426 if ((lro->iph->saddr != ip->saddr) ||
8427 (lro->iph->daddr != ip->daddr) ||
8428 (lro->tcph->source != tcp->source) ||
8429 (lro->tcph->dest != tcp->dest))
8430 return -1;
8431 return 0;
8432 }
8433
8434 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8435 {
8436 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
8437 }
8438
8439 static void initiate_new_session(struct lro *lro, u8 *l2h,
8440 struct iphdr *ip, struct tcphdr *tcp,
8441 u32 tcp_pyld_len, u16 vlan_tag)
8442 {
8443 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8444 lro->l2h = l2h;
8445 lro->iph = ip;
8446 lro->tcph = tcp;
8447 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8448 lro->tcp_ack = tcp->ack_seq;
8449 lro->sg_num = 1;
8450 lro->total_len = ntohs(ip->tot_len);
8451 lro->frags_len = 0;
8452 lro->vlan_tag = vlan_tag;
8453 /*
8454 * Check if we saw TCP timestamp.
8455 * Other consistency checks have already been done.
8456 */
8457 if (tcp->doff == 8) {
8458 __be32 *ptr;
8459 ptr = (__be32 *)(tcp+1);
8460 lro->saw_ts = 1;
8461 lro->cur_tsval = ntohl(*(ptr+1));
8462 lro->cur_tsecr = *(ptr+2);
8463 }
8464 lro->in_use = 1;
8465 }
8466
8467 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8468 {
8469 struct iphdr *ip = lro->iph;
8470 struct tcphdr *tcp = lro->tcph;
8471 __sum16 nchk;
8472 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8473
8474 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8475
8476 /* Update L3 header */
8477 ip->tot_len = htons(lro->total_len);
8478 ip->check = 0;
8479 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8480 ip->check = nchk;
8481
8482 /* Update L4 header */
8483 tcp->ack_seq = lro->tcp_ack;
8484 tcp->window = lro->window;
8485
8486 /* Update tsecr field if this session has timestamps enabled */
8487 if (lro->saw_ts) {
8488 __be32 *ptr = (__be32 *)(tcp + 1);
8489 *(ptr+2) = lro->cur_tsecr;
8490 }
8491
8492 /* Update counters required for calculation of
8493 * average no. of packets aggregated.
8494 */
8495 swstats->sum_avg_pkts_aggregated += lro->sg_num;
8496 swstats->num_aggregations++;
8497 }
8498
8499 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8500 struct tcphdr *tcp, u32 l4_pyld)
8501 {
8502 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8503 lro->total_len += l4_pyld;
8504 lro->frags_len += l4_pyld;
8505 lro->tcp_next_seq += l4_pyld;
8506 lro->sg_num++;
8507
8508 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8509 lro->tcp_ack = tcp->ack_seq;
8510 lro->window = tcp->window;
8511
8512 if (lro->saw_ts) {
8513 __be32 *ptr;
8514 /* Update tsecr and tsval from this packet */
8515 ptr = (__be32 *)(tcp+1);
8516 lro->cur_tsval = ntohl(*(ptr+1));
8517 lro->cur_tsecr = *(ptr + 2);
8518 }
8519 }
8520
8521 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8522 struct tcphdr *tcp, u32 tcp_pyld_len)
8523 {
8524 u8 *ptr;
8525
8526 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8527
8528 if (!tcp_pyld_len) {
8529 /* Runt frame or a pure ack */
8530 return -1;
8531 }
8532
8533 if (ip->ihl != 5) /* IP has options */
8534 return -1;
8535
8536 /* If we see CE codepoint in IP header, packet is not mergeable */
8537 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8538 return -1;
8539
8540 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8541 if (tcp->urg || tcp->psh || tcp->rst ||
8542 tcp->syn || tcp->fin ||
8543 tcp->ece || tcp->cwr || !tcp->ack) {
8544 /*
8545 * Currently recognize only the ack control word and
8546 * any other control field being set would result in
8547 * flushing the LRO session
8548 */
8549 return -1;
8550 }
8551
8552 /*
8553 * Allow only one TCP timestamp option. Don't aggregate if
8554 * any other options are detected.
8555 */
8556 if (tcp->doff != 5 && tcp->doff != 8)
8557 return -1;
8558
8559 if (tcp->doff == 8) {
8560 ptr = (u8 *)(tcp + 1);
8561 while (*ptr == TCPOPT_NOP)
8562 ptr++;
8563 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8564 return -1;
8565
8566 /* Ensure timestamp value increases monotonically */
8567 if (l_lro)
8568 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8569 return -1;
8570
8571 /* timestamp echo reply should be non-zero */
8572 if (*((__be32 *)(ptr+6)) == 0)
8573 return -1;
8574 }
8575
8576 return 0;
8577 }
8578
8579 static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8580 u8 **tcp, u32 *tcp_len, struct lro **lro,
8581 struct RxD_t *rxdp, struct s2io_nic *sp)
8582 {
8583 struct iphdr *ip;
8584 struct tcphdr *tcph;
8585 int ret = 0, i;
8586 u16 vlan_tag = 0;
8587 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8588
8589 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8590 rxdp, sp);
8591 if (ret)
8592 return ret;
8593
8594 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8595
8596 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8597 tcph = (struct tcphdr *)*tcp;
8598 *tcp_len = get_l4_pyld_length(ip, tcph);
8599 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8600 struct lro *l_lro = &ring_data->lro0_n[i];
8601 if (l_lro->in_use) {
8602 if (check_for_socket_match(l_lro, ip, tcph))
8603 continue;
8604 /* Sock pair matched */
8605 *lro = l_lro;
8606
8607 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8608 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8609 "expected 0x%x, actual 0x%x\n",
8610 __func__,
8611 (*lro)->tcp_next_seq,
8612 ntohl(tcph->seq));
8613
8614 swstats->outof_sequence_pkts++;
8615 ret = 2;
8616 break;
8617 }
8618
8619 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8620 *tcp_len))
8621 ret = 1; /* Aggregate */
8622 else
8623 ret = 2; /* Flush both */
8624 break;
8625 }
8626 }
8627
8628 if (ret == 0) {
8629 /* Before searching for available LRO objects,
8630 * check if the pkt is L3/L4 aggregatable. If not
8631 * don't create new LRO session. Just send this
8632 * packet up.
8633 */
8634 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
8635 return 5;
8636
8637 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8638 struct lro *l_lro = &ring_data->lro0_n[i];
8639 if (!(l_lro->in_use)) {
8640 *lro = l_lro;
8641 ret = 3; /* Begin anew */
8642 break;
8643 }
8644 }
8645 }
8646
8647 if (ret == 0) { /* sessions exceeded */
8648 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
8649 __func__);
8650 *lro = NULL;
8651 return ret;
8652 }
8653
8654 switch (ret) {
8655 case 3:
8656 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8657 vlan_tag);
8658 break;
8659 case 2:
8660 update_L3L4_header(sp, *lro);
8661 break;
8662 case 1:
8663 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8664 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8665 update_L3L4_header(sp, *lro);
8666 ret = 4; /* Flush the LRO */
8667 }
8668 break;
8669 default:
8670 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
8671 break;
8672 }
8673
8674 return ret;
8675 }
8676
8677 static void clear_lro_session(struct lro *lro)
8678 {
8679 static u16 lro_struct_size = sizeof(struct lro);
8680
8681 memset(lro, 0, lro_struct_size);
8682 }
8683
8684 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8685 {
8686 struct net_device *dev = skb->dev;
8687 struct s2io_nic *sp = netdev_priv(dev);
8688
8689 skb->protocol = eth_type_trans(skb, dev);
8690 if (sp->vlgrp && vlan_tag && (sp->vlan_strip_flag)) {
8691 /* Queueing the vlan frame to the upper layer */
8692 if (sp->config.napi)
8693 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8694 else
8695 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8696 } else {
8697 if (sp->config.napi)
8698 netif_receive_skb(skb);
8699 else
8700 netif_rx(skb);
8701 }
8702 }
8703
8704 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8705 struct sk_buff *skb, u32 tcp_len)
8706 {
8707 struct sk_buff *first = lro->parent;
8708 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8709
8710 first->len += tcp_len;
8711 first->data_len = lro->frags_len;
8712 skb_pull(skb, (skb->len - tcp_len));
8713 if (skb_shinfo(first)->frag_list)
8714 lro->last_frag->next = skb;
8715 else
8716 skb_shinfo(first)->frag_list = skb;
8717 first->truesize += skb->truesize;
8718 lro->last_frag = skb;
8719 swstats->clubbed_frms_cnt++;
8720 }
8721
8722 /**
8723 * s2io_io_error_detected - called when PCI error is detected
8724 * @pdev: Pointer to PCI device
8725 * @state: The current pci connection state
8726 *
8727 * This function is called after a PCI bus error affecting
8728 * this device has been detected.
8729 */
8730 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8731 pci_channel_state_t state)
8732 {
8733 struct net_device *netdev = pci_get_drvdata(pdev);
8734 struct s2io_nic *sp = netdev_priv(netdev);
8735
8736 netif_device_detach(netdev);
8737
8738 if (state == pci_channel_io_perm_failure)
8739 return PCI_ERS_RESULT_DISCONNECT;
8740
8741 if (netif_running(netdev)) {
8742 /* Bring down the card, while avoiding PCI I/O */
8743 do_s2io_card_down(sp, 0);
8744 }
8745 pci_disable_device(pdev);
8746
8747 return PCI_ERS_RESULT_NEED_RESET;
8748 }
8749
8750 /**
8751 * s2io_io_slot_reset - called after the pci bus has been reset.
8752 * @pdev: Pointer to PCI device
8753 *
8754 * Restart the card from scratch, as if from a cold-boot.
8755 * At this point, the card has exprienced a hard reset,
8756 * followed by fixups by BIOS, and has its config space
8757 * set up identically to what it was at cold boot.
8758 */
8759 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8760 {
8761 struct net_device *netdev = pci_get_drvdata(pdev);
8762 struct s2io_nic *sp = netdev_priv(netdev);
8763
8764 if (pci_enable_device(pdev)) {
8765 pr_err("Cannot re-enable PCI device after reset.\n");
8766 return PCI_ERS_RESULT_DISCONNECT;
8767 }
8768
8769 pci_set_master(pdev);
8770 s2io_reset(sp);
8771
8772 return PCI_ERS_RESULT_RECOVERED;
8773 }
8774
8775 /**
8776 * s2io_io_resume - called when traffic can start flowing again.
8777 * @pdev: Pointer to PCI device
8778 *
8779 * This callback is called when the error recovery driver tells
8780 * us that its OK to resume normal operation.
8781 */
8782 static void s2io_io_resume(struct pci_dev *pdev)
8783 {
8784 struct net_device *netdev = pci_get_drvdata(pdev);
8785 struct s2io_nic *sp = netdev_priv(netdev);
8786
8787 if (netif_running(netdev)) {
8788 if (s2io_card_up(sp)) {
8789 pr_err("Can't bring device back up after reset.\n");
8790 return;
8791 }
8792
8793 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8794 s2io_card_down(sp);
8795 pr_err("Can't restore mac addr after reset.\n");
8796 return;
8797 }
8798 }
8799
8800 netif_device_attach(netdev);
8801 netif_tx_wake_all_queues(netdev);
8802 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree