drivers/net/wireless/ath9k/ath9k.h

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef ATH9K_H
  18 #define ATH9K_H
  19
  20 #include <linux/io.h>
  21
  22 #define ATHEROS_VENDOR_ID       0x168c
  23
  24 #define AR5416_DEVID_PCI        0x0023
  25 #define AR5416_DEVID_PCIE       0x0024
  26 #define AR9160_DEVID_PCI        0x0027
  27 #define AR9280_DEVID_PCI        0x0029
  28 #define AR9280_DEVID_PCIE       0x002a
  29
  30 #define AR5416_AR9100_DEVID     0x000b
  31
  32 #define AR_SUBVENDOR_ID_NOG     0x0e11
  33 #define AR_SUBVENDOR_ID_NEW_A   0x7065
  34
  35 #define ATH9K_TXERR_XRETRY         0x01
  36 #define ATH9K_TXERR_FILT           0x02
  37 #define ATH9K_TXERR_FIFO           0x04
  38 #define ATH9K_TXERR_XTXOP          0x08
  39 #define ATH9K_TXERR_TIMER_EXPIRED  0x10
  40
  41 #define ATH9K_TX_BA                0x01
  42 #define ATH9K_TX_PWRMGMT           0x02
  43 #define ATH9K_TX_DESC_CFG_ERR      0x04
  44 #define ATH9K_TX_DATA_UNDERRUN     0x08
  45 #define ATH9K_TX_DELIM_UNDERRUN    0x10
  46 #define ATH9K_TX_SW_ABORTED        0x40
  47 #define ATH9K_TX_SW_FILTERED       0x80
  48
  49 #define NBBY    8
  50
  51 struct ath_tx_status {
  52         u32 ts_tstamp;
  53         u16 ts_seqnum;
  54         u8 ts_status;
  55         u8 ts_ratecode;
  56         u8 ts_rateindex;
  57         int8_t ts_rssi;
  58         u8 ts_shortretry;
  59         u8 ts_longretry;
  60         u8 ts_virtcol;
  61         u8 ts_antenna;
  62         u8 ts_flags;
  63         int8_t ts_rssi_ctl0;
  64         int8_t ts_rssi_ctl1;
  65         int8_t ts_rssi_ctl2;
  66         int8_t ts_rssi_ext0;
  67         int8_t ts_rssi_ext1;
  68         int8_t ts_rssi_ext2;
  69         u8 pad[3];
  70         u32 ba_low;
  71         u32 ba_high;
  72         u32 evm0;
  73         u32 evm1;
  74         u32 evm2;
  75 };
  76
  77 struct ath_rx_status {
  78         u32 rs_tstamp;
  79         u16 rs_datalen;
  80         u8 rs_status;
  81         u8 rs_phyerr;
  82         int8_t rs_rssi;
  83         u8 rs_keyix;
  84         u8 rs_rate;
  85         u8 rs_antenna;
  86         u8 rs_more;
  87         int8_t rs_rssi_ctl0;
  88         int8_t rs_rssi_ctl1;
  89         int8_t rs_rssi_ctl2;
  90         int8_t rs_rssi_ext0;
  91         int8_t rs_rssi_ext1;
  92         int8_t rs_rssi_ext2;
  93         u8 rs_isaggr;
  94         u8 rs_moreaggr;
  95         u8 rs_num_delims;
  96         u8 rs_flags;
  97         u32 evm0;
  98         u32 evm1;
  99         u32 evm2;
 100 };
 101
 102 #define ATH9K_RXERR_CRC           0x01
 103 #define ATH9K_RXERR_PHY           0x02
 104 #define ATH9K_RXERR_FIFO          0x04
 105 #define ATH9K_RXERR_DECRYPT       0x08
 106 #define ATH9K_RXERR_MIC           0x10
 107
 108 #define ATH9K_RX_MORE             0x01
 109 #define ATH9K_RX_MORE_AGGR        0x02
 110 #define ATH9K_RX_GI               0x04
 111 #define ATH9K_RX_2040             0x08
 112 #define ATH9K_RX_DELIM_CRC_PRE    0x10
 113 #define ATH9K_RX_DELIM_CRC_POST   0x20
 114 #define ATH9K_RX_DECRYPT_BUSY     0x40
 115
 116 #define ATH9K_RXKEYIX_INVALID   ((u8)-1)
 117 #define ATH9K_TXKEYIX_INVALID   ((u32)-1)
 118
 119 struct ath_desc {
 120         u32 ds_link;
 121         u32 ds_data;
 122         u32 ds_ctl0;
 123         u32 ds_ctl1;
 124         u32 ds_hw[20];
 125         union {
 126                 struct ath_tx_status tx;
 127                 struct ath_rx_status rx;
 128                 void *stats;
 129         } ds_us;
 130         void *ds_vdata;
 131 } __packed;
 132
 133 #define ds_txstat       ds_us.tx
 134 #define ds_rxstat       ds_us.rx
 135 #define ds_stat         ds_us.stats
 136
 137 #define ATH9K_TXDESC_CLRDMASK           0x0001
 138 #define ATH9K_TXDESC_NOACK              0x0002
 139 #define ATH9K_TXDESC_RTSENA             0x0004
 140 #define ATH9K_TXDESC_CTSENA             0x0008
 141 #define ATH9K_TXDESC_INTREQ             0x0010
 142 #define ATH9K_TXDESC_VEOL               0x0020
 143 #define ATH9K_TXDESC_EXT_ONLY           0x0040
 144 #define ATH9K_TXDESC_EXT_AND_CTL        0x0080
 145 #define ATH9K_TXDESC_VMF                0x0100
 146 #define ATH9K_TXDESC_FRAG_IS_ON         0x0200
 147
 148 #define ATH9K_RXDESC_INTREQ             0x0020
 149
 150 enum ath9k_hw_caps {
 151         ATH9K_HW_CAP_CHAN_SPREAD                = BIT(0),
 152         ATH9K_HW_CAP_MIC_AESCCM                 = BIT(1),
 153         ATH9K_HW_CAP_MIC_CKIP                   = BIT(2),
 154         ATH9K_HW_CAP_MIC_TKIP                   = BIT(3),
 155         ATH9K_HW_CAP_CIPHER_AESCCM              = BIT(4),
 156         ATH9K_HW_CAP_CIPHER_CKIP                = BIT(5),
 157         ATH9K_HW_CAP_CIPHER_TKIP                = BIT(6),
 158         ATH9K_HW_CAP_VEOL                       = BIT(7),
 159         ATH9K_HW_CAP_BSSIDMASK                  = BIT(8),
 160         ATH9K_HW_CAP_MCAST_KEYSEARCH            = BIT(9),
 161         ATH9K_HW_CAP_CHAN_HALFRATE              = BIT(10),
 162         ATH9K_HW_CAP_CHAN_QUARTERRATE           = BIT(11),
 163         ATH9K_HW_CAP_HT                         = BIT(12),
 164         ATH9K_HW_CAP_GTT                        = BIT(13),
 165         ATH9K_HW_CAP_FASTCC                     = BIT(14),
 166         ATH9K_HW_CAP_RFSILENT                   = BIT(15),
 167         ATH9K_HW_CAP_WOW                        = BIT(16),
 168         ATH9K_HW_CAP_CST                        = BIT(17),
 169         ATH9K_HW_CAP_ENHANCEDPM                 = BIT(18),
 170         ATH9K_HW_CAP_AUTOSLEEP                  = BIT(19),
 171         ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(20),
 172         ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT     = BIT(21),
 173 };
 174
 175 enum ath9k_capability_type {
 176         ATH9K_CAP_CIPHER = 0,
 177         ATH9K_CAP_TKIP_MIC,
 178         ATH9K_CAP_TKIP_SPLIT,
 179         ATH9K_CAP_PHYCOUNTERS,
 180         ATH9K_CAP_DIVERSITY,
 181         ATH9K_CAP_TXPOW,
 182         ATH9K_CAP_PHYDIAG,
 183         ATH9K_CAP_MCAST_KEYSRCH,
 184         ATH9K_CAP_TSF_ADJUST,
 185         ATH9K_CAP_WME_TKIPMIC,
 186         ATH9K_CAP_RFSILENT,
 187         ATH9K_CAP_ANT_CFG_2GHZ,
 188         ATH9K_CAP_ANT_CFG_5GHZ
 189 };
 190
 191 struct ath9k_hw_capabilities {
 192         u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
 193         u32 wireless_modes;
 194         u16 total_queues;
 195         u16 keycache_size;
 196         u16 low_5ghz_chan, high_5ghz_chan;
 197         u16 low_2ghz_chan, high_2ghz_chan;
 198         u16 num_mr_retries;
 199         u16 rts_aggr_limit;
 200         u8 tx_chainmask;
 201         u8 rx_chainmask;
 202         u16 tx_triglevel_max;
 203         u16 reg_cap;
 204         u8 num_gpio_pins;
 205         u8 num_antcfg_2ghz;
 206         u8 num_antcfg_5ghz;
 207 };
 208
 209 struct ath9k_ops_config {
 210         int dma_beacon_response_time;
 211         int sw_beacon_response_time;
 212         int additional_swba_backoff;
 213         int ack_6mb;
 214         int cwm_ignore_extcca;
 215         u8 pcie_powersave_enable;
 216         u8 pcie_l1skp_enable;
 217         u8 pcie_clock_req;
 218         u32 pcie_waen;
 219         int pcie_power_reset;
 220         u8 pcie_restore;
 221         u8 analog_shiftreg;
 222         u8 ht_enable;
 223         u32 ofdm_trig_low;
 224         u32 ofdm_trig_high;
 225         u32 cck_trig_high;
 226         u32 cck_trig_low;
 227         u32 enable_ani;
 228         u8 noise_immunity_level;
 229         u32 ofdm_weaksignal_det;
 230         u32 cck_weaksignal_thr;
 231         u8 spur_immunity_level;
 232         u8 firstep_level;
 233         int8_t rssi_thr_high;
 234         int8_t rssi_thr_low;
 235         u16 diversity_control;
 236         u16 antenna_switch_swap;
 237         int serialize_regmode;
 238         int intr_mitigation;
 239 #define SPUR_DISABLE            0
 240 #define SPUR_ENABLE_IOCTL       1
 241 #define SPUR_ENABLE_EEPROM      2
 242 #define AR_EEPROM_MODAL_SPURS   5
 243 #define AR_SPUR_5413_1          1640
 244 #define AR_SPUR_5413_2          1200
 245 #define AR_NO_SPUR              0x8000
 246 #define AR_BASE_FREQ_2GHZ       2300
 247 #define AR_BASE_FREQ_5GHZ       4900
 248 #define AR_SPUR_FEEQ_BOUND_HT40 19
 249 #define AR_SPUR_FEEQ_BOUND_HT20 10
 250         int spurmode;
 251         u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
 252 };
 253
 254 enum ath9k_tx_queue {
 255         ATH9K_TX_QUEUE_INACTIVE = 0,
 256         ATH9K_TX_QUEUE_DATA,
 257         ATH9K_TX_QUEUE_BEACON,
 258         ATH9K_TX_QUEUE_CAB,
 259         ATH9K_TX_QUEUE_UAPSD,
 260         ATH9K_TX_QUEUE_PSPOLL
 261 };
 262
 263 #define ATH9K_NUM_TX_QUEUES 10
 264
 265 enum ath9k_tx_queue_subtype {
 266         ATH9K_WME_AC_BK = 0,
 267         ATH9K_WME_AC_BE,
 268         ATH9K_WME_AC_VI,
 269         ATH9K_WME_AC_VO,
 270         ATH9K_WME_UPSD
 271 };
 272
 273 enum ath9k_tx_queue_flags {
 274         TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
 275         TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
 276         TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
 277         TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
 278         TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
 279         TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
 280         TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
 281         TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
 282         TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
 283 };
 284
 285 struct ath9k_txq_info {
 286         u32 tqi_ver;
 287         enum ath9k_tx_queue_subtype tqi_subtype;
 288         enum ath9k_tx_queue_flags tqi_qflags;
 289         u32 tqi_priority;
 290         u32 tqi_aifs;
 291         u32 tqi_cwmin;
 292         u32 tqi_cwmax;
 293         u16 tqi_shretry;
 294         u16 tqi_lgretry;
 295         u32 tqi_cbrPeriod;
 296         u32 tqi_cbrOverflowLimit;
 297         u32 tqi_burstTime;
 298         u32 tqi_readyTime;
 299         u32 tqi_compBuf;
 300 };
 301
 302 #define ATH9K_TXQ_USEDEFAULT ((u32) -1)
 303
 304 #define ATH9K_DECOMP_MASK_SIZE     128
 305 #define ATH9K_READY_TIME_LO_BOUND  50
 306 #define ATH9K_READY_TIME_HI_BOUND  96
 307
 308 enum ath9k_pkt_type {
 309         ATH9K_PKT_TYPE_NORMAL = 0,
 310         ATH9K_PKT_TYPE_ATIM,
 311         ATH9K_PKT_TYPE_PSPOLL,
 312         ATH9K_PKT_TYPE_BEACON,
 313         ATH9K_PKT_TYPE_PROBE_RESP,
 314         ATH9K_PKT_TYPE_CHIRP,
 315         ATH9K_PKT_TYPE_GRP_POLL,
 316 };
 317
 318 struct ath9k_tx_queue_info {
 319         u32 tqi_ver;
 320         enum ath9k_tx_queue tqi_type;
 321         enum ath9k_tx_queue_subtype tqi_subtype;
 322         enum ath9k_tx_queue_flags tqi_qflags;
 323         u32 tqi_priority;
 324         u32 tqi_aifs;
 325         u32 tqi_cwmin;
 326         u32 tqi_cwmax;
 327         u16 tqi_shretry;
 328         u16 tqi_lgretry;
 329         u32 tqi_cbrPeriod;
 330         u32 tqi_cbrOverflowLimit;
 331         u32 tqi_burstTime;
 332         u32 tqi_readyTime;
 333         u32 tqi_physCompBuf;
 334         u32 tqi_intFlags;
 335 };
 336
 337 enum ath9k_rx_filter {
 338         ATH9K_RX_FILTER_UCAST = 0x00000001,
 339         ATH9K_RX_FILTER_MCAST = 0x00000002,
 340         ATH9K_RX_FILTER_BCAST = 0x00000004,
 341         ATH9K_RX_FILTER_CONTROL = 0x00000008,
 342         ATH9K_RX_FILTER_BEACON = 0x00000010,
 343         ATH9K_RX_FILTER_PROM = 0x00000020,
 344         ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
 345         ATH9K_RX_FILTER_PSPOLL = 0x00004000,
 346         ATH9K_RX_FILTER_PHYERR = 0x00000100,
 347         ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
 348 };
 349
 350 enum ath9k_int {
 351         ATH9K_INT_RX = 0x00000001,
 352         ATH9K_INT_RXDESC = 0x00000002,
 353         ATH9K_INT_RXNOFRM = 0x00000008,
 354         ATH9K_INT_RXEOL = 0x00000010,
 355         ATH9K_INT_RXORN = 0x00000020,
 356         ATH9K_INT_TX = 0x00000040,
 357         ATH9K_INT_TXDESC = 0x00000080,
 358         ATH9K_INT_TIM_TIMER = 0x00000100,
 359         ATH9K_INT_TXURN = 0x00000800,
 360         ATH9K_INT_MIB = 0x00001000,
 361         ATH9K_INT_RXPHY = 0x00004000,
 362         ATH9K_INT_RXKCM = 0x00008000,
 363         ATH9K_INT_SWBA = 0x00010000,
 364         ATH9K_INT_BMISS = 0x00040000,
 365         ATH9K_INT_BNR = 0x00100000,
 366         ATH9K_INT_TIM = 0x00200000,
 367         ATH9K_INT_DTIM = 0x00400000,
 368         ATH9K_INT_DTIMSYNC = 0x00800000,
 369         ATH9K_INT_GPIO = 0x01000000,
 370         ATH9K_INT_CABEND = 0x02000000,
 371         ATH9K_INT_CST = 0x10000000,
 372         ATH9K_INT_GTT = 0x20000000,
 373         ATH9K_INT_FATAL = 0x40000000,
 374         ATH9K_INT_GLOBAL = 0x80000000,
 375         ATH9K_INT_BMISC = ATH9K_INT_TIM |
 376                 ATH9K_INT_DTIM |
 377                 ATH9K_INT_DTIMSYNC |
 378                 ATH9K_INT_CABEND,
 379         ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
 380                 ATH9K_INT_RXDESC |
 381                 ATH9K_INT_RXEOL |
 382                 ATH9K_INT_RXORN |
 383                 ATH9K_INT_TXURN |
 384                 ATH9K_INT_TXDESC |
 385                 ATH9K_INT_MIB |
 386                 ATH9K_INT_RXPHY |
 387                 ATH9K_INT_RXKCM |
 388                 ATH9K_INT_SWBA |
 389                 ATH9K_INT_BMISS |
 390                 ATH9K_INT_GPIO,
 391         ATH9K_INT_NOCARD = 0xffffffff
 392 };
 393
 394 struct ath9k_rate_table {
 395         int rateCount;
 396         u8 rateCodeToIndex[256];
 397         struct {
 398                 u8 valid;
 399                 u8 phy;
 400                 u32 rateKbps;
 401                 u8 rateCode;
 402                 u8 shortPreamble;
 403                 u8 dot11Rate;
 404                 u8 controlRate;
 405                 u16 lpAckDuration;
 406                 u16 spAckDuration;
 407         } info[32];
 408 };
 409
 410 #define ATH9K_RATESERIES_RTS_CTS  0x0001
 411 #define ATH9K_RATESERIES_2040     0x0002
 412 #define ATH9K_RATESERIES_HALFGI   0x0004
 413
 414 struct ath9k_11n_rate_series {
 415         u32 Tries;
 416         u32 Rate;
 417         u32 PktDuration;
 418         u32 ChSel;
 419         u32 RateFlags;
 420 };
 421
 422 #define CHANNEL_CW_INT    0x00002
 423 #define CHANNEL_CCK       0x00020
 424 #define CHANNEL_OFDM      0x00040
 425 #define CHANNEL_2GHZ      0x00080
 426 #define CHANNEL_5GHZ      0x00100
 427 #define CHANNEL_PASSIVE   0x00200
 428 #define CHANNEL_DYN       0x00400
 429 #define CHANNEL_HALF      0x04000
 430 #define CHANNEL_QUARTER   0x08000
 431 #define CHANNEL_HT20      0x10000
 432 #define CHANNEL_HT40PLUS  0x20000
 433 #define CHANNEL_HT40MINUS 0x40000
 434
 435 #define CHANNEL_INTERFERENCE    0x01
 436 #define CHANNEL_DFS             0x02
 437 #define CHANNEL_4MS_LIMIT       0x04
 438 #define CHANNEL_DFS_CLEAR       0x08
 439 #define CHANNEL_DISALLOW_ADHOC  0x10
 440 #define CHANNEL_PER_11D_ADHOC   0x20
 441
 442 #define CHANNEL_A           (CHANNEL_5GHZ|CHANNEL_OFDM)
 443 #define CHANNEL_B           (CHANNEL_2GHZ|CHANNEL_CCK)
 444 #define CHANNEL_G           (CHANNEL_2GHZ|CHANNEL_OFDM)
 445 #define CHANNEL_G_HT20      (CHANNEL_2GHZ|CHANNEL_HT20)
 446 #define CHANNEL_A_HT20      (CHANNEL_5GHZ|CHANNEL_HT20)
 447 #define CHANNEL_G_HT40PLUS  (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
 448 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
 449 #define CHANNEL_A_HT40PLUS  (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
 450 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
 451 #define CHANNEL_ALL                             \
 452         (CHANNEL_OFDM|                          \
 453          CHANNEL_CCK|                           \
 454          CHANNEL_2GHZ |                         \
 455          CHANNEL_5GHZ |                         \
 456          CHANNEL_HT20 |                         \
 457          CHANNEL_HT40PLUS |                     \
 458          CHANNEL_HT40MINUS)
 459
 460 struct ath9k_channel {
 461         u16 channel;
 462         u32 channelFlags;
 463         u8 privFlags;
 464         int8_t maxRegTxPower;
 465         int8_t maxTxPower;
 466         int8_t minTxPower;
 467         u32 chanmode;
 468         int32_t CalValid;
 469         bool oneTimeCalsDone;
 470         int8_t iCoff;
 471         int8_t qCoff;
 472         int16_t rawNoiseFloor;
 473         int8_t antennaMax;
 474         u32 regDmnFlags;
 475         u32 conformanceTestLimit[3]; /* 0:11a, 1: 11b, 2:11g */
 476 #ifdef ATH_NF_PER_CHAN
 477         struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
 478 #endif
 479 };
 480
 481 #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
 482        (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
 483        (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
 484        (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS))
 485 #define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B)
 486 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
 487        (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
 488        (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
 489        (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
 490 #define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0)
 491 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
 492 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
 493 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
 494 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
 495 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
 496 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
 497
 498 /* These macros check chanmode and not channelFlags */
 499 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
 500                           ((_c)->chanmode == CHANNEL_G_HT20))
 501 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) ||     \
 502                           ((_c)->chanmode == CHANNEL_A_HT40MINUS) ||    \
 503                           ((_c)->chanmode == CHANNEL_G_HT40PLUS) ||     \
 504                           ((_c)->chanmode == CHANNEL_G_HT40MINUS))
 505 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
 506
 507 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
 508 #define IS_CHAN_A_5MHZ_SPACED(_c)                       \
 509         ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) &&  \
 510          (((_c)->channel % 20) != 0) &&                 \
 511          (((_c)->channel % 10) != 0))
 512
 513 struct ath9k_keyval {
 514         u8 kv_type;
 515         u8 kv_pad;
 516         u16 kv_len;
 517         u8 kv_val[16];
 518         u8 kv_mic[8];
 519         u8 kv_txmic[8];
 520 };
 521
 522 enum ath9k_key_type {
 523         ATH9K_KEY_TYPE_CLEAR,
 524         ATH9K_KEY_TYPE_WEP,
 525         ATH9K_KEY_TYPE_AES,
 526         ATH9K_KEY_TYPE_TKIP,
 527 };
 528
 529 enum ath9k_cipher {
 530         ATH9K_CIPHER_WEP = 0,
 531         ATH9K_CIPHER_AES_OCB = 1,
 532         ATH9K_CIPHER_AES_CCM = 2,
 533         ATH9K_CIPHER_CKIP = 3,
 534         ATH9K_CIPHER_TKIP = 4,
 535         ATH9K_CIPHER_CLR = 5,
 536         ATH9K_CIPHER_MIC = 127
 537 };
 538
 539 #define AR_EEPROM_EEPCAP_COMPRESS_DIS   0x0001
 540 #define AR_EEPROM_EEPCAP_AES_DIS        0x0002
 541 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS  0x0004
 542 #define AR_EEPROM_EEPCAP_BURST_DIS      0x0008
 543 #define AR_EEPROM_EEPCAP_MAXQCU         0x01F0
 544 #define AR_EEPROM_EEPCAP_MAXQCU_S       4
 545 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN  0x0200
 546 #define AR_EEPROM_EEPCAP_KC_ENTRIES     0xF000
 547 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S   12
 548
 549 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND   0x0040
 550 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN    0x0080
 551 #define AR_EEPROM_EEREGCAP_EN_KK_U2         0x0100
 552 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND    0x0200
 553 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD     0x0400
 554 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A    0x0800
 555
 556 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0  0x4000
 557 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
 558
 559 #define SD_NO_CTL               0xE0
 560 #define NO_CTL                  0xff
 561 #define CTL_MODE_M              7
 562 #define CTL_11A                 0
 563 #define CTL_11B                 1
 564 #define CTL_11G                 2
 565 #define CTL_2GHT20              5
 566 #define CTL_5GHT20              6
 567 #define CTL_2GHT40              7
 568 #define CTL_5GHT40              8
 569
 570 #define AR_EEPROM_MAC(i)        (0x1d+(i))
 571 #define EEP_SCALE       100
 572 #define EEP_DELTA       10
 573
 574 #define AR_EEPROM_RFSILENT_GPIO_SEL     0x001c
 575 #define AR_EEPROM_RFSILENT_GPIO_SEL_S   2
 576 #define AR_EEPROM_RFSILENT_POLARITY     0x0002
 577 #define AR_EEPROM_RFSILENT_POLARITY_S   1
 578
 579 #define CTRY_DEBUG 0x1ff
 580 #define CTRY_DEFAULT 0
 581
 582 enum reg_ext_bitmap {
 583         REG_EXT_JAPAN_MIDBAND = 1,
 584         REG_EXT_FCC_DFS_HT40 = 2,
 585         REG_EXT_JAPAN_NONDFS_HT40 = 3,
 586         REG_EXT_JAPAN_DFS_HT40 = 4
 587 };
 588
 589 struct ath9k_country_entry {
 590         u16 countryCode;
 591         u16 regDmnEnum;
 592         u16 regDmn5G;
 593         u16 regDmn2G;
 594         u8 isMultidomain;
 595         u8 iso[3];
 596 };
 597
 598 #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
 599 #define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg)
 600
 601 #define SM(_v, _f)  (((_v) << _f##_S) & _f)
 602 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
 603 #define REG_RMW(_a, _r, _set, _clr)    \
 604         REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
 605 #define REG_RMW_FIELD(_a, _r, _f, _v) \
 606         REG_WRITE(_a, _r, \
 607         (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
 608 #define REG_SET_BIT(_a, _r, _f) \
 609         REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
 610 #define REG_CLR_BIT(_a, _r, _f) \
 611         REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
 612
 613 #define ATH9K_COMP_BUF_MAX_SIZE   9216
 614 #define ATH9K_COMP_BUF_ALIGN_SIZE 512
 615
 616 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS   0x00000001
 617
 618 #define INIT_AIFS       2
 619 #define INIT_CWMIN      15
 620 #define INIT_CWMIN_11B  31
 621 #define INIT_CWMAX      1023
 622 #define INIT_SH_RETRY   10
 623 #define INIT_LG_RETRY   10
 624 #define INIT_SSH_RETRY  32
 625 #define INIT_SLG_RETRY  32
 626
 627 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4)
 628
 629 #define ATH_AMPDU_LIMIT_MAX      (64 * 1024 - 1)
 630 #define ATH_AMPDU_LIMIT_DEFAULT  ATH_AMPDU_LIMIT_MAX
 631
 632 #define IEEE80211_WEP_IVLEN      3
 633 #define IEEE80211_WEP_KIDLEN     1
 634 #define IEEE80211_WEP_CRCLEN     4
 635 #define IEEE80211_MAX_MPDU_LEN  (3840 + FCS_LEN +               \
 636                                  (IEEE80211_WEP_IVLEN +         \
 637                                   IEEE80211_WEP_KIDLEN +        \
 638                                   IEEE80211_WEP_CRCLEN))
 639 #define IEEE80211_MAX_LEN       (2300 + FCS_LEN +               \
 640                                  (IEEE80211_WEP_IVLEN +         \
 641                                   IEEE80211_WEP_KIDLEN +        \
 642                                   IEEE80211_WEP_CRCLEN))
 643
 644 #define MAX_REG_ADD_COUNT   129
 645 #define MAX_RATE_POWER 63
 646
 647 enum ath9k_power_mode {
 648         ATH9K_PM_AWAKE = 0,
 649         ATH9K_PM_FULL_SLEEP,
 650         ATH9K_PM_NETWORK_SLEEP,
 651         ATH9K_PM_UNDEFINED
 652 };
 653
 654 #define HAL_ANTENNA_MIN_MODE  0
 655 #define HAL_ANTENNA_FIXED_A   1
 656 #define HAL_ANTENNA_FIXED_B   2
 657 #define HAL_ANTENNA_MAX_MODE  3
 658
 659 struct ath9k_mib_stats {
 660         u32 ackrcv_bad;
 661         u32 rts_bad;
 662         u32 rts_good;
 663         u32 fcs_bad;
 664         u32 beacons;
 665 };
 666
 667 enum ath9k_ant_setting {
 668         ATH9K_ANT_VARIABLE = 0,
 669         ATH9K_ANT_FIXED_A,
 670         ATH9K_ANT_FIXED_B
 671 };
 672
 673 enum ath9k_opmode {
 674         ATH9K_M_STA = 1,
 675         ATH9K_M_IBSS = 0,
 676         ATH9K_M_HOSTAP = 6,
 677         ATH9K_M_MONITOR = 8
 678 };
 679
 680 #define ATH9K_SLOT_TIME_6 6
 681 #define ATH9K_SLOT_TIME_9 9
 682 #define ATH9K_SLOT_TIME_20 20
 683
 684 enum ath9k_ht_macmode {
 685         ATH9K_HT_MACMODE_20 = 0,
 686         ATH9K_HT_MACMODE_2040 = 1,
 687 };
 688
 689 enum ath9k_ht_extprotspacing {
 690         ATH9K_HT_EXTPROTSPACING_20 = 0,
 691         ATH9K_HT_EXTPROTSPACING_25 = 1,
 692 };
 693
 694 struct ath9k_ht_cwm {
 695         enum ath9k_ht_macmode ht_macmode;
 696         enum ath9k_ht_extprotspacing ht_extprotspacing;
 697 };
 698
 699 enum hal_freq_band {
 700         HAL_FREQ_BAND_5GHZ = 0,
 701         HAL_FREQ_BAND_2GHZ = 1,
 702 };
 703
 704 enum ath9k_ani_cmd {
 705         ATH9K_ANI_PRESENT = 0x1,
 706         ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
 707         ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
 708         ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
 709         ATH9K_ANI_FIRSTEP_LEVEL = 0x10,
 710         ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
 711         ATH9K_ANI_MODE = 0x40,
 712         ATH9K_ANI_PHYERR_RESET = 0x80,
 713         ATH9K_ANI_ALL = 0xff
 714 };
 715
 716 enum phytype {
 717         PHY_DS,
 718         PHY_FH,
 719         PHY_OFDM,
 720         PHY_HT,
 721         PHY_MAX
 722 };
 723 #define PHY_CCK PHY_DS
 724
 725 enum start_adhoc_option {
 726         START_ADHOC_NO_11A,
 727         START_ADHOC_PER_11D,
 728         START_ADHOC_IN_11A,
 729         START_ADHOC_IN_11B,
 730 };
 731
 732 enum ath9k_tp_scale {
 733         ATH9K_TP_SCALE_MAX = 0,
 734         ATH9K_TP_SCALE_50,
 735         ATH9K_TP_SCALE_25,
 736         ATH9K_TP_SCALE_12,
 737         ATH9K_TP_SCALE_MIN
 738 };
 739
 740 enum ser_reg_mode {
 741         SER_REG_MODE_OFF = 0,
 742         SER_REG_MODE_ON = 1,
 743         SER_REG_MODE_AUTO = 2,
 744 };
 745
 746 #define AR_PHY_CCA_MAX_GOOD_VALUE               -85
 747 #define AR_PHY_CCA_MAX_HIGH_VALUE               -62
 748 #define AR_PHY_CCA_MIN_BAD_VALUE                -121
 749 #define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT     3
 750 #define AR_PHY_CCA_FILTERWINDOW_LENGTH          5
 751
 752 #define ATH9K_NF_CAL_HIST_MAX           5
 753 #define NUM_NF_READINGS                 6
 754
 755 struct ath9k_nfcal_hist {
 756         int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX];
 757         u8 currIndex;
 758         int16_t privNF;
 759         u8 invalidNFcount;
 760 };
 761
 762 struct ath9k_beacon_state {
 763         u32 bs_nexttbtt;
 764         u32 bs_nextdtim;
 765         u32 bs_intval;
 766 #define ATH9K_BEACON_PERIOD       0x0000ffff
 767 #define ATH9K_BEACON_ENA          0x00800000
 768 #define ATH9K_BEACON_RESET_TSF    0x01000000
 769         u32 bs_dtimperiod;
 770         u16 bs_cfpperiod;
 771         u16 bs_cfpmaxduration;
 772         u32 bs_cfpnext;
 773         u16 bs_timoffset;
 774         u16 bs_bmissthreshold;
 775         u32 bs_sleepduration;
 776 };
 777
 778 struct ath9k_node_stats {
 779         u32 ns_avgbrssi;
 780         u32 ns_avgrssi;
 781         u32 ns_avgtxrssi;
 782         u32 ns_avgtxrate;
 783 };
 784
 785 #define ATH9K_RSSI_EP_MULTIPLIER  (1<<7)
 786
 787 enum ath9k_gpio_output_mux_type {
 788         ATH9K_GPIO_OUTPUT_MUX_AS_OUTPUT,
 789         ATH9K_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED,
 790         ATH9K_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED,
 791         ATH9K_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED,
 792         ATH9K_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED,
 793         ATH9K_GPIO_OUTPUT_MUX_NUM_ENTRIES
 794 };
 795
 796 enum {
 797         ATH9K_RESET_POWER_ON,
 798         ATH9K_RESET_WARM,
 799         ATH9K_RESET_COLD,
 800 };
 801
 802 #define AH_USE_EEPROM   0x1
 803
 804 struct ath_hal {
 805         u32 ah_magic;
 806         u16 ah_devid;
 807         u16 ah_subvendorid;
 808         struct ath_softc *ah_sc;
 809         void __iomem *ah_sh;
 810         u16 ah_countryCode;
 811         u32 ah_macVersion;
 812         u16 ah_macRev;
 813         u16 ah_phyRev;
 814         u16 ah_analog5GhzRev;
 815         u16 ah_analog2GhzRev;
 816         u8 ah_decompMask[ATH9K_DECOMP_MASK_SIZE];
 817         u32 ah_flags;
 818         enum ath9k_opmode ah_opmode;
 819         struct ath9k_ops_config ah_config;
 820         struct ath9k_hw_capabilities ah_caps;
 821         int16_t ah_powerLimit;
 822         u16 ah_maxPowerLevel;
 823         u32 ah_tpScale;
 824         u16 ah_currentRD;
 825         u16 ah_currentRDExt;
 826         u16 ah_currentRDInUse;
 827         u16 ah_currentRD5G;
 828         u16 ah_currentRD2G;
 829         char ah_iso[4];
 830         enum start_adhoc_option ah_adHocMode;
 831         bool ah_commonMode;
 832         struct ath9k_channel ah_channels[150];
 833         u32 ah_nchan;
 834         struct ath9k_channel *ah_curchan;
 835         u16 ah_rfsilent;
 836         bool ah_rfkillEnabled;
 837         bool ah_isPciExpress;
 838         u16 ah_txTrigLevel;
 839 #ifndef ATH_NF_PER_CHAN
 840         struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
 841 #endif
 842 };
 843
 844 enum wireless_mode {
 845         WIRELESS_MODE_11a = 0,
 846         WIRELESS_MODE_11b = 2,
 847         WIRELESS_MODE_11g = 3,
 848         WIRELESS_MODE_11NA_HT20 = 6,
 849         WIRELESS_MODE_11NG_HT20 = 7,
 850         WIRELESS_MODE_11NA_HT40PLUS = 8,
 851         WIRELESS_MODE_11NA_HT40MINUS = 9,
 852         WIRELESS_MODE_11NG_HT40PLUS = 10,
 853         WIRELESS_MODE_11NG_HT40MINUS = 11,
 854         WIRELESS_MODE_MAX
 855 };
 856
 857 enum {
 858         ATH9K_MODE_SEL_11A = 0x00001,
 859         ATH9K_MODE_SEL_11B = 0x00002,
 860         ATH9K_MODE_SEL_11G = 0x00004,
 861         ATH9K_MODE_SEL_11NG_HT20 = 0x00008,
 862         ATH9K_MODE_SEL_11NA_HT20 = 0x00010,
 863         ATH9K_MODE_SEL_11NG_HT40PLUS = 0x00020,
 864         ATH9K_MODE_SEL_11NG_HT40MINUS = 0x00040,
 865         ATH9K_MODE_SEL_11NA_HT40PLUS = 0x00080,
 866         ATH9K_MODE_SEL_11NA_HT40MINUS = 0x00100,
 867         ATH9K_MODE_SEL_2GHZ = (ATH9K_MODE_SEL_11B |
 868                                ATH9K_MODE_SEL_11G |
 869                                ATH9K_MODE_SEL_11NG_HT20),
 870         ATH9K_MODE_SEL_5GHZ = (ATH9K_MODE_SEL_11A |
 871                                ATH9K_MODE_SEL_11NA_HT20),
 872         ATH9K_MODE_SEL_ALL = 0xffffffff
 873 };
 874
 875 struct chan_centers {
 876         u16 synth_center;
 877         u16 ctl_center;
 878         u16 ext_center;
 879 };
 880
 881 int ath_hal_getcapability(struct ath_hal *ah,
 882                           enum ath9k_capability_type type,
 883                           u32 capability,
 884                           u32 *result);
 885 const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
 886                                                      u32 mode);
 887 void ath9k_hw_detach(struct ath_hal *ah);
 888 struct ath_hal *ath9k_hw_attach(u16 devid,
 889                                 struct ath_softc *sc,
 890                                 void __iomem *mem,
 891                                 int *error);
 892 bool ath9k_regd_init_channels(struct ath_hal *ah,
 893                               u32 maxchans, u32 *nchans,
 894                               u8 *regclassids,
 895                               u32 maxregids, u32 *nregids,
 896                               u16 cc, u32 modeSelect,
 897                               bool enableOutdoor,
 898                               bool enableExtendedChannels);
 899 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
 900 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah,
 901                                      enum ath9k_int ints);
 902 bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode,
 903                     struct ath9k_channel *chan,
 904                     enum ath9k_ht_macmode macmode,
 905                     u8 txchainmask, u8 rxchainmask,
 906                     enum ath9k_ht_extprotspacing extprotspacing,
 907                     bool bChannelChange,
 908                     int *status);
 909 bool ath9k_hw_phy_disable(struct ath_hal *ah);
 910 void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
 911                              bool *isCalDone);
 912 void ath9k_hw_ani_monitor(struct ath_hal *ah,
 913                           const struct ath9k_node_stats *stats,
 914                           struct ath9k_channel *chan);
 915 bool ath9k_hw_calibrate(struct ath_hal *ah,
 916                         struct ath9k_channel *chan,
 917                         u8 rxchainmask,
 918                         bool longcal,
 919                         bool *isCalDone);
 920 int16_t ath9k_hw_getchan_noise(struct ath_hal *ah,
 921                                struct ath9k_channel *chan);
 922 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
 923                             u16 assocId);
 924 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits);
 925 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
 926                             u16 assocId);
 927 bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q);
 928 void ath9k_hw_reset_tsf(struct ath_hal *ah);
 929 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry);
 930 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry,
 931                         const u8 *mac);
 932 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
 933                                  u16 entry,
 934                                  const struct ath9k_keyval *k,
 935                                  const u8 *mac,
 936                                  int xorKey);
 937 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
 938                             u32 setting);
 939 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
 940 bool ath9k_hw_intrpend(struct ath_hal *ah);
 941 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked);
 942 bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
 943                                 bool bIncTrigLevel);
 944 void ath9k_hw_procmibevent(struct ath_hal *ah,
 945                            const struct ath9k_node_stats *stats);
 946 bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
 947 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
 948 bool ath9k_hw_phycounters(struct ath_hal *ah);
 949 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry);
 950 bool ath9k_hw_getcapability(struct ath_hal *ah,
 951                             enum ath9k_capability_type type,
 952                             u32 capability,
 953                             u32 *result);
 954 bool ath9k_hw_setcapability(struct ath_hal *ah,
 955                             enum ath9k_capability_type type,
 956                             u32 capability,
 957                             u32 setting,
 958                             int *status);
 959 u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
 960 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac);
 961 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask);
 962 bool ath9k_hw_setbssidmask(struct ath_hal *ah,
 963                            const u8 *mask);
 964 bool ath9k_hw_setpower(struct ath_hal *ah,
 965                        enum ath9k_power_mode mode);
 966 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah);
 967 u64 ath9k_hw_gettsf64(struct ath_hal *ah);
 968 u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
 969 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us);
 970 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
 971                                enum ath9k_ant_setting settings,
 972                                struct ath9k_channel *chan,
 973                                u8 *tx_chainmask,
 974                                u8 *rx_chainmask,
 975                                u8 *antenna_cfgd);
 976 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna);
 977 int ath9k_hw_select_antconfig(struct ath_hal *ah,
 978                               u32 cfg);
 979 bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q,
 980                        u32 txdp);
 981 bool ath9k_hw_txstart(struct ath_hal *ah, u32 q);
 982 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
 983                                  const struct ath9k_rate_table *rates,
 984                                  u32 frameLen, u16 rateix,
 985                                  bool shortPreamble);
 986 void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
 987                                   struct ath_desc *lastds,
 988                                   u32 durUpdateEn, u32 rtsctsRate,
 989                                   u32 rtsctsDuration,
 990                                   struct ath9k_11n_rate_series series[],
 991                                   u32 nseries, u32 flags);
 992 void ath9k_hw_set11n_burstduration(struct ath_hal *ah,
 993                                    struct ath_desc *ds,
 994                                    u32 burstDuration);
 995 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
 996 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
 997 bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q);
 998 u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
 999 u32 ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
1000                                      struct ath9k_channel *chan);
1001 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
1002 bool ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
1003                               struct ath9k_txq_info *qInfo);
1004 bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
1005                               const struct ath9k_txq_info *qInfo);
1006 struct ath9k_channel *ath9k_regd_check_channel(struct ath_hal *ah,
1007                                               const struct ath9k_channel *c);
1008 void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
1009                             u32 pktLen, enum ath9k_pkt_type type,
1010                             u32 txPower, u32 keyIx,
1011                             enum ath9k_key_type keyType, u32 flags);
1012 bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
1013                          u32 segLen, bool firstSeg,
1014                          bool lastSeg,
1015                          const struct ath_desc *ds0);
1016 u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
1017                                         u32 *rxc_pcnt,
1018                                         u32 *rxf_pcnt,
1019                                         u32 *txf_pcnt);
1020 void ath9k_hw_dmaRegDump(struct ath_hal *ah);
1021 void ath9k_hw_beaconinit(struct ath_hal *ah,
1022                          u32 next_beacon, u32 beacon_period);
1023 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
1024                                     const struct ath9k_beacon_state *bs);
1025 bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
1026                           u32 size, u32 flags);
1027 void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp);
1028 void ath9k_hw_rxena(struct ath_hal *ah);
1029 void ath9k_hw_setopmode(struct ath_hal *ah);
1030 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac);
1031 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0,
1032                              u32 filter1);
1033 u32 ath9k_hw_getrxfilter(struct ath_hal *ah);
1034 void ath9k_hw_startpcureceive(struct ath_hal *ah);
1035 void ath9k_hw_stoppcurecv(struct ath_hal *ah);
1036 bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
1037 int ath9k_hw_rxprocdesc(struct ath_hal *ah,
1038                         struct ath_desc *ds, u32 pa,
1039                         struct ath_desc *nds, u64 tsf);
1040 u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q);
1041 int ath9k_hw_txprocdesc(struct ath_hal *ah,
1042                         struct ath_desc *ds);
1043 void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
1044                                  u32 numDelims);
1045 void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
1046                                 u32 aggrLen);
1047 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
1048 bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q);
1049 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs);
1050 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
1051 void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah,
1052                                      struct ath_desc *ds, u32 vmf);
1053 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit);
1054 bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
1055 int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
1056                           const struct ath9k_txq_info *qInfo);
1057 u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q);
1058 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
1059 bool ath9k_hw_disable(struct ath_hal *ah);
1060 void ath9k_hw_rfdetach(struct ath_hal *ah);
1061 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
1062                                   struct ath9k_channel *chan,
1063                                   struct chan_centers *centers);
1064 bool ath9k_get_channel_edges(struct ath_hal *ah,
1065                              u16 flags, u16 *low,
1066                              u16 *high);
1067 #endif