2 * $Id: synclink_gt.c,v 4.50 2007/07/25 19:29:25 paulkf Exp $
4 * Device driver for Microgate SyncLink GT serial adapters.
6 * written by Paul Fulghum for Microgate Corporation
9 * Microgate and SyncLink are trademarks of Microgate Corporation
11 * This code is released under the GNU General Public License (GPL)
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
17 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
21 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
23 * OF THE POSSIBILITY OF SUCH DAMAGE.
27 * DEBUG OUTPUT DEFINITIONS
29 * uncomment lines below to enable specific types of debug output
31 * DBGINFO information - most verbose output
32 * DBGERR serious errors
33 * DBGBH bottom half service routine debugging
34 * DBGISR interrupt service routine debugging
35 * DBGDATA output receive and transmit data
36 * DBGTBUF output transmit DMA buffers and registers
37 * DBGRBUF output receive DMA buffers and registers
40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
45 //#define DBGTBUF(info) dump_tbufs(info)
46 //#define DBGRBUF(info) dump_rbufs(info)
49 #include <linux/module.h>
50 #include <linux/version.h>
51 #include <linux/errno.h>
52 #include <linux/signal.h>
53 #include <linux/sched.h>
54 #include <linux/timer.h>
55 #include <linux/interrupt.h>
56 #include <linux/pci.h>
57 #include <linux/tty.h>
58 #include <linux/tty_flip.h>
59 #include <linux/serial.h>
60 #include <linux/major.h>
61 #include <linux/string.h>
62 #include <linux/fcntl.h>
63 #include <linux/ptrace.h>
64 #include <linux/ioport.h>
66 #include <linux/slab.h>
67 #include <linux/netdevice.h>
68 #include <linux/vmalloc.h>
69 #include <linux/init.h>
70 #include <linux/delay.h>
71 #include <linux/ioctl.h>
72 #include <linux/termios.h>
73 #include <linux/bitops.h>
74 #include <linux/workqueue.h>
75 #include <linux/hdlc.h>
76 #include <linux/synclink.h>
78 #include <asm/system.h>
82 #include <asm/types.h>
83 #include <asm/uaccess.h>
85 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
86 #define SYNCLINK_GENERIC_HDLC 1
88 #define SYNCLINK_GENERIC_HDLC 0
92 * module identification
94 static char *driver_name
= "SyncLink GT";
95 static char *driver_version
= "$Revision: 4.50 $";
96 static char *tty_driver_name
= "synclink_gt";
97 static char *tty_dev_prefix
= "ttySLG";
98 MODULE_LICENSE("GPL");
99 #define MGSL_MAGIC 0x5401
100 #define MAX_DEVICES 32
102 static struct pci_device_id pci_table
[] = {
103 {PCI_VENDOR_ID_MICROGATE
, SYNCLINK_GT_DEVICE_ID
, PCI_ANY_ID
, PCI_ANY_ID
,},
104 {PCI_VENDOR_ID_MICROGATE
, SYNCLINK_GT2_DEVICE_ID
, PCI_ANY_ID
, PCI_ANY_ID
,},
105 {PCI_VENDOR_ID_MICROGATE
, SYNCLINK_GT4_DEVICE_ID
, PCI_ANY_ID
, PCI_ANY_ID
,},
106 {PCI_VENDOR_ID_MICROGATE
, SYNCLINK_AC_DEVICE_ID
, PCI_ANY_ID
, PCI_ANY_ID
,},
107 {0,}, /* terminate list */
109 MODULE_DEVICE_TABLE(pci
, pci_table
);
111 static int init_one(struct pci_dev
*dev
,const struct pci_device_id
*ent
);
112 static void remove_one(struct pci_dev
*dev
);
113 static struct pci_driver pci_driver
= {
114 .name
= "synclink_gt",
115 .id_table
= pci_table
,
117 .remove
= __devexit_p(remove_one
),
120 static bool pci_registered
;
123 * module configuration and status
125 static struct slgt_info
*slgt_device_list
;
126 static int slgt_device_count
;
129 static int debug_level
;
130 static int maxframe
[MAX_DEVICES
];
131 static int dosyncppp
[MAX_DEVICES
];
133 module_param(ttymajor
, int, 0);
134 module_param(debug_level
, int, 0);
135 module_param_array(maxframe
, int, NULL
, 0);
136 module_param_array(dosyncppp
, int, NULL
, 0);
138 MODULE_PARM_DESC(ttymajor
, "TTY major device number override: 0=auto assigned");
139 MODULE_PARM_DESC(debug_level
, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
140 MODULE_PARM_DESC(maxframe
, "Maximum frame size used by device (4096 to 65535)");
141 MODULE_PARM_DESC(dosyncppp
, "Enable synchronous net device, 0=disable 1=enable");
144 * tty support and callbacks
146 static struct tty_driver
*serial_driver
;
148 static int open(struct tty_struct
*tty
, struct file
* filp
);
149 static void close(struct tty_struct
*tty
, struct file
* filp
);
150 static void hangup(struct tty_struct
*tty
);
151 static void set_termios(struct tty_struct
*tty
, struct ktermios
*old_termios
);
153 static int write(struct tty_struct
*tty
, const unsigned char *buf
, int count
);
154 static void put_char(struct tty_struct
*tty
, unsigned char ch
);
155 static void send_xchar(struct tty_struct
*tty
, char ch
);
156 static void wait_until_sent(struct tty_struct
*tty
, int timeout
);
157 static int write_room(struct tty_struct
*tty
);
158 static void flush_chars(struct tty_struct
*tty
);
159 static void flush_buffer(struct tty_struct
*tty
);
160 static void tx_hold(struct tty_struct
*tty
);
161 static void tx_release(struct tty_struct
*tty
);
163 static int ioctl(struct tty_struct
*tty
, struct file
*file
, unsigned int cmd
, unsigned long arg
);
164 static int read_proc(char *page
, char **start
, off_t off
, int count
,int *eof
, void *data
);
165 static int chars_in_buffer(struct tty_struct
*tty
);
166 static void throttle(struct tty_struct
* tty
);
167 static void unthrottle(struct tty_struct
* tty
);
168 static void set_break(struct tty_struct
*tty
, int break_state
);
171 * generic HDLC support and callbacks
173 #if SYNCLINK_GENERIC_HDLC
174 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
175 static void hdlcdev_tx_done(struct slgt_info
*info
);
176 static void hdlcdev_rx(struct slgt_info
*info
, char *buf
, int size
);
177 static int hdlcdev_init(struct slgt_info
*info
);
178 static void hdlcdev_exit(struct slgt_info
*info
);
183 * device specific structures, macros and functions
186 #define SLGT_MAX_PORTS 4
187 #define SLGT_REG_SIZE 256
190 * conditional wait facility
193 struct cond_wait
*next
;
198 static void init_cond_wait(struct cond_wait
*w
, unsigned int data
);
199 static void add_cond_wait(struct cond_wait
**head
, struct cond_wait
*w
);
200 static void remove_cond_wait(struct cond_wait
**head
, struct cond_wait
*w
);
201 static void flush_cond_wait(struct cond_wait
**head
);
204 * DMA buffer descriptor and access macros
210 __le32 pbuf
; /* physical address of data buffer */
211 __le32 next
; /* physical address of next descriptor */
213 /* driver book keeping */
214 char *buf
; /* virtual address of data buffer */
215 unsigned int pdesc
; /* physical address of this descriptor */
216 dma_addr_t buf_dma_addr
;
219 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
220 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
221 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
222 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
223 #define desc_count(a) (le16_to_cpu((a).count))
224 #define desc_status(a) (le16_to_cpu((a).status))
225 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
226 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
227 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
228 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
229 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
231 struct _input_signal_events
{
243 * device instance data structure
246 void *if_ptr
; /* General purpose pointer (used by SPPP) */
248 struct slgt_info
*next_device
; /* device list link */
253 char device_name
[25];
254 struct pci_dev
*pdev
;
256 int port_count
; /* count of ports on adapter */
257 int adapter_num
; /* adapter instance number */
258 int port_num
; /* port instance number */
260 /* array of pointers to port contexts on this adapter */
261 struct slgt_info
*port_array
[SLGT_MAX_PORTS
];
263 int count
; /* count of opens */
264 int line
; /* tty line instance number */
265 unsigned short close_delay
;
266 unsigned short closing_wait
; /* time to wait before closing */
268 struct mgsl_icount icount
;
270 struct tty_struct
*tty
;
272 int x_char
; /* xon/xoff character */
273 int blocked_open
; /* # of blocked opens */
274 unsigned int read_status_mask
;
275 unsigned int ignore_status_mask
;
277 wait_queue_head_t open_wait
;
278 wait_queue_head_t close_wait
;
280 wait_queue_head_t status_event_wait_q
;
281 wait_queue_head_t event_wait_q
;
282 struct timer_list tx_timer
;
283 struct timer_list rx_timer
;
285 unsigned int gpio_present
;
286 struct cond_wait
*gpio_wait_q
;
288 spinlock_t lock
; /* spinlock for synchronizing with ISR */
290 struct work_struct task
;
296 bool irq_requested
; /* true if IRQ requested */
297 bool irq_occurred
; /* for diagnostics use */
299 /* device configuration */
301 unsigned int bus_type
;
302 unsigned int irq_level
;
303 unsigned long irq_flags
;
305 unsigned char __iomem
* reg_addr
; /* memory mapped registers address */
307 bool reg_addr_requested
;
309 MGSL_PARAMS params
; /* communications parameters */
311 u32 max_frame_size
; /* as set by device config */
313 unsigned int raw_rx_size
;
314 unsigned int if_mode
;
324 unsigned char signals
; /* serial signal states */
325 int init_error
; /* initialization error */
327 unsigned char *tx_buf
;
330 char flag_buf
[MAX_ASYNC_BUFFER_SIZE
];
331 char char_buf
[MAX_ASYNC_BUFFER_SIZE
];
332 bool drop_rts_on_tx_done
;
333 struct _input_signal_events input_signal_events
;
335 int dcd_chkcount
; /* check counts to prevent */
336 int cts_chkcount
; /* too many IRQs if a signal */
337 int dsr_chkcount
; /* is floating */
340 char *bufs
; /* virtual address of DMA buffer lists */
341 dma_addr_t bufs_dma_addr
; /* physical address of buffer descriptors */
343 unsigned int rbuf_count
;
344 struct slgt_desc
*rbufs
;
345 unsigned int rbuf_current
;
346 unsigned int rbuf_index
;
348 unsigned int tbuf_count
;
349 struct slgt_desc
*tbufs
;
350 unsigned int tbuf_current
;
351 unsigned int tbuf_start
;
353 unsigned char *tmp_rbuf
;
354 unsigned int tmp_rbuf_count
;
356 /* SPPP/Cisco HDLC device parts */
361 #if SYNCLINK_GENERIC_HDLC
362 struct net_device
*netdev
;
367 static MGSL_PARAMS default_params
= {
368 .mode
= MGSL_MODE_HDLC
,
370 .flags
= HDLC_FLAG_UNDERRUN_ABORT15
,
371 .encoding
= HDLC_ENCODING_NRZI_SPACE
,
374 .crc_type
= HDLC_CRC_16_CCITT
,
375 .preamble_length
= HDLC_PREAMBLE_LENGTH_8BITS
,
376 .preamble
= HDLC_PREAMBLE_PATTERN_NONE
,
380 .parity
= ASYNC_PARITY_NONE
385 #define BH_TRANSMIT 2
387 #define IO_PIN_SHUTDOWN_LIMIT 100
389 #define DMABUFSIZE 256
390 #define DESC_LIST_SIZE 4096
392 #define MASK_PARITY BIT1
393 #define MASK_FRAMING BIT0
394 #define MASK_BREAK BIT14
395 #define MASK_OVERRUN BIT4
397 #define GSR 0x00 /* global status */
398 #define JCR 0x04 /* JTAG control */
399 #define IODR 0x08 /* GPIO direction */
400 #define IOER 0x0c /* GPIO interrupt enable */
401 #define IOVR 0x10 /* GPIO value */
402 #define IOSR 0x14 /* GPIO interrupt status */
403 #define TDR 0x80 /* tx data */
404 #define RDR 0x80 /* rx data */
405 #define TCR 0x82 /* tx control */
406 #define TIR 0x84 /* tx idle */
407 #define TPR 0x85 /* tx preamble */
408 #define RCR 0x86 /* rx control */
409 #define VCR 0x88 /* V.24 control */
410 #define CCR 0x89 /* clock control */
411 #define BDR 0x8a /* baud divisor */
412 #define SCR 0x8c /* serial control */
413 #define SSR 0x8e /* serial status */
414 #define RDCSR 0x90 /* rx DMA control/status */
415 #define TDCSR 0x94 /* tx DMA control/status */
416 #define RDDAR 0x98 /* rx DMA descriptor address */
417 #define TDDAR 0x9c /* tx DMA descriptor address */
420 #define RXBREAK BIT14
421 #define IRQ_TXDATA BIT13
422 #define IRQ_TXIDLE BIT12
423 #define IRQ_TXUNDER BIT11 /* HDLC */
424 #define IRQ_RXDATA BIT10
425 #define IRQ_RXIDLE BIT9 /* HDLC */
426 #define IRQ_RXBREAK BIT9 /* async */
427 #define IRQ_RXOVER BIT8
432 #define IRQ_ALL 0x3ff0
433 #define IRQ_MASTER BIT0
435 #define slgt_irq_on(info, mask) \
436 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
437 #define slgt_irq_off(info, mask) \
438 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
440 static __u8
rd_reg8(struct slgt_info
*info
, unsigned int addr
);
441 static void wr_reg8(struct slgt_info
*info
, unsigned int addr
, __u8 value
);
442 static __u16
rd_reg16(struct slgt_info
*info
, unsigned int addr
);
443 static void wr_reg16(struct slgt_info
*info
, unsigned int addr
, __u16 value
);
444 static __u32
rd_reg32(struct slgt_info
*info
, unsigned int addr
);
445 static void wr_reg32(struct slgt_info
*info
, unsigned int addr
, __u32 value
);
447 static void msc_set_vcr(struct slgt_info
*info
);
449 static int startup(struct slgt_info
*info
);
450 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,struct slgt_info
*info
);
451 static void shutdown(struct slgt_info
*info
);
452 static void program_hw(struct slgt_info
*info
);
453 static void change_params(struct slgt_info
*info
);
455 static int register_test(struct slgt_info
*info
);
456 static int irq_test(struct slgt_info
*info
);
457 static int loopback_test(struct slgt_info
*info
);
458 static int adapter_test(struct slgt_info
*info
);
460 static void reset_adapter(struct slgt_info
*info
);
461 static void reset_port(struct slgt_info
*info
);
462 static void async_mode(struct slgt_info
*info
);
463 static void sync_mode(struct slgt_info
*info
);
465 static void rx_stop(struct slgt_info
*info
);
466 static void rx_start(struct slgt_info
*info
);
467 static void reset_rbufs(struct slgt_info
*info
);
468 static void free_rbufs(struct slgt_info
*info
, unsigned int first
, unsigned int last
);
469 static void rdma_reset(struct slgt_info
*info
);
470 static bool rx_get_frame(struct slgt_info
*info
);
471 static bool rx_get_buf(struct slgt_info
*info
);
473 static void tx_start(struct slgt_info
*info
);
474 static void tx_stop(struct slgt_info
*info
);
475 static void tx_set_idle(struct slgt_info
*info
);
476 static unsigned int free_tbuf_count(struct slgt_info
*info
);
477 static void reset_tbufs(struct slgt_info
*info
);
478 static void tdma_reset(struct slgt_info
*info
);
479 static void tdma_start(struct slgt_info
*info
);
480 static void tx_load(struct slgt_info
*info
, const char *buf
, unsigned int count
);
482 static void get_signals(struct slgt_info
*info
);
483 static void set_signals(struct slgt_info
*info
);
484 static void enable_loopback(struct slgt_info
*info
);
485 static void set_rate(struct slgt_info
*info
, u32 data_rate
);
487 static int bh_action(struct slgt_info
*info
);
488 static void bh_handler(struct work_struct
*work
);
489 static void bh_transmit(struct slgt_info
*info
);
490 static void isr_serial(struct slgt_info
*info
);
491 static void isr_rdma(struct slgt_info
*info
);
492 static void isr_txeom(struct slgt_info
*info
, unsigned short status
);
493 static void isr_tdma(struct slgt_info
*info
);
495 static int alloc_dma_bufs(struct slgt_info
*info
);
496 static void free_dma_bufs(struct slgt_info
*info
);
497 static int alloc_desc(struct slgt_info
*info
);
498 static void free_desc(struct slgt_info
*info
);
499 static int alloc_bufs(struct slgt_info
*info
, struct slgt_desc
*bufs
, int count
);
500 static void free_bufs(struct slgt_info
*info
, struct slgt_desc
*bufs
, int count
);
502 static int alloc_tmp_rbuf(struct slgt_info
*info
);
503 static void free_tmp_rbuf(struct slgt_info
*info
);
505 static void tx_timeout(unsigned long context
);
506 static void rx_timeout(unsigned long context
);
511 static int get_stats(struct slgt_info
*info
, struct mgsl_icount __user
*user_icount
);
512 static int get_params(struct slgt_info
*info
, MGSL_PARAMS __user
*params
);
513 static int set_params(struct slgt_info
*info
, MGSL_PARAMS __user
*params
);
514 static int get_txidle(struct slgt_info
*info
, int __user
*idle_mode
);
515 static int set_txidle(struct slgt_info
*info
, int idle_mode
);
516 static int tx_enable(struct slgt_info
*info
, int enable
);
517 static int tx_abort(struct slgt_info
*info
);
518 static int rx_enable(struct slgt_info
*info
, int enable
);
519 static int modem_input_wait(struct slgt_info
*info
,int arg
);
520 static int wait_mgsl_event(struct slgt_info
*info
, int __user
*mask_ptr
);
521 static int tiocmget(struct tty_struct
*tty
, struct file
*file
);
522 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
523 unsigned int set
, unsigned int clear
);
524 static void set_break(struct tty_struct
*tty
, int break_state
);
525 static int get_interface(struct slgt_info
*info
, int __user
*if_mode
);
526 static int set_interface(struct slgt_info
*info
, int if_mode
);
527 static int set_gpio(struct slgt_info
*info
, struct gpio_desc __user
*gpio
);
528 static int get_gpio(struct slgt_info
*info
, struct gpio_desc __user
*gpio
);
529 static int wait_gpio(struct slgt_info
*info
, struct gpio_desc __user
*gpio
);
534 static void add_device(struct slgt_info
*info
);
535 static void device_init(int adapter_num
, struct pci_dev
*pdev
);
536 static int claim_resources(struct slgt_info
*info
);
537 static void release_resources(struct slgt_info
*info
);
556 static void trace_block(struct slgt_info
*info
, const char *data
, int count
, const char *label
)
560 printk("%s %s data:\n",info
->device_name
, label
);
562 linecount
= (count
> 16) ? 16 : count
;
563 for(i
=0; i
< linecount
; i
++)
564 printk("%02X ",(unsigned char)data
[i
]);
567 for(i
=0;i
<linecount
;i
++) {
568 if (data
[i
]>=040 && data
[i
]<=0176)
569 printk("%c",data
[i
]);
579 #define DBGDATA(info, buf, size, label)
583 static void dump_tbufs(struct slgt_info
*info
)
586 printk("tbuf_current=%d\n", info
->tbuf_current
);
587 for (i
=0 ; i
< info
->tbuf_count
; i
++) {
588 printk("%d: count=%04X status=%04X\n",
589 i
, le16_to_cpu(info
->tbufs
[i
].count
), le16_to_cpu(info
->tbufs
[i
].status
));
593 #define DBGTBUF(info)
597 static void dump_rbufs(struct slgt_info
*info
)
600 printk("rbuf_current=%d\n", info
->rbuf_current
);
601 for (i
=0 ; i
< info
->rbuf_count
; i
++) {
602 printk("%d: count=%04X status=%04X\n",
603 i
, le16_to_cpu(info
->rbufs
[i
].count
), le16_to_cpu(info
->rbufs
[i
].status
));
607 #define DBGRBUF(info)
610 static inline int sanity_check(struct slgt_info
*info
, char *devname
, const char *name
)
614 printk("null struct slgt_info for (%s) in %s\n", devname
, name
);
617 if (info
->magic
!= MGSL_MAGIC
) {
618 printk("bad magic number struct slgt_info (%s) in %s\n", devname
, name
);
629 * line discipline callback wrappers
631 * The wrappers maintain line discipline references
632 * while calling into the line discipline.
634 * ldisc_receive_buf - pass receive data to line discipline
636 static void ldisc_receive_buf(struct tty_struct
*tty
,
637 const __u8
*data
, char *flags
, int count
)
639 struct tty_ldisc
*ld
;
642 ld
= tty_ldisc_ref(tty
);
645 ld
->receive_buf(tty
, data
, flags
, count
);
652 static int open(struct tty_struct
*tty
, struct file
*filp
)
654 struct slgt_info
*info
;
659 if ((line
< 0) || (line
>= slgt_device_count
)) {
660 DBGERR(("%s: open with invalid line #%d.\n", driver_name
, line
));
664 info
= slgt_device_list
;
665 while(info
&& info
->line
!= line
)
666 info
= info
->next_device
;
667 if (sanity_check(info
, tty
->name
, "open"))
669 if (info
->init_error
) {
670 DBGERR(("%s init error=%d\n", info
->device_name
, info
->init_error
));
674 tty
->driver_data
= info
;
677 DBGINFO(("%s open, old ref count = %d\n", info
->device_name
, info
->count
));
679 /* If port is closing, signal caller to try again */
680 if (tty_hung_up_p(filp
) || info
->flags
& ASYNC_CLOSING
){
681 if (info
->flags
& ASYNC_CLOSING
)
682 interruptible_sleep_on(&info
->close_wait
);
683 retval
= ((info
->flags
& ASYNC_HUP_NOTIFY
) ?
684 -EAGAIN
: -ERESTARTSYS
);
688 info
->tty
->low_latency
= (info
->flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
690 spin_lock_irqsave(&info
->netlock
, flags
);
691 if (info
->netcount
) {
693 spin_unlock_irqrestore(&info
->netlock
, flags
);
697 spin_unlock_irqrestore(&info
->netlock
, flags
);
699 if (info
->count
== 1) {
700 /* 1st open on this device, init hardware */
701 retval
= startup(info
);
706 retval
= block_til_ready(tty
, filp
, info
);
708 DBGINFO(("%s block_til_ready rc=%d\n", info
->device_name
, retval
));
717 info
->tty
= NULL
; /* tty layer will release tty struct */
722 DBGINFO(("%s open rc=%d\n", info
->device_name
, retval
));
726 static void close(struct tty_struct
*tty
, struct file
*filp
)
728 struct slgt_info
*info
= tty
->driver_data
;
730 if (sanity_check(info
, tty
->name
, "close"))
732 DBGINFO(("%s close entry, count=%d\n", info
->device_name
, info
->count
));
737 if (tty_hung_up_p(filp
))
740 if ((tty
->count
== 1) && (info
->count
!= 1)) {
742 * tty->count is 1 and the tty structure will be freed.
743 * info->count should be one in this case.
744 * if it's not, correct it so that the port is shutdown.
746 DBGERR(("%s close: bad refcount; tty->count=1, "
747 "info->count=%d\n", info
->device_name
, info
->count
));
753 /* if at least one open remaining, leave hardware active */
757 info
->flags
|= ASYNC_CLOSING
;
759 /* set tty->closing to notify line discipline to
760 * only process XON/XOFF characters. Only the N_TTY
761 * discipline appears to use this (ppp does not).
765 /* wait for transmit data to clear all layers */
767 if (info
->closing_wait
!= ASYNC_CLOSING_WAIT_NONE
) {
768 DBGINFO(("%s call tty_wait_until_sent\n", info
->device_name
));
769 tty_wait_until_sent(tty
, info
->closing_wait
);
772 if (info
->flags
& ASYNC_INITIALIZED
)
773 wait_until_sent(tty
, info
->timeout
);
774 if (tty
->driver
->flush_buffer
)
775 tty
->driver
->flush_buffer(tty
);
776 tty_ldisc_flush(tty
);
783 if (info
->blocked_open
) {
784 if (info
->close_delay
) {
785 msleep_interruptible(jiffies_to_msecs(info
->close_delay
));
787 wake_up_interruptible(&info
->open_wait
);
790 info
->flags
&= ~(ASYNC_NORMAL_ACTIVE
|ASYNC_CLOSING
);
792 wake_up_interruptible(&info
->close_wait
);
795 DBGINFO(("%s close exit, count=%d\n", tty
->driver
->name
, info
->count
));
798 static void hangup(struct tty_struct
*tty
)
800 struct slgt_info
*info
= tty
->driver_data
;
802 if (sanity_check(info
, tty
->name
, "hangup"))
804 DBGINFO(("%s hangup\n", info
->device_name
));
810 info
->flags
&= ~ASYNC_NORMAL_ACTIVE
;
813 wake_up_interruptible(&info
->open_wait
);
816 static void set_termios(struct tty_struct
*tty
, struct ktermios
*old_termios
)
818 struct slgt_info
*info
= tty
->driver_data
;
821 DBGINFO(("%s set_termios\n", tty
->driver
->name
));
825 /* Handle transition to B0 status */
826 if (old_termios
->c_cflag
& CBAUD
&&
827 !(tty
->termios
->c_cflag
& CBAUD
)) {
828 info
->signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
829 spin_lock_irqsave(&info
->lock
,flags
);
831 spin_unlock_irqrestore(&info
->lock
,flags
);
834 /* Handle transition away from B0 status */
835 if (!(old_termios
->c_cflag
& CBAUD
) &&
836 tty
->termios
->c_cflag
& CBAUD
) {
837 info
->signals
|= SerialSignal_DTR
;
838 if (!(tty
->termios
->c_cflag
& CRTSCTS
) ||
839 !test_bit(TTY_THROTTLED
, &tty
->flags
)) {
840 info
->signals
|= SerialSignal_RTS
;
842 spin_lock_irqsave(&info
->lock
,flags
);
844 spin_unlock_irqrestore(&info
->lock
,flags
);
847 /* Handle turning off CRTSCTS */
848 if (old_termios
->c_cflag
& CRTSCTS
&&
849 !(tty
->termios
->c_cflag
& CRTSCTS
)) {
855 static int write(struct tty_struct
*tty
,
856 const unsigned char *buf
, int count
)
859 struct slgt_info
*info
= tty
->driver_data
;
862 if (sanity_check(info
, tty
->name
, "write"))
864 DBGINFO(("%s write count=%d\n", info
->device_name
, count
));
869 if (count
> info
->max_frame_size
) {
877 if (info
->params
.mode
== MGSL_MODE_RAW
||
878 info
->params
.mode
== MGSL_MODE_MONOSYNC
||
879 info
->params
.mode
== MGSL_MODE_BISYNC
) {
880 unsigned int bufs_needed
= (count
/DMABUFSIZE
);
881 unsigned int bufs_free
= free_tbuf_count(info
);
882 if (count
% DMABUFSIZE
)
884 if (bufs_needed
> bufs_free
)
889 if (info
->tx_count
) {
890 /* send accumulated data from send_char() calls */
891 /* as frame and wait before accepting more data. */
892 tx_load(info
, info
->tx_buf
, info
->tx_count
);
897 ret
= info
->tx_count
= count
;
898 tx_load(info
, buf
, count
);
902 if (info
->tx_count
&& !tty
->stopped
&& !tty
->hw_stopped
) {
903 spin_lock_irqsave(&info
->lock
,flags
);
904 if (!info
->tx_active
)
908 spin_unlock_irqrestore(&info
->lock
,flags
);
912 DBGINFO(("%s write rc=%d\n", info
->device_name
, ret
));
916 static void put_char(struct tty_struct
*tty
, unsigned char ch
)
918 struct slgt_info
*info
= tty
->driver_data
;
921 if (sanity_check(info
, tty
->name
, "put_char"))
923 DBGINFO(("%s put_char(%d)\n", info
->device_name
, ch
));
926 spin_lock_irqsave(&info
->lock
,flags
);
927 if (!info
->tx_active
&& (info
->tx_count
< info
->max_frame_size
))
928 info
->tx_buf
[info
->tx_count
++] = ch
;
929 spin_unlock_irqrestore(&info
->lock
,flags
);
932 static void send_xchar(struct tty_struct
*tty
, char ch
)
934 struct slgt_info
*info
= tty
->driver_data
;
937 if (sanity_check(info
, tty
->name
, "send_xchar"))
939 DBGINFO(("%s send_xchar(%d)\n", info
->device_name
, ch
));
942 spin_lock_irqsave(&info
->lock
,flags
);
943 if (!info
->tx_enabled
)
945 spin_unlock_irqrestore(&info
->lock
,flags
);
949 static void wait_until_sent(struct tty_struct
*tty
, int timeout
)
951 struct slgt_info
*info
= tty
->driver_data
;
952 unsigned long orig_jiffies
, char_time
;
956 if (sanity_check(info
, tty
->name
, "wait_until_sent"))
958 DBGINFO(("%s wait_until_sent entry\n", info
->device_name
));
959 if (!(info
->flags
& ASYNC_INITIALIZED
))
962 orig_jiffies
= jiffies
;
964 /* Set check interval to 1/5 of estimated time to
965 * send a character, and make it at least 1. The check
966 * interval should also be less than the timeout.
967 * Note: use tight timings here to satisfy the NIST-PCTS.
970 if (info
->params
.data_rate
) {
971 char_time
= info
->timeout
/(32 * 5);
978 char_time
= min_t(unsigned long, char_time
, timeout
);
980 while (info
->tx_active
) {
981 msleep_interruptible(jiffies_to_msecs(char_time
));
982 if (signal_pending(current
))
984 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
989 DBGINFO(("%s wait_until_sent exit\n", info
->device_name
));
992 static int write_room(struct tty_struct
*tty
)
994 struct slgt_info
*info
= tty
->driver_data
;
997 if (sanity_check(info
, tty
->name
, "write_room"))
999 ret
= (info
->tx_active
) ? 0 : HDLC_MAX_FRAME_SIZE
;
1000 DBGINFO(("%s write_room=%d\n", info
->device_name
, ret
));
1004 static void flush_chars(struct tty_struct
*tty
)
1006 struct slgt_info
*info
= tty
->driver_data
;
1007 unsigned long flags
;
1009 if (sanity_check(info
, tty
->name
, "flush_chars"))
1011 DBGINFO(("%s flush_chars entry tx_count=%d\n", info
->device_name
, info
->tx_count
));
1013 if (info
->tx_count
<= 0 || tty
->stopped
||
1014 tty
->hw_stopped
|| !info
->tx_buf
)
1017 DBGINFO(("%s flush_chars start transmit\n", info
->device_name
));
1019 spin_lock_irqsave(&info
->lock
,flags
);
1020 if (!info
->tx_active
&& info
->tx_count
) {
1021 tx_load(info
, info
->tx_buf
,info
->tx_count
);
1024 spin_unlock_irqrestore(&info
->lock
,flags
);
1027 static void flush_buffer(struct tty_struct
*tty
)
1029 struct slgt_info
*info
= tty
->driver_data
;
1030 unsigned long flags
;
1032 if (sanity_check(info
, tty
->name
, "flush_buffer"))
1034 DBGINFO(("%s flush_buffer\n", info
->device_name
));
1036 spin_lock_irqsave(&info
->lock
,flags
);
1037 if (!info
->tx_active
)
1039 spin_unlock_irqrestore(&info
->lock
,flags
);
1045 * throttle (stop) transmitter
1047 static void tx_hold(struct tty_struct
*tty
)
1049 struct slgt_info
*info
= tty
->driver_data
;
1050 unsigned long flags
;
1052 if (sanity_check(info
, tty
->name
, "tx_hold"))
1054 DBGINFO(("%s tx_hold\n", info
->device_name
));
1055 spin_lock_irqsave(&info
->lock
,flags
);
1056 if (info
->tx_enabled
&& info
->params
.mode
== MGSL_MODE_ASYNC
)
1058 spin_unlock_irqrestore(&info
->lock
,flags
);
1062 * release (start) transmitter
1064 static void tx_release(struct tty_struct
*tty
)
1066 struct slgt_info
*info
= tty
->driver_data
;
1067 unsigned long flags
;
1069 if (sanity_check(info
, tty
->name
, "tx_release"))
1071 DBGINFO(("%s tx_release\n", info
->device_name
));
1072 spin_lock_irqsave(&info
->lock
,flags
);
1073 if (!info
->tx_active
&& info
->tx_count
) {
1074 tx_load(info
, info
->tx_buf
, info
->tx_count
);
1077 spin_unlock_irqrestore(&info
->lock
,flags
);
1081 * Service an IOCTL request
1085 * tty pointer to tty instance data
1086 * file pointer to associated file object for device
1087 * cmd IOCTL command code
1088 * arg command argument/context
1090 * Return 0 if success, otherwise error code
1092 static int ioctl(struct tty_struct
*tty
, struct file
*file
,
1093 unsigned int cmd
, unsigned long arg
)
1095 struct slgt_info
*info
= tty
->driver_data
;
1096 struct mgsl_icount cnow
; /* kernel counter temps */
1097 struct serial_icounter_struct __user
*p_cuser
; /* user space */
1098 unsigned long flags
;
1099 void __user
*argp
= (void __user
*)arg
;
1101 if (sanity_check(info
, tty
->name
, "ioctl"))
1103 DBGINFO(("%s ioctl() cmd=%08X\n", info
->device_name
, cmd
));
1105 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
1106 (cmd
!= TIOCMIWAIT
) && (cmd
!= TIOCGICOUNT
)) {
1107 if (tty
->flags
& (1 << TTY_IO_ERROR
))
1112 case MGSL_IOCGPARAMS
:
1113 return get_params(info
, argp
);
1114 case MGSL_IOCSPARAMS
:
1115 return set_params(info
, argp
);
1116 case MGSL_IOCGTXIDLE
:
1117 return get_txidle(info
, argp
);
1118 case MGSL_IOCSTXIDLE
:
1119 return set_txidle(info
, (int)arg
);
1120 case MGSL_IOCTXENABLE
:
1121 return tx_enable(info
, (int)arg
);
1122 case MGSL_IOCRXENABLE
:
1123 return rx_enable(info
, (int)arg
);
1124 case MGSL_IOCTXABORT
:
1125 return tx_abort(info
);
1126 case MGSL_IOCGSTATS
:
1127 return get_stats(info
, argp
);
1128 case MGSL_IOCWAITEVENT
:
1129 return wait_mgsl_event(info
, argp
);
1131 return modem_input_wait(info
,(int)arg
);
1133 return get_interface(info
, argp
);
1135 return set_interface(info
,(int)arg
);
1137 return set_gpio(info
, argp
);
1139 return get_gpio(info
, argp
);
1140 case MGSL_IOCWAITGPIO
:
1141 return wait_gpio(info
, argp
);
1143 spin_lock_irqsave(&info
->lock
,flags
);
1144 cnow
= info
->icount
;
1145 spin_unlock_irqrestore(&info
->lock
,flags
);
1147 if (put_user(cnow
.cts
, &p_cuser
->cts
) ||
1148 put_user(cnow
.dsr
, &p_cuser
->dsr
) ||
1149 put_user(cnow
.rng
, &p_cuser
->rng
) ||
1150 put_user(cnow
.dcd
, &p_cuser
->dcd
) ||
1151 put_user(cnow
.rx
, &p_cuser
->rx
) ||
1152 put_user(cnow
.tx
, &p_cuser
->tx
) ||
1153 put_user(cnow
.frame
, &p_cuser
->frame
) ||
1154 put_user(cnow
.overrun
, &p_cuser
->overrun
) ||
1155 put_user(cnow
.parity
, &p_cuser
->parity
) ||
1156 put_user(cnow
.brk
, &p_cuser
->brk
) ||
1157 put_user(cnow
.buf_overrun
, &p_cuser
->buf_overrun
))
1161 return -ENOIOCTLCMD
;
1167 * support for 32 bit ioctl calls on 64 bit systems
1169 #ifdef CONFIG_COMPAT
1170 static long get_params32(struct slgt_info
*info
, struct MGSL_PARAMS32 __user
*user_params
)
1172 struct MGSL_PARAMS32 tmp_params
;
1174 DBGINFO(("%s get_params32\n", info
->device_name
));
1175 tmp_params
.mode
= (compat_ulong_t
)info
->params
.mode
;
1176 tmp_params
.loopback
= info
->params
.loopback
;
1177 tmp_params
.flags
= info
->params
.flags
;
1178 tmp_params
.encoding
= info
->params
.encoding
;
1179 tmp_params
.clock_speed
= (compat_ulong_t
)info
->params
.clock_speed
;
1180 tmp_params
.addr_filter
= info
->params
.addr_filter
;
1181 tmp_params
.crc_type
= info
->params
.crc_type
;
1182 tmp_params
.preamble_length
= info
->params
.preamble_length
;
1183 tmp_params
.preamble
= info
->params
.preamble
;
1184 tmp_params
.data_rate
= (compat_ulong_t
)info
->params
.data_rate
;
1185 tmp_params
.data_bits
= info
->params
.data_bits
;
1186 tmp_params
.stop_bits
= info
->params
.stop_bits
;
1187 tmp_params
.parity
= info
->params
.parity
;
1188 if (copy_to_user(user_params
, &tmp_params
, sizeof(struct MGSL_PARAMS32
)))
1193 static long set_params32(struct slgt_info
*info
, struct MGSL_PARAMS32 __user
*new_params
)
1195 struct MGSL_PARAMS32 tmp_params
;
1197 DBGINFO(("%s set_params32\n", info
->device_name
));
1198 if (copy_from_user(&tmp_params
, new_params
, sizeof(struct MGSL_PARAMS32
)))
1201 spin_lock(&info
->lock
);
1202 info
->params
.mode
= tmp_params
.mode
;
1203 info
->params
.loopback
= tmp_params
.loopback
;
1204 info
->params
.flags
= tmp_params
.flags
;
1205 info
->params
.encoding
= tmp_params
.encoding
;
1206 info
->params
.clock_speed
= tmp_params
.clock_speed
;
1207 info
->params
.addr_filter
= tmp_params
.addr_filter
;
1208 info
->params
.crc_type
= tmp_params
.crc_type
;
1209 info
->params
.preamble_length
= tmp_params
.preamble_length
;
1210 info
->params
.preamble
= tmp_params
.preamble
;
1211 info
->params
.data_rate
= tmp_params
.data_rate
;
1212 info
->params
.data_bits
= tmp_params
.data_bits
;
1213 info
->params
.stop_bits
= tmp_params
.stop_bits
;
1214 info
->params
.parity
= tmp_params
.parity
;
1215 spin_unlock(&info
->lock
);
1217 change_params(info
);
1222 static long slgt_compat_ioctl(struct tty_struct
*tty
, struct file
*file
,
1223 unsigned int cmd
, unsigned long arg
)
1225 struct slgt_info
*info
= tty
->driver_data
;
1226 int rc
= -ENOIOCTLCMD
;
1228 if (sanity_check(info
, tty
->name
, "compat_ioctl"))
1230 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info
->device_name
, cmd
));
1234 case MGSL_IOCSPARAMS32
:
1235 rc
= set_params32(info
, compat_ptr(arg
));
1238 case MGSL_IOCGPARAMS32
:
1239 rc
= get_params32(info
, compat_ptr(arg
));
1242 case MGSL_IOCGPARAMS
:
1243 case MGSL_IOCSPARAMS
:
1244 case MGSL_IOCGTXIDLE
:
1245 case MGSL_IOCGSTATS
:
1246 case MGSL_IOCWAITEVENT
:
1250 case MGSL_IOCWAITGPIO
:
1252 rc
= ioctl(tty
, file
, cmd
, (unsigned long)(compat_ptr(arg
)));
1255 case MGSL_IOCSTXIDLE
:
1256 case MGSL_IOCTXENABLE
:
1257 case MGSL_IOCRXENABLE
:
1258 case MGSL_IOCTXABORT
:
1261 rc
= ioctl(tty
, file
, cmd
, arg
);
1265 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info
->device_name
, cmd
, rc
));
1269 #define slgt_compat_ioctl NULL
1270 #endif /* ifdef CONFIG_COMPAT */
1275 static inline int line_info(char *buf
, struct slgt_info
*info
)
1279 unsigned long flags
;
1281 ret
= sprintf(buf
, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1282 info
->device_name
, info
->phys_reg_addr
,
1283 info
->irq_level
, info
->max_frame_size
);
1285 /* output current serial signal states */
1286 spin_lock_irqsave(&info
->lock
,flags
);
1288 spin_unlock_irqrestore(&info
->lock
,flags
);
1292 if (info
->signals
& SerialSignal_RTS
)
1293 strcat(stat_buf
, "|RTS");
1294 if (info
->signals
& SerialSignal_CTS
)
1295 strcat(stat_buf
, "|CTS");
1296 if (info
->signals
& SerialSignal_DTR
)
1297 strcat(stat_buf
, "|DTR");
1298 if (info
->signals
& SerialSignal_DSR
)
1299 strcat(stat_buf
, "|DSR");
1300 if (info
->signals
& SerialSignal_DCD
)
1301 strcat(stat_buf
, "|CD");
1302 if (info
->signals
& SerialSignal_RI
)
1303 strcat(stat_buf
, "|RI");
1305 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
1306 ret
+= sprintf(buf
+ret
, "\tHDLC txok:%d rxok:%d",
1307 info
->icount
.txok
, info
->icount
.rxok
);
1308 if (info
->icount
.txunder
)
1309 ret
+= sprintf(buf
+ret
, " txunder:%d", info
->icount
.txunder
);
1310 if (info
->icount
.txabort
)
1311 ret
+= sprintf(buf
+ret
, " txabort:%d", info
->icount
.txabort
);
1312 if (info
->icount
.rxshort
)
1313 ret
+= sprintf(buf
+ret
, " rxshort:%d", info
->icount
.rxshort
);
1314 if (info
->icount
.rxlong
)
1315 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxlong
);
1316 if (info
->icount
.rxover
)
1317 ret
+= sprintf(buf
+ret
, " rxover:%d", info
->icount
.rxover
);
1318 if (info
->icount
.rxcrc
)
1319 ret
+= sprintf(buf
+ret
, " rxcrc:%d", info
->icount
.rxcrc
);
1321 ret
+= sprintf(buf
+ret
, "\tASYNC tx:%d rx:%d",
1322 info
->icount
.tx
, info
->icount
.rx
);
1323 if (info
->icount
.frame
)
1324 ret
+= sprintf(buf
+ret
, " fe:%d", info
->icount
.frame
);
1325 if (info
->icount
.parity
)
1326 ret
+= sprintf(buf
+ret
, " pe:%d", info
->icount
.parity
);
1327 if (info
->icount
.brk
)
1328 ret
+= sprintf(buf
+ret
, " brk:%d", info
->icount
.brk
);
1329 if (info
->icount
.overrun
)
1330 ret
+= sprintf(buf
+ret
, " oe:%d", info
->icount
.overrun
);
1333 /* Append serial signal status to end */
1334 ret
+= sprintf(buf
+ret
, " %s\n", stat_buf
+1);
1336 ret
+= sprintf(buf
+ret
, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1337 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
1343 /* Called to print information about devices
1345 static int read_proc(char *page
, char **start
, off_t off
, int count
,
1346 int *eof
, void *data
)
1350 struct slgt_info
*info
;
1352 len
+= sprintf(page
, "synclink_gt driver:%s\n", driver_version
);
1354 info
= slgt_device_list
;
1356 l
= line_info(page
+ len
, info
);
1358 if (len
+begin
> off
+count
)
1360 if (len
+begin
< off
) {
1364 info
= info
->next_device
;
1369 if (off
>= len
+begin
)
1371 *start
= page
+ (off
-begin
);
1372 return ((count
< begin
+len
-off
) ? count
: begin
+len
-off
);
1376 * return count of bytes in transmit buffer
1378 static int chars_in_buffer(struct tty_struct
*tty
)
1380 struct slgt_info
*info
= tty
->driver_data
;
1381 if (sanity_check(info
, tty
->name
, "chars_in_buffer"))
1383 DBGINFO(("%s chars_in_buffer()=%d\n", info
->device_name
, info
->tx_count
));
1384 return info
->tx_count
;
1388 * signal remote device to throttle send data (our receive data)
1390 static void throttle(struct tty_struct
* tty
)
1392 struct slgt_info
*info
= tty
->driver_data
;
1393 unsigned long flags
;
1395 if (sanity_check(info
, tty
->name
, "throttle"))
1397 DBGINFO(("%s throttle\n", info
->device_name
));
1399 send_xchar(tty
, STOP_CHAR(tty
));
1400 if (tty
->termios
->c_cflag
& CRTSCTS
) {
1401 spin_lock_irqsave(&info
->lock
,flags
);
1402 info
->signals
&= ~SerialSignal_RTS
;
1404 spin_unlock_irqrestore(&info
->lock
,flags
);
1409 * signal remote device to stop throttling send data (our receive data)
1411 static void unthrottle(struct tty_struct
* tty
)
1413 struct slgt_info
*info
= tty
->driver_data
;
1414 unsigned long flags
;
1416 if (sanity_check(info
, tty
->name
, "unthrottle"))
1418 DBGINFO(("%s unthrottle\n", info
->device_name
));
1423 send_xchar(tty
, START_CHAR(tty
));
1425 if (tty
->termios
->c_cflag
& CRTSCTS
) {
1426 spin_lock_irqsave(&info
->lock
,flags
);
1427 info
->signals
|= SerialSignal_RTS
;
1429 spin_unlock_irqrestore(&info
->lock
,flags
);
1434 * set or clear transmit break condition
1435 * break_state -1=set break condition, 0=clear
1437 static void set_break(struct tty_struct
*tty
, int break_state
)
1439 struct slgt_info
*info
= tty
->driver_data
;
1440 unsigned short value
;
1441 unsigned long flags
;
1443 if (sanity_check(info
, tty
->name
, "set_break"))
1445 DBGINFO(("%s set_break(%d)\n", info
->device_name
, break_state
));
1447 spin_lock_irqsave(&info
->lock
,flags
);
1448 value
= rd_reg16(info
, TCR
);
1449 if (break_state
== -1)
1453 wr_reg16(info
, TCR
, value
);
1454 spin_unlock_irqrestore(&info
->lock
,flags
);
1457 #if SYNCLINK_GENERIC_HDLC
1460 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1461 * set encoding and frame check sequence (FCS) options
1463 * dev pointer to network device structure
1464 * encoding serial encoding setting
1465 * parity FCS setting
1467 * returns 0 if success, otherwise error code
1469 static int hdlcdev_attach(struct net_device
*dev
, unsigned short encoding
,
1470 unsigned short parity
)
1472 struct slgt_info
*info
= dev_to_port(dev
);
1473 unsigned char new_encoding
;
1474 unsigned short new_crctype
;
1476 /* return error if TTY interface open */
1480 DBGINFO(("%s hdlcdev_attach\n", info
->device_name
));
1484 case ENCODING_NRZ
: new_encoding
= HDLC_ENCODING_NRZ
; break;
1485 case ENCODING_NRZI
: new_encoding
= HDLC_ENCODING_NRZI_SPACE
; break;
1486 case ENCODING_FM_MARK
: new_encoding
= HDLC_ENCODING_BIPHASE_MARK
; break;
1487 case ENCODING_FM_SPACE
: new_encoding
= HDLC_ENCODING_BIPHASE_SPACE
; break;
1488 case ENCODING_MANCHESTER
: new_encoding
= HDLC_ENCODING_BIPHASE_LEVEL
; break;
1489 default: return -EINVAL
;
1494 case PARITY_NONE
: new_crctype
= HDLC_CRC_NONE
; break;
1495 case PARITY_CRC16_PR1_CCITT
: new_crctype
= HDLC_CRC_16_CCITT
; break;
1496 case PARITY_CRC32_PR1_CCITT
: new_crctype
= HDLC_CRC_32_CCITT
; break;
1497 default: return -EINVAL
;
1500 info
->params
.encoding
= new_encoding
;
1501 info
->params
.crc_type
= new_crctype
;
1503 /* if network interface up, reprogram hardware */
1511 * called by generic HDLC layer to send frame
1513 * skb socket buffer containing HDLC frame
1514 * dev pointer to network device structure
1516 * returns 0 if success, otherwise error code
1518 static int hdlcdev_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1520 struct slgt_info
*info
= dev_to_port(dev
);
1521 struct net_device_stats
*stats
= hdlc_stats(dev
);
1522 unsigned long flags
;
1524 DBGINFO(("%s hdlc_xmit\n", dev
->name
));
1526 /* stop sending until this frame completes */
1527 netif_stop_queue(dev
);
1529 /* copy data to device buffers */
1530 info
->tx_count
= skb
->len
;
1531 tx_load(info
, skb
->data
, skb
->len
);
1533 /* update network statistics */
1534 stats
->tx_packets
++;
1535 stats
->tx_bytes
+= skb
->len
;
1537 /* done with socket buffer, so free it */
1540 /* save start time for transmit timeout detection */
1541 dev
->trans_start
= jiffies
;
1543 /* start hardware transmitter if necessary */
1544 spin_lock_irqsave(&info
->lock
,flags
);
1545 if (!info
->tx_active
)
1547 spin_unlock_irqrestore(&info
->lock
,flags
);
1553 * called by network layer when interface enabled
1554 * claim resources and initialize hardware
1556 * dev pointer to network device structure
1558 * returns 0 if success, otherwise error code
1560 static int hdlcdev_open(struct net_device
*dev
)
1562 struct slgt_info
*info
= dev_to_port(dev
);
1564 unsigned long flags
;
1566 if (!try_module_get(THIS_MODULE
))
1569 DBGINFO(("%s hdlcdev_open\n", dev
->name
));
1571 /* generic HDLC layer open processing */
1572 if ((rc
= hdlc_open(dev
)))
1575 /* arbitrate between network and tty opens */
1576 spin_lock_irqsave(&info
->netlock
, flags
);
1577 if (info
->count
!= 0 || info
->netcount
!= 0) {
1578 DBGINFO(("%s hdlc_open busy\n", dev
->name
));
1579 spin_unlock_irqrestore(&info
->netlock
, flags
);
1583 spin_unlock_irqrestore(&info
->netlock
, flags
);
1585 /* claim resources and init adapter */
1586 if ((rc
= startup(info
)) != 0) {
1587 spin_lock_irqsave(&info
->netlock
, flags
);
1589 spin_unlock_irqrestore(&info
->netlock
, flags
);
1593 /* assert DTR and RTS, apply hardware settings */
1594 info
->signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
1597 /* enable network layer transmit */
1598 dev
->trans_start
= jiffies
;
1599 netif_start_queue(dev
);
1601 /* inform generic HDLC layer of current DCD status */
1602 spin_lock_irqsave(&info
->lock
, flags
);
1604 spin_unlock_irqrestore(&info
->lock
, flags
);
1605 if (info
->signals
& SerialSignal_DCD
)
1606 netif_carrier_on(dev
);
1608 netif_carrier_off(dev
);
1613 * called by network layer when interface is disabled
1614 * shutdown hardware and release resources
1616 * dev pointer to network device structure
1618 * returns 0 if success, otherwise error code
1620 static int hdlcdev_close(struct net_device
*dev
)
1622 struct slgt_info
*info
= dev_to_port(dev
);
1623 unsigned long flags
;
1625 DBGINFO(("%s hdlcdev_close\n", dev
->name
));
1627 netif_stop_queue(dev
);
1629 /* shutdown adapter and release resources */
1634 spin_lock_irqsave(&info
->netlock
, flags
);
1636 spin_unlock_irqrestore(&info
->netlock
, flags
);
1638 module_put(THIS_MODULE
);
1643 * called by network layer to process IOCTL call to network device
1645 * dev pointer to network device structure
1646 * ifr pointer to network interface request structure
1647 * cmd IOCTL command code
1649 * returns 0 if success, otherwise error code
1651 static int hdlcdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1653 const size_t size
= sizeof(sync_serial_settings
);
1654 sync_serial_settings new_line
;
1655 sync_serial_settings __user
*line
= ifr
->ifr_settings
.ifs_ifsu
.sync
;
1656 struct slgt_info
*info
= dev_to_port(dev
);
1659 DBGINFO(("%s hdlcdev_ioctl\n", dev
->name
));
1661 /* return error if TTY interface open */
1665 if (cmd
!= SIOCWANDEV
)
1666 return hdlc_ioctl(dev
, ifr
, cmd
);
1668 switch(ifr
->ifr_settings
.type
) {
1669 case IF_GET_IFACE
: /* return current sync_serial_settings */
1671 ifr
->ifr_settings
.type
= IF_IFACE_SYNC_SERIAL
;
1672 if (ifr
->ifr_settings
.size
< size
) {
1673 ifr
->ifr_settings
.size
= size
; /* data size wanted */
1677 flags
= info
->params
.flags
& (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1678 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1679 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1680 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
1683 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
): new_line
.clock_type
= CLOCK_EXT
; break;
1684 case (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_INT
; break;
1685 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_TXINT
; break;
1686 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
): new_line
.clock_type
= CLOCK_TXFROMRX
; break;
1687 default: new_line
.clock_type
= CLOCK_DEFAULT
;
1690 new_line
.clock_rate
= info
->params
.clock_speed
;
1691 new_line
.loopback
= info
->params
.loopback
? 1:0;
1693 if (copy_to_user(line
, &new_line
, size
))
1697 case IF_IFACE_SYNC_SERIAL
: /* set sync_serial_settings */
1699 if(!capable(CAP_NET_ADMIN
))
1701 if (copy_from_user(&new_line
, line
, size
))
1704 switch (new_line
.clock_type
)
1706 case CLOCK_EXT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
; break;
1707 case CLOCK_TXFROMRX
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
; break;
1708 case CLOCK_INT
: flags
= HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
; break;
1709 case CLOCK_TXINT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
; break;
1710 case CLOCK_DEFAULT
: flags
= info
->params
.flags
&
1711 (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1712 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1713 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1714 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
); break;
1715 default: return -EINVAL
;
1718 if (new_line
.loopback
!= 0 && new_line
.loopback
!= 1)
1721 info
->params
.flags
&= ~(HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1722 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1723 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1724 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
1725 info
->params
.flags
|= flags
;
1727 info
->params
.loopback
= new_line
.loopback
;
1729 if (flags
& (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
))
1730 info
->params
.clock_speed
= new_line
.clock_rate
;
1732 info
->params
.clock_speed
= 0;
1734 /* if network interface up, reprogram hardware */
1740 return hdlc_ioctl(dev
, ifr
, cmd
);
1745 * called by network layer when transmit timeout is detected
1747 * dev pointer to network device structure
1749 static void hdlcdev_tx_timeout(struct net_device
*dev
)
1751 struct slgt_info
*info
= dev_to_port(dev
);
1752 struct net_device_stats
*stats
= hdlc_stats(dev
);
1753 unsigned long flags
;
1755 DBGINFO(("%s hdlcdev_tx_timeout\n", dev
->name
));
1758 stats
->tx_aborted_errors
++;
1760 spin_lock_irqsave(&info
->lock
,flags
);
1762 spin_unlock_irqrestore(&info
->lock
,flags
);
1764 netif_wake_queue(dev
);
1768 * called by device driver when transmit completes
1769 * reenable network layer transmit if stopped
1771 * info pointer to device instance information
1773 static void hdlcdev_tx_done(struct slgt_info
*info
)
1775 if (netif_queue_stopped(info
->netdev
))
1776 netif_wake_queue(info
->netdev
);
1780 * called by device driver when frame received
1781 * pass frame to network layer
1783 * info pointer to device instance information
1784 * buf pointer to buffer contianing frame data
1785 * size count of data bytes in buf
1787 static void hdlcdev_rx(struct slgt_info
*info
, char *buf
, int size
)
1789 struct sk_buff
*skb
= dev_alloc_skb(size
);
1790 struct net_device
*dev
= info
->netdev
;
1791 struct net_device_stats
*stats
= hdlc_stats(dev
);
1793 DBGINFO(("%s hdlcdev_rx\n", dev
->name
));
1796 DBGERR(("%s: can't alloc skb, drop packet\n", dev
->name
));
1797 stats
->rx_dropped
++;
1801 memcpy(skb_put(skb
, size
),buf
,size
);
1803 skb
->protocol
= hdlc_type_trans(skb
, info
->netdev
);
1805 stats
->rx_packets
++;
1806 stats
->rx_bytes
+= size
;
1810 info
->netdev
->last_rx
= jiffies
;
1814 * called by device driver when adding device instance
1815 * do generic HDLC initialization
1817 * info pointer to device instance information
1819 * returns 0 if success, otherwise error code
1821 static int hdlcdev_init(struct slgt_info
*info
)
1824 struct net_device
*dev
;
1827 /* allocate and initialize network and HDLC layer objects */
1829 if (!(dev
= alloc_hdlcdev(info
))) {
1830 printk(KERN_ERR
"%s hdlc device alloc failure\n", info
->device_name
);
1834 /* for network layer reporting purposes only */
1835 dev
->mem_start
= info
->phys_reg_addr
;
1836 dev
->mem_end
= info
->phys_reg_addr
+ SLGT_REG_SIZE
- 1;
1837 dev
->irq
= info
->irq_level
;
1839 /* network layer callbacks and settings */
1840 dev
->do_ioctl
= hdlcdev_ioctl
;
1841 dev
->open
= hdlcdev_open
;
1842 dev
->stop
= hdlcdev_close
;
1843 dev
->tx_timeout
= hdlcdev_tx_timeout
;
1844 dev
->watchdog_timeo
= 10*HZ
;
1845 dev
->tx_queue_len
= 50;
1847 /* generic HDLC layer callbacks and settings */
1848 hdlc
= dev_to_hdlc(dev
);
1849 hdlc
->attach
= hdlcdev_attach
;
1850 hdlc
->xmit
= hdlcdev_xmit
;
1852 /* register objects with HDLC layer */
1853 if ((rc
= register_hdlc_device(dev
))) {
1854 printk(KERN_WARNING
"%s:unable to register hdlc device\n",__FILE__
);
1864 * called by device driver when removing device instance
1865 * do generic HDLC cleanup
1867 * info pointer to device instance information
1869 static void hdlcdev_exit(struct slgt_info
*info
)
1871 unregister_hdlc_device(info
->netdev
);
1872 free_netdev(info
->netdev
);
1873 info
->netdev
= NULL
;
1876 #endif /* ifdef CONFIG_HDLC */
1879 * get async data from rx DMA buffers
1881 static void rx_async(struct slgt_info
*info
)
1883 struct tty_struct
*tty
= info
->tty
;
1884 struct mgsl_icount
*icount
= &info
->icount
;
1885 unsigned int start
, end
;
1887 unsigned char status
;
1888 struct slgt_desc
*bufs
= info
->rbufs
;
1894 start
= end
= info
->rbuf_current
;
1896 while(desc_complete(bufs
[end
])) {
1897 count
= desc_count(bufs
[end
]) - info
->rbuf_index
;
1898 p
= bufs
[end
].buf
+ info
->rbuf_index
;
1900 DBGISR(("%s rx_async count=%d\n", info
->device_name
, count
));
1901 DBGDATA(info
, p
, count
, "rx");
1903 for(i
=0 ; i
< count
; i
+=2, p
+=2) {
1909 if ((status
= *(p
+1) & (BIT1
+ BIT0
))) {
1912 else if (status
& BIT0
)
1914 /* discard char if tty control flags say so */
1915 if (status
& info
->ignore_status_mask
)
1919 else if (status
& BIT0
)
1923 tty_insert_flip_char(tty
, ch
, stat
);
1929 /* receive buffer not completed */
1930 info
->rbuf_index
+= i
;
1931 mod_timer(&info
->rx_timer
, jiffies
+ 1);
1935 info
->rbuf_index
= 0;
1936 free_rbufs(info
, end
, end
);
1938 if (++end
== info
->rbuf_count
)
1941 /* if entire list searched then no frame available */
1947 tty_flip_buffer_push(tty
);
1951 * return next bottom half action to perform
1953 static int bh_action(struct slgt_info
*info
)
1955 unsigned long flags
;
1958 spin_lock_irqsave(&info
->lock
,flags
);
1960 if (info
->pending_bh
& BH_RECEIVE
) {
1961 info
->pending_bh
&= ~BH_RECEIVE
;
1963 } else if (info
->pending_bh
& BH_TRANSMIT
) {
1964 info
->pending_bh
&= ~BH_TRANSMIT
;
1966 } else if (info
->pending_bh
& BH_STATUS
) {
1967 info
->pending_bh
&= ~BH_STATUS
;
1970 /* Mark BH routine as complete */
1971 info
->bh_running
= false;
1972 info
->bh_requested
= false;
1976 spin_unlock_irqrestore(&info
->lock
,flags
);
1982 * perform bottom half processing
1984 static void bh_handler(struct work_struct
*work
)
1986 struct slgt_info
*info
= container_of(work
, struct slgt_info
, task
);
1991 info
->bh_running
= true;
1993 while((action
= bh_action(info
))) {
1996 DBGBH(("%s bh receive\n", info
->device_name
));
1997 switch(info
->params
.mode
) {
1998 case MGSL_MODE_ASYNC
:
2001 case MGSL_MODE_HDLC
:
2002 while(rx_get_frame(info
));
2005 case MGSL_MODE_MONOSYNC
:
2006 case MGSL_MODE_BISYNC
:
2007 while(rx_get_buf(info
));
2010 /* restart receiver if rx DMA buffers exhausted */
2011 if (info
->rx_restart
)
2018 DBGBH(("%s bh status\n", info
->device_name
));
2019 info
->ri_chkcount
= 0;
2020 info
->dsr_chkcount
= 0;
2021 info
->dcd_chkcount
= 0;
2022 info
->cts_chkcount
= 0;
2025 DBGBH(("%s unknown action\n", info
->device_name
));
2029 DBGBH(("%s bh_handler exit\n", info
->device_name
));
2032 static void bh_transmit(struct slgt_info
*info
)
2034 struct tty_struct
*tty
= info
->tty
;
2036 DBGBH(("%s bh_transmit\n", info
->device_name
));
2041 static void dsr_change(struct slgt_info
*info
, unsigned short status
)
2043 if (status
& BIT3
) {
2044 info
->signals
|= SerialSignal_DSR
;
2045 info
->input_signal_events
.dsr_up
++;
2047 info
->signals
&= ~SerialSignal_DSR
;
2048 info
->input_signal_events
.dsr_down
++;
2050 DBGISR(("dsr_change %s signals=%04X\n", info
->device_name
, info
->signals
));
2051 if ((info
->dsr_chkcount
)++ == IO_PIN_SHUTDOWN_LIMIT
) {
2052 slgt_irq_off(info
, IRQ_DSR
);
2056 wake_up_interruptible(&info
->status_event_wait_q
);
2057 wake_up_interruptible(&info
->event_wait_q
);
2058 info
->pending_bh
|= BH_STATUS
;
2061 static void cts_change(struct slgt_info
*info
, unsigned short status
)
2063 if (status
& BIT2
) {
2064 info
->signals
|= SerialSignal_CTS
;
2065 info
->input_signal_events
.cts_up
++;
2067 info
->signals
&= ~SerialSignal_CTS
;
2068 info
->input_signal_events
.cts_down
++;
2070 DBGISR(("cts_change %s signals=%04X\n", info
->device_name
, info
->signals
));
2071 if ((info
->cts_chkcount
)++ == IO_PIN_SHUTDOWN_LIMIT
) {
2072 slgt_irq_off(info
, IRQ_CTS
);
2076 wake_up_interruptible(&info
->status_event_wait_q
);
2077 wake_up_interruptible(&info
->event_wait_q
);
2078 info
->pending_bh
|= BH_STATUS
;
2080 if (info
->flags
& ASYNC_CTS_FLOW
) {
2082 if (info
->tty
->hw_stopped
) {
2083 if (info
->signals
& SerialSignal_CTS
) {
2084 info
->tty
->hw_stopped
= 0;
2085 info
->pending_bh
|= BH_TRANSMIT
;
2089 if (!(info
->signals
& SerialSignal_CTS
))
2090 info
->tty
->hw_stopped
= 1;
2096 static void dcd_change(struct slgt_info
*info
, unsigned short status
)
2098 if (status
& BIT1
) {
2099 info
->signals
|= SerialSignal_DCD
;
2100 info
->input_signal_events
.dcd_up
++;
2102 info
->signals
&= ~SerialSignal_DCD
;
2103 info
->input_signal_events
.dcd_down
++;
2105 DBGISR(("dcd_change %s signals=%04X\n", info
->device_name
, info
->signals
));
2106 if ((info
->dcd_chkcount
)++ == IO_PIN_SHUTDOWN_LIMIT
) {
2107 slgt_irq_off(info
, IRQ_DCD
);
2111 #if SYNCLINK_GENERIC_HDLC
2112 if (info
->netcount
) {
2113 if (info
->signals
& SerialSignal_DCD
)
2114 netif_carrier_on(info
->netdev
);
2116 netif_carrier_off(info
->netdev
);
2119 wake_up_interruptible(&info
->status_event_wait_q
);
2120 wake_up_interruptible(&info
->event_wait_q
);
2121 info
->pending_bh
|= BH_STATUS
;
2123 if (info
->flags
& ASYNC_CHECK_CD
) {
2124 if (info
->signals
& SerialSignal_DCD
)
2125 wake_up_interruptible(&info
->open_wait
);
2128 tty_hangup(info
->tty
);
2133 static void ri_change(struct slgt_info
*info
, unsigned short status
)
2135 if (status
& BIT0
) {
2136 info
->signals
|= SerialSignal_RI
;
2137 info
->input_signal_events
.ri_up
++;
2139 info
->signals
&= ~SerialSignal_RI
;
2140 info
->input_signal_events
.ri_down
++;
2142 DBGISR(("ri_change %s signals=%04X\n", info
->device_name
, info
->signals
));
2143 if ((info
->ri_chkcount
)++ == IO_PIN_SHUTDOWN_LIMIT
) {
2144 slgt_irq_off(info
, IRQ_RI
);
2148 wake_up_interruptible(&info
->status_event_wait_q
);
2149 wake_up_interruptible(&info
->event_wait_q
);
2150 info
->pending_bh
|= BH_STATUS
;
2153 static void isr_serial(struct slgt_info
*info
)
2155 unsigned short status
= rd_reg16(info
, SSR
);
2157 DBGISR(("%s isr_serial status=%04X\n", info
->device_name
, status
));
2159 wr_reg16(info
, SSR
, status
); /* clear pending */
2161 info
->irq_occurred
= true;
2163 if (info
->params
.mode
== MGSL_MODE_ASYNC
) {
2164 if (status
& IRQ_TXIDLE
) {
2166 isr_txeom(info
, status
);
2168 if ((status
& IRQ_RXBREAK
) && (status
& RXBREAK
)) {
2170 /* process break detection if tty control allows */
2172 if (!(status
& info
->ignore_status_mask
)) {
2173 if (info
->read_status_mask
& MASK_BREAK
) {
2174 tty_insert_flip_char(info
->tty
, 0, TTY_BREAK
);
2175 if (info
->flags
& ASYNC_SAK
)
2182 if (status
& (IRQ_TXIDLE
+ IRQ_TXUNDER
))
2183 isr_txeom(info
, status
);
2185 if (status
& IRQ_RXIDLE
) {
2186 if (status
& RXIDLE
)
2187 info
->icount
.rxidle
++;
2189 info
->icount
.exithunt
++;
2190 wake_up_interruptible(&info
->event_wait_q
);
2193 if (status
& IRQ_RXOVER
)
2197 if (status
& IRQ_DSR
)
2198 dsr_change(info
, status
);
2199 if (status
& IRQ_CTS
)
2200 cts_change(info
, status
);
2201 if (status
& IRQ_DCD
)
2202 dcd_change(info
, status
);
2203 if (status
& IRQ_RI
)
2204 ri_change(info
, status
);
2207 static void isr_rdma(struct slgt_info
*info
)
2209 unsigned int status
= rd_reg32(info
, RDCSR
);
2211 DBGISR(("%s isr_rdma status=%08x\n", info
->device_name
, status
));
2213 /* RDCSR (rx DMA control/status)
2216 * 06 save status byte to DMA buffer
2218 * 04 eol (end of list)
2219 * 03 eob (end of buffer)
2224 wr_reg32(info
, RDCSR
, status
); /* clear pending */
2226 if (status
& (BIT5
+ BIT4
)) {
2227 DBGISR(("%s isr_rdma rx_restart=1\n", info
->device_name
));
2228 info
->rx_restart
= true;
2230 info
->pending_bh
|= BH_RECEIVE
;
2233 static void isr_tdma(struct slgt_info
*info
)
2235 unsigned int status
= rd_reg32(info
, TDCSR
);
2237 DBGISR(("%s isr_tdma status=%08x\n", info
->device_name
, status
));
2239 /* TDCSR (tx DMA control/status)
2243 * 04 eol (end of list)
2244 * 03 eob (end of buffer)
2249 wr_reg32(info
, TDCSR
, status
); /* clear pending */
2251 if (status
& (BIT5
+ BIT4
+ BIT3
)) {
2252 // another transmit buffer has completed
2253 // run bottom half to get more send data from user
2254 info
->pending_bh
|= BH_TRANSMIT
;
2258 static void isr_txeom(struct slgt_info
*info
, unsigned short status
)
2260 DBGISR(("%s txeom status=%04x\n", info
->device_name
, status
));
2262 slgt_irq_off(info
, IRQ_TXDATA
+ IRQ_TXIDLE
+ IRQ_TXUNDER
);
2265 if (status
& IRQ_TXUNDER
) {
2266 unsigned short val
= rd_reg16(info
, TCR
);
2267 wr_reg16(info
, TCR
, (unsigned short)(val
| BIT2
)); /* set reset bit */
2268 wr_reg16(info
, TCR
, val
); /* clear reset bit */
2271 if (info
->tx_active
) {
2272 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
2273 if (status
& IRQ_TXUNDER
)
2274 info
->icount
.txunder
++;
2275 else if (status
& IRQ_TXIDLE
)
2276 info
->icount
.txok
++;
2279 info
->tx_active
= false;
2282 del_timer(&info
->tx_timer
);
2284 if (info
->params
.mode
!= MGSL_MODE_ASYNC
&& info
->drop_rts_on_tx_done
) {
2285 info
->signals
&= ~SerialSignal_RTS
;
2286 info
->drop_rts_on_tx_done
= false;
2290 #if SYNCLINK_GENERIC_HDLC
2292 hdlcdev_tx_done(info
);
2296 if (info
->tty
&& (info
->tty
->stopped
|| info
->tty
->hw_stopped
)) {
2300 info
->pending_bh
|= BH_TRANSMIT
;
2305 static void isr_gpio(struct slgt_info
*info
, unsigned int changed
, unsigned int state
)
2307 struct cond_wait
*w
, *prev
;
2309 /* wake processes waiting for specific transitions */
2310 for (w
= info
->gpio_wait_q
, prev
= NULL
; w
!= NULL
; w
= w
->next
) {
2311 if (w
->data
& changed
) {
2313 wake_up_interruptible(&w
->q
);
2315 prev
->next
= w
->next
;
2317 info
->gpio_wait_q
= w
->next
;
2323 /* interrupt service routine
2325 * irq interrupt number
2326 * dev_id device ID supplied during interrupt registration
2328 static irqreturn_t
slgt_interrupt(int dummy
, void *dev_id
)
2330 struct slgt_info
*info
= dev_id
;
2334 DBGISR(("slgt_interrupt irq=%d entry\n", info
->irq_level
));
2336 spin_lock(&info
->lock
);
2338 while((gsr
= rd_reg32(info
, GSR
) & 0xffffff00)) {
2339 DBGISR(("%s gsr=%08x\n", info
->device_name
, gsr
));
2340 info
->irq_occurred
= true;
2341 for(i
=0; i
< info
->port_count
; i
++) {
2342 if (info
->port_array
[i
] == NULL
)
2344 if (gsr
& (BIT8
<< i
))
2345 isr_serial(info
->port_array
[i
]);
2346 if (gsr
& (BIT16
<< (i
*2)))
2347 isr_rdma(info
->port_array
[i
]);
2348 if (gsr
& (BIT17
<< (i
*2)))
2349 isr_tdma(info
->port_array
[i
]);
2353 if (info
->gpio_present
) {
2355 unsigned int changed
;
2356 while ((changed
= rd_reg32(info
, IOSR
)) != 0) {
2357 DBGISR(("%s iosr=%08x\n", info
->device_name
, changed
));
2358 /* read latched state of GPIO signals */
2359 state
= rd_reg32(info
, IOVR
);
2360 /* clear pending GPIO interrupt bits */
2361 wr_reg32(info
, IOSR
, changed
);
2362 for (i
=0 ; i
< info
->port_count
; i
++) {
2363 if (info
->port_array
[i
] != NULL
)
2364 isr_gpio(info
->port_array
[i
], changed
, state
);
2369 for(i
=0; i
< info
->port_count
; i
++) {
2370 struct slgt_info
*port
= info
->port_array
[i
];
2372 if (port
&& (port
->count
|| port
->netcount
) &&
2373 port
->pending_bh
&& !port
->bh_running
&&
2374 !port
->bh_requested
) {
2375 DBGISR(("%s bh queued\n", port
->device_name
));
2376 schedule_work(&port
->task
);
2377 port
->bh_requested
= true;
2381 spin_unlock(&info
->lock
);
2383 DBGISR(("slgt_interrupt irq=%d exit\n", info
->irq_level
));
2387 static int startup(struct slgt_info
*info
)
2389 DBGINFO(("%s startup\n", info
->device_name
));
2391 if (info
->flags
& ASYNC_INITIALIZED
)
2394 if (!info
->tx_buf
) {
2395 info
->tx_buf
= kmalloc(info
->max_frame_size
, GFP_KERNEL
);
2396 if (!info
->tx_buf
) {
2397 DBGERR(("%s can't allocate tx buffer\n", info
->device_name
));
2402 info
->pending_bh
= 0;
2404 memset(&info
->icount
, 0, sizeof(info
->icount
));
2406 /* program hardware for current parameters */
2407 change_params(info
);
2410 clear_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
2412 info
->flags
|= ASYNC_INITIALIZED
;
2418 * called by close() and hangup() to shutdown hardware
2420 static void shutdown(struct slgt_info
*info
)
2422 unsigned long flags
;
2424 if (!(info
->flags
& ASYNC_INITIALIZED
))
2427 DBGINFO(("%s shutdown\n", info
->device_name
));
2429 /* clear status wait queue because status changes */
2430 /* can't happen after shutting down the hardware */
2431 wake_up_interruptible(&info
->status_event_wait_q
);
2432 wake_up_interruptible(&info
->event_wait_q
);
2434 del_timer_sync(&info
->tx_timer
);
2435 del_timer_sync(&info
->rx_timer
);
2437 kfree(info
->tx_buf
);
2438 info
->tx_buf
= NULL
;
2440 spin_lock_irqsave(&info
->lock
,flags
);
2445 slgt_irq_off(info
, IRQ_ALL
| IRQ_MASTER
);
2447 if (!info
->tty
|| info
->tty
->termios
->c_cflag
& HUPCL
) {
2448 info
->signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
2452 flush_cond_wait(&info
->gpio_wait_q
);
2454 spin_unlock_irqrestore(&info
->lock
,flags
);
2457 set_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
2459 info
->flags
&= ~ASYNC_INITIALIZED
;
2462 static void program_hw(struct slgt_info
*info
)
2464 unsigned long flags
;
2466 spin_lock_irqsave(&info
->lock
,flags
);
2471 if (info
->params
.mode
!= MGSL_MODE_ASYNC
||
2479 info
->dcd_chkcount
= 0;
2480 info
->cts_chkcount
= 0;
2481 info
->ri_chkcount
= 0;
2482 info
->dsr_chkcount
= 0;
2484 slgt_irq_on(info
, IRQ_DCD
| IRQ_CTS
| IRQ_DSR
);
2487 if (info
->netcount
||
2488 (info
->tty
&& info
->tty
->termios
->c_cflag
& CREAD
))
2491 spin_unlock_irqrestore(&info
->lock
,flags
);
2495 * reconfigure adapter based on new parameters
2497 static void change_params(struct slgt_info
*info
)
2502 if (!info
->tty
|| !info
->tty
->termios
)
2504 DBGINFO(("%s change_params\n", info
->device_name
));
2506 cflag
= info
->tty
->termios
->c_cflag
;
2508 /* if B0 rate (hangup) specified then negate DTR and RTS */
2509 /* otherwise assert DTR and RTS */
2511 info
->signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
2513 info
->signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
2515 /* byte size and parity */
2517 switch (cflag
& CSIZE
) {
2518 case CS5
: info
->params
.data_bits
= 5; break;
2519 case CS6
: info
->params
.data_bits
= 6; break;
2520 case CS7
: info
->params
.data_bits
= 7; break;
2521 case CS8
: info
->params
.data_bits
= 8; break;
2522 default: info
->params
.data_bits
= 7; break;
2525 info
->params
.stop_bits
= (cflag
& CSTOPB
) ? 2 : 1;
2528 info
->params
.parity
= (cflag
& PARODD
) ? ASYNC_PARITY_ODD
: ASYNC_PARITY_EVEN
;
2530 info
->params
.parity
= ASYNC_PARITY_NONE
;
2532 /* calculate number of jiffies to transmit a full
2533 * FIFO (32 bytes) at specified data rate
2535 bits_per_char
= info
->params
.data_bits
+
2536 info
->params
.stop_bits
+ 1;
2538 info
->params
.data_rate
= tty_get_baud_rate(info
->tty
);
2540 if (info
->params
.data_rate
) {
2541 info
->timeout
= (32*HZ
*bits_per_char
) /
2542 info
->params
.data_rate
;
2544 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
2546 if (cflag
& CRTSCTS
)
2547 info
->flags
|= ASYNC_CTS_FLOW
;
2549 info
->flags
&= ~ASYNC_CTS_FLOW
;
2552 info
->flags
&= ~ASYNC_CHECK_CD
;
2554 info
->flags
|= ASYNC_CHECK_CD
;
2556 /* process tty input control flags */
2558 info
->read_status_mask
= IRQ_RXOVER
;
2559 if (I_INPCK(info
->tty
))
2560 info
->read_status_mask
|= MASK_PARITY
| MASK_FRAMING
;
2561 if (I_BRKINT(info
->tty
) || I_PARMRK(info
->tty
))
2562 info
->read_status_mask
|= MASK_BREAK
;
2563 if (I_IGNPAR(info
->tty
))
2564 info
->ignore_status_mask
|= MASK_PARITY
| MASK_FRAMING
;
2565 if (I_IGNBRK(info
->tty
)) {
2566 info
->ignore_status_mask
|= MASK_BREAK
;
2567 /* If ignoring parity and break indicators, ignore
2568 * overruns too. (For real raw support).
2570 if (I_IGNPAR(info
->tty
))
2571 info
->ignore_status_mask
|= MASK_OVERRUN
;
2577 static int get_stats(struct slgt_info
*info
, struct mgsl_icount __user
*user_icount
)
2579 DBGINFO(("%s get_stats\n", info
->device_name
));
2581 memset(&info
->icount
, 0, sizeof(info
->icount
));
2583 if (copy_to_user(user_icount
, &info
->icount
, sizeof(struct mgsl_icount
)))
2589 static int get_params(struct slgt_info
*info
, MGSL_PARAMS __user
*user_params
)
2591 DBGINFO(("%s get_params\n", info
->device_name
));
2592 if (copy_to_user(user_params
, &info
->params
, sizeof(MGSL_PARAMS
)))
2597 static int set_params(struct slgt_info
*info
, MGSL_PARAMS __user
*new_params
)
2599 unsigned long flags
;
2600 MGSL_PARAMS tmp_params
;
2602 DBGINFO(("%s set_params\n", info
->device_name
));
2603 if (copy_from_user(&tmp_params
, new_params
, sizeof(MGSL_PARAMS
)))
2606 spin_lock_irqsave(&info
->lock
, flags
);
2607 memcpy(&info
->params
, &tmp_params
, sizeof(MGSL_PARAMS
));
2608 spin_unlock_irqrestore(&info
->lock
, flags
);
2610 change_params(info
);
2615 static int get_txidle(struct slgt_info
*info
, int __user
*idle_mode
)
2617 DBGINFO(("%s get_txidle=%d\n", info
->device_name
, info
->idle_mode
));
2618 if (put_user(info
->idle_mode
, idle_mode
))
2623 static int set_txidle(struct slgt_info
*info
, int idle_mode
)
2625 unsigned long flags
;
2626 DBGINFO(("%s set_txidle(%d)\n", info
->device_name
, idle_mode
));
2627 spin_lock_irqsave(&info
->lock
,flags
);
2628 info
->idle_mode
= idle_mode
;
2629 if (info
->params
.mode
!= MGSL_MODE_ASYNC
)
2631 spin_unlock_irqrestore(&info
->lock
,flags
);
2635 static int tx_enable(struct slgt_info
*info
, int enable
)
2637 unsigned long flags
;
2638 DBGINFO(("%s tx_enable(%d)\n", info
->device_name
, enable
));
2639 spin_lock_irqsave(&info
->lock
,flags
);
2641 if (!info
->tx_enabled
)
2644 if (info
->tx_enabled
)
2647 spin_unlock_irqrestore(&info
->lock
,flags
);
2652 * abort transmit HDLC frame
2654 static int tx_abort(struct slgt_info
*info
)
2656 unsigned long flags
;
2657 DBGINFO(("%s tx_abort\n", info
->device_name
));
2658 spin_lock_irqsave(&info
->lock
,flags
);
2660 spin_unlock_irqrestore(&info
->lock
,flags
);
2664 static int rx_enable(struct slgt_info
*info
, int enable
)
2666 unsigned long flags
;
2667 DBGINFO(("%s rx_enable(%d)\n", info
->device_name
, enable
));
2668 spin_lock_irqsave(&info
->lock
,flags
);
2670 if (!info
->rx_enabled
)
2672 else if (enable
== 2) {
2673 /* force hunt mode (write 1 to RCR[3]) */
2674 wr_reg16(info
, RCR
, rd_reg16(info
, RCR
) | BIT3
);
2677 if (info
->rx_enabled
)
2680 spin_unlock_irqrestore(&info
->lock
,flags
);
2685 * wait for specified event to occur
2687 static int wait_mgsl_event(struct slgt_info
*info
, int __user
*mask_ptr
)
2689 unsigned long flags
;
2692 struct mgsl_icount cprev
, cnow
;
2695 struct _input_signal_events oldsigs
, newsigs
;
2696 DECLARE_WAITQUEUE(wait
, current
);
2698 if (get_user(mask
, mask_ptr
))
2701 DBGINFO(("%s wait_mgsl_event(%d)\n", info
->device_name
, mask
));
2703 spin_lock_irqsave(&info
->lock
,flags
);
2705 /* return immediately if state matches requested events */
2710 ( ((s
& SerialSignal_DSR
) ? MgslEvent_DsrActive
:MgslEvent_DsrInactive
) +
2711 ((s
& SerialSignal_DCD
) ? MgslEvent_DcdActive
:MgslEvent_DcdInactive
) +
2712 ((s
& SerialSignal_CTS
) ? MgslEvent_CtsActive
:MgslEvent_CtsInactive
) +
2713 ((s
& SerialSignal_RI
) ? MgslEvent_RiActive
:MgslEvent_RiInactive
) );
2715 spin_unlock_irqrestore(&info
->lock
,flags
);
2719 /* save current irq counts */
2720 cprev
= info
->icount
;
2721 oldsigs
= info
->input_signal_events
;
2723 /* enable hunt and idle irqs if needed */
2724 if (mask
& (MgslEvent_ExitHuntMode
+MgslEvent_IdleReceived
)) {
2725 unsigned short val
= rd_reg16(info
, SCR
);
2726 if (!(val
& IRQ_RXIDLE
))
2727 wr_reg16(info
, SCR
, (unsigned short)(val
| IRQ_RXIDLE
));
2730 set_current_state(TASK_INTERRUPTIBLE
);
2731 add_wait_queue(&info
->event_wait_q
, &wait
);
2733 spin_unlock_irqrestore(&info
->lock
,flags
);
2737 if (signal_pending(current
)) {
2742 /* get current irq counts */
2743 spin_lock_irqsave(&info
->lock
,flags
);
2744 cnow
= info
->icount
;
2745 newsigs
= info
->input_signal_events
;
2746 set_current_state(TASK_INTERRUPTIBLE
);
2747 spin_unlock_irqrestore(&info
->lock
,flags
);
2749 /* if no change, wait aborted for some reason */
2750 if (newsigs
.dsr_up
== oldsigs
.dsr_up
&&
2751 newsigs
.dsr_down
== oldsigs
.dsr_down
&&
2752 newsigs
.dcd_up
== oldsigs
.dcd_up
&&
2753 newsigs
.dcd_down
== oldsigs
.dcd_down
&&
2754 newsigs
.cts_up
== oldsigs
.cts_up
&&
2755 newsigs
.cts_down
== oldsigs
.cts_down
&&
2756 newsigs
.ri_up
== oldsigs
.ri_up
&&
2757 newsigs
.ri_down
== oldsigs
.ri_down
&&
2758 cnow
.exithunt
== cprev
.exithunt
&&
2759 cnow
.rxidle
== cprev
.rxidle
) {
2765 ( (newsigs
.dsr_up
!= oldsigs
.dsr_up
? MgslEvent_DsrActive
:0) +
2766 (newsigs
.dsr_down
!= oldsigs
.dsr_down
? MgslEvent_DsrInactive
:0) +
2767 (newsigs
.dcd_up
!= oldsigs
.dcd_up
? MgslEvent_DcdActive
:0) +
2768 (newsigs
.dcd_down
!= oldsigs
.dcd_down
? MgslEvent_DcdInactive
:0) +
2769 (newsigs
.cts_up
!= oldsigs
.cts_up
? MgslEvent_CtsActive
:0) +
2770 (newsigs
.cts_down
!= oldsigs
.cts_down
? MgslEvent_CtsInactive
:0) +
2771 (newsigs
.ri_up
!= oldsigs
.ri_up
? MgslEvent_RiActive
:0) +
2772 (newsigs
.ri_down
!= oldsigs
.ri_down
? MgslEvent_RiInactive
:0) +
2773 (cnow
.exithunt
!= cprev
.exithunt
? MgslEvent_ExitHuntMode
:0) +
2774 (cnow
.rxidle
!= cprev
.rxidle
? MgslEvent_IdleReceived
:0) );
2782 remove_wait_queue(&info
->event_wait_q
, &wait
);
2783 set_current_state(TASK_RUNNING
);
2786 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2787 spin_lock_irqsave(&info
->lock
,flags
);
2788 if (!waitqueue_active(&info
->event_wait_q
)) {
2789 /* disable enable exit hunt mode/idle rcvd IRQs */
2791 (unsigned short)(rd_reg16(info
, SCR
) & ~IRQ_RXIDLE
));
2793 spin_unlock_irqrestore(&info
->lock
,flags
);
2797 rc
= put_user(events
, mask_ptr
);
2801 static int get_interface(struct slgt_info
*info
, int __user
*if_mode
)
2803 DBGINFO(("%s get_interface=%x\n", info
->device_name
, info
->if_mode
));
2804 if (put_user(info
->if_mode
, if_mode
))
2809 static int set_interface(struct slgt_info
*info
, int if_mode
)
2811 unsigned long flags
;
2814 DBGINFO(("%s set_interface=%x)\n", info
->device_name
, if_mode
));
2815 spin_lock_irqsave(&info
->lock
,flags
);
2816 info
->if_mode
= if_mode
;
2820 /* TCR (tx control) 07 1=RTS driver control */
2821 val
= rd_reg16(info
, TCR
);
2822 if (info
->if_mode
& MGSL_INTERFACE_RTS_EN
)
2826 wr_reg16(info
, TCR
, val
);
2828 spin_unlock_irqrestore(&info
->lock
,flags
);
2833 * set general purpose IO pin state and direction
2836 * state each bit indicates a pin state
2837 * smask set bit indicates pin state to set
2838 * dir each bit indicates a pin direction (0=input, 1=output)
2839 * dmask set bit indicates pin direction to set
2841 static int set_gpio(struct slgt_info
*info
, struct gpio_desc __user
*user_gpio
)
2843 unsigned long flags
;
2844 struct gpio_desc gpio
;
2847 if (!info
->gpio_present
)
2849 if (copy_from_user(&gpio
, user_gpio
, sizeof(gpio
)))
2851 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2852 info
->device_name
, gpio
.state
, gpio
.smask
,
2853 gpio
.dir
, gpio
.dmask
));
2855 spin_lock_irqsave(&info
->lock
,flags
);
2857 data
= rd_reg32(info
, IODR
);
2858 data
|= gpio
.dmask
& gpio
.dir
;
2859 data
&= ~(gpio
.dmask
& ~gpio
.dir
);
2860 wr_reg32(info
, IODR
, data
);
2863 data
= rd_reg32(info
, IOVR
);
2864 data
|= gpio
.smask
& gpio
.state
;
2865 data
&= ~(gpio
.smask
& ~gpio
.state
);
2866 wr_reg32(info
, IOVR
, data
);
2868 spin_unlock_irqrestore(&info
->lock
,flags
);
2874 * get general purpose IO pin state and direction
2876 static int get_gpio(struct slgt_info
*info
, struct gpio_desc __user
*user_gpio
)
2878 struct gpio_desc gpio
;
2879 if (!info
->gpio_present
)
2881 gpio
.state
= rd_reg32(info
, IOVR
);
2882 gpio
.smask
= 0xffffffff;
2883 gpio
.dir
= rd_reg32(info
, IODR
);
2884 gpio
.dmask
= 0xffffffff;
2885 if (copy_to_user(user_gpio
, &gpio
, sizeof(gpio
)))
2887 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2888 info
->device_name
, gpio
.state
, gpio
.dir
));
2893 * conditional wait facility
2895 static void init_cond_wait(struct cond_wait
*w
, unsigned int data
)
2897 init_waitqueue_head(&w
->q
);
2898 init_waitqueue_entry(&w
->wait
, current
);
2902 static void add_cond_wait(struct cond_wait
**head
, struct cond_wait
*w
)
2904 set_current_state(TASK_INTERRUPTIBLE
);
2905 add_wait_queue(&w
->q
, &w
->wait
);
2910 static void remove_cond_wait(struct cond_wait
**head
, struct cond_wait
*cw
)
2912 struct cond_wait
*w
, *prev
;
2913 remove_wait_queue(&cw
->q
, &cw
->wait
);
2914 set_current_state(TASK_RUNNING
);
2915 for (w
= *head
, prev
= NULL
; w
!= NULL
; prev
= w
, w
= w
->next
) {
2918 prev
->next
= w
->next
;
2926 static void flush_cond_wait(struct cond_wait
**head
)
2928 while (*head
!= NULL
) {
2929 wake_up_interruptible(&(*head
)->q
);
2930 *head
= (*head
)->next
;
2935 * wait for general purpose I/O pin(s) to enter specified state
2938 * state - bit indicates target pin state
2939 * smask - set bit indicates watched pin
2941 * The wait ends when at least one watched pin enters the specified
2942 * state. When 0 (no error) is returned, user_gpio->state is set to the
2943 * state of all GPIO pins when the wait ends.
2945 * Note: Each pin may be a dedicated input, dedicated output, or
2946 * configurable input/output. The number and configuration of pins
2947 * varies with the specific adapter model. Only input pins (dedicated
2948 * or configured) can be monitored with this function.
2950 static int wait_gpio(struct slgt_info
*info
, struct gpio_desc __user
*user_gpio
)
2952 unsigned long flags
;
2954 struct gpio_desc gpio
;
2955 struct cond_wait wait
;
2958 if (!info
->gpio_present
)
2960 if (copy_from_user(&gpio
, user_gpio
, sizeof(gpio
)))
2962 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2963 info
->device_name
, gpio
.state
, gpio
.smask
));
2964 /* ignore output pins identified by set IODR bit */
2965 if ((gpio
.smask
&= ~rd_reg32(info
, IODR
)) == 0)
2967 init_cond_wait(&wait
, gpio
.smask
);
2969 spin_lock_irqsave(&info
->lock
, flags
);
2970 /* enable interrupts for watched pins */
2971 wr_reg32(info
, IOER
, rd_reg32(info
, IOER
) | gpio
.smask
);
2972 /* get current pin states */
2973 state
= rd_reg32(info
, IOVR
);
2975 if (gpio
.smask
& ~(state
^ gpio
.state
)) {
2976 /* already in target state */
2979 /* wait for target state */
2980 add_cond_wait(&info
->gpio_wait_q
, &wait
);
2981 spin_unlock_irqrestore(&info
->lock
, flags
);
2983 if (signal_pending(current
))
2986 gpio
.state
= wait
.data
;
2987 spin_lock_irqsave(&info
->lock
, flags
);
2988 remove_cond_wait(&info
->gpio_wait_q
, &wait
);
2991 /* disable all GPIO interrupts if no waiting processes */
2992 if (info
->gpio_wait_q
== NULL
)
2993 wr_reg32(info
, IOER
, 0);
2994 spin_unlock_irqrestore(&info
->lock
,flags
);
2996 if ((rc
== 0) && copy_to_user(user_gpio
, &gpio
, sizeof(gpio
)))
3001 static int modem_input_wait(struct slgt_info
*info
,int arg
)
3003 unsigned long flags
;
3005 struct mgsl_icount cprev
, cnow
;
3006 DECLARE_WAITQUEUE(wait
, current
);
3008 /* save current irq counts */
3009 spin_lock_irqsave(&info
->lock
,flags
);
3010 cprev
= info
->icount
;
3011 add_wait_queue(&info
->status_event_wait_q
, &wait
);
3012 set_current_state(TASK_INTERRUPTIBLE
);
3013 spin_unlock_irqrestore(&info
->lock
,flags
);
3017 if (signal_pending(current
)) {
3022 /* get new irq counts */
3023 spin_lock_irqsave(&info
->lock
,flags
);
3024 cnow
= info
->icount
;
3025 set_current_state(TASK_INTERRUPTIBLE
);
3026 spin_unlock_irqrestore(&info
->lock
,flags
);
3028 /* if no change, wait aborted for some reason */
3029 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
3030 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
) {
3035 /* check for change in caller specified modem input */
3036 if ((arg
& TIOCM_RNG
&& cnow
.rng
!= cprev
.rng
) ||
3037 (arg
& TIOCM_DSR
&& cnow
.dsr
!= cprev
.dsr
) ||
3038 (arg
& TIOCM_CD
&& cnow
.dcd
!= cprev
.dcd
) ||
3039 (arg
& TIOCM_CTS
&& cnow
.cts
!= cprev
.cts
)) {
3046 remove_wait_queue(&info
->status_event_wait_q
, &wait
);
3047 set_current_state(TASK_RUNNING
);
3052 * return state of serial control and status signals
3054 static int tiocmget(struct tty_struct
*tty
, struct file
*file
)
3056 struct slgt_info
*info
= tty
->driver_data
;
3057 unsigned int result
;
3058 unsigned long flags
;
3060 spin_lock_irqsave(&info
->lock
,flags
);
3062 spin_unlock_irqrestore(&info
->lock
,flags
);
3064 result
= ((info
->signals
& SerialSignal_RTS
) ? TIOCM_RTS
:0) +
3065 ((info
->signals
& SerialSignal_DTR
) ? TIOCM_DTR
:0) +
3066 ((info
->signals
& SerialSignal_DCD
) ? TIOCM_CAR
:0) +
3067 ((info
->signals
& SerialSignal_RI
) ? TIOCM_RNG
:0) +
3068 ((info
->signals
& SerialSignal_DSR
) ? TIOCM_DSR
:0) +
3069 ((info
->signals
& SerialSignal_CTS
) ? TIOCM_CTS
:0);
3071 DBGINFO(("%s tiocmget value=%08X\n", info
->device_name
, result
));
3076 * set modem control signals (DTR/RTS)
3078 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3079 * TIOCMSET = set/clear signal values
3080 * value bit mask for command
3082 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
3083 unsigned int set
, unsigned int clear
)
3085 struct slgt_info
*info
= tty
->driver_data
;
3086 unsigned long flags
;
3088 DBGINFO(("%s tiocmset(%x,%x)\n", info
->device_name
, set
, clear
));
3090 if (set
& TIOCM_RTS
)
3091 info
->signals
|= SerialSignal_RTS
;
3092 if (set
& TIOCM_DTR
)
3093 info
->signals
|= SerialSignal_DTR
;
3094 if (clear
& TIOCM_RTS
)
3095 info
->signals
&= ~SerialSignal_RTS
;
3096 if (clear
& TIOCM_DTR
)
3097 info
->signals
&= ~SerialSignal_DTR
;
3099 spin_lock_irqsave(&info
->lock
,flags
);
3101 spin_unlock_irqrestore(&info
->lock
,flags
);
3106 * block current process until the device is ready to open
3108 static int block_til_ready(struct tty_struct
*tty
, struct file
*filp
,
3109 struct slgt_info
*info
)
3111 DECLARE_WAITQUEUE(wait
, current
);
3113 bool do_clocal
= false;
3114 bool extra_count
= false;
3115 unsigned long flags
;
3117 DBGINFO(("%s block_til_ready\n", tty
->driver
->name
));
3119 if (filp
->f_flags
& O_NONBLOCK
|| tty
->flags
& (1 << TTY_IO_ERROR
)){
3120 /* nonblock mode is set or port is not enabled */
3121 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3125 if (tty
->termios
->c_cflag
& CLOCAL
)
3128 /* Wait for carrier detect and the line to become
3129 * free (i.e., not in use by the callout). While we are in
3130 * this loop, info->count is dropped by one, so that
3131 * close() knows when to free things. We restore it upon
3132 * exit, either normal or abnormal.
3136 add_wait_queue(&info
->open_wait
, &wait
);
3138 spin_lock_irqsave(&info
->lock
, flags
);
3139 if (!tty_hung_up_p(filp
)) {
3143 spin_unlock_irqrestore(&info
->lock
, flags
);
3144 info
->blocked_open
++;
3147 if ((tty
->termios
->c_cflag
& CBAUD
)) {
3148 spin_lock_irqsave(&info
->lock
,flags
);
3149 info
->signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
3151 spin_unlock_irqrestore(&info
->lock
,flags
);
3154 set_current_state(TASK_INTERRUPTIBLE
);
3156 if (tty_hung_up_p(filp
) || !(info
->flags
& ASYNC_INITIALIZED
)){
3157 retval
= (info
->flags
& ASYNC_HUP_NOTIFY
) ?
3158 -EAGAIN
: -ERESTARTSYS
;
3162 spin_lock_irqsave(&info
->lock
,flags
);
3164 spin_unlock_irqrestore(&info
->lock
,flags
);
3166 if (!(info
->flags
& ASYNC_CLOSING
) &&
3167 (do_clocal
|| (info
->signals
& SerialSignal_DCD
)) ) {
3171 if (signal_pending(current
)) {
3172 retval
= -ERESTARTSYS
;
3176 DBGINFO(("%s block_til_ready wait\n", tty
->driver
->name
));
3180 set_current_state(TASK_RUNNING
);
3181 remove_wait_queue(&info
->open_wait
, &wait
);
3185 info
->blocked_open
--;
3188 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3190 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty
->driver
->name
, retval
));
3194 static int alloc_tmp_rbuf(struct slgt_info
*info
)
3196 info
->tmp_rbuf
= kmalloc(info
->max_frame_size
+ 5, GFP_KERNEL
);
3197 if (info
->tmp_rbuf
== NULL
)
3202 static void free_tmp_rbuf(struct slgt_info
*info
)
3204 kfree(info
->tmp_rbuf
);
3205 info
->tmp_rbuf
= NULL
;
3209 * allocate DMA descriptor lists.
3211 static int alloc_desc(struct slgt_info
*info
)
3216 /* allocate memory to hold descriptor lists */
3217 info
->bufs
= pci_alloc_consistent(info
->pdev
, DESC_LIST_SIZE
, &info
->bufs_dma_addr
);
3218 if (info
->bufs
== NULL
)
3221 memset(info
->bufs
, 0, DESC_LIST_SIZE
);
3223 info
->rbufs
= (struct slgt_desc
*)info
->bufs
;
3224 info
->tbufs
= ((struct slgt_desc
*)info
->bufs
) + info
->rbuf_count
;
3226 pbufs
= (unsigned int)info
->bufs_dma_addr
;
3229 * Build circular lists of descriptors
3232 for (i
=0; i
< info
->rbuf_count
; i
++) {
3233 /* physical address of this descriptor */
3234 info
->rbufs
[i
].pdesc
= pbufs
+ (i
* sizeof(struct slgt_desc
));
3236 /* physical address of next descriptor */
3237 if (i
== info
->rbuf_count
- 1)
3238 info
->rbufs
[i
].next
= cpu_to_le32(pbufs
);
3240 info
->rbufs
[i
].next
= cpu_to_le32(pbufs
+ ((i
+1) * sizeof(struct slgt_desc
)));
3241 set_desc_count(info
->rbufs
[i
], DMABUFSIZE
);
3244 for (i
=0; i
< info
->tbuf_count
; i
++) {
3245 /* physical address of this descriptor */
3246 info
->tbufs
[i
].pdesc
= pbufs
+ ((info
->rbuf_count
+ i
) * sizeof(struct slgt_desc
));
3248 /* physical address of next descriptor */
3249 if (i
== info
->tbuf_count
- 1)
3250 info
->tbufs
[i
].next
= cpu_to_le32(pbufs
+ info
->rbuf_count
* sizeof(struct slgt_desc
));
3252 info
->tbufs
[i
].next
= cpu_to_le32(pbufs
+ ((info
->rbuf_count
+ i
+ 1) * sizeof(struct slgt_desc
)));
3258 static void free_desc(struct slgt_info
*info
)
3260 if (info
->bufs
!= NULL
) {
3261 pci_free_consistent(info
->pdev
, DESC_LIST_SIZE
, info
->bufs
, info
->bufs_dma_addr
);
3268 static int alloc_bufs(struct slgt_info
*info
, struct slgt_desc
*bufs
, int count
)
3271 for (i
=0; i
< count
; i
++) {
3272 if ((bufs
[i
].buf
= pci_alloc_consistent(info
->pdev
, DMABUFSIZE
, &bufs
[i
].buf_dma_addr
)) == NULL
)
3274 bufs
[i
].pbuf
= cpu_to_le32((unsigned int)bufs
[i
].buf_dma_addr
);
3279 static void free_bufs(struct slgt_info
*info
, struct slgt_desc
*bufs
, int count
)
3282 for (i
=0; i
< count
; i
++) {
3283 if (bufs
[i
].buf
== NULL
)
3285 pci_free_consistent(info
->pdev
, DMABUFSIZE
, bufs
[i
].buf
, bufs
[i
].buf_dma_addr
);
3290 static int alloc_dma_bufs(struct slgt_info
*info
)
3292 info
->rbuf_count
= 32;
3293 info
->tbuf_count
= 32;
3295 if (alloc_desc(info
) < 0 ||
3296 alloc_bufs(info
, info
->rbufs
, info
->rbuf_count
) < 0 ||
3297 alloc_bufs(info
, info
->tbufs
, info
->tbuf_count
) < 0 ||
3298 alloc_tmp_rbuf(info
) < 0) {
3299 DBGERR(("%s DMA buffer alloc fail\n", info
->device_name
));
3306 static void free_dma_bufs(struct slgt_info
*info
)
3309 free_bufs(info
, info
->rbufs
, info
->rbuf_count
);
3310 free_bufs(info
, info
->tbufs
, info
->tbuf_count
);
3313 free_tmp_rbuf(info
);
3316 static int claim_resources(struct slgt_info
*info
)
3318 if (request_mem_region(info
->phys_reg_addr
, SLGT_REG_SIZE
, "synclink_gt") == NULL
) {
3319 DBGERR(("%s reg addr conflict, addr=%08X\n",
3320 info
->device_name
, info
->phys_reg_addr
));
3321 info
->init_error
= DiagStatus_AddressConflict
;
3325 info
->reg_addr_requested
= true;
3327 info
->reg_addr
= ioremap(info
->phys_reg_addr
, SLGT_REG_SIZE
);
3328 if (!info
->reg_addr
) {
3329 DBGERR(("%s cant map device registers, addr=%08X\n",
3330 info
->device_name
, info
->phys_reg_addr
));
3331 info
->init_error
= DiagStatus_CantAssignPciResources
;
3337 release_resources(info
);
3341 static void release_resources(struct slgt_info
*info
)
3343 if (info
->irq_requested
) {
3344 free_irq(info
->irq_level
, info
);
3345 info
->irq_requested
= false;
3348 if (info
->reg_addr_requested
) {
3349 release_mem_region(info
->phys_reg_addr
, SLGT_REG_SIZE
);
3350 info
->reg_addr_requested
= false;
3353 if (info
->reg_addr
) {
3354 iounmap(info
->reg_addr
);
3355 info
->reg_addr
= NULL
;
3359 /* Add the specified device instance data structure to the
3360 * global linked list of devices and increment the device count.
3362 static void add_device(struct slgt_info
*info
)
3366 info
->next_device
= NULL
;
3367 info
->line
= slgt_device_count
;
3368 sprintf(info
->device_name
, "%s%d", tty_dev_prefix
, info
->line
);
3370 if (info
->line
< MAX_DEVICES
) {
3371 if (maxframe
[info
->line
])
3372 info
->max_frame_size
= maxframe
[info
->line
];
3373 info
->dosyncppp
= dosyncppp
[info
->line
];
3376 slgt_device_count
++;
3378 if (!slgt_device_list
)
3379 slgt_device_list
= info
;
3381 struct slgt_info
*current_dev
= slgt_device_list
;
3382 while(current_dev
->next_device
)
3383 current_dev
= current_dev
->next_device
;
3384 current_dev
->next_device
= info
;
3387 if (info
->max_frame_size
< 4096)
3388 info
->max_frame_size
= 4096;
3389 else if (info
->max_frame_size
> 65535)
3390 info
->max_frame_size
= 65535;
3392 switch(info
->pdev
->device
) {
3393 case SYNCLINK_GT_DEVICE_ID
:
3396 case SYNCLINK_GT2_DEVICE_ID
:
3399 case SYNCLINK_GT4_DEVICE_ID
:
3402 case SYNCLINK_AC_DEVICE_ID
:
3404 info
->params
.mode
= MGSL_MODE_ASYNC
;
3407 devstr
= "(unknown model)";
3409 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3410 devstr
, info
->device_name
, info
->phys_reg_addr
,
3411 info
->irq_level
, info
->max_frame_size
);
3413 #if SYNCLINK_GENERIC_HDLC
3419 * allocate device instance structure, return NULL on failure
3421 static struct slgt_info
*alloc_dev(int adapter_num
, int port_num
, struct pci_dev
*pdev
)
3423 struct slgt_info
*info
;
3425 info
= kzalloc(sizeof(struct slgt_info
), GFP_KERNEL
);
3428 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3429 driver_name
, adapter_num
, port_num
));
3431 info
->magic
= MGSL_MAGIC
;
3432 INIT_WORK(&info
->task
, bh_handler
);
3433 info
->max_frame_size
= 4096;
3434 info
->raw_rx_size
= DMABUFSIZE
;
3435 info
->close_delay
= 5*HZ
/10;
3436 info
->closing_wait
= 30*HZ
;
3437 init_waitqueue_head(&info
->open_wait
);
3438 init_waitqueue_head(&info
->close_wait
);
3439 init_waitqueue_head(&info
->status_event_wait_q
);
3440 init_waitqueue_head(&info
->event_wait_q
);
3441 spin_lock_init(&info
->netlock
);
3442 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
3443 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
3444 info
->adapter_num
= adapter_num
;
3445 info
->port_num
= port_num
;
3447 setup_timer(&info
->tx_timer
, tx_timeout
, (unsigned long)info
);
3448 setup_timer(&info
->rx_timer
, rx_timeout
, (unsigned long)info
);
3450 /* Copy configuration info to device instance data */
3452 info
->irq_level
= pdev
->irq
;
3453 info
->phys_reg_addr
= pci_resource_start(pdev
,0);
3455 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
3456 info
->irq_flags
= IRQF_SHARED
;
3458 info
->init_error
= -1; /* assume error, set to 0 on successful init */
3464 static void device_init(int adapter_num
, struct pci_dev
*pdev
)
3466 struct slgt_info
*port_array
[SLGT_MAX_PORTS
];
3470 if (pdev
->device
== SYNCLINK_GT2_DEVICE_ID
)
3472 else if (pdev
->device
== SYNCLINK_GT4_DEVICE_ID
)
3475 /* allocate device instances for all ports */
3476 for (i
=0; i
< port_count
; ++i
) {
3477 port_array
[i
] = alloc_dev(adapter_num
, i
, pdev
);
3478 if (port_array
[i
] == NULL
) {
3479 for (--i
; i
>= 0; --i
)
3480 kfree(port_array
[i
]);
3485 /* give copy of port_array to all ports and add to device list */
3486 for (i
=0; i
< port_count
; ++i
) {
3487 memcpy(port_array
[i
]->port_array
, port_array
, sizeof(port_array
));
3488 add_device(port_array
[i
]);
3489 port_array
[i
]->port_count
= port_count
;
3490 spin_lock_init(&port_array
[i
]->lock
);
3493 /* Allocate and claim adapter resources */
3494 if (!claim_resources(port_array
[0])) {
3496 alloc_dma_bufs(port_array
[0]);
3498 /* copy resource information from first port to others */
3499 for (i
= 1; i
< port_count
; ++i
) {
3500 port_array
[i
]->lock
= port_array
[0]->lock
;
3501 port_array
[i
]->irq_level
= port_array
[0]->irq_level
;
3502 port_array
[i
]->reg_addr
= port_array
[0]->reg_addr
;
3503 alloc_dma_bufs(port_array
[i
]);
3506 if (request_irq(port_array
[0]->irq_level
,
3508 port_array
[0]->irq_flags
,
3509 port_array
[0]->device_name
,
3510 port_array
[0]) < 0) {
3511 DBGERR(("%s request_irq failed IRQ=%d\n",
3512 port_array
[0]->device_name
,
3513 port_array
[0]->irq_level
));
3515 port_array
[0]->irq_requested
= true;
3516 adapter_test(port_array
[0]);
3517 for (i
=1 ; i
< port_count
; i
++) {
3518 port_array
[i
]->init_error
= port_array
[0]->init_error
;
3519 port_array
[i
]->gpio_present
= port_array
[0]->gpio_present
;
3524 for (i
=0; i
< port_count
; ++i
)
3525 tty_register_device(serial_driver
, port_array
[i
]->line
, &(port_array
[i
]->pdev
->dev
));
3528 static int __devinit
init_one(struct pci_dev
*dev
,
3529 const struct pci_device_id
*ent
)
3531 if (pci_enable_device(dev
)) {
3532 printk("error enabling pci device %p\n", dev
);
3535 pci_set_master(dev
);
3536 device_init(slgt_device_count
, dev
);
3540 static void __devexit
remove_one(struct pci_dev
*dev
)
3544 static const struct tty_operations ops
= {
3548 .put_char
= put_char
,
3549 .flush_chars
= flush_chars
,
3550 .write_room
= write_room
,
3551 .chars_in_buffer
= chars_in_buffer
,
3552 .flush_buffer
= flush_buffer
,
3554 .compat_ioctl
= slgt_compat_ioctl
,
3555 .throttle
= throttle
,
3556 .unthrottle
= unthrottle
,
3557 .send_xchar
= send_xchar
,
3558 .break_ctl
= set_break
,
3559 .wait_until_sent
= wait_until_sent
,
3560 .read_proc
= read_proc
,
3561 .set_termios
= set_termios
,
3563 .start
= tx_release
,
3565 .tiocmget
= tiocmget
,
3566 .tiocmset
= tiocmset
,
3569 static void slgt_cleanup(void)
3572 struct slgt_info
*info
;
3573 struct slgt_info
*tmp
;
3575 printk("unload %s %s\n", driver_name
, driver_version
);
3577 if (serial_driver
) {
3578 for (info
=slgt_device_list
; info
!= NULL
; info
=info
->next_device
)
3579 tty_unregister_device(serial_driver
, info
->line
);
3580 if ((rc
= tty_unregister_driver(serial_driver
)))
3581 DBGERR(("tty_unregister_driver error=%d\n", rc
));
3582 put_tty_driver(serial_driver
);
3586 info
= slgt_device_list
;
3589 info
= info
->next_device
;
3592 /* release devices */
3593 info
= slgt_device_list
;
3595 #if SYNCLINK_GENERIC_HDLC
3598 free_dma_bufs(info
);
3599 free_tmp_rbuf(info
);
3600 if (info
->port_num
== 0)
3601 release_resources(info
);
3603 info
= info
->next_device
;
3608 pci_unregister_driver(&pci_driver
);
3612 * Driver initialization entry point.
3614 static int __init
slgt_init(void)
3618 printk("%s %s\n", driver_name
, driver_version
);
3620 serial_driver
= alloc_tty_driver(MAX_DEVICES
);
3621 if (!serial_driver
) {
3622 printk("%s can't allocate tty driver\n", driver_name
);
3626 /* Initialize the tty_driver structure */
3628 serial_driver
->owner
= THIS_MODULE
;
3629 serial_driver
->driver_name
= tty_driver_name
;
3630 serial_driver
->name
= tty_dev_prefix
;
3631 serial_driver
->major
= ttymajor
;
3632 serial_driver
->minor_start
= 64;
3633 serial_driver
->type
= TTY_DRIVER_TYPE_SERIAL
;
3634 serial_driver
->subtype
= SERIAL_TYPE_NORMAL
;
3635 serial_driver
->init_termios
= tty_std_termios
;
3636 serial_driver
->init_termios
.c_cflag
=
3637 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
3638 serial_driver
->init_termios
.c_ispeed
= 9600;
3639 serial_driver
->init_termios
.c_ospeed
= 9600;
3640 serial_driver
->flags
= TTY_DRIVER_REAL_RAW
| TTY_DRIVER_DYNAMIC_DEV
;
3641 tty_set_operations(serial_driver
, &ops
);
3642 if ((rc
= tty_register_driver(serial_driver
)) < 0) {
3643 DBGERR(("%s can't register serial driver\n", driver_name
));
3644 put_tty_driver(serial_driver
);
3645 serial_driver
= NULL
;
3649 printk("%s %s, tty major#%d\n",
3650 driver_name
, driver_version
,
3651 serial_driver
->major
);
3653 slgt_device_count
= 0;
3654 if ((rc
= pci_register_driver(&pci_driver
)) < 0) {
3655 printk("%s pci_register_driver error=%d\n", driver_name
, rc
);
3658 pci_registered
= true;
3660 if (!slgt_device_list
)
3661 printk("%s no devices found\n",driver_name
);
3670 static void __exit
slgt_exit(void)
3675 module_init(slgt_init
);
3676 module_exit(slgt_exit
);
3679 * register access routines
3682 #define CALC_REGADDR() \
3683 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3685 reg_addr += (info->port_num) * 32;
3687 static __u8
rd_reg8(struct slgt_info
*info
, unsigned int addr
)
3690 return readb((void __iomem
*)reg_addr
);
3693 static void wr_reg8(struct slgt_info
*info
, unsigned int addr
, __u8 value
)
3696 writeb(value
, (void __iomem
*)reg_addr
);
3699 static __u16
rd_reg16(struct slgt_info
*info
, unsigned int addr
)
3702 return readw((void __iomem
*)reg_addr
);
3705 static void wr_reg16(struct slgt_info
*info
, unsigned int addr
, __u16 value
)
3708 writew(value
, (void __iomem
*)reg_addr
);
3711 static __u32
rd_reg32(struct slgt_info
*info
, unsigned int addr
)
3714 return readl((void __iomem
*)reg_addr
);
3717 static void wr_reg32(struct slgt_info
*info
, unsigned int addr
, __u32 value
)
3720 writel(value
, (void __iomem
*)reg_addr
);
3723 static void rdma_reset(struct slgt_info
*info
)
3728 wr_reg32(info
, RDCSR
, BIT1
);
3730 /* wait for enable bit cleared */
3731 for(i
=0 ; i
< 1000 ; i
++)
3732 if (!(rd_reg32(info
, RDCSR
) & BIT0
))
3736 static void tdma_reset(struct slgt_info
*info
)
3741 wr_reg32(info
, TDCSR
, BIT1
);
3743 /* wait for enable bit cleared */
3744 for(i
=0 ; i
< 1000 ; i
++)
3745 if (!(rd_reg32(info
, TDCSR
) & BIT0
))
3750 * enable internal loopback
3751 * TxCLK and RxCLK are generated from BRG
3752 * and TxD is looped back to RxD internally.
3754 static void enable_loopback(struct slgt_info
*info
)
3756 /* SCR (serial control) BIT2=looopback enable */
3757 wr_reg16(info
, SCR
, (unsigned short)(rd_reg16(info
, SCR
) | BIT2
));
3759 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
3760 /* CCR (clock control)
3761 * 07..05 tx clock source (010 = BRG)
3762 * 04..02 rx clock source (010 = BRG)
3763 * 01 auxclk enable (0 = disable)
3764 * 00 BRG enable (1 = enable)
3768 wr_reg8(info
, CCR
, 0x49);
3770 /* set speed if available, otherwise use default */
3771 if (info
->params
.clock_speed
)
3772 set_rate(info
, info
->params
.clock_speed
);
3774 set_rate(info
, 3686400);
3779 * set baud rate generator to specified rate
3781 static void set_rate(struct slgt_info
*info
, u32 rate
)
3784 static unsigned int osc
= 14745600;
3786 /* div = osc/rate - 1
3788 * Round div up if osc/rate is not integer to
3789 * force to next slowest rate.
3794 if (!(osc
% rate
) && div
)
3796 wr_reg16(info
, BDR
, (unsigned short)div
);
3800 static void rx_stop(struct slgt_info
*info
)
3804 /* disable and reset receiver */
3805 val
= rd_reg16(info
, RCR
) & ~BIT1
; /* clear enable bit */
3806 wr_reg16(info
, RCR
, (unsigned short)(val
| BIT2
)); /* set reset bit */
3807 wr_reg16(info
, RCR
, val
); /* clear reset bit */
3809 slgt_irq_off(info
, IRQ_RXOVER
+ IRQ_RXDATA
+ IRQ_RXIDLE
);
3811 /* clear pending rx interrupts */
3812 wr_reg16(info
, SSR
, IRQ_RXIDLE
+ IRQ_RXOVER
);
3816 info
->rx_enabled
= false;
3817 info
->rx_restart
= false;
3820 static void rx_start(struct slgt_info
*info
)
3824 slgt_irq_off(info
, IRQ_RXOVER
+ IRQ_RXDATA
);
3826 /* clear pending rx overrun IRQ */
3827 wr_reg16(info
, SSR
, IRQ_RXOVER
);
3829 /* reset and disable receiver */
3830 val
= rd_reg16(info
, RCR
) & ~BIT1
; /* clear enable bit */
3831 wr_reg16(info
, RCR
, (unsigned short)(val
| BIT2
)); /* set reset bit */
3832 wr_reg16(info
, RCR
, val
); /* clear reset bit */
3837 /* set 1st descriptor address */
3838 wr_reg32(info
, RDDAR
, info
->rbufs
[0].pdesc
);
3840 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
3841 /* enable rx DMA and DMA interrupt */
3842 wr_reg32(info
, RDCSR
, (BIT2
+ BIT0
));
3844 /* enable saving of rx status, rx DMA and DMA interrupt */
3845 wr_reg32(info
, RDCSR
, (BIT6
+ BIT2
+ BIT0
));
3848 slgt_irq_on(info
, IRQ_RXOVER
);
3850 /* enable receiver */
3851 wr_reg16(info
, RCR
, (unsigned short)(rd_reg16(info
, RCR
) | BIT1
));
3853 info
->rx_restart
= false;
3854 info
->rx_enabled
= true;
3857 static void tx_start(struct slgt_info
*info
)
3859 if (!info
->tx_enabled
) {
3861 (unsigned short)((rd_reg16(info
, TCR
) | BIT1
) & ~BIT2
));
3862 info
->tx_enabled
= true;
3865 if (info
->tx_count
) {
3866 info
->drop_rts_on_tx_done
= false;
3868 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
3869 if (info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
3871 if (!(info
->signals
& SerialSignal_RTS
)) {
3872 info
->signals
|= SerialSignal_RTS
;
3874 info
->drop_rts_on_tx_done
= true;
3878 slgt_irq_off(info
, IRQ_TXDATA
);
3879 slgt_irq_on(info
, IRQ_TXUNDER
+ IRQ_TXIDLE
);
3880 /* clear tx idle and underrun status bits */
3881 wr_reg16(info
, SSR
, (unsigned short)(IRQ_TXIDLE
+ IRQ_TXUNDER
));
3882 if (info
->params
.mode
== MGSL_MODE_HDLC
)
3883 mod_timer(&info
->tx_timer
, jiffies
+
3884 msecs_to_jiffies(5000));
3886 slgt_irq_off(info
, IRQ_TXDATA
);
3887 slgt_irq_on(info
, IRQ_TXIDLE
);
3888 /* clear tx idle status bit */
3889 wr_reg16(info
, SSR
, IRQ_TXIDLE
);
3892 info
->tx_active
= true;
3897 * start transmit DMA if inactive and there are unsent buffers
3899 static void tdma_start(struct slgt_info
*info
)
3903 if (rd_reg32(info
, TDCSR
) & BIT0
)
3906 /* transmit DMA inactive, check for unsent buffers */
3907 i
= info
->tbuf_start
;
3908 while (!desc_count(info
->tbufs
[i
])) {
3909 if (++i
== info
->tbuf_count
)
3911 if (i
== info
->tbuf_current
)
3914 info
->tbuf_start
= i
;
3916 /* there are unsent buffers, start transmit DMA */
3918 /* reset needed if previous error condition */
3921 /* set 1st descriptor address */
3922 wr_reg32(info
, TDDAR
, info
->tbufs
[info
->tbuf_start
].pdesc
);
3923 switch(info
->params
.mode
) {
3925 case MGSL_MODE_MONOSYNC
:
3926 case MGSL_MODE_BISYNC
:
3927 wr_reg32(info
, TDCSR
, BIT2
+ BIT0
); /* IRQ + DMA enable */
3930 wr_reg32(info
, TDCSR
, BIT0
); /* DMA enable */
3934 static void tx_stop(struct slgt_info
*info
)
3938 del_timer(&info
->tx_timer
);
3942 /* reset and disable transmitter */
3943 val
= rd_reg16(info
, TCR
) & ~BIT1
; /* clear enable bit */
3944 wr_reg16(info
, TCR
, (unsigned short)(val
| BIT2
)); /* set reset bit */
3946 slgt_irq_off(info
, IRQ_TXDATA
+ IRQ_TXIDLE
+ IRQ_TXUNDER
);
3948 /* clear tx idle and underrun status bit */
3949 wr_reg16(info
, SSR
, (unsigned short)(IRQ_TXIDLE
+ IRQ_TXUNDER
));
3953 info
->tx_enabled
= false;
3954 info
->tx_active
= false;
3957 static void reset_port(struct slgt_info
*info
)
3959 if (!info
->reg_addr
)
3965 info
->signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
3968 slgt_irq_off(info
, IRQ_ALL
| IRQ_MASTER
);
3971 static void reset_adapter(struct slgt_info
*info
)
3974 for (i
=0; i
< info
->port_count
; ++i
) {
3975 if (info
->port_array
[i
])
3976 reset_port(info
->port_array
[i
]);
3980 static void async_mode(struct slgt_info
*info
)
3984 slgt_irq_off(info
, IRQ_ALL
| IRQ_MASTER
);
3990 * 15..13 mode, 010=async
3991 * 12..10 encoding, 000=NRZ
3993 * 08 1=odd parity, 0=even parity
3994 * 07 1=RTS driver control
3996 * 05..04 character length
4001 * 03 0=1 stop bit, 1=2 stop bits
4004 * 00 auto-CTS enable
4008 if (info
->if_mode
& MGSL_INTERFACE_RTS_EN
)
4011 if (info
->params
.parity
!= ASYNC_PARITY_NONE
) {
4013 if (info
->params
.parity
== ASYNC_PARITY_ODD
)
4017 switch (info
->params
.data_bits
)
4019 case 6: val
|= BIT4
; break;
4020 case 7: val
|= BIT5
; break;
4021 case 8: val
|= BIT5
+ BIT4
; break;
4024 if (info
->params
.stop_bits
!= 1)
4027 if (info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
4030 wr_reg16(info
, TCR
, val
);
4034 * 15..13 mode, 010=async
4035 * 12..10 encoding, 000=NRZ
4037 * 08 1=odd parity, 0=even parity
4038 * 07..06 reserved, must be 0
4039 * 05..04 character length
4044 * 03 reserved, must be zero
4047 * 00 auto-DCD enable
4051 if (info
->params
.parity
!= ASYNC_PARITY_NONE
) {
4053 if (info
->params
.parity
== ASYNC_PARITY_ODD
)
4057 switch (info
->params
.data_bits
)
4059 case 6: val
|= BIT4
; break;
4060 case 7: val
|= BIT5
; break;
4061 case 8: val
|= BIT5
+ BIT4
; break;
4064 if (info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
4067 wr_reg16(info
, RCR
, val
);
4069 /* CCR (clock control)
4071 * 07..05 011 = tx clock source is BRG/16
4072 * 04..02 010 = rx clock source is BRG
4073 * 01 0 = auxclk disabled
4074 * 00 1 = BRG enabled
4078 wr_reg8(info
, CCR
, 0x69);
4082 /* SCR (serial control)
4084 * 15 1=tx req on FIFO half empty
4085 * 14 1=rx req on FIFO half full
4086 * 13 tx data IRQ enable
4087 * 12 tx idle IRQ enable
4088 * 11 rx break on IRQ enable
4089 * 10 rx data IRQ enable
4090 * 09 rx break off IRQ enable
4091 * 08 overrun IRQ enable
4096 * 03 reserved, must be zero
4097 * 02 1=txd->rxd internal loopback enable
4098 * 01 reserved, must be zero
4099 * 00 1=master IRQ enable
4101 val
= BIT15
+ BIT14
+ BIT0
;
4102 wr_reg16(info
, SCR
, val
);
4104 slgt_irq_on(info
, IRQ_RXBREAK
| IRQ_RXOVER
);
4106 set_rate(info
, info
->params
.data_rate
* 16);
4108 if (info
->params
.loopback
)
4109 enable_loopback(info
);
4112 static void sync_mode(struct slgt_info
*info
)
4116 slgt_irq_off(info
, IRQ_ALL
| IRQ_MASTER
);
4122 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4126 * 07 1=RTS driver control
4127 * 06 preamble enable
4128 * 05..04 preamble length
4129 * 03 share open/close flag
4132 * 00 auto-CTS enable
4136 switch(info
->params
.mode
) {
4137 case MGSL_MODE_MONOSYNC
: val
|= BIT14
+ BIT13
; break;
4138 case MGSL_MODE_BISYNC
: val
|= BIT15
; break;
4139 case MGSL_MODE_RAW
: val
|= BIT13
; break;
4141 if (info
->if_mode
& MGSL_INTERFACE_RTS_EN
)
4144 switch(info
->params
.encoding
)
4146 case HDLC_ENCODING_NRZB
: val
|= BIT10
; break;
4147 case HDLC_ENCODING_NRZI_MARK
: val
|= BIT11
; break;
4148 case HDLC_ENCODING_NRZI
: val
|= BIT11
+ BIT10
; break;
4149 case HDLC_ENCODING_BIPHASE_MARK
: val
|= BIT12
; break;
4150 case HDLC_ENCODING_BIPHASE_SPACE
: val
|= BIT12
+ BIT10
; break;
4151 case HDLC_ENCODING_BIPHASE_LEVEL
: val
|= BIT12
+ BIT11
; break;
4152 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: val
|= BIT12
+ BIT11
+ BIT10
; break;
4155 switch (info
->params
.crc_type
& HDLC_CRC_MASK
)
4157 case HDLC_CRC_16_CCITT
: val
|= BIT9
; break;
4158 case HDLC_CRC_32_CCITT
: val
|= BIT9
+ BIT8
; break;
4161 if (info
->params
.preamble
!= HDLC_PREAMBLE_PATTERN_NONE
)
4164 switch (info
->params
.preamble_length
)
4166 case HDLC_PREAMBLE_LENGTH_16BITS
: val
|= BIT5
; break;
4167 case HDLC_PREAMBLE_LENGTH_32BITS
: val
|= BIT4
; break;
4168 case HDLC_PREAMBLE_LENGTH_64BITS
: val
|= BIT5
+ BIT4
; break;
4171 if (info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
4174 wr_reg16(info
, TCR
, val
);
4176 /* TPR (transmit preamble) */
4178 switch (info
->params
.preamble
)
4180 case HDLC_PREAMBLE_PATTERN_FLAGS
: val
= 0x7e; break;
4181 case HDLC_PREAMBLE_PATTERN_ONES
: val
= 0xff; break;
4182 case HDLC_PREAMBLE_PATTERN_ZEROS
: val
= 0x00; break;
4183 case HDLC_PREAMBLE_PATTERN_10
: val
= 0x55; break;
4184 case HDLC_PREAMBLE_PATTERN_01
: val
= 0xaa; break;
4185 default: val
= 0x7e; break;
4187 wr_reg8(info
, TPR
, (unsigned char)val
);
4191 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4195 * 07..03 reserved, must be 0
4198 * 00 auto-DCD enable
4202 switch(info
->params
.mode
) {
4203 case MGSL_MODE_MONOSYNC
: val
|= BIT14
+ BIT13
; break;
4204 case MGSL_MODE_BISYNC
: val
|= BIT15
; break;
4205 case MGSL_MODE_RAW
: val
|= BIT13
; break;
4208 switch(info
->params
.encoding
)
4210 case HDLC_ENCODING_NRZB
: val
|= BIT10
; break;
4211 case HDLC_ENCODING_NRZI_MARK
: val
|= BIT11
; break;
4212 case HDLC_ENCODING_NRZI
: val
|= BIT11
+ BIT10
; break;
4213 case HDLC_ENCODING_BIPHASE_MARK
: val
|= BIT12
; break;
4214 case HDLC_ENCODING_BIPHASE_SPACE
: val
|= BIT12
+ BIT10
; break;
4215 case HDLC_ENCODING_BIPHASE_LEVEL
: val
|= BIT12
+ BIT11
; break;
4216 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: val
|= BIT12
+ BIT11
+ BIT10
; break;
4219 switch (info
->params
.crc_type
& HDLC_CRC_MASK
)
4221 case HDLC_CRC_16_CCITT
: val
|= BIT9
; break;
4222 case HDLC_CRC_32_CCITT
: val
|= BIT9
+ BIT8
; break;
4225 if (info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
4228 wr_reg16(info
, RCR
, val
);
4230 /* CCR (clock control)
4232 * 07..05 tx clock source
4233 * 04..02 rx clock source
4239 if (info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4241 // when RxC source is DPLL, BRG generates 16X DPLL
4242 // reference clock, so take TxC from BRG/16 to get
4243 // transmit clock at actual data rate
4244 if (info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4245 val
|= BIT6
+ BIT5
; /* 011, txclk = BRG/16 */
4247 val
|= BIT6
; /* 010, txclk = BRG */
4249 else if (info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
4250 val
|= BIT7
; /* 100, txclk = DPLL Input */
4251 else if (info
->params
.flags
& HDLC_FLAG_TXC_RXCPIN
)
4252 val
|= BIT5
; /* 001, txclk = RXC Input */
4254 if (info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
4255 val
|= BIT3
; /* 010, rxclk = BRG */
4256 else if (info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4257 val
|= BIT4
; /* 100, rxclk = DPLL */
4258 else if (info
->params
.flags
& HDLC_FLAG_RXC_TXCPIN
)
4259 val
|= BIT2
; /* 001, rxclk = TXC Input */
4261 if (info
->params
.clock_speed
)
4264 wr_reg8(info
, CCR
, (unsigned char)val
);
4266 if (info
->params
.flags
& (HDLC_FLAG_TXC_DPLL
+ HDLC_FLAG_RXC_DPLL
))
4268 // program DPLL mode
4269 switch(info
->params
.encoding
)
4271 case HDLC_ENCODING_BIPHASE_MARK
:
4272 case HDLC_ENCODING_BIPHASE_SPACE
:
4274 case HDLC_ENCODING_BIPHASE_LEVEL
:
4275 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
:
4276 val
= BIT7
+ BIT6
; break;
4277 default: val
= BIT6
; // NRZ encodings
4279 wr_reg16(info
, RCR
, (unsigned short)(rd_reg16(info
, RCR
) | val
));
4281 // DPLL requires a 16X reference clock from BRG
4282 set_rate(info
, info
->params
.clock_speed
* 16);
4285 set_rate(info
, info
->params
.clock_speed
);
4291 /* SCR (serial control)
4293 * 15 1=tx req on FIFO half empty
4294 * 14 1=rx req on FIFO half full
4295 * 13 tx data IRQ enable
4296 * 12 tx idle IRQ enable
4297 * 11 underrun IRQ enable
4298 * 10 rx data IRQ enable
4299 * 09 rx idle IRQ enable
4300 * 08 overrun IRQ enable
4305 * 03 reserved, must be zero
4306 * 02 1=txd->rxd internal loopback enable
4307 * 01 reserved, must be zero
4308 * 00 1=master IRQ enable
4310 wr_reg16(info
, SCR
, BIT15
+ BIT14
+ BIT0
);
4312 if (info
->params
.loopback
)
4313 enable_loopback(info
);
4317 * set transmit idle mode
4319 static void tx_set_idle(struct slgt_info
*info
)
4324 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4325 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4327 tcr
= rd_reg16(info
, TCR
);
4328 if (info
->idle_mode
& HDLC_TXIDLE_CUSTOM_16
) {
4329 /* disable preamble, set idle size to 16 bits */
4330 tcr
= (tcr
& ~(BIT6
+ BIT5
)) | BIT4
;
4331 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4332 wr_reg8(info
, TPR
, (unsigned char)((info
->idle_mode
>> 8) & 0xff));
4333 } else if (!(tcr
& BIT6
)) {
4334 /* preamble is disabled, set idle size to 8 bits */
4335 tcr
&= ~(BIT5
+ BIT4
);
4337 wr_reg16(info
, TCR
, tcr
);
4339 if (info
->idle_mode
& (HDLC_TXIDLE_CUSTOM_8
| HDLC_TXIDLE_CUSTOM_16
)) {
4340 /* LSB of custom tx idle specified in tx idle register */
4341 val
= (unsigned char)(info
->idle_mode
& 0xff);
4343 /* standard 8 bit idle patterns */
4344 switch(info
->idle_mode
)
4346 case HDLC_TXIDLE_FLAGS
: val
= 0x7e; break;
4347 case HDLC_TXIDLE_ALT_ZEROS_ONES
:
4348 case HDLC_TXIDLE_ALT_MARK_SPACE
: val
= 0xaa; break;
4349 case HDLC_TXIDLE_ZEROS
:
4350 case HDLC_TXIDLE_SPACE
: val
= 0x00; break;
4351 default: val
= 0xff;
4355 wr_reg8(info
, TIR
, val
);
4359 * get state of V24 status (input) signals
4361 static void get_signals(struct slgt_info
*info
)
4363 unsigned short status
= rd_reg16(info
, SSR
);
4365 /* clear all serial signals except DTR and RTS */
4366 info
->signals
&= SerialSignal_DTR
+ SerialSignal_RTS
;
4369 info
->signals
|= SerialSignal_DSR
;
4371 info
->signals
|= SerialSignal_CTS
;
4373 info
->signals
|= SerialSignal_DCD
;
4375 info
->signals
|= SerialSignal_RI
;
4379 * set V.24 Control Register based on current configuration
4381 static void msc_set_vcr(struct slgt_info
*info
)
4383 unsigned char val
= 0;
4385 /* VCR (V.24 control)
4387 * 07..04 serial IF select
4394 switch(info
->if_mode
& MGSL_INTERFACE_MASK
)
4396 case MGSL_INTERFACE_RS232
:
4397 val
|= BIT5
; /* 0010 */
4399 case MGSL_INTERFACE_V35
:
4400 val
|= BIT7
+ BIT6
+ BIT5
; /* 1110 */
4402 case MGSL_INTERFACE_RS422
:
4403 val
|= BIT6
; /* 0100 */
4407 if (info
->signals
& SerialSignal_DTR
)
4409 if (info
->signals
& SerialSignal_RTS
)
4411 if (info
->if_mode
& MGSL_INTERFACE_LL
)
4413 if (info
->if_mode
& MGSL_INTERFACE_RL
)
4415 wr_reg8(info
, VCR
, val
);
4419 * set state of V24 control (output) signals
4421 static void set_signals(struct slgt_info
*info
)
4423 unsigned char val
= rd_reg8(info
, VCR
);
4424 if (info
->signals
& SerialSignal_DTR
)
4428 if (info
->signals
& SerialSignal_RTS
)
4432 wr_reg8(info
, VCR
, val
);
4436 * free range of receive DMA buffers (i to last)
4438 static void free_rbufs(struct slgt_info
*info
, unsigned int i
, unsigned int last
)
4443 /* reset current buffer for reuse */
4444 info
->rbufs
[i
].status
= 0;
4445 switch(info
->params
.mode
) {
4447 case MGSL_MODE_MONOSYNC
:
4448 case MGSL_MODE_BISYNC
:
4449 set_desc_count(info
->rbufs
[i
], info
->raw_rx_size
);
4452 set_desc_count(info
->rbufs
[i
], DMABUFSIZE
);
4457 if (++i
== info
->rbuf_count
)
4460 info
->rbuf_current
= i
;
4464 * mark all receive DMA buffers as free
4466 static void reset_rbufs(struct slgt_info
*info
)
4468 free_rbufs(info
, 0, info
->rbuf_count
- 1);
4472 * pass receive HDLC frame to upper layer
4474 * return true if frame available, otherwise false
4476 static bool rx_get_frame(struct slgt_info
*info
)
4478 unsigned int start
, end
;
4479 unsigned short status
;
4480 unsigned int framesize
= 0;
4481 unsigned long flags
;
4482 struct tty_struct
*tty
= info
->tty
;
4483 unsigned char addr_field
= 0xff;
4484 unsigned int crc_size
= 0;
4486 switch (info
->params
.crc_type
& HDLC_CRC_MASK
) {
4487 case HDLC_CRC_16_CCITT
: crc_size
= 2; break;
4488 case HDLC_CRC_32_CCITT
: crc_size
= 4; break;
4495 start
= end
= info
->rbuf_current
;
4498 if (!desc_complete(info
->rbufs
[end
]))
4501 if (framesize
== 0 && info
->params
.addr_filter
!= 0xff)
4502 addr_field
= info
->rbufs
[end
].buf
[0];
4504 framesize
+= desc_count(info
->rbufs
[end
]);
4506 if (desc_eof(info
->rbufs
[end
]))
4509 if (++end
== info
->rbuf_count
)
4512 if (end
== info
->rbuf_current
) {
4513 if (info
->rx_enabled
){
4514 spin_lock_irqsave(&info
->lock
,flags
);
4516 spin_unlock_irqrestore(&info
->lock
,flags
);
4524 * 15 buffer complete
4527 * 02 eof (end of frame)
4531 status
= desc_status(info
->rbufs
[end
]);
4533 /* ignore CRC bit if not using CRC (bit is undefined) */
4534 if ((info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_NONE
)
4537 if (framesize
== 0 ||
4538 (addr_field
!= 0xff && addr_field
!= info
->params
.addr_filter
)) {
4539 free_rbufs(info
, start
, end
);
4543 if (framesize
< (2 + crc_size
) || status
& BIT0
) {
4544 info
->icount
.rxshort
++;
4546 } else if (status
& BIT1
) {
4547 info
->icount
.rxcrc
++;
4548 if (!(info
->params
.crc_type
& HDLC_CRC_RETURN_EX
))
4552 #if SYNCLINK_GENERIC_HDLC
4553 if (framesize
== 0) {
4554 struct net_device_stats
*stats
= hdlc_stats(info
->netdev
);
4556 stats
->rx_frame_errors
++;
4560 DBGBH(("%s rx frame status=%04X size=%d\n",
4561 info
->device_name
, status
, framesize
));
4562 DBGDATA(info
, info
->rbufs
[start
].buf
, min_t(int, framesize
, DMABUFSIZE
), "rx");
4565 if (!(info
->params
.crc_type
& HDLC_CRC_RETURN_EX
)) {
4566 framesize
-= crc_size
;
4570 if (framesize
> info
->max_frame_size
+ crc_size
)
4571 info
->icount
.rxlong
++;
4573 /* copy dma buffer(s) to contiguous temp buffer */
4574 int copy_count
= framesize
;
4576 unsigned char *p
= info
->tmp_rbuf
;
4577 info
->tmp_rbuf_count
= framesize
;
4579 info
->icount
.rxok
++;
4582 int partial_count
= min(copy_count
, DMABUFSIZE
);
4583 memcpy(p
, info
->rbufs
[i
].buf
, partial_count
);
4585 copy_count
-= partial_count
;
4586 if (++i
== info
->rbuf_count
)
4590 if (info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) {
4591 *p
= (status
& BIT1
) ? RX_CRC_ERROR
: RX_OK
;
4595 #if SYNCLINK_GENERIC_HDLC
4597 hdlcdev_rx(info
,info
->tmp_rbuf
, framesize
);
4600 ldisc_receive_buf(tty
, info
->tmp_rbuf
, info
->flag_buf
, framesize
);
4603 free_rbufs(info
, start
, end
);
4611 * pass receive buffer (RAW synchronous mode) to tty layer
4612 * return true if buffer available, otherwise false
4614 static bool rx_get_buf(struct slgt_info
*info
)
4616 unsigned int i
= info
->rbuf_current
;
4619 if (!desc_complete(info
->rbufs
[i
]))
4621 count
= desc_count(info
->rbufs
[i
]);
4622 switch(info
->params
.mode
) {
4623 case MGSL_MODE_MONOSYNC
:
4624 case MGSL_MODE_BISYNC
:
4625 /* ignore residue in byte synchronous modes */
4626 if (desc_residue(info
->rbufs
[i
]))
4630 DBGDATA(info
, info
->rbufs
[i
].buf
, count
, "rx");
4631 DBGINFO(("rx_get_buf size=%d\n", count
));
4633 ldisc_receive_buf(info
->tty
, info
->rbufs
[i
].buf
,
4634 info
->flag_buf
, count
);
4635 free_rbufs(info
, i
, i
);
4639 static void reset_tbufs(struct slgt_info
*info
)
4642 info
->tbuf_current
= 0;
4643 for (i
=0 ; i
< info
->tbuf_count
; i
++) {
4644 info
->tbufs
[i
].status
= 0;
4645 info
->tbufs
[i
].count
= 0;
4650 * return number of free transmit DMA buffers
4652 static unsigned int free_tbuf_count(struct slgt_info
*info
)
4654 unsigned int count
= 0;
4655 unsigned int i
= info
->tbuf_current
;
4659 if (desc_count(info
->tbufs
[i
]))
4660 break; /* buffer in use */
4662 if (++i
== info
->tbuf_count
)
4664 } while (i
!= info
->tbuf_current
);
4666 /* if tx DMA active, last zero count buffer is in use */
4667 if (count
&& (rd_reg32(info
, TDCSR
) & BIT0
))
4674 * load transmit DMA buffer(s) with data
4676 static void tx_load(struct slgt_info
*info
, const char *buf
, unsigned int size
)
4678 unsigned short count
;
4680 struct slgt_desc
*d
;
4685 DBGDATA(info
, buf
, size
, "tx");
4687 info
->tbuf_start
= i
= info
->tbuf_current
;
4690 d
= &info
->tbufs
[i
];
4691 if (++i
== info
->tbuf_count
)
4694 count
= (unsigned short)((size
> DMABUFSIZE
) ? DMABUFSIZE
: size
);
4695 memcpy(d
->buf
, buf
, count
);
4701 * set EOF bit for last buffer of HDLC frame or
4702 * for every buffer in raw mode
4704 if ((!size
&& info
->params
.mode
== MGSL_MODE_HDLC
) ||
4705 info
->params
.mode
== MGSL_MODE_RAW
)
4706 set_desc_eof(*d
, 1);
4708 set_desc_eof(*d
, 0);
4710 set_desc_count(*d
, count
);
4713 info
->tbuf_current
= i
;
4716 static int register_test(struct slgt_info
*info
)
4718 static unsigned short patterns
[] =
4719 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4720 static unsigned int count
= sizeof(patterns
)/sizeof(patterns
[0]);
4724 for (i
=0 ; i
< count
; i
++) {
4725 wr_reg16(info
, TIR
, patterns
[i
]);
4726 wr_reg16(info
, BDR
, patterns
[(i
+1)%count
]);
4727 if ((rd_reg16(info
, TIR
) != patterns
[i
]) ||
4728 (rd_reg16(info
, BDR
) != patterns
[(i
+1)%count
])) {
4733 info
->gpio_present
= (rd_reg32(info
, JCR
) & BIT5
) ? 1 : 0;
4734 info
->init_error
= rc
? 0 : DiagStatus_AddressFailure
;
4738 static int irq_test(struct slgt_info
*info
)
4740 unsigned long timeout
;
4741 unsigned long flags
;
4742 struct tty_struct
*oldtty
= info
->tty
;
4743 u32 speed
= info
->params
.data_rate
;
4745 info
->params
.data_rate
= 921600;
4748 spin_lock_irqsave(&info
->lock
, flags
);
4750 slgt_irq_on(info
, IRQ_TXIDLE
);
4752 /* enable transmitter */
4754 (unsigned short)(rd_reg16(info
, TCR
) | BIT1
));
4756 /* write one byte and wait for tx idle */
4757 wr_reg16(info
, TDR
, 0);
4759 /* assume failure */
4760 info
->init_error
= DiagStatus_IrqFailure
;
4761 info
->irq_occurred
= false;
4763 spin_unlock_irqrestore(&info
->lock
, flags
);
4766 while(timeout
-- && !info
->irq_occurred
)
4767 msleep_interruptible(10);
4769 spin_lock_irqsave(&info
->lock
,flags
);
4771 spin_unlock_irqrestore(&info
->lock
,flags
);
4773 info
->params
.data_rate
= speed
;
4776 info
->init_error
= info
->irq_occurred
? 0 : DiagStatus_IrqFailure
;
4777 return info
->irq_occurred
? 0 : -ENODEV
;
4780 static int loopback_test_rx(struct slgt_info
*info
)
4782 unsigned char *src
, *dest
;
4785 if (desc_complete(info
->rbufs
[0])) {
4786 count
= desc_count(info
->rbufs
[0]);
4787 src
= info
->rbufs
[0].buf
;
4788 dest
= info
->tmp_rbuf
;
4790 for( ; count
; count
-=2, src
+=2) {
4791 /* src=data byte (src+1)=status byte */
4792 if (!(*(src
+1) & (BIT9
+ BIT8
))) {
4795 info
->tmp_rbuf_count
++;
4798 DBGDATA(info
, info
->tmp_rbuf
, info
->tmp_rbuf_count
, "rx");
4804 static int loopback_test(struct slgt_info
*info
)
4806 #define TESTFRAMESIZE 20
4808 unsigned long timeout
;
4809 u16 count
= TESTFRAMESIZE
;
4810 unsigned char buf
[TESTFRAMESIZE
];
4812 unsigned long flags
;
4814 struct tty_struct
*oldtty
= info
->tty
;
4817 memcpy(¶ms
, &info
->params
, sizeof(params
));
4819 info
->params
.mode
= MGSL_MODE_ASYNC
;
4820 info
->params
.data_rate
= 921600;
4821 info
->params
.loopback
= 1;
4824 /* build and send transmit frame */
4825 for (count
= 0; count
< TESTFRAMESIZE
; ++count
)
4826 buf
[count
] = (unsigned char)count
;
4828 info
->tmp_rbuf_count
= 0;
4829 memset(info
->tmp_rbuf
, 0, TESTFRAMESIZE
);
4831 /* program hardware for HDLC and enabled receiver */
4832 spin_lock_irqsave(&info
->lock
,flags
);
4835 info
->tx_count
= count
;
4836 tx_load(info
, buf
, count
);
4838 spin_unlock_irqrestore(&info
->lock
, flags
);
4840 /* wait for receive complete */
4841 for (timeout
= 100; timeout
; --timeout
) {
4842 msleep_interruptible(10);
4843 if (loopback_test_rx(info
)) {
4849 /* verify received frame length and contents */
4850 if (!rc
&& (info
->tmp_rbuf_count
!= count
||
4851 memcmp(buf
, info
->tmp_rbuf
, count
))) {
4855 spin_lock_irqsave(&info
->lock
,flags
);
4856 reset_adapter(info
);
4857 spin_unlock_irqrestore(&info
->lock
,flags
);
4859 memcpy(&info
->params
, ¶ms
, sizeof(info
->params
));
4862 info
->init_error
= rc
? DiagStatus_DmaFailure
: 0;
4866 static int adapter_test(struct slgt_info
*info
)
4868 DBGINFO(("testing %s\n", info
->device_name
));
4869 if (register_test(info
) < 0) {
4870 printk("register test failure %s addr=%08X\n",
4871 info
->device_name
, info
->phys_reg_addr
);
4872 } else if (irq_test(info
) < 0) {
4873 printk("IRQ test failure %s IRQ=%d\n",
4874 info
->device_name
, info
->irq_level
);
4875 } else if (loopback_test(info
) < 0) {
4876 printk("loopback test failure %s\n", info
->device_name
);
4878 return info
->init_error
;
4882 * transmit timeout handler
4884 static void tx_timeout(unsigned long context
)
4886 struct slgt_info
*info
= (struct slgt_info
*)context
;
4887 unsigned long flags
;
4889 DBGINFO(("%s tx_timeout\n", info
->device_name
));
4890 if(info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
) {
4891 info
->icount
.txtimeout
++;
4893 spin_lock_irqsave(&info
->lock
,flags
);
4894 info
->tx_active
= false;
4896 spin_unlock_irqrestore(&info
->lock
,flags
);
4898 #if SYNCLINK_GENERIC_HDLC
4900 hdlcdev_tx_done(info
);
4907 * receive buffer polling timer
4909 static void rx_timeout(unsigned long context
)
4911 struct slgt_info
*info
= (struct slgt_info
*)context
;
4912 unsigned long flags
;
4914 DBGINFO(("%s rx_timeout\n", info
->device_name
));
4915 spin_lock_irqsave(&info
->lock
, flags
);
4916 info
->pending_bh
|= BH_RECEIVE
;
4917 spin_unlock_irqrestore(&info
->lock
, flags
);
4918 bh_handler(&info
->task
);