drivers/net/benet/be_cmds.h

   1 /*
   2  * Copyright (C) 2005 - 2009 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17
  18 /*
  19  * The driver sends configuration and managements command requests to the
  20  * firmware in the BE. These requests are communicated to the processor
  21  * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
  22  * WRB inside a MAILBOX.
  23  * The commands are serviced by the ARM processor in the BladeEngine's MPU.
  24  */
  25
  26 struct be_sge {
  27         u32 pa_lo;
  28         u32 pa_hi;
  29         u32 len;
  30 };
  31
  32 #define MCC_WRB_EMBEDDED_MASK   1       /* bit 0 of dword 0*/
  33 #define MCC_WRB_SGE_CNT_SHIFT   3       /* bits 3 - 7 of dword 0 */
  34 #define MCC_WRB_SGE_CNT_MASK    0x1F    /* bits 3 - 7 of dword 0 */
  35 struct be_mcc_wrb {
  36         u32 embedded;           /* dword 0 */
  37         u32 payload_length;     /* dword 1 */
  38         u32 tag0;               /* dword 2 */
  39         u32 tag1;               /* dword 3 */
  40         u32 rsvd;               /* dword 4 */
  41         union {
  42                 u8 embedded_payload[236]; /* used by embedded cmds */
  43                 struct be_sge sgl[19];    /* used by non-embedded cmds */
  44         } payload;
  45 };
  46
  47 #define CQE_FLAGS_VALID_MASK            (1 << 31)
  48 #define CQE_FLAGS_ASYNC_MASK            (1 << 30)
  49 #define CQE_FLAGS_COMPLETED_MASK        (1 << 28)
  50 #define CQE_FLAGS_CONSUMED_MASK         (1 << 27)
  51
  52 /* Completion Status */
  53 enum {
  54         MCC_STATUS_SUCCESS = 0x0,
  55 /* The client does not have sufficient privileges to execute the command */
  56         MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
  57 /* A parameter in the command was invalid. */
  58         MCC_STATUS_INVALID_PARAMETER = 0x2,
  59 /* There are insufficient chip resources to execute the command */
  60         MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
  61 /* The command is completing because the queue was getting flushed */
  62         MCC_STATUS_QUEUE_FLUSHING = 0x4,
  63 /* The command is completing with a DMA error */
  64         MCC_STATUS_DMA_FAILED = 0x5
  65 };
  66
  67 #define CQE_STATUS_COMPL_MASK           0xFFFF
  68 #define CQE_STATUS_COMPL_SHIFT          0       /* bits 0 - 15 */
  69 #define CQE_STATUS_EXTD_MASK            0xFFFF
  70 #define CQE_STATUS_EXTD_SHIFT           0       /* bits 0 - 15 */
  71
  72 struct be_mcc_cq_entry {
  73         u32 status;             /* dword 0 */
  74         u32 tag0;               /* dword 1 */
  75         u32 tag1;               /* dword 2 */
  76         u32 flags;              /* dword 3 */
  77 };
  78
  79 struct be_mcc_mailbox {
  80         struct be_mcc_wrb wrb;
  81         struct be_mcc_cq_entry cqe;
  82 };
  83
  84 #define CMD_SUBSYSTEM_COMMON    0x1
  85 #define CMD_SUBSYSTEM_ETH       0x3
  86
  87 #define OPCODE_COMMON_NTWK_MAC_QUERY                    1
  88 #define OPCODE_COMMON_NTWK_MAC_SET                      2
  89 #define OPCODE_COMMON_NTWK_MULTICAST_SET                3
  90 #define OPCODE_COMMON_NTWK_VLAN_CONFIG                  4
  91 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY            5
  92 #define OPCODE_COMMON_CQ_CREATE                         12
  93 #define OPCODE_COMMON_EQ_CREATE                         13
  94 #define OPCODE_COMMON_MCC_CREATE                        21
  95 #define OPCODE_COMMON_NTWK_RX_FILTER                    34
  96 #define OPCODE_COMMON_GET_FW_VERSION                    35
  97 #define OPCODE_COMMON_SET_FLOW_CONTROL                  36
  98 #define OPCODE_COMMON_GET_FLOW_CONTROL                  37
  99 #define OPCODE_COMMON_SET_FRAME_SIZE                    39
 100 #define OPCODE_COMMON_MODIFY_EQ_DELAY                   41
 101 #define OPCODE_COMMON_FIRMWARE_CONFIG                   42
 102 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE             50
 103 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY            51
 104 #define OPCODE_COMMON_MCC_DESTROY                       53
 105 #define OPCODE_COMMON_CQ_DESTROY                        54
 106 #define OPCODE_COMMON_EQ_DESTROY                        55
 107 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG             58
 108 #define OPCODE_COMMON_NTWK_PMAC_ADD                     59
 109 #define OPCODE_COMMON_NTWK_PMAC_DEL                     60
 110
 111 #define OPCODE_ETH_ACPI_CONFIG                          2
 112 #define OPCODE_ETH_PROMISCUOUS                          3
 113 #define OPCODE_ETH_GET_STATISTICS                       4
 114 #define OPCODE_ETH_TX_CREATE                            7
 115 #define OPCODE_ETH_RX_CREATE                            8
 116 #define OPCODE_ETH_TX_DESTROY                           9
 117 #define OPCODE_ETH_RX_DESTROY                           10
 118
 119 struct be_cmd_req_hdr {
 120         u8 opcode;              /* dword 0 */
 121         u8 subsystem;           /* dword 0 */
 122         u8 port_number;         /* dword 0 */
 123         u8 domain;              /* dword 0 */
 124         u32 timeout;            /* dword 1 */
 125         u32 request_length;     /* dword 2 */
 126         u32 rsvd;               /* dword 3 */
 127 };
 128
 129 #define RESP_HDR_INFO_OPCODE_SHIFT      0       /* bits 0 - 7 */
 130 #define RESP_HDR_INFO_SUBSYS_SHIFT      8       /* bits 8 - 15 */
 131 struct be_cmd_resp_hdr {
 132         u32 info;               /* dword 0 */
 133         u32 status;             /* dword 1 */
 134         u32 response_length;    /* dword 2 */
 135         u32 actual_resp_len;    /* dword 3 */
 136 };
 137
 138 struct phys_addr {
 139         u32 lo;
 140         u32 hi;
 141 };
 142
 143 /**************************
 144  * BE Command definitions *
 145  **************************/
 146
 147 /* Pseudo amap definition in which each bit of the actual structure is defined
 148  * as a byte: used to calculate offset/shift/mask of each field */
 149 struct amap_eq_context {
 150         u8 cidx[13];            /* dword 0*/
 151         u8 rsvd0[3];            /* dword 0*/
 152         u8 epidx[13];           /* dword 0*/
 153         u8 valid;               /* dword 0*/
 154         u8 rsvd1;               /* dword 0*/
 155         u8 size;                /* dword 0*/
 156         u8 pidx[13];            /* dword 1*/
 157         u8 rsvd2[3];            /* dword 1*/
 158         u8 pd[10];              /* dword 1*/
 159         u8 count[3];            /* dword 1*/
 160         u8 solevent;            /* dword 1*/
 161         u8 stalled;             /* dword 1*/
 162         u8 armed;               /* dword 1*/
 163         u8 rsvd3[4];            /* dword 2*/
 164         u8 func[8];             /* dword 2*/
 165         u8 rsvd4;               /* dword 2*/
 166         u8 delaymult[10];       /* dword 2*/
 167         u8 rsvd5[2];            /* dword 2*/
 168         u8 phase[2];            /* dword 2*/
 169         u8 nodelay;             /* dword 2*/
 170         u8 rsvd6[4];            /* dword 2*/
 171         u8 rsvd7[32];           /* dword 3*/
 172 } __packed;
 173
 174 struct be_cmd_req_eq_create {
 175         struct be_cmd_req_hdr hdr;
 176         u16 num_pages;          /* sword */
 177         u16 rsvd0;              /* sword */
 178         u8 context[sizeof(struct amap_eq_context) / 8];
 179         struct phys_addr pages[8];
 180 } __packed;
 181
 182 struct be_cmd_resp_eq_create {
 183         struct be_cmd_resp_hdr resp_hdr;
 184         u16 eq_id;              /* sword */
 185         u16 rsvd0;              /* sword */
 186 } __packed;
 187
 188 /******************** Mac query ***************************/
 189 enum {
 190         MAC_ADDRESS_TYPE_STORAGE = 0x0,
 191         MAC_ADDRESS_TYPE_NETWORK = 0x1,
 192         MAC_ADDRESS_TYPE_PD = 0x2,
 193         MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
 194 };
 195
 196 struct mac_addr {
 197         u16 size_of_struct;
 198         u8 addr[ETH_ALEN];
 199 } __packed;
 200
 201 struct be_cmd_req_mac_query {
 202         struct be_cmd_req_hdr hdr;
 203         u8 type;
 204         u8 permanent;
 205         u16 if_id;
 206 } __packed;
 207
 208 struct be_cmd_resp_mac_query {
 209         struct be_cmd_resp_hdr hdr;
 210         struct mac_addr mac;
 211 };
 212
 213 /******************** PMac Add ***************************/
 214 struct be_cmd_req_pmac_add {
 215         struct be_cmd_req_hdr hdr;
 216         u32 if_id;
 217         u8 mac_address[ETH_ALEN];
 218         u8 rsvd0[2];
 219 } __packed;
 220
 221 struct be_cmd_resp_pmac_add {
 222         struct be_cmd_resp_hdr hdr;
 223         u32 pmac_id;
 224 };
 225
 226 /******************** PMac Del ***************************/
 227 struct be_cmd_req_pmac_del {
 228         struct be_cmd_req_hdr hdr;
 229         u32 if_id;
 230         u32 pmac_id;
 231 };
 232
 233 /******************** Create CQ ***************************/
 234 /* Pseudo amap definition in which each bit of the actual structure is defined
 235  * as a byte: used to calculate offset/shift/mask of each field */
 236 struct amap_cq_context {
 237         u8 cidx[11];            /* dword 0*/
 238         u8 rsvd0;               /* dword 0*/
 239         u8 coalescwm[2];        /* dword 0*/
 240         u8 nodelay;             /* dword 0*/
 241         u8 epidx[11];           /* dword 0*/
 242         u8 rsvd1;               /* dword 0*/
 243         u8 count[2];            /* dword 0*/
 244         u8 valid;               /* dword 0*/
 245         u8 solevent;            /* dword 0*/
 246         u8 eventable;           /* dword 0*/
 247         u8 pidx[11];            /* dword 1*/
 248         u8 rsvd2;               /* dword 1*/
 249         u8 pd[10];              /* dword 1*/
 250         u8 eqid[8];             /* dword 1*/
 251         u8 stalled;             /* dword 1*/
 252         u8 armed;               /* dword 1*/
 253         u8 rsvd3[4];            /* dword 2*/
 254         u8 func[8];             /* dword 2*/
 255         u8 rsvd4[20];           /* dword 2*/
 256         u8 rsvd5[32];           /* dword 3*/
 257 } __packed;
 258
 259 struct be_cmd_req_cq_create {
 260         struct be_cmd_req_hdr hdr;
 261         u16 num_pages;
 262         u16 rsvd0;
 263         u8 context[sizeof(struct amap_cq_context) / 8];
 264         struct phys_addr pages[8];
 265 } __packed;
 266
 267 struct be_cmd_resp_cq_create {
 268         struct be_cmd_resp_hdr hdr;
 269         u16 cq_id;
 270         u16 rsvd0;
 271 } __packed;
 272
 273 /******************** Create MCCQ ***************************/
 274 /* Pseudo amap definition in which each bit of the actual structure is defined
 275  * as a byte: used to calculate offset/shift/mask of each field */
 276 struct amap_mcc_context {
 277         u8 con_index[14];
 278         u8 rsvd0[2];
 279         u8 ring_size[4];
 280         u8 fetch_wrb;
 281         u8 fetch_r2t;
 282         u8 cq_id[10];
 283         u8 prod_index[14];
 284         u8 fid[8];
 285         u8 pdid[9];
 286         u8 valid;
 287         u8 rsvd1[32];
 288         u8 rsvd2[32];
 289 } __packed;
 290
 291 struct be_cmd_req_mcc_create {
 292         struct be_cmd_req_hdr hdr;
 293         u16 num_pages;
 294         u16 rsvd0;
 295         u8 context[sizeof(struct amap_mcc_context) / 8];
 296         struct phys_addr pages[8];
 297 } __packed;
 298
 299 struct be_cmd_resp_mcc_create {
 300         struct be_cmd_resp_hdr hdr;
 301         u16 id;
 302         u16 rsvd0;
 303 } __packed;
 304
 305 /******************** Create TxQ ***************************/
 306 #define BE_ETH_TX_RING_TYPE_STANDARD            2
 307 #define BE_ULP1_NUM                             1
 308
 309 /* Pseudo amap definition in which each bit of the actual structure is defined
 310  * as a byte: used to calculate offset/shift/mask of each field */
 311 struct amap_tx_context {
 312         u8 rsvd0[16];           /* dword 0 */
 313         u8 tx_ring_size[4];     /* dword 0 */
 314         u8 rsvd1[26];           /* dword 0 */
 315         u8 pci_func_id[8];      /* dword 1 */
 316         u8 rsvd2[9];            /* dword 1 */
 317         u8 ctx_valid;           /* dword 1 */
 318         u8 cq_id_send[16];      /* dword 2 */
 319         u8 rsvd3[16];           /* dword 2 */
 320         u8 rsvd4[32];           /* dword 3 */
 321         u8 rsvd5[32];           /* dword 4 */
 322         u8 rsvd6[32];           /* dword 5 */
 323         u8 rsvd7[32];           /* dword 6 */
 324         u8 rsvd8[32];           /* dword 7 */
 325         u8 rsvd9[32];           /* dword 8 */
 326         u8 rsvd10[32];          /* dword 9 */
 327         u8 rsvd11[32];          /* dword 10 */
 328         u8 rsvd12[32];          /* dword 11 */
 329         u8 rsvd13[32];          /* dword 12 */
 330         u8 rsvd14[32];          /* dword 13 */
 331         u8 rsvd15[32];          /* dword 14 */
 332         u8 rsvd16[32];          /* dword 15 */
 333 } __packed;
 334
 335 struct be_cmd_req_eth_tx_create {
 336         struct be_cmd_req_hdr hdr;
 337         u8 num_pages;
 338         u8 ulp_num;
 339         u8 type;
 340         u8 bound_port;
 341         u8 context[sizeof(struct amap_tx_context) / 8];
 342         struct phys_addr pages[8];
 343 } __packed;
 344
 345 struct be_cmd_resp_eth_tx_create {
 346         struct be_cmd_resp_hdr hdr;
 347         u16 cid;
 348         u16 rsvd0;
 349 } __packed;
 350
 351 /******************** Create RxQ ***************************/
 352 struct be_cmd_req_eth_rx_create {
 353         struct be_cmd_req_hdr hdr;
 354         u16 cq_id;
 355         u8 frag_size;
 356         u8 num_pages;
 357         struct phys_addr pages[2];
 358         u32 interface_id;
 359         u16 max_frame_size;
 360         u16 rsvd0;
 361         u32 rss_queue;
 362 } __packed;
 363
 364 struct be_cmd_resp_eth_rx_create {
 365         struct be_cmd_resp_hdr hdr;
 366         u16 id;
 367         u8 cpu_id;
 368         u8 rsvd0;
 369 } __packed;
 370
 371 /******************** Q Destroy  ***************************/
 372 /* Type of Queue to be destroyed */
 373 enum {
 374         QTYPE_EQ = 1,
 375         QTYPE_CQ,
 376         QTYPE_TXQ,
 377         QTYPE_RXQ,
 378         QTYPE_MCCQ
 379 };
 380
 381 struct be_cmd_req_q_destroy {
 382         struct be_cmd_req_hdr hdr;
 383         u16 id;
 384         u16 bypass_flush;       /* valid only for rx q destroy */
 385 } __packed;
 386
 387 /************ I/f Create (it's actually I/f Config Create)**********/
 388
 389 /* Capability flags for the i/f */
 390 enum be_if_flags {
 391         BE_IF_FLAGS_RSS = 0x4,
 392         BE_IF_FLAGS_PROMISCUOUS = 0x8,
 393         BE_IF_FLAGS_BROADCAST = 0x10,
 394         BE_IF_FLAGS_UNTAGGED = 0x20,
 395         BE_IF_FLAGS_ULP = 0x40,
 396         BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
 397         BE_IF_FLAGS_VLAN = 0x100,
 398         BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
 399         BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
 400         BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800
 401 };
 402
 403 /* An RX interface is an object with one or more MAC addresses and
 404  * filtering capabilities. */
 405 struct be_cmd_req_if_create {
 406         struct be_cmd_req_hdr hdr;
 407         u32 version;            /* ignore currntly */
 408         u32 capability_flags;
 409         u32 enable_flags;
 410         u8 mac_addr[ETH_ALEN];
 411         u8 rsvd0;
 412         u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
 413         u32 vlan_tag;    /* not used currently */
 414 } __packed;
 415
 416 struct be_cmd_resp_if_create {
 417         struct be_cmd_resp_hdr hdr;
 418         u32 interface_id;
 419         u32 pmac_id;
 420 };
 421
 422 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
 423 struct be_cmd_req_if_destroy {
 424         struct be_cmd_req_hdr hdr;
 425         u32 interface_id;
 426 };
 427
 428 /*************** HW Stats Get **********************************/
 429 struct be_port_rxf_stats {
 430         u32 rx_bytes_lsd;       /* dword 0*/
 431         u32 rx_bytes_msd;       /* dword 1*/
 432         u32 rx_total_frames;    /* dword 2*/
 433         u32 rx_unicast_frames;  /* dword 3*/
 434         u32 rx_multicast_frames;        /* dword 4*/
 435         u32 rx_broadcast_frames;        /* dword 5*/
 436         u32 rx_crc_errors;      /* dword 6*/
 437         u32 rx_alignment_symbol_errors; /* dword 7*/
 438         u32 rx_pause_frames;    /* dword 8*/
 439         u32 rx_control_frames;  /* dword 9*/
 440         u32 rx_in_range_errors; /* dword 10*/
 441         u32 rx_out_range_errors;        /* dword 11*/
 442         u32 rx_frame_too_long;  /* dword 12*/
 443         u32 rx_address_match_errors;    /* dword 13*/
 444         u32 rx_vlan_mismatch;   /* dword 14*/
 445         u32 rx_dropped_too_small;       /* dword 15*/
 446         u32 rx_dropped_too_short;       /* dword 16*/
 447         u32 rx_dropped_header_too_small;        /* dword 17*/
 448         u32 rx_dropped_tcp_length;      /* dword 18*/
 449         u32 rx_dropped_runt;    /* dword 19*/
 450         u32 rx_64_byte_packets; /* dword 20*/
 451         u32 rx_65_127_byte_packets;     /* dword 21*/
 452         u32 rx_128_256_byte_packets;    /* dword 22*/
 453         u32 rx_256_511_byte_packets;    /* dword 23*/
 454         u32 rx_512_1023_byte_packets;   /* dword 24*/
 455         u32 rx_1024_1518_byte_packets;  /* dword 25*/
 456         u32 rx_1519_2047_byte_packets;  /* dword 26*/
 457         u32 rx_2048_4095_byte_packets;  /* dword 27*/
 458         u32 rx_4096_8191_byte_packets;  /* dword 28*/
 459         u32 rx_8192_9216_byte_packets;  /* dword 29*/
 460         u32 rx_ip_checksum_errs;        /* dword 30*/
 461         u32 rx_tcp_checksum_errs;       /* dword 31*/
 462         u32 rx_udp_checksum_errs;       /* dword 32*/
 463         u32 rx_non_rss_packets; /* dword 33*/
 464         u32 rx_ipv4_packets;    /* dword 34*/
 465         u32 rx_ipv6_packets;    /* dword 35*/
 466         u32 rx_ipv4_bytes_lsd;  /* dword 36*/
 467         u32 rx_ipv4_bytes_msd;  /* dword 37*/
 468         u32 rx_ipv6_bytes_lsd;  /* dword 38*/
 469         u32 rx_ipv6_bytes_msd;  /* dword 39*/
 470         u32 rx_chute1_packets;  /* dword 40*/
 471         u32 rx_chute2_packets;  /* dword 41*/
 472         u32 rx_chute3_packets;  /* dword 42*/
 473         u32 rx_management_packets;      /* dword 43*/
 474         u32 rx_switched_unicast_packets;        /* dword 44*/
 475         u32 rx_switched_multicast_packets;      /* dword 45*/
 476         u32 rx_switched_broadcast_packets;      /* dword 46*/
 477         u32 tx_bytes_lsd;       /* dword 47*/
 478         u32 tx_bytes_msd;       /* dword 48*/
 479         u32 tx_unicastframes;   /* dword 49*/
 480         u32 tx_multicastframes; /* dword 50*/
 481         u32 tx_broadcastframes; /* dword 51*/
 482         u32 tx_pauseframes;     /* dword 52*/
 483         u32 tx_controlframes;   /* dword 53*/
 484         u32 tx_64_byte_packets; /* dword 54*/
 485         u32 tx_65_127_byte_packets;     /* dword 55*/
 486         u32 tx_128_256_byte_packets;    /* dword 56*/
 487         u32 tx_256_511_byte_packets;    /* dword 57*/
 488         u32 tx_512_1023_byte_packets;   /* dword 58*/
 489         u32 tx_1024_1518_byte_packets;  /* dword 59*/
 490         u32 tx_1519_2047_byte_packets;  /* dword 60*/
 491         u32 tx_2048_4095_byte_packets;  /* dword 61*/
 492         u32 tx_4096_8191_byte_packets;  /* dword 62*/
 493         u32 tx_8192_9216_byte_packets;  /* dword 63*/
 494         u32 rx_fifo_overflow;   /* dword 64*/
 495         u32 rx_input_fifo_overflow;     /* dword 65*/
 496 };
 497
 498 struct be_rxf_stats {
 499         struct be_port_rxf_stats port[2];
 500         u32 rx_drops_no_pbuf;   /* dword 132*/
 501         u32 rx_drops_no_txpb;   /* dword 133*/
 502         u32 rx_drops_no_erx_descr;      /* dword 134*/
 503         u32 rx_drops_no_tpre_descr;     /* dword 135*/
 504         u32 management_rx_port_packets; /* dword 136*/
 505         u32 management_rx_port_bytes;   /* dword 137*/
 506         u32 management_rx_port_pause_frames;    /* dword 138*/
 507         u32 management_rx_port_errors;  /* dword 139*/
 508         u32 management_tx_port_packets; /* dword 140*/
 509         u32 management_tx_port_bytes;   /* dword 141*/
 510         u32 management_tx_port_pause;   /* dword 142*/
 511         u32 management_rx_port_rxfifo_overflow; /* dword 143*/
 512         u32 rx_drops_too_many_frags;    /* dword 144*/
 513         u32 rx_drops_invalid_ring;      /* dword 145*/
 514         u32 forwarded_packets;  /* dword 146*/
 515         u32 rx_drops_mtu;       /* dword 147*/
 516         u32 rsvd0[15];
 517 };
 518
 519 struct be_erx_stats {
 520         u32 rx_drops_no_fragments[44];     /* dwordS 0 to 43*/
 521         u32 debug_wdma_sent_hold;          /* dword 44*/
 522         u32 debug_wdma_pbfree_sent_hold;   /* dword 45*/
 523         u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
 524         u32 debug_pmem_pbuf_dealloc;       /* dword 47*/
 525 };
 526
 527 struct be_hw_stats {
 528         struct be_rxf_stats rxf;
 529         u32 rsvd[48];
 530         struct be_erx_stats erx;
 531 };
 532
 533 struct be_cmd_req_get_stats {
 534         struct be_cmd_req_hdr hdr;
 535         u8 rsvd[sizeof(struct be_hw_stats)];
 536 };
 537
 538 struct be_cmd_resp_get_stats {
 539         struct be_cmd_resp_hdr hdr;
 540         struct be_hw_stats hw_stats;
 541 };
 542
 543 struct be_cmd_req_vlan_config {
 544         struct be_cmd_req_hdr hdr;
 545         u8 interface_id;
 546         u8 promiscuous;
 547         u8 untagged;
 548         u8 num_vlan;
 549         u16 normal_vlan[64];
 550 } __packed;
 551
 552 struct be_cmd_req_promiscuous_config {
 553         struct be_cmd_req_hdr hdr;
 554         u8 port0_promiscuous;
 555         u8 port1_promiscuous;
 556         u16 rsvd0;
 557 } __packed;
 558
 559 struct macaddr {
 560         u8 byte[ETH_ALEN];
 561 };
 562
 563 struct be_cmd_req_mcast_mac_config {
 564         struct be_cmd_req_hdr hdr;
 565         u16 num_mac;
 566         u8 promiscuous;
 567         u8 interface_id;
 568         struct macaddr mac[32];
 569 } __packed;
 570
 571 static inline struct be_hw_stats *
 572 hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
 573 {
 574         return &cmd->hw_stats;
 575 }
 576
 577 /******************** Link Status Query *******************/
 578 struct be_cmd_req_link_status {
 579         struct be_cmd_req_hdr hdr;
 580         u32 rsvd;
 581 };
 582
 583 struct be_link_info {
 584         u8 duplex;
 585         u8 speed;
 586         u8 fault;
 587 };
 588
 589 enum {
 590         PHY_LINK_DUPLEX_NONE = 0x0,
 591         PHY_LINK_DUPLEX_HALF = 0x1,
 592         PHY_LINK_DUPLEX_FULL = 0x2
 593 };
 594
 595 enum {
 596         PHY_LINK_SPEED_ZERO = 0x0,      /* => No link */
 597         PHY_LINK_SPEED_10MBPS = 0x1,
 598         PHY_LINK_SPEED_100MBPS = 0x2,
 599         PHY_LINK_SPEED_1GBPS = 0x3,
 600         PHY_LINK_SPEED_10GBPS = 0x4
 601 };
 602
 603 struct be_cmd_resp_link_status {
 604         struct be_cmd_resp_hdr hdr;
 605         u8 physical_port;
 606         u8 mac_duplex;
 607         u8 mac_speed;
 608         u8 mac_fault;
 609         u8 mgmt_mac_duplex;
 610         u8 mgmt_mac_speed;
 611         u16 rsvd0;
 612 } __packed;
 613
 614 /******************** Get FW Version *******************/
 615 #define FW_VER_LEN                      32
 616 struct be_cmd_req_get_fw_version {
 617         struct be_cmd_req_hdr hdr;
 618         u8 rsvd0[FW_VER_LEN];
 619         u8 rsvd1[FW_VER_LEN];
 620 } __packed;
 621
 622 struct be_cmd_resp_get_fw_version {
 623         struct be_cmd_resp_hdr hdr;
 624         u8 firmware_version_string[FW_VER_LEN];
 625         u8 fw_on_flash_version_string[FW_VER_LEN];
 626 } __packed;
 627
 628 /******************** Set Flow Contrl *******************/
 629 struct be_cmd_req_set_flow_control {
 630         struct be_cmd_req_hdr hdr;
 631         u16 tx_flow_control;
 632         u16 rx_flow_control;
 633 } __packed;
 634
 635 /******************** Get Flow Contrl *******************/
 636 struct be_cmd_req_get_flow_control {
 637         struct be_cmd_req_hdr hdr;
 638         u32 rsvd;
 639 };
 640
 641 struct be_cmd_resp_get_flow_control {
 642         struct be_cmd_resp_hdr hdr;
 643         u16 tx_flow_control;
 644         u16 rx_flow_control;
 645 } __packed;
 646
 647 /******************** Modify EQ Delay *******************/
 648 struct be_cmd_req_modify_eq_delay {
 649         struct be_cmd_req_hdr hdr;
 650         u32 num_eq;
 651         struct {
 652                 u32 eq_id;
 653                 u32 phase;
 654                 u32 delay_multiplier;
 655         } delay[8];
 656 } __packed;
 657
 658 struct be_cmd_resp_modify_eq_delay {
 659         struct be_cmd_resp_hdr hdr;
 660         u32 rsvd0;
 661 } __packed;
 662
 663 /******************** Get FW Config *******************/
 664 struct be_cmd_req_query_fw_cfg {
 665         struct be_cmd_req_hdr hdr;
 666         u32 rsvd[30];
 667 };
 668
 669 struct be_cmd_resp_query_fw_cfg {
 670         struct be_cmd_resp_hdr hdr;
 671         u32 be_config_number;
 672         u32 asic_revision;
 673         u32 phys_port;
 674         u32 function_mode;
 675         u32 rsvd[26];
 676 };
 677
 678 extern int be_pci_fnum_get(struct be_ctrl_info *ctrl);
 679 extern int be_cmd_POST(struct be_ctrl_info *ctrl);
 680 extern int be_cmd_mac_addr_query(struct be_ctrl_info *ctrl, u8 *mac_addr,
 681                         u8 type, bool permanent, u32 if_handle);
 682 extern int be_cmd_pmac_add(struct be_ctrl_info *ctrl, u8 *mac_addr,
 683                         u32 if_id, u32 *pmac_id);
 684 extern int be_cmd_pmac_del(struct be_ctrl_info *ctrl, u32 if_id, u32 pmac_id);
 685 extern int be_cmd_if_create(struct be_ctrl_info *ctrl, u32 if_flags, u8 *mac,
 686                         bool pmac_invalid, u32 *if_handle, u32 *pmac_id);
 687 extern int be_cmd_if_destroy(struct be_ctrl_info *ctrl, u32 if_handle);
 688 extern int be_cmd_eq_create(struct be_ctrl_info *ctrl,
 689                         struct be_queue_info *eq, int eq_delay);
 690 extern int be_cmd_cq_create(struct be_ctrl_info *ctrl,
 691                         struct be_queue_info *cq, struct be_queue_info *eq,
 692                         bool sol_evts, bool no_delay,
 693                         int num_cqe_dma_coalesce);
 694 extern int be_cmd_mccq_create(struct be_ctrl_info *ctrl,
 695                         struct be_queue_info *mccq,
 696                         struct be_queue_info *cq);
 697 extern int be_cmd_txq_create(struct be_ctrl_info *ctrl,
 698                         struct be_queue_info *txq,
 699                         struct be_queue_info *cq);
 700 extern int be_cmd_rxq_create(struct be_ctrl_info *ctrl,
 701                         struct be_queue_info *rxq, u16 cq_id,
 702                         u16 frag_size, u16 max_frame_size, u32 if_id,
 703                         u32 rss);
 704 extern int be_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
 705                         int type);
 706 extern int be_cmd_link_status_query(struct be_ctrl_info *ctrl,
 707                         struct be_link_info *link);
 708 extern int be_cmd_reset(struct be_ctrl_info *ctrl);
 709 extern int be_cmd_get_stats(struct be_ctrl_info *ctrl,
 710                         struct be_dma_mem *nonemb_cmd);
 711 extern int be_cmd_get_fw_ver(struct be_ctrl_info *ctrl, char *fw_ver);
 712
 713 extern int be_cmd_modify_eqd(struct be_ctrl_info *ctrl, u32 eq_id, u32 eqd);
 714 extern int be_cmd_vlan_config(struct be_ctrl_info *ctrl, u32 if_id,
 715                         u16 *vtag_array, u32 num, bool untagged,
 716                         bool promiscuous);
 717 extern int be_cmd_promiscuous_config(struct be_ctrl_info *ctrl,
 718                         u8 port_num, bool en);
 719 extern int be_cmd_mcast_mac_set(struct be_ctrl_info *ctrl, u32 if_id,
 720                         u8 *mac_table, u32 num, bool promiscuous);
 721 extern int be_cmd_set_flow_control(struct be_ctrl_info *ctrl,
 722                         u32 tx_fc, u32 rx_fc);
 723 extern int be_cmd_get_flow_control(struct be_ctrl_info *ctrl,
 724                         u32 *tx_fc, u32 *rx_fc);
 725 extern int be_cmd_query_fw_cfg(struct be_ctrl_info *ctrl, u32 *port_num);
 726 extern void be_process_mcc(struct be_ctrl_info *ctrl);