?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Staging: comedi: remove comedi-specific wrappers
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / comedi / drivers / s626.h
blob27ae02be530003cb4d81c38af69bbcce3264effc
1 /*
2 comedi/drivers/s626.h
3 Sensoray s626 Comedi driver, header file
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
7
8 Based on Sensoray Model 626 Linux driver Version 0.2
9 Copyright (C) 2002-2004 Sensoray Co., Inc.
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24
25 */
26
27 /*
28 Driver: s626.o (s626.ko)
29 Description: Sensoray 626 driver
30 Devices: Sensoray s626
31 Authors: Gianluca Palli <gpalli@deis.unibo.it>,
32 Updated: Thu, 12 Jul 2005
33 Status: experimental
34
35 Configuration Options:
36 analog input:
37 none
38
39 analog output:
40 none
41
42 digital channel:
43 s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
44 supported configuration options:
45 INSN_CONFIG_DIO_QUERY
46 COMEDI_INPUT
47 COMEDI_OUTPUT
48
49 encoder:
50 Every channel must be configured before reading.
51
52 Example code
53
54 insn.insn=INSN_CONFIG; // configuration instruction
55 insn.n=1; // number of operation (must be 1)
56 insn.data=&initialvalue; // initial value loaded into encoder
57 // during configuration
58 insn.subdev=5; // encoder subdevice
59 insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); // encoder_channel
60 // to configure
61
62 comedi_do_insn(cf,&insn); // executing configuration
63 */
64
65 #ifdef _DEBUG_
66 #define DEBUG(...); printk(__VA_ARGS__);
67 #else
68 #define DEBUG(...)
69 #endif
70
71 #if !defined(TRUE)
72 #define TRUE (1)
73 #endif
74
75 #if !defined(FALSE)
76 #define FALSE (0)
77 #endif
78
79 #if !defined(EXTERN)
80 #if defined(__cplusplus)
81 #define EXTERN extern "C"
82 #else
83 #define EXTERN extern
84 #endif
85 #endif
86
87 #if !defined(INLINE)
88 #define INLINE static __inline
89 #endif
90
91 #include<linux/slab.h>
92
93 #define S626_SIZE 0x0200
94 #define SIZEOF_ADDRESS_SPACE 0x0200
95 #define DMABUF_SIZE 4096 /* 4k pages */
96
97 #define S626_ADC_CHANNELS 16
98 #define S626_DAC_CHANNELS 4
99 #define S626_ENCODER_CHANNELS 6
100 #define S626_DIO_CHANNELS 48
101 #define S626_DIO_BANKS 3 /* Number of DIO groups. */
102 #define S626_DIO_EXTCHANS 40 /* Number of */
103 /* extended-capability */
104 /* DIO channels. */
105
106 #define NUM_TRIMDACS 12 /* Number of valid TrimDAC channels. */
107
108 /* PCI bus interface types. */
109 #define INTEL 1 /* Intel bus type. */
110 #define MOTOROLA 2 /* Motorola bus type. */
111
112 #define PLATFORM INTEL /* *** SELECT PLATFORM TYPE *** */
113
114 #define RANGE_5V 0x10 /* +/-5V range */
115 #define RANGE_10V 0x00 /* +/-10V range */
116
117 #define EOPL 0x80 /* End of ADC poll list marker. */
118 #define GSEL_BIPOLAR5V 0x00F0 /* LP_GSEL setting for 5V bipolar range. */
119 #define GSEL_BIPOLAR10V 0x00A0 /* LP_GSEL setting for 10V bipolar range. */
120
121 /* Error codes that must be visible to this base class. */
122 #define ERR_ILLEGAL_PARM 0x00010000 /* Illegal function parameter value was specified. */
123 #define ERR_I2C 0x00020000 /* I2C error. */
124 #define ERR_COUNTERSETUP 0x00200000 /* Illegal setup specified for counter channel. */
125 #define ERR_DEBI_TIMEOUT 0x00400000 /* DEBI transfer timed out. */
126
127 /* Organization (physical order) and size (in DWORDs) of logical DMA buffers contained by ANA_DMABUF. */
128 #define ADC_DMABUF_DWORDS 40 /* ADC DMA buffer must hold 16 samples, plus pre/post garbage samples. */
129 #define DAC_WDMABUF_DWORDS 1 /* DAC output DMA buffer holds a single sample. */
130
131 /* All remaining space in 4KB DMA buffer is available for the RPS1 program. */
132
133 /* Address offsets, in DWORDS, from base of DMA buffer. */
134 #define DAC_WDMABUF_OS ADC_DMABUF_DWORDS
135
136 /* Interrupt enab bit in ISR and IER. */
137 #define IRQ_GPIO3 0x00000040 /* IRQ enable for GPIO3. */
138 #define IRQ_RPS1 0x10000000
139 #define ISR_AFOU 0x00000800
140 /* Audio fifo under/overflow detected. */
141
142 #define IRQ_COINT1A 0x0400 /* conter 1A overflow interrupt mask */
143 #define IRQ_COINT1B 0x0800 /* conter 1B overflow interrupt mask */
144 #define IRQ_COINT2A 0x1000 /* conter 2A overflow interrupt mask */
145 #define IRQ_COINT2B 0x2000 /* conter 2B overflow interrupt mask */
146 #define IRQ_COINT3A 0x4000 /* conter 3A overflow interrupt mask */
147 #define IRQ_COINT3B 0x8000 /* conter 3B overflow interrupt mask */
148
149 /* RPS command codes. */
150 #define RPS_CLRSIGNAL 0x00000000 /* CLEAR SIGNAL */
151 #define RPS_SETSIGNAL 0x10000000 /* SET SIGNAL */
152 #define RPS_NOP 0x00000000 /* NOP */
153 #define RPS_PAUSE 0x20000000 /* PAUSE */
154 #define RPS_UPLOAD 0x40000000 /* UPLOAD */
155 #define RPS_JUMP 0x80000000 /* JUMP */
156 #define RPS_LDREG 0x90000100 /* LDREG (1 uint32_t only) */
157 #define RPS_STREG 0xA0000100 /* STREG (1 uint32_t only) */
158 #define RPS_STOP 0x50000000 /* STOP */
159 #define RPS_IRQ 0x60000000 /* IRQ */
160
161 #define RPS_LOGICAL_OR 0x08000000 /* Logical OR conditionals. */
162 #define RPS_INVERT 0x04000000 /* Test for negated semaphores. */
163 #define RPS_DEBI 0x00000002 /* DEBI done */
164
165 #define RPS_SIG0 0x00200000 /* RPS semaphore 0 (used by ADC). */
166 #define RPS_SIG1 0x00400000 /* RPS semaphore 1 (used by DAC). */
167 #define RPS_SIG2 0x00800000 /* RPS semaphore 2 (not used). */
168 #define RPS_GPIO2 0x00080000 /* RPS GPIO2 */
169 #define RPS_GPIO3 0x00100000 /* RPS GPIO3 */
170
171 #define RPS_SIGADC RPS_SIG0 /* Trigger/status for ADC's RPS program. */
172 #define RPS_SIGDAC RPS_SIG1 /* Trigger/status for DAC's RPS program. */
173
174 /* RPS clock parameters. */
175 #define RPSCLK_SCALAR 8 /* This is apparent ratio of PCI/RPS clks (undocumented!!). */
176 #define RPSCLK_PER_US (33 / RPSCLK_SCALAR) /* Number of RPS clocks in one microsecond. */
177
178 /* Event counter source addresses. */
179 #define SBA_RPS_A0 0x27 /* Time of RPS0 busy, in PCI clocks. */
180
181 /* GPIO constants. */
182 #define GPIO_BASE 0x10004000 /* GPIO 0,2,3 = inputs, GPIO3 = IRQ; GPIO1 = out. */
183 #define GPIO1_LO 0x00000000 /* GPIO1 set to LOW. */
184 #define GPIO1_HI 0x00001000 /* GPIO1 set to HIGH. */
185
186 /* Primary Status Register (PSR) constants. */
187 #define PSR_DEBI_E 0x00040000 /* DEBI event flag. */
188 #define PSR_DEBI_S 0x00080000 /* DEBI status flag. */
189 #define PSR_A2_IN 0x00008000 /* Audio output DMA2 protection address reached. */
190 #define PSR_AFOU 0x00000800 /* Audio FIFO under/overflow detected. */
191 #define PSR_GPIO2 0x00000020 /* GPIO2 input pin: 0=AdcBusy, 1=AdcIdle. */
192 #define PSR_EC0S 0x00000001 /* Event counter 0 threshold reached. */
193
194 /* Secondary Status Register (SSR) constants. */
195 #define SSR_AF2_OUT 0x00000200 /* Audio 2 output FIFO under/overflow detected. */
196
197 /* Master Control Register 1 (MC1) constants. */
198 #define MC1_SOFT_RESET 0x80000000 /* Invoke 7146 soft reset. */
199 #define MC1_SHUTDOWN 0x3FFF0000 /* Shut down all MC1-controlled enables. */
200
201 #define MC1_ERPS1 0x2000 /* enab/disable RPS task 1. */
202 #define MC1_ERPS0 0x1000 /* enab/disable RPS task 0. */
203 #define MC1_DEBI 0x0800 /* enab/disable DEBI pins. */
204 #define MC1_AUDIO 0x0200 /* enab/disable audio port pins. */
205 #define MC1_I2C 0x0100 /* enab/disable I2C interface. */
206 #define MC1_A2OUT 0x0008 /* enab/disable transfer on A2 out. */
207 #define MC1_A2IN 0x0004 /* enab/disable transfer on A2 in. */
208 #define MC1_A1IN 0x0001 /* enab/disable transfer on A1 in. */
209
210 /* Master Control Register 2 (MC2) constants. */
211 #define MC2_UPLD_DEBIq 0x00020002 /* Upload DEBI registers. */
212 #define MC2_UPLD_IICq 0x00010001 /* Upload I2C registers. */
213 #define MC2_RPSSIG2_ONq 0x20002000 /* Assert RPS_SIG2. */
214 #define MC2_RPSSIG1_ONq 0x10001000 /* Assert RPS_SIG1. */
215 #define MC2_RPSSIG0_ONq 0x08000800 /* Assert RPS_SIG0. */
216 #define MC2_UPLD_DEBI_MASKq 0x00000002 /* Upload DEBI mask. */
217 #define MC2_UPLD_IIC_MASKq 0x00000001 /* Upload I2C mask. */
218 #define MC2_RPSSIG2_MASKq 0x00002000 /* RPS_SIG2 bit mask. */
219 #define MC2_RPSSIG1_MASKq 0x00001000 /* RPS_SIG1 bit mask. */
220 #define MC2_RPSSIG0_MASKq 0x00000800 /* RPS_SIG0 bit mask. */
221
222 #define MC2_DELAYTRIG_4USq MC2_RPSSIG1_ON
223 #define MC2_DELAYBUSY_4USq MC2_RPSSIG1_MASK
224
225 #define MC2_DELAYTRIG_6USq MC2_RPSSIG2_ON
226 #define MC2_DELAYBUSY_6USq MC2_RPSSIG2_MASK
227
228 #define MC2_UPLD_DEBI 0x0002 /* Upload DEBI. */
229 #define MC2_UPLD_IIC 0x0001 /* Upload I2C. */
230 #define MC2_RPSSIG2 0x2000 /* RPS signal 2 (not used). */
231 #define MC2_RPSSIG1 0x1000 /* RPS signal 1 (DAC RPS busy). */
232 #define MC2_RPSSIG0 0x0800 /* RPS signal 0 (ADC RPS busy). */
233
234 #define MC2_ADC_RPS MC2_RPSSIG0 /* ADC RPS busy. */
235 #define MC2_DAC_RPS MC2_RPSSIG1 /* DAC RPS busy. */
236
237 /* ***** oldies ***** */
238 #define MC2_UPLD_DEBIQ 0x00020002 /* Upload DEBI registers. */
239 #define MC2_UPLD_IICQ 0x00010001 /* Upload I2C registers. */
240
241 /* PCI BUS (SAA7146) REGISTER ADDRESS OFFSETS */
242 #define P_PCI_BT_A 0x004C /* Audio DMA burst/threshold control. */
243 #define P_DEBICFG 0x007C /* DEBI configuration. */
244 #define P_DEBICMD 0x0080 /* DEBI command. */
245 #define P_DEBIPAGE 0x0084 /* DEBI page. */
246 #define P_DEBIAD 0x0088 /* DEBI target address. */
247 #define P_I2CCTRL 0x008C /* I2C control. */
248 #define P_I2CSTAT 0x0090 /* I2C status. */
249 #define P_BASEA2_IN 0x00AC /* Audio input 2 base physical DMAbuf
250 * address. */
251 #define P_PROTA2_IN 0x00B0 /* Audio input 2 physical DMAbuf
252 * protection address. */
253 #define P_PAGEA2_IN 0x00B4 /* Audio input 2 paging attributes. */
254 #define P_BASEA2_OUT 0x00B8 /* Audio output 2 base physical DMAbuf
255 * address. */
256 #define P_PROTA2_OUT 0x00BC /* Audio output 2 physical DMAbuf
257 * protection address. */
258 #define P_PAGEA2_OUT 0x00C0 /* Audio output 2 paging attributes. */
259 #define P_RPSPAGE0 0x00C4 /* RPS0 page. */
260 #define P_RPSPAGE1 0x00C8 /* RPS1 page. */
261 #define P_RPS0_TOUT 0x00D4 /* RPS0 time-out. */
262 #define P_RPS1_TOUT 0x00D8 /* RPS1 time-out. */
263 #define P_IER 0x00DC /* Interrupt enable. */
264 #define P_GPIO 0x00E0 /* General-purpose I/O. */
265 #define P_EC1SSR 0x00E4 /* Event counter set 1 source select. */
266 #define P_ECT1R 0x00EC /* Event counter threshold set 1. */
267 #define P_ACON1 0x00F4 /* Audio control 1. */
268 #define P_ACON2 0x00F8 /* Audio control 2. */
269 #define P_MC1 0x00FC /* Master control 1. */
270 #define P_MC2 0x0100 /* Master control 2. */
271 #define P_RPSADDR0 0x0104 /* RPS0 instruction pointer. */
272 #define P_RPSADDR1 0x0108 /* RPS1 instruction pointer. */
273 #define P_ISR 0x010C /* Interrupt status. */
274 #define P_PSR 0x0110 /* Primary status. */
275 #define P_SSR 0x0114 /* Secondary status. */
276 #define P_EC1R 0x0118 /* Event counter set 1. */
277 #define P_ADP4 0x0138 /* Logical audio DMA pointer of audio
278 * input FIFO A2_IN. */
279 #define P_FB_BUFFER1 0x0144 /* Audio feedback buffer 1. */
280 #define P_FB_BUFFER2 0x0148 /* Audio feedback buffer 2. */
281 #define P_TSL1 0x0180 /* Audio time slot list 1. */
282 #define P_TSL2 0x01C0 /* Audio time slot list 2. */
283
284 /* LOCAL BUS (GATE ARRAY) REGISTER ADDRESS OFFSETS */
285 /* Analog I/O registers: */
286 #define LP_DACPOL 0x0082 /* Write DAC polarity. */
287 #define LP_GSEL 0x0084 /* Write ADC gain. */
288 #define LP_ISEL 0x0086 /* Write ADC channel select. */
289 /* Digital I/O (write only): */
290 #define LP_WRINTSELA 0x0042 /* Write A interrupt enable. */
291 #define LP_WREDGSELA 0x0044 /* Write A edge selection. */
292 #define LP_WRCAPSELA 0x0046 /* Write A capture enable. */
293 #define LP_WRDOUTA 0x0048 /* Write A digital output. */
294 #define LP_WRINTSELB 0x0052 /* Write B interrupt enable. */
295 #define LP_WREDGSELB 0x0054 /* Write B edge selection. */
296 #define LP_WRCAPSELB 0x0056 /* Write B capture enable. */
297 #define LP_WRDOUTB 0x0058 /* Write B digital output. */
298 #define LP_WRINTSELC 0x0062 /* Write C interrupt enable. */
299 #define LP_WREDGSELC 0x0064 /* Write C edge selection. */
300 #define LP_WRCAPSELC 0x0066 /* Write C capture enable. */
301 #define LP_WRDOUTC 0x0068 /* Write C digital output. */
302
303 /* Digital I/O (read only): */
304 #define LP_RDDINA 0x0040 /* Read digital input. */
305 #define LP_RDCAPFLGA 0x0048 /* Read edges captured. */
306 #define LP_RDINTSELA 0x004A /* Read interrupt enable register. */
307 #define LP_RDEDGSELA 0x004C /* Read edge selection register. */
308 #define LP_RDCAPSELA 0x004E /* Read capture enable register. */
309 #define LP_RDDINB 0x0050 /* Read digital input. */
310 #define LP_RDCAPFLGB 0x0058 /* Read edges captured. */
311 #define LP_RDINTSELB 0x005A /* Read interrupt enable register. */
312 #define LP_RDEDGSELB 0x005C /* Read edge selection register. */
313 #define LP_RDCAPSELB 0x005E /* Read capture enable register. */
314 #define LP_RDDINC 0x0060 /* Read digital input. */
315 #define LP_RDCAPFLGC 0x0068 /* Read edges captured. */
316 #define LP_RDINTSELC 0x006A /* Read interrupt enable register. */
317 #define LP_RDEDGSELC 0x006C /* Read edge selection register. */
318 #define LP_RDCAPSELC 0x006E /* Read capture enable register. */
319
320 /* Counter Registers (read/write): */
321 #define LP_CR0A 0x0000 /* 0A setup register. */
322 #define LP_CR0B 0x0002 /* 0B setup register. */
323 #define LP_CR1A 0x0004 /* 1A setup register. */
324 #define LP_CR1B 0x0006 /* 1B setup register. */
325 #define LP_CR2A 0x0008 /* 2A setup register. */
326 #define LP_CR2B 0x000A /* 2B setup register. */
327
328 /* Counter PreLoad (write) and Latch (read) Registers: */
329 #define LP_CNTR0ALSW 0x000C /* 0A lsw. */
330 #define LP_CNTR0AMSW 0x000E /* 0A msw. */
331 #define LP_CNTR0BLSW 0x0010 /* 0B lsw. */
332 #define LP_CNTR0BMSW 0x0012 /* 0B msw. */
333 #define LP_CNTR1ALSW 0x0014 /* 1A lsw. */
334 #define LP_CNTR1AMSW 0x0016 /* 1A msw. */
335 #define LP_CNTR1BLSW 0x0018 /* 1B lsw. */
336 #define LP_CNTR1BMSW 0x001A /* 1B msw. */
337 #define LP_CNTR2ALSW 0x001C /* 2A lsw. */
338 #define LP_CNTR2AMSW 0x001E /* 2A msw. */
339 #define LP_CNTR2BLSW 0x0020 /* 2B lsw. */
340 #define LP_CNTR2BMSW 0x0022 /* 2B msw. */
341
342 /* Miscellaneous Registers (read/write): */
343 #define LP_MISC1 0x0088 /* Read/write Misc1. */
344 #define LP_WRMISC2 0x0090 /* Write Misc2. */
345 #define LP_RDMISC2 0x0082 /* Read Misc2. */
346
347 /* Bit masks for MISC1 register that are the same for reads and writes. */
348 #define MISC1_WENABLE 0x8000 /* enab writes to MISC2 (except Clear
349 * Watchdog bit). */
350 #define MISC1_WDISABLE 0x0000 /* Disable writes to MISC2. */
351 #define MISC1_EDCAP 0x1000 /* enab edge capture on DIO chans
352 * specified by LP_WRCAPSELx. */
353 #define MISC1_NOEDCAP 0x0000 /* Disable edge capture on specified
354 * DIO chans. */
355
356 /* Bit masks for MISC1 register reads. */
357 #define RDMISC1_WDTIMEOUT 0x4000 /* Watchdog timer timed out. */
358
359 /* Bit masks for MISC2 register writes. */
360 #define WRMISC2_WDCLEAR 0x8000 /* Reset watchdog timer to zero. */
361 #define WRMISC2_CHARGE_ENABLE 0x4000 /* enab battery trickle charging. */
362
363 /* Bit masks for MISC2 register that are the same for reads and writes. */
364 #define MISC2_BATT_ENABLE 0x0008 /* Backup battery enable. */
365 #define MISC2_WDENABLE 0x0004 /* Watchdog timer enable. */
366 #define MISC2_WDPERIOD_MASK 0x0003 /* Watchdog interval */
367 /* select mask. */
368
369 /* Bit masks for ACON1 register. */
370 #define A2_RUN 0x40000000 /* Run A2 based on TSL2. */
371 #define A1_RUN 0x20000000 /* Run A1 based on TSL1. */
372 #define A1_SWAP 0x00200000 /* Use big-endian for A1. */
373 #define A2_SWAP 0x00100000 /* Use big-endian for A2. */
374 #define WS_MODES 0x00019999 /* WS0 = TSL1 trigger */
375 /* input, WS1-WS4 = */
376 /* CS* outputs. */
377
378 #if PLATFORM == INTEL /* Base ACON1 config: always run A1 based
379 * on TSL1. */
380 #define ACON1_BASE (WS_MODES | A1_RUN)
381 #elif PLATFORM == MOTOROLA
382 #define ACON1_BASE (WS_MODES | A1_RUN | A1_SWAP | A2_SWAP)
383 #endif
384
385 #define ACON1_ADCSTART ACON1_BASE /* Start ADC: run A1
386 * based on TSL1. */
387 #define ACON1_DACSTART (ACON1_BASE | A2_RUN)
388 /* Start transmit to DAC: run A2 based on TSL2. */
389 #define ACON1_DACSTOP ACON1_BASE /* Halt A2. */
390
391 /* Bit masks for ACON2 register. */
392 #define A1_CLKSRC_BCLK1 0x00000000 /* A1 bit rate = BCLK1 (ADC). */
393 #define A2_CLKSRC_X1 0x00800000 /* A2 bit rate = ACLK/1 (DACs). */
394 #define A2_CLKSRC_X2 0x00C00000 /* A2 bit rate = ACLK/2 (DACs). */
395 #define A2_CLKSRC_X4 0x01400000 /* A2 bit rate = ACLK/4 (DACs). */
396 #define INVERT_BCLK2 0x00100000 /* Invert BCLK2 (DACs). */
397 #define BCLK2_OE 0x00040000 /* enab BCLK2 (DACs). */
398 #define ACON2_XORMASK 0x000C0000 /* XOR mask for ACON2 */
399 /* active-low bits. */
400
401 #define ACON2_INIT (ACON2_XORMASK ^ (A1_CLKSRC_BCLK1 | A2_CLKSRC_X2 | INVERT_BCLK2 | BCLK2_OE))
402
403 /* Bit masks for timeslot records. */
404 #define WS1 0x40000000 /* WS output to assert. */
405 #define WS2 0x20000000
406 #define WS3 0x10000000
407 #define WS4 0x08000000
408 #define RSD1 0x01000000 /* Shift A1 data in on SD1. */
409 #define SDW_A1 0x00800000 /* Store rcv'd char at next
410 * char slot of DWORD1 buffer. */
411 #define SIB_A1 0x00400000 /* Store rcv'd char at next
412 * char slot of FB1 buffer. */
413 #define SF_A1 0x00200000 /* Write unsigned long
414 * buffer to input FIFO. */
415
416 /* Select parallel-to-serial converter's data source: */
417 #define XFIFO_0 0x00000000 /* Data fifo byte 0. */
418 #define XFIFO_1 0x00000010 /* Data fifo byte 1. */
419 #define XFIFO_2 0x00000020 /* Data fifo byte 2. */
420 #define XFIFO_3 0x00000030 /* Data fifo byte 3. */
421 #define XFB0 0x00000040 /* FB_BUFFER byte 0. */
422 #define XFB1 0x00000050 /* FB_BUFFER byte 1. */
423 #define XFB2 0x00000060 /* FB_BUFFER byte 2. */
424 #define XFB3 0x00000070 /* FB_BUFFER byte 3. */
425 #define SIB_A2 0x00000200 /* Store next dword from A2's
426 * input shifter to FB2 buffer. */
427 #define SF_A2 0x00000100 /* Store next dword from A2's
428 * input shifter to its input
429 * fifo. */
430 #define LF_A2 0x00000080 /* Load next dword from A2's
431 * output fifo into its
432 * output dword buffer. */
433 #define XSD2 0x00000008 /* Shift data out on SD2. */
434 #define RSD3 0x00001800 /* Shift data in on SD3. */
435 #define RSD2 0x00001000 /* Shift data in on SD2. */
436 #define LOW_A2 0x00000002 /* Drive last SD low */
437 /* for 7 clks, then */
438 /* tri-state. */
439 #define EOS 0x00000001 /* End of superframe. */
440
441
442 /* I2C configuration constants. */
443 #define I2C_CLKSEL 0x0400
444 /* I2C bit rate = PCIclk/480 = 68.75 KHz. */
445
446 #define I2C_BITRATE 68.75
447 /* I2C bus data bit rate (determined by I2C_CLKSEL) in KHz. */
448
449 #define I2C_WRTIME 15.0
450 /* Worst case time, in msec, for EEPROM internal write op. */
451
452 /* I2C manifest constants. */
453
454 /* Max retries to wait for EEPROM write. */
455 #define I2C_RETRIES (I2C_WRTIME * I2C_BITRATE / 9.0)
456 #define I2C_ERR 0x0002 /* I2C control/status */
457 /* flag ERROR. */
458 #define I2C_BUSY 0x0001 /* I2C control/status */
459 /* flag BUSY. */
460 #define I2C_ABORT 0x0080 /* I2C status flag ABORT. */
461 #define I2C_ATTRSTART 0x3 /* I2C attribute START. */
462 #define I2C_ATTRCONT 0x2 /* I2C attribute CONT. */
463 #define I2C_ATTRSTOP 0x1 /* I2C attribute STOP. */
464 #define I2C_ATTRNOP 0x0 /* I2C attribute NOP. */
465
466 /* I2C read command | EEPROM address. */
467 #define I2CR (devpriv->I2CAdrs | 1)
468
469 /* I2C write command | EEPROM address. */
470 #define I2CW (devpriv->I2CAdrs)
471
472 /* Code macros used for constructing I2C command bytes. */
473 #define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24))
474 #define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16))
475 #define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8))
476
477 /* oldest */
478 #define P_DEBICFGq 0x007C /* DEBI configuration. */
479 #define P_DEBICMDq 0x0080 /* DEBI command. */
480 #define P_DEBIPAGEq 0x0084 /* DEBI page. */
481 #define P_DEBIADq 0x0088 /* DEBI target address. */
482
483 #define DEBI_CFG_TOQ 0x03C00000 /* timeout (15 PCI cycles) */
484 #define DEBI_CFG_FASTQ 0x10000000 /* fast mode enable */
485 #define DEBI_CFG_16Q 0x00080000 /* 16-bit access enable */
486 #define DEBI_CFG_INCQ 0x00040000 /* enable address increment */
487 #define DEBI_CFG_TIMEROFFQ 0x00010000 /* disable timer */
488 #define DEBI_CMD_RDQ 0x00050000 /* read immediate 2 bytes */
489 #define DEBI_CMD_WRQ 0x00040000 /* write immediate 2 bytes */
490 #define DEBI_PAGE_DISABLEQ 0x00000000 /* paging disable */
491
492 /* DEBI command constants. */
493 #define DEBI_CMD_SIZE16 (2 << 17) /* Transfer size is */
494 /* always 2 bytes. */
495 #define DEBI_CMD_READ 0x00010000 /* Read operation. */
496 #define DEBI_CMD_WRITE 0x00000000 /* Write operation. */
497
498 /* Read immediate 2 bytes. */
499 #define DEBI_CMD_RDWORD (DEBI_CMD_READ | DEBI_CMD_SIZE16)
500
501 /* Write immediate 2 bytes. */
502 #define DEBI_CMD_WRWORD (DEBI_CMD_WRITE | DEBI_CMD_SIZE16)
503
504 /* DEBI configuration constants. */
505 #define DEBI_CFG_XIRQ_EN 0x80000000 /* enab external */
506 /* interrupt on GPIO3. */
507 #define DEBI_CFG_XRESUME 0x40000000 /* Resume block */
508 /* transfer when XIRQ */
509 /* deasserted. */
510 #define DEBI_CFG_FAST 0x10000000 /* Fast mode enable. */
511
512 /* 4-bit field that specifies DEBI timeout value in PCI clock cycles: */
513 #define DEBI_CFG_TOUT_BIT 22 /* Finish DEBI cycle after */
514 /* this many clocks. */
515
516 /* 2-bit field that specifies Endian byte lane steering: */
517 #define DEBI_CFG_SWAP_NONE 0x00000000 /* Straight - don't */
518 /* swap any bytes */
519 /* (Intel). */
520 #define DEBI_CFG_SWAP_2 0x00100000 /* 2-byte swap (Motorola). */
521 #define DEBI_CFG_SWAP_4 0x00200000 /* 4-byte swap. */
522 #define DEBI_CFG_16 0x00080000 /* Slave is able to */
523 /* serve 16-bit */
524 /* cycles. */
525
526 #define DEBI_CFG_SLAVE16 0x00080000 /* Slave is able to */
527 /* serve 16-bit */
528 /* cycles. */
529 #define DEBI_CFG_INC 0x00040000 /* enab address */
530 /* increment for block */
531 /* transfers. */
532 #define DEBI_CFG_INTEL 0x00020000 /* Intel style local bus. */
533 #define DEBI_CFG_TIMEROFF 0x00010000 /* Disable timer. */
534
535 #if PLATFORM == INTEL
536
537 #define DEBI_TOUT 7 /* Wait 7 PCI clocks */
538 /* (212 ns) before */
539 /* polling RDY. */
540
541 /* Intel byte lane steering (pass through all byte lanes). */
542 #define DEBI_SWAP DEBI_CFG_SWAP_NONE
543
544 #elif PLATFORM == MOTOROLA
545
546 #define DEBI_TOUT 15 /* Wait 15 PCI clocks (454 ns) */
547 /* maximum before timing out. */
548 #define DEBI_SWAP DEBI_CFG_SWAP_2 /* Motorola byte lane steering. */
549
550 #endif
551
552 /* DEBI page table constants. */
553 #define DEBI_PAGE_DISABLE 0x00000000 /* Paging disable. */
554
555 /* ******* EXTRA FROM OTHER SANSORAY * .h ******* */
556
557 /* LoadSrc values: */
558 #define LOADSRC_INDX 0 /* Preload core in response to */
559 /* Index. */
560 #define LOADSRC_OVER 1 /* Preload core in response to */
561 /* Overflow. */
562 #define LOADSRCB_OVERA 2 /* Preload B core in response */
563 /* to A Overflow. */
564 #define LOADSRC_NONE 3 /* Never preload core. */
565
566 /* IntSrc values: */
567 #define INTSRC_NONE 0 /* Interrupts disabled. */
568 #define INTSRC_OVER 1 /* Interrupt on Overflow. */
569 #define INTSRC_INDX 2 /* Interrupt on Index. */
570 #define INTSRC_BOTH 3 /* Interrupt on Index or Overflow. */
571
572 /* LatchSrc values: */
573 #define LATCHSRC_AB_READ 0 /* Latch on read. */
574 #define LATCHSRC_A_INDXA 1 /* Latch A on A Index. */
575 #define LATCHSRC_B_INDXB 2 /* Latch B on B Index. */
576 #define LATCHSRC_B_OVERA 3 /* Latch B on A Overflow. */
577
578 /* IndxSrc values: */
579 #define INDXSRC_HARD 0 /* Hardware or software index. */
580 #define INDXSRC_SOFT 1 /* Software index only. */
581
582 /* IndxPol values: */
583 #define INDXPOL_POS 0 /* Index input is active high. */
584 #define INDXPOL_NEG 1 /* Index input is active low. */
585
586 /* ClkSrc values: */
587 #define CLKSRC_COUNTER 0 /* Counter mode. */
588 #define CLKSRC_TIMER 2 /* Timer mode. */
589 #define CLKSRC_EXTENDER 3 /* Extender mode. */
590
591 /* ClkPol values: */
592 #define CLKPOL_POS 0 /* Counter/Extender clock is */
593 /* active high. */
594 #define CLKPOL_NEG 1 /* Counter/Extender clock is */
595 /* active low. */
596 #define CNTDIR_UP 0 /* Timer counts up. */
597 #define CNTDIR_DOWN 1 /* Timer counts down. */
598
599 /* ClkEnab values: */
600 #define CLKENAB_ALWAYS 0 /* Clock always enabled. */
601 #define CLKENAB_INDEX 1 /* Clock is enabled by index. */
602
603 /* ClkMult values: */
604 #define CLKMULT_4X 0 /* 4x clock multiplier. */
605 #define CLKMULT_2X 1 /* 2x clock multiplier. */
606 #define CLKMULT_1X 2 /* 1x clock multiplier. */
607
608 /* Bit Field positions in COUNTER_SETUP structure: */
609 #define BF_LOADSRC 9 /* Preload trigger. */
610 #define BF_INDXSRC 7 /* Index source. */
611 #define BF_INDXPOL 6 /* Index polarity. */
612 #define BF_CLKSRC 4 /* Clock source. */
613 #define BF_CLKPOL 3 /* Clock polarity/count direction. */
614 #define BF_CLKMULT 1 /* Clock multiplier. */
615 #define BF_CLKENAB 0 /* Clock enable. */
616
617 /* Enumerated counter operating modes specified by ClkSrc bit field in */
618 /* a COUNTER_SETUP. */
619
620 #define CLKSRC_COUNTER 0 /* Counter: ENC_C clock, ENC_D */
621 /* direction. */
622 #define CLKSRC_TIMER 2 /* Timer: SYS_C clock, */
623 /* direction specified by */
624 /* ClkPol. */
625 #define CLKSRC_EXTENDER 3 /* Extender: OVR_A clock, */
626 /* ENC_D direction. */
627
628 /* Enumerated counter clock multipliers. */
629
630 #define MULT_X0 0x0003 /* Supports no multipliers; */
631 /* fixed physical multiplier = */
632 /* 3. */
633 #define MULT_X1 0x0002 /* Supports multiplier x1; */
634 /* fixed physical multiplier = */
635 /* 2. */
636 #define MULT_X2 0x0001 /* Supports multipliers x1, */
637 /* x2; physical multipliers = */
638 /* 1 or 2. */
639 #define MULT_X4 0x0000 /* Supports multipliers x1, */
640 /* x2, x4; physical */
641 /* multipliers = 0, 1 or 2. */
642
643 /* Sanity-check limits for parameters. */
644
645 #define NUM_COUNTERS 6 /* Maximum valid counter */
646 /* logical channel number. */
647 #define NUM_INTSOURCES 4
648 #define NUM_LATCHSOURCES 4
649 #define NUM_CLKMULTS 4
650 #define NUM_CLKSOURCES 4
651 #define NUM_CLKPOLS 2
652 #define NUM_INDEXPOLS 2
653 #define NUM_INDEXSOURCES 2
654 #define NUM_LOADTRIGS 4
655
656 /* Bit field positions in CRA and CRB counter control registers. */
657
658 /* Bit field positions in CRA: */
659 #define CRABIT_INDXSRC_B 14 /* B index source. */
660 #define CRABIT_CLKSRC_B 12 /* B clock source. */
661 #define CRABIT_INDXPOL_A 11 /* A index polarity. */
662 #define CRABIT_LOADSRC_A 9 /* A preload trigger. */
663 #define CRABIT_CLKMULT_A 7 /* A clock multiplier. */
664 #define CRABIT_INTSRC_A 5 /* A interrupt source. */
665 #define CRABIT_CLKPOL_A 4 /* A clock polarity. */
666 #define CRABIT_INDXSRC_A 2 /* A index source. */
667 #define CRABIT_CLKSRC_A 0 /* A clock source. */
668
669 /* Bit field positions in CRB: */
670 #define CRBBIT_INTRESETCMD 15 /* Interrupt reset command. */
671 #define CRBBIT_INTRESET_B 14 /* B interrupt reset enable. */
672 #define CRBBIT_INTRESET_A 13 /* A interrupt reset enable. */
673 #define CRBBIT_CLKENAB_A 12 /* A clock enable. */
674 #define CRBBIT_INTSRC_B 10 /* B interrupt source. */
675 #define CRBBIT_LATCHSRC 8 /* A/B latch source. */
676 #define CRBBIT_LOADSRC_B 6 /* B preload trigger. */
677 #define CRBBIT_CLKMULT_B 3 /* B clock multiplier. */
678 #define CRBBIT_CLKENAB_B 2 /* B clock enable. */
679 #define CRBBIT_INDXPOL_B 1 /* B index polarity. */
680 #define CRBBIT_CLKPOL_B 0 /* B clock polarity. */
681
682 /* Bit field masks for CRA and CRB. */
683
684 #define CRAMSK_INDXSRC_B ((uint16_t)(3 << CRABIT_INDXSRC_B))
685 #define CRAMSK_CLKSRC_B ((uint16_t)(3 << CRABIT_CLKSRC_B))
686 #define CRAMSK_INDXPOL_A ((uint16_t)(1 << CRABIT_INDXPOL_A))
687 #define CRAMSK_LOADSRC_A ((uint16_t)(3 << CRABIT_LOADSRC_A))
688 #define CRAMSK_CLKMULT_A ((uint16_t)(3 << CRABIT_CLKMULT_A))
689 #define CRAMSK_INTSRC_A ((uint16_t)(3 << CRABIT_INTSRC_A))
690 #define CRAMSK_CLKPOL_A ((uint16_t)(3 << CRABIT_CLKPOL_A))
691 #define CRAMSK_INDXSRC_A ((uint16_t)(3 << CRABIT_INDXSRC_A))
692 #define CRAMSK_CLKSRC_A ((uint16_t)(3 << CRABIT_CLKSRC_A))
693
694 #define CRBMSK_INTRESETCMD ((uint16_t)(1 << CRBBIT_INTRESETCMD))
695 #define CRBMSK_INTRESET_B ((uint16_t)(1 << CRBBIT_INTRESET_B))
696 #define CRBMSK_INTRESET_A ((uint16_t)(1 << CRBBIT_INTRESET_A))
697 #define CRBMSK_CLKENAB_A ((uint16_t)(1 << CRBBIT_CLKENAB_A))
698 #define CRBMSK_INTSRC_B ((uint16_t)(3 << CRBBIT_INTSRC_B))
699 #define CRBMSK_LATCHSRC ((uint16_t)(3 << CRBBIT_LATCHSRC))
700 #define CRBMSK_LOADSRC_B ((uint16_t)(3 << CRBBIT_LOADSRC_B))
701 #define CRBMSK_CLKMULT_B ((uint16_t)(3 << CRBBIT_CLKMULT_B))
702 #define CRBMSK_CLKENAB_B ((uint16_t)(1 << CRBBIT_CLKENAB_B))
703 #define CRBMSK_INDXPOL_B ((uint16_t)(1 << CRBBIT_INDXPOL_B))
704 #define CRBMSK_CLKPOL_B ((uint16_t)(1 << CRBBIT_CLKPOL_B))
705
706 #define CRBMSK_INTCTRL (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A | CRBMSK_INTRESET_B) /* Interrupt reset control bits. */
707
708 /* Bit field positions for standardized SETUP structure. */
709
710 #define STDBIT_INTSRC 13
711 #define STDBIT_LATCHSRC 11
712 #define STDBIT_LOADSRC 9
713 #define STDBIT_INDXSRC 7
714 #define STDBIT_INDXPOL 6
715 #define STDBIT_CLKSRC 4
716 #define STDBIT_CLKPOL 3
717 #define STDBIT_CLKMULT 1
718 #define STDBIT_CLKENAB 0
719
720 /* Bit field masks for standardized SETUP structure. */
721
722 #define STDMSK_INTSRC ((uint16_t)(3 << STDBIT_INTSRC))
723 #define STDMSK_LATCHSRC ((uint16_t)(3 << STDBIT_LATCHSRC))
724 #define STDMSK_LOADSRC ((uint16_t)(3 << STDBIT_LOADSRC))
725 #define STDMSK_INDXSRC ((uint16_t)(1 << STDBIT_INDXSRC))
726 #define STDMSK_INDXPOL ((uint16_t)(1 << STDBIT_INDXPOL))
727 #define STDMSK_CLKSRC ((uint16_t)(3 << STDBIT_CLKSRC))
728 #define STDMSK_CLKPOL ((uint16_t)(1 << STDBIT_CLKPOL))
729 #define STDMSK_CLKMULT ((uint16_t)(3 << STDBIT_CLKMULT))
730 #define STDMSK_CLKENAB ((uint16_t)(1 << STDBIT_CLKENAB))
731
732
733 /* typedef struct indexCounter */
734 /* { */
735 /* unsigned int ao; */
736 /* unsigned int ai; */
737 /* unsigned int digout; */
738 /* unsigned int digin; */
739 /* unsigned int enc; */
740 /* }CallCounter; */
741
742 struct bufferDMA {
743 dma_addr_t PhysicalBase;
744 void *LogicalBase;
745 uint32_t DMAHandle;
746 };
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree