2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 This file is meant to be included by another file, e.g.,
27 ni_atmio.c or ni_pcimio.c.
29 Interrupt support originally added by Truxton Fulton
32 References (from ftp://ftp.natinst.com/support/manuals):
34 340747b.pdf AT-MIO E series Register Level Programmer Manual
35 341079b.pdf PCI E Series RLPM
36 340934b.pdf DAQ-STC reference manual
37 67xx and 611x registers (from http://www.ni.com/pdf/daq/us)
40 Other possibly relevant info:
42 320517c.pdf User manual (obsolete)
43 320517f.pdf User manual (new)
45 320906c.pdf maximum signal ratings
47 321791a.pdf discontinuation of at-mio-16e-10 rev. c
48 321808a.pdf about at-mio-16e-10 rev P
49 321837a.pdf discontinuation of at-mio-16de-10 rev d
50 321838a.pdf about at-mio-16de-10 rev N
54 - the interrupt routine needs to be cleaned up
56 2006-02-07: S-Series PCI-6143: Support has been added but is not
57 fully tested as yet. Terry Barnaby, BEAM Ltd.
60 /* #define DEBUG_INTERRUPT */
61 /* #define DEBUG_STATUS_A */
62 /* #define DEBUG_STATUS_B */
66 #include "comedi_fc.h"
69 #define MDPRINTK(format, args...)
73 #define NI_TIMEOUT 1000
74 static const unsigned old_RTSI_clock_channel
= 7;
76 /* Note: this table must match the ai_gain_* definitions */
77 static const short ni_gainlkup
[][16] = {
78 [ai_gain_16
] = {0, 1, 2, 3, 4, 5, 6, 7,
79 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
80 [ai_gain_8
] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
81 [ai_gain_14
] = {1, 2, 3, 4, 5, 6, 7,
82 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
83 [ai_gain_4
] = {0, 1, 4, 7},
84 [ai_gain_611x
] = {0x00a, 0x00b, 0x001, 0x002,
85 0x003, 0x004, 0x005, 0x006},
86 [ai_gain_622x
] = {0, 1, 4, 5},
87 [ai_gain_628x
] = {1, 2, 3, 4, 5, 6, 7},
88 [ai_gain_6143
] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
91 static const struct comedi_lrange range_ni_E_ai
= { 16, {
110 static const struct comedi_lrange range_ni_E_ai_limited
= { 8, {
121 static const struct comedi_lrange range_ni_E_ai_limited14
= { 14, {
138 static const struct comedi_lrange range_ni_E_ai_bipolar4
= { 4, {
145 static const struct comedi_lrange range_ni_E_ai_611x
= { 8, {
156 static const struct comedi_lrange range_ni_M_ai_622x
= { 4, {
163 static const struct comedi_lrange range_ni_M_ai_628x
= { 7, {
173 static const struct comedi_lrange range_ni_S_ai_6143
= { 1, {
177 static const struct comedi_lrange range_ni_E_ao_ext
= { 4, {
185 static const struct comedi_lrange
*const ni_range_lkup
[] = {
186 [ai_gain_16
] = &range_ni_E_ai
,
187 [ai_gain_8
] = &range_ni_E_ai_limited
,
188 [ai_gain_14
] = &range_ni_E_ai_limited14
,
189 [ai_gain_4
] = &range_ni_E_ai_bipolar4
,
190 [ai_gain_611x
] = &range_ni_E_ai_611x
,
191 [ai_gain_622x
] = &range_ni_M_ai_622x
,
192 [ai_gain_628x
] = &range_ni_M_ai_628x
,
193 [ai_gain_6143
] = &range_ni_S_ai_6143
196 static int ni_dio_insn_config(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
197 struct comedi_insn
*insn
, unsigned int *data
);
198 static int ni_dio_insn_bits(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
199 struct comedi_insn
*insn
, unsigned int *data
);
200 static int ni_cdio_cmdtest(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
201 struct comedi_cmd
*cmd
);
202 static int ni_cdio_cmd(struct comedi_device
*dev
, struct comedi_subdevice
*s
);
203 static int ni_cdio_cancel(struct comedi_device
*dev
, struct comedi_subdevice
*s
);
204 static void handle_cdio_interrupt(struct comedi_device
*dev
);
205 static int ni_cdo_inttrig(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
206 unsigned int trignum
);
208 static int ni_serial_insn_config(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
209 struct comedi_insn
*insn
, unsigned int *data
);
210 static int ni_serial_hw_readwrite8(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
211 unsigned char data_out
, unsigned char *data_in
);
212 static int ni_serial_sw_readwrite8(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
213 unsigned char data_out
, unsigned char *data_in
);
215 static int ni_calib_insn_read(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
216 struct comedi_insn
*insn
, unsigned int *data
);
217 static int ni_calib_insn_write(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
218 struct comedi_insn
*insn
, unsigned int *data
);
220 static int ni_eeprom_insn_read(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
221 struct comedi_insn
*insn
, unsigned int *data
);
222 static int ni_m_series_eeprom_insn_read(struct comedi_device
*dev
,
223 struct comedi_subdevice
*s
, struct comedi_insn
*insn
, unsigned int *data
);
225 static int ni_pfi_insn_bits(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
226 struct comedi_insn
*insn
, unsigned int *data
);
227 static int ni_pfi_insn_config(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
228 struct comedi_insn
*insn
, unsigned int *data
);
229 static unsigned ni_old_get_pfi_routing(struct comedi_device
*dev
, unsigned chan
);
231 static void ni_rtsi_init(struct comedi_device
*dev
);
232 static int ni_rtsi_insn_bits(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
233 struct comedi_insn
*insn
, unsigned int *data
);
234 static int ni_rtsi_insn_config(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
235 struct comedi_insn
*insn
, unsigned int *data
);
237 static void caldac_setup(struct comedi_device
*dev
, struct comedi_subdevice
*s
);
238 static int ni_read_eeprom(struct comedi_device
*dev
, int addr
);
240 #ifdef DEBUG_STATUS_A
241 static void ni_mio_print_status_a(int status
);
243 #define ni_mio_print_status_a(a)
245 #ifdef DEBUG_STATUS_B
246 static void ni_mio_print_status_b(int status
);
248 #define ni_mio_print_status_b(a)
251 static int ni_ai_reset(struct comedi_device
*dev
, struct comedi_subdevice
*s
);
253 static void ni_handle_fifo_half_full(struct comedi_device
*dev
);
254 static int ni_ao_fifo_half_empty(struct comedi_device
*dev
, struct comedi_subdevice
*s
);
256 static void ni_handle_fifo_dregs(struct comedi_device
*dev
);
257 static int ni_ai_inttrig(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
258 unsigned int trignum
);
259 static void ni_load_channelgain_list(struct comedi_device
*dev
, unsigned int n_chan
,
261 static void shutdown_ai_command(struct comedi_device
*dev
);
263 static int ni_ao_inttrig(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
264 unsigned int trignum
);
266 static int ni_ao_reset(struct comedi_device
*dev
, struct comedi_subdevice
*s
);
268 static int ni_8255_callback(int dir
, int port
, int data
, unsigned long arg
);
270 static int ni_gpct_insn_write(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
271 struct comedi_insn
*insn
, unsigned int *data
);
272 static int ni_gpct_insn_read(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
273 struct comedi_insn
*insn
, unsigned int *data
);
274 static int ni_gpct_insn_config(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
275 struct comedi_insn
*insn
, unsigned int *data
);
276 static int ni_gpct_cmd(struct comedi_device
*dev
, struct comedi_subdevice
*s
);
277 static int ni_gpct_cmdtest(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
278 struct comedi_cmd
*cmd
);
279 static int ni_gpct_cancel(struct comedi_device
*dev
, struct comedi_subdevice
*s
);
280 static void handle_gpct_interrupt(struct comedi_device
*dev
,
281 unsigned short counter_index
);
283 static int init_cs5529(struct comedi_device
*dev
);
284 static int cs5529_do_conversion(struct comedi_device
*dev
, unsigned short *data
);
285 static int cs5529_ai_insn_read(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
286 struct comedi_insn
*insn
, unsigned int *data
);
287 #ifdef NI_CS5529_DEBUG
288 static unsigned int cs5529_config_read(struct comedi_device
*dev
,
289 unsigned int reg_select_bits
);
291 static void cs5529_config_write(struct comedi_device
*dev
, unsigned int value
,
292 unsigned int reg_select_bits
);
294 static int ni_m_series_pwm_config(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
295 struct comedi_insn
*insn
, unsigned int *data
);
296 static int ni_6143_pwm_config(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
297 struct comedi_insn
*insn
, unsigned int *data
);
299 static int ni_set_master_clock(struct comedi_device
*dev
, unsigned source
,
301 static void ack_a_interrupt(struct comedi_device
*dev
, unsigned short a_status
);
302 static void ack_b_interrupt(struct comedi_device
*dev
, unsigned short b_status
);
306 AIMODE_HALF_FULL
= 1,
311 enum ni_common_subdevices
{
317 NI_CALIBRATION_SUBDEV
,
320 NI_CS5529_CALIBRATION_SUBDEV
,
328 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index
)
330 switch (counter_index
) {
332 return NI_GPCT0_SUBDEV
;
335 return NI_GPCT1_SUBDEV
;
341 return NI_GPCT0_SUBDEV
;
344 enum timebase_nanoseconds
{
346 TIMEBASE_2_NS
= 10000
349 #define SERIAL_DISABLED 0
350 #define SERIAL_600NS 600
351 #define SERIAL_1_2US 1200
352 #define SERIAL_10US 10000
354 static const int num_adc_stages_611x
= 3;
356 static void handle_a_interrupt(struct comedi_device
*dev
, unsigned short status
,
357 unsigned ai_mite_status
);
358 static void handle_b_interrupt(struct comedi_device
*dev
, unsigned short status
,
359 unsigned ao_mite_status
);
360 static void get_last_sample_611x(struct comedi_device
*dev
);
361 static void get_last_sample_6143(struct comedi_device
*dev
);
363 static inline void ni_set_bitfield(struct comedi_device
*dev
, int reg
,
364 unsigned bit_mask
, unsigned bit_values
)
368 spin_lock_irqsave(&devpriv
->soft_reg_copy_lock
, flags
);
370 case Interrupt_A_Enable_Register
:
371 devpriv
->int_a_enable_reg
&= ~bit_mask
;
372 devpriv
->int_a_enable_reg
|= bit_values
& bit_mask
;
373 devpriv
->stc_writew(dev
, devpriv
->int_a_enable_reg
,
374 Interrupt_A_Enable_Register
);
376 case Interrupt_B_Enable_Register
:
377 devpriv
->int_b_enable_reg
&= ~bit_mask
;
378 devpriv
->int_b_enable_reg
|= bit_values
& bit_mask
;
379 devpriv
->stc_writew(dev
, devpriv
->int_b_enable_reg
,
380 Interrupt_B_Enable_Register
);
382 case IO_Bidirection_Pin_Register
:
383 devpriv
->io_bidirection_pin_reg
&= ~bit_mask
;
384 devpriv
->io_bidirection_pin_reg
|= bit_values
& bit_mask
;
385 devpriv
->stc_writew(dev
, devpriv
->io_bidirection_pin_reg
,
386 IO_Bidirection_Pin_Register
);
389 devpriv
->ai_ao_select_reg
&= ~bit_mask
;
390 devpriv
->ai_ao_select_reg
|= bit_values
& bit_mask
;
391 ni_writeb(devpriv
->ai_ao_select_reg
, AI_AO_Select
);
394 devpriv
->g0_g1_select_reg
&= ~bit_mask
;
395 devpriv
->g0_g1_select_reg
|= bit_values
& bit_mask
;
396 ni_writeb(devpriv
->g0_g1_select_reg
, G0_G1_Select
);
399 printk("Warning %s() called with invalid register\n",
401 printk("reg is %d\n", reg
);
405 spin_unlock_irqrestore(&devpriv
->soft_reg_copy_lock
, flags
);
409 static int ni_ai_drain_dma(struct comedi_device
*dev
);
411 /* DMA channel setup */
413 /* negative channel means no channel */
414 static inline void ni_set_ai_dma_channel(struct comedi_device
*dev
, int channel
)
420 (ni_stc_dma_channel_select_bitfield(channel
) <<
421 AI_DMA_Select_Shift
) & AI_DMA_Select_Mask
;
425 ni_set_bitfield(dev
, AI_AO_Select
, AI_DMA_Select_Mask
, bitfield
);
428 /* negative channel means no channel */
429 static inline void ni_set_ao_dma_channel(struct comedi_device
*dev
, int channel
)
435 (ni_stc_dma_channel_select_bitfield(channel
) <<
436 AO_DMA_Select_Shift
) & AO_DMA_Select_Mask
;
440 ni_set_bitfield(dev
, AI_AO_Select
, AO_DMA_Select_Mask
, bitfield
);
443 /* negative mite_channel means no channel */
444 static inline void ni_set_gpct_dma_channel(struct comedi_device
*dev
,
445 unsigned gpct_index
, int mite_channel
)
449 if (mite_channel
>= 0) {
450 bitfield
= GPCT_DMA_Select_Bits(gpct_index
, mite_channel
);
454 ni_set_bitfield(dev
, G0_G1_Select
, GPCT_DMA_Select_Mask(gpct_index
),
458 /* negative mite_channel means no channel */
459 static inline void ni_set_cdo_dma_channel(struct comedi_device
*dev
, int mite_channel
)
463 spin_lock_irqsave(&devpriv
->soft_reg_copy_lock
, flags
);
464 devpriv
->cdio_dma_select_reg
&= ~CDO_DMA_Select_Mask
;
465 if (mite_channel
>= 0) {
466 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
467 under the assumption the cdio dma selection works just like ai/ao/gpct.
468 Definitely works for dma channels 0 and 1. */
469 devpriv
->cdio_dma_select_reg
|=
470 (ni_stc_dma_channel_select_bitfield(mite_channel
) <<
471 CDO_DMA_Select_Shift
) & CDO_DMA_Select_Mask
;
473 ni_writeb(devpriv
->cdio_dma_select_reg
, M_Offset_CDIO_DMA_Select
);
475 spin_unlock_irqrestore(&devpriv
->soft_reg_copy_lock
, flags
);
478 static int ni_request_ai_mite_channel(struct comedi_device
*dev
)
482 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
483 BUG_ON(devpriv
->ai_mite_chan
);
484 devpriv
->ai_mite_chan
=
485 mite_request_channel(devpriv
->mite
, devpriv
->ai_mite_ring
);
486 if (devpriv
->ai_mite_chan
== NULL
) {
487 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
,
490 "failed to reserve mite dma channel for analog input.");
493 devpriv
->ai_mite_chan
->dir
= COMEDI_INPUT
;
494 ni_set_ai_dma_channel(dev
, devpriv
->ai_mite_chan
->channel
);
495 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
499 static int ni_request_ao_mite_channel(struct comedi_device
*dev
)
503 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
504 BUG_ON(devpriv
->ao_mite_chan
);
505 devpriv
->ao_mite_chan
=
506 mite_request_channel(devpriv
->mite
, devpriv
->ao_mite_ring
);
507 if (devpriv
->ao_mite_chan
== NULL
) {
508 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
,
511 "failed to reserve mite dma channel for analog outut.");
514 devpriv
->ao_mite_chan
->dir
= COMEDI_OUTPUT
;
515 ni_set_ao_dma_channel(dev
, devpriv
->ao_mite_chan
->channel
);
516 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
520 static int ni_request_gpct_mite_channel(struct comedi_device
*dev
,
521 unsigned gpct_index
, enum comedi_io_direction direction
)
524 struct mite_channel
*mite_chan
;
526 BUG_ON(gpct_index
>= NUM_GPCT
);
527 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
528 BUG_ON(devpriv
->counter_dev
->counters
[gpct_index
].mite_chan
);
530 mite_request_channel(devpriv
->mite
,
531 devpriv
->gpct_mite_ring
[gpct_index
]);
532 if (mite_chan
== NULL
) {
533 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
,
536 "failed to reserve mite dma channel for counter.");
539 mite_chan
->dir
= direction
;
540 ni_tio_set_mite_channel(&devpriv
->counter_dev
->counters
[gpct_index
],
542 ni_set_gpct_dma_channel(dev
, gpct_index
, mite_chan
->channel
);
543 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
549 static int ni_request_cdo_mite_channel(struct comedi_device
*dev
)
554 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
555 BUG_ON(devpriv
->cdo_mite_chan
);
556 devpriv
->cdo_mite_chan
=
557 mite_request_channel(devpriv
->mite
, devpriv
->cdo_mite_ring
);
558 if (devpriv
->cdo_mite_chan
== NULL
) {
559 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
,
562 "failed to reserve mite dma channel for correlated digital outut.");
565 devpriv
->cdo_mite_chan
->dir
= COMEDI_OUTPUT
;
566 ni_set_cdo_dma_channel(dev
, devpriv
->cdo_mite_chan
->channel
);
567 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
572 static void ni_release_ai_mite_channel(struct comedi_device
*dev
)
577 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
578 if (devpriv
->ai_mite_chan
) {
579 ni_set_ai_dma_channel(dev
, -1);
580 mite_release_channel(devpriv
->ai_mite_chan
);
581 devpriv
->ai_mite_chan
= NULL
;
583 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
587 static void ni_release_ao_mite_channel(struct comedi_device
*dev
)
592 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
593 if (devpriv
->ao_mite_chan
) {
594 ni_set_ao_dma_channel(dev
, -1);
595 mite_release_channel(devpriv
->ao_mite_chan
);
596 devpriv
->ao_mite_chan
= NULL
;
598 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
602 void ni_release_gpct_mite_channel(struct comedi_device
*dev
, unsigned gpct_index
)
607 BUG_ON(gpct_index
>= NUM_GPCT
);
608 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
609 if (devpriv
->counter_dev
->counters
[gpct_index
].mite_chan
) {
610 struct mite_channel
*mite_chan
=
611 devpriv
->counter_dev
->counters
[gpct_index
].mite_chan
;
613 ni_set_gpct_dma_channel(dev
, gpct_index
, -1);
614 ni_tio_set_mite_channel(&devpriv
->counter_dev
->
615 counters
[gpct_index
], NULL
);
616 mite_release_channel(mite_chan
);
618 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
622 static void ni_release_cdo_mite_channel(struct comedi_device
*dev
)
627 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
628 if (devpriv
->cdo_mite_chan
) {
629 ni_set_cdo_dma_channel(dev
, -1);
630 mite_release_channel(devpriv
->cdo_mite_chan
);
631 devpriv
->cdo_mite_chan
= NULL
;
633 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
637 /* e-series boards use the second irq signals to generate dma requests for their counters */
639 static void ni_e_series_enable_second_irq(struct comedi_device
*dev
,
640 unsigned gpct_index
, short enable
)
642 if (boardtype
.reg_type
& ni_reg_m_series_mask
)
644 switch (gpct_index
) {
647 devpriv
->stc_writew(dev
, G0_Gate_Second_Irq_Enable
,
648 Second_IRQ_A_Enable_Register
);
650 devpriv
->stc_writew(dev
, 0,
651 Second_IRQ_A_Enable_Register
);
656 devpriv
->stc_writew(dev
, G1_Gate_Second_Irq_Enable
,
657 Second_IRQ_B_Enable_Register
);
659 devpriv
->stc_writew(dev
, 0,
660 Second_IRQ_B_Enable_Register
);
670 static void ni_clear_ai_fifo(struct comedi_device
*dev
)
672 if (boardtype
.reg_type
== ni_reg_6143
) {
673 /* Flush the 6143 data FIFO */
674 ni_writel(0x10, AIFIFO_Control_6143
); /* Flush fifo */
675 ni_writel(0x00, AIFIFO_Control_6143
); /* Flush fifo */
676 while (ni_readl(AIFIFO_Status_6143
) & 0x10) ; /* Wait for complete */
678 devpriv
->stc_writew(dev
, 1, ADC_FIFO_Clear
);
679 if (boardtype
.reg_type
== ni_reg_625x
) {
680 ni_writeb(0, M_Offset_Static_AI_Control(0));
681 ni_writeb(1, M_Offset_Static_AI_Control(0));
683 /* the NI example code does 3 convert pulses for 625x boards,
684 but that appears to be wrong in practice. */
685 devpriv
->stc_writew(dev
, AI_CONVERT_Pulse
,
686 AI_Command_1_Register
);
687 devpriv
->stc_writew(dev
, AI_CONVERT_Pulse
,
688 AI_Command_1_Register
);
689 devpriv
->stc_writew(dev
, AI_CONVERT_Pulse
,
690 AI_Command_1_Register
);
696 static void win_out2(struct comedi_device
*dev
, uint32_t data
, int reg
)
698 devpriv
->stc_writew(dev
, data
>> 16, reg
);
699 devpriv
->stc_writew(dev
, data
& 0xffff, reg
+ 1);
702 static uint32_t win_in2(struct comedi_device
*dev
, int reg
)
705 bits
= devpriv
->stc_readw(dev
, reg
) << 16;
706 bits
|= devpriv
->stc_readw(dev
, reg
+ 1);
710 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
711 static inline void ni_ao_win_outw(struct comedi_device
*dev
, uint16_t data
, int addr
)
715 spin_lock_irqsave(&devpriv
->window_lock
, flags
);
716 ni_writew(addr
, AO_Window_Address_611x
);
717 ni_writew(data
, AO_Window_Data_611x
);
718 spin_unlock_irqrestore(&devpriv
->window_lock
, flags
);
721 static inline void ni_ao_win_outl(struct comedi_device
*dev
, uint32_t data
, int addr
)
725 spin_lock_irqsave(&devpriv
->window_lock
, flags
);
726 ni_writew(addr
, AO_Window_Address_611x
);
727 ni_writel(data
, AO_Window_Data_611x
);
728 spin_unlock_irqrestore(&devpriv
->window_lock
, flags
);
731 static inline unsigned short ni_ao_win_inw(struct comedi_device
*dev
, int addr
)
736 spin_lock_irqsave(&devpriv
->window_lock
, flags
);
737 ni_writew(addr
, AO_Window_Address_611x
);
738 data
= ni_readw(AO_Window_Data_611x
);
739 spin_unlock_irqrestore(&devpriv
->window_lock
, flags
);
743 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
744 * share registers (such as Interrupt_A_Register) without interfering with
747 * NOTE: the switch/case statements are optimized out for a constant argument
748 * so this is actually quite fast--- If you must wrap another function around this
749 * make it inline to avoid a large speed penalty.
751 * value should only be 1 or 0.
753 static inline void ni_set_bits(struct comedi_device
*dev
, int reg
, unsigned bits
,
762 ni_set_bitfield(dev
, reg
, bits
, bit_values
);
765 static irqreturn_t
ni_E_interrupt(int irq
, void *d
)
767 struct comedi_device
*dev
= d
;
768 unsigned short a_status
;
769 unsigned short b_status
;
770 unsigned int ai_mite_status
= 0;
771 unsigned int ao_mite_status
= 0;
774 struct mite_struct
*mite
= devpriv
->mite
;
777 if (dev
->attached
== 0)
779 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
781 /* lock to avoid race with comedi_poll */
782 spin_lock_irqsave(&dev
->spinlock
, flags
);
783 a_status
= devpriv
->stc_readw(dev
, AI_Status_1_Register
);
784 b_status
= devpriv
->stc_readw(dev
, AO_Status_1_Register
);
787 unsigned long flags_too
;
789 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags_too
);
790 if (devpriv
->ai_mite_chan
) {
791 ai_mite_status
= mite_get_status(devpriv
->ai_mite_chan
);
792 if (ai_mite_status
& CHSR_LINKC
)
794 devpriv
->mite
->mite_io_addr
+
795 MITE_CHOR(devpriv
->ai_mite_chan
->
798 if (devpriv
->ao_mite_chan
) {
799 ao_mite_status
= mite_get_status(devpriv
->ao_mite_chan
);
800 if (ao_mite_status
& CHSR_LINKC
)
803 MITE_CHOR(devpriv
->ao_mite_chan
->
806 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags_too
);
809 ack_a_interrupt(dev
, a_status
);
810 ack_b_interrupt(dev
, b_status
);
811 if ((a_status
& Interrupt_A_St
) || (ai_mite_status
& CHSR_INT
))
812 handle_a_interrupt(dev
, a_status
, ai_mite_status
);
813 if ((b_status
& Interrupt_B_St
) || (ao_mite_status
& CHSR_INT
))
814 handle_b_interrupt(dev
, b_status
, ao_mite_status
);
815 handle_gpct_interrupt(dev
, 0);
816 handle_gpct_interrupt(dev
, 1);
817 handle_cdio_interrupt(dev
);
819 spin_unlock_irqrestore(&dev
->spinlock
, flags
);
824 static void ni_sync_ai_dma(struct comedi_device
*dev
)
826 struct comedi_subdevice
*s
= dev
->subdevices
+ NI_AI_SUBDEV
;
829 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
830 if (devpriv
->ai_mite_chan
)
831 mite_sync_input_dma(devpriv
->ai_mite_chan
, s
->async
);
832 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
835 static void mite_handle_b_linkc(struct mite_struct
*mite
, struct comedi_device
* dev
)
837 struct comedi_subdevice
*s
= dev
->subdevices
+ NI_AO_SUBDEV
;
840 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
841 if (devpriv
->ao_mite_chan
) {
842 mite_sync_output_dma(devpriv
->ao_mite_chan
, s
->async
);
844 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
847 static int ni_ao_wait_for_dma_load(struct comedi_device
*dev
)
849 static const int timeout
= 10000;
851 for (i
= 0; i
< timeout
; i
++) {
852 unsigned short b_status
;
854 b_status
= devpriv
->stc_readw(dev
, AO_Status_1_Register
);
855 if (b_status
& AO_FIFO_Half_Full_St
)
857 /* if we poll too often, the pci bus activity seems
858 to slow the dma transfer down */
862 comedi_error(dev
, "timed out waiting for dma load");
869 static void ni_handle_eos(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
871 if (devpriv
->aimode
== AIMODE_SCAN
) {
873 static const int timeout
= 10;
876 for (i
= 0; i
< timeout
; i
++) {
878 if ((s
->async
->events
& COMEDI_CB_EOS
))
883 ni_handle_fifo_dregs(dev
);
884 s
->async
->events
|= COMEDI_CB_EOS
;
887 /* handle special case of single scan using AI_End_On_End_Of_Scan */
888 if ((devpriv
->ai_cmd2
& AI_End_On_End_Of_Scan
)) {
889 shutdown_ai_command(dev
);
893 static void shutdown_ai_command(struct comedi_device
*dev
)
895 struct comedi_subdevice
*s
= dev
->subdevices
+ NI_AI_SUBDEV
;
898 ni_ai_drain_dma(dev
);
900 ni_handle_fifo_dregs(dev
);
901 get_last_sample_611x(dev
);
902 get_last_sample_6143(dev
);
904 s
->async
->events
|= COMEDI_CB_EOA
;
907 static void ni_event(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
910 events
& (COMEDI_CB_ERROR
| COMEDI_CB_OVERFLOW
| COMEDI_CB_EOA
))
912 switch (s
- dev
->subdevices
) {
919 case NI_GPCT0_SUBDEV
:
920 case NI_GPCT1_SUBDEV
:
921 ni_gpct_cancel(dev
, s
);
924 ni_cdio_cancel(dev
, s
);
930 comedi_event(dev
, s
);
933 static void handle_gpct_interrupt(struct comedi_device
*dev
,
934 unsigned short counter_index
)
937 struct comedi_subdevice
*s
= dev
->subdevices
+ NI_GPCT_SUBDEV(counter_index
);
939 ni_tio_handle_interrupt(&devpriv
->counter_dev
->counters
[counter_index
],
941 if (s
->async
->events
)
946 static void ack_a_interrupt(struct comedi_device
*dev
, unsigned short a_status
)
948 unsigned short ack
= 0;
950 if (a_status
& AI_SC_TC_St
) {
951 ack
|= AI_SC_TC_Interrupt_Ack
;
953 if (a_status
& AI_START1_St
) {
954 ack
|= AI_START1_Interrupt_Ack
;
956 if (a_status
& AI_START_St
) {
957 ack
|= AI_START_Interrupt_Ack
;
959 if (a_status
& AI_STOP_St
) {
960 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
961 ack
|= AI_STOP_Interrupt_Ack
/*| AI_START_Interrupt_Ack */ ;
964 devpriv
->stc_writew(dev
, ack
, Interrupt_A_Ack_Register
);
967 static void handle_a_interrupt(struct comedi_device
*dev
, unsigned short status
,
968 unsigned ai_mite_status
)
970 struct comedi_subdevice
*s
= dev
->subdevices
+ NI_AI_SUBDEV
;
972 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
973 if (s
->type
== COMEDI_SUBD_UNUSED
)
976 #ifdef DEBUG_INTERRUPT
978 ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
979 status
, ai_mite_status
);
980 ni_mio_print_status_a(status
);
983 if (ai_mite_status
& CHSR_LINKC
) {
987 if (ai_mite_status
& ~(CHSR_INT
| CHSR_LINKC
| CHSR_DONE
| CHSR_MRDY
|
988 CHSR_DRDY
| CHSR_DRQ1
| CHSR_DRQ0
| CHSR_ERROR
|
989 CHSR_SABORT
| CHSR_XFERR
| CHSR_LxERR_mask
)) {
991 ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
993 /* mite_print_chsr(ai_mite_status); */
994 s
->async
->events
|= COMEDI_CB_ERROR
| COMEDI_CB_EOA
;
995 /* disable_irq(dev->irq); */
999 /* test for all uncommon interrupt events at the same time */
1000 if (status
& (AI_Overrun_St
| AI_Overflow_St
| AI_SC_TC_Error_St
|
1001 AI_SC_TC_St
| AI_START1_St
)) {
1002 if (status
== 0xffff) {
1004 ("ni_mio_common: a_status=0xffff. Card removed?\n");
1005 /* we probably aren't even running a command now,
1006 * so it's a good idea to be careful. */
1007 if (comedi_get_subdevice_runflags(s
) & SRF_RUNNING
) {
1009 COMEDI_CB_ERROR
| COMEDI_CB_EOA
;
1014 if (status
& (AI_Overrun_St
| AI_Overflow_St
|
1015 AI_SC_TC_Error_St
)) {
1016 printk("ni_mio_common: ai error a_status=%04x\n",
1018 ni_mio_print_status_a(status
);
1020 shutdown_ai_command(dev
);
1022 s
->async
->events
|= COMEDI_CB_ERROR
;
1023 if (status
& (AI_Overrun_St
| AI_Overflow_St
))
1024 s
->async
->events
|= COMEDI_CB_OVERFLOW
;
1030 if (status
& AI_SC_TC_St
) {
1031 #ifdef DEBUG_INTERRUPT
1032 printk("ni_mio_common: SC_TC interrupt\n");
1034 if (!devpriv
->ai_continuous
) {
1035 shutdown_ai_command(dev
);
1040 if (status
& AI_FIFO_Half_Full_St
) {
1042 static const int timeout
= 10;
1043 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1044 *fail to get the fifo less than half full, so loop to be sure.*/
1045 for (i
= 0; i
< timeout
; ++i
) {
1046 ni_handle_fifo_half_full(dev
);
1047 if ((devpriv
->stc_readw(dev
,
1048 AI_Status_1_Register
) &
1049 AI_FIFO_Half_Full_St
) == 0)
1053 #endif /* !PCIDMA */
1055 if ((status
& AI_STOP_St
)) {
1056 ni_handle_eos(dev
, s
);
1061 #ifdef DEBUG_INTERRUPT
1062 status
= devpriv
->stc_readw(dev
, AI_Status_1_Register
);
1063 if (status
& Interrupt_A_St
) {
1065 ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1071 static void ack_b_interrupt(struct comedi_device
*dev
, unsigned short b_status
)
1073 unsigned short ack
= 0;
1074 if (b_status
& AO_BC_TC_St
) {
1075 ack
|= AO_BC_TC_Interrupt_Ack
;
1077 if (b_status
& AO_Overrun_St
) {
1078 ack
|= AO_Error_Interrupt_Ack
;
1080 if (b_status
& AO_START_St
) {
1081 ack
|= AO_START_Interrupt_Ack
;
1083 if (b_status
& AO_START1_St
) {
1084 ack
|= AO_START1_Interrupt_Ack
;
1086 if (b_status
& AO_UC_TC_St
) {
1087 ack
|= AO_UC_TC_Interrupt_Ack
;
1089 if (b_status
& AO_UI2_TC_St
) {
1090 ack
|= AO_UI2_TC_Interrupt_Ack
;
1092 if (b_status
& AO_UPDATE_St
) {
1093 ack
|= AO_UPDATE_Interrupt_Ack
;
1096 devpriv
->stc_writew(dev
, ack
, Interrupt_B_Ack_Register
);
1099 static void handle_b_interrupt(struct comedi_device
*dev
, unsigned short b_status
,
1100 unsigned ao_mite_status
)
1102 struct comedi_subdevice
*s
= dev
->subdevices
+ NI_AO_SUBDEV
;
1103 /* unsigned short ack=0; */
1104 #ifdef DEBUG_INTERRUPT
1105 printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1106 b_status
, ao_mite_status
);
1107 ni_mio_print_status_b(b_status
);
1111 /* Currently, mite.c requires us to handle LINKC */
1112 if (ao_mite_status
& CHSR_LINKC
) {
1113 mite_handle_b_linkc(devpriv
->mite
, dev
);
1116 if (ao_mite_status
& ~(CHSR_INT
| CHSR_LINKC
| CHSR_DONE
| CHSR_MRDY
|
1117 CHSR_DRDY
| CHSR_DRQ1
| CHSR_DRQ0
| CHSR_ERROR
|
1118 CHSR_SABORT
| CHSR_XFERR
| CHSR_LxERR_mask
)) {
1120 ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1122 /* mite_print_chsr(ao_mite_status); */
1123 s
->async
->events
|= COMEDI_CB_EOA
| COMEDI_CB_ERROR
;
1127 if (b_status
== 0xffff)
1129 if (b_status
& AO_Overrun_St
) {
1131 ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1132 b_status
, devpriv
->stc_readw(dev
,
1133 AO_Status_2_Register
));
1134 s
->async
->events
|= COMEDI_CB_OVERFLOW
;
1137 if (b_status
& AO_BC_TC_St
) {
1138 MDPRINTK("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n", b_status
, devpriv
->stc_readw(dev
, AO_Status_2_Register
));
1139 s
->async
->events
|= COMEDI_CB_EOA
;
1142 if (b_status
& AO_FIFO_Request_St
) {
1145 ret
= ni_ao_fifo_half_empty(dev
, s
);
1147 printk("ni_mio_common: AO buffer underrun\n");
1148 ni_set_bits(dev
, Interrupt_B_Enable_Register
,
1149 AO_FIFO_Interrupt_Enable
|
1150 AO_Error_Interrupt_Enable
, 0);
1151 s
->async
->events
|= COMEDI_CB_OVERFLOW
;
1159 #ifdef DEBUG_STATUS_A
1160 static const char *const status_a_strings
[] = {
1161 "passthru0", "fifo", "G0_gate", "G0_TC",
1162 "stop", "start", "sc_tc", "start1",
1163 "start2", "sc_tc_error", "overflow", "overrun",
1164 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1167 static void ni_mio_print_status_a(int status
)
1171 printk("A status:");
1172 for (i
= 15; i
>= 0; i
--) {
1173 if (status
& (1 << i
)) {
1174 printk(" %s", status_a_strings
[i
]);
1181 #ifdef DEBUG_STATUS_B
1182 static const char *const status_b_strings
[] = {
1183 "passthru1", "fifo", "G1_gate", "G1_TC",
1184 "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1185 "start1", "overrun", "start", "bc_tc_error",
1186 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1189 static void ni_mio_print_status_b(int status
)
1193 printk("B status:");
1194 for (i
= 15; i
>= 0; i
--) {
1195 if (status
& (1 << i
)) {
1196 printk(" %s", status_b_strings
[i
]);
1205 static void ni_ao_fifo_load(struct comedi_device
*dev
, struct comedi_subdevice
*s
, int n
)
1207 struct comedi_async
*async
= s
->async
;
1208 struct comedi_cmd
*cmd
= &async
->cmd
;
1216 chan
= async
->cur_chan
;
1217 for (i
= 0; i
< n
; i
++) {
1218 err
&= comedi_buf_get(async
, &d
);
1222 range
= CR_RANGE(cmd
->chanlist
[chan
]);
1224 if (boardtype
.reg_type
& ni_reg_6xxx_mask
) {
1225 packed_data
= d
& 0xffff;
1226 /* 6711 only has 16 bit wide ao fifo */
1227 if (boardtype
.reg_type
!= ni_reg_6711
) {
1228 err
&= comedi_buf_get(async
, &d
);
1233 packed_data
|= (d
<< 16) & 0xffff0000;
1235 ni_writel(packed_data
, DAC_FIFO_Data_611x
);
1237 ni_writew(d
, DAC_FIFO_Data
);
1240 chan
%= cmd
->chanlist_len
;
1242 async
->cur_chan
= chan
;
1244 async
->events
|= COMEDI_CB_OVERFLOW
;
1249 * There's a small problem if the FIFO gets really low and we
1250 * don't have the data to fill it. Basically, if after we fill
1251 * the FIFO with all the data available, the FIFO is _still_
1252 * less than half full, we never clear the interrupt. If the
1253 * IRQ is in edge mode, we never get another interrupt, because
1254 * this one wasn't cleared. If in level mode, we get flooded
1255 * with interrupts that we can't fulfill, because nothing ever
1256 * gets put into the buffer.
1258 * This kind of situation is recoverable, but it is easier to
1259 * just pretend we had a FIFO underrun, since there is a good
1260 * chance it will happen anyway. This is _not_ the case for
1261 * RT code, as RT code might purposely be running close to the
1262 * metal. Needs to be fixed eventually.
1264 static int ni_ao_fifo_half_empty(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
1268 n
= comedi_buf_read_n_available(s
->async
);
1270 s
->async
->events
|= COMEDI_CB_OVERFLOW
;
1275 if (n
> boardtype
.ao_fifo_depth
/ 2)
1276 n
= boardtype
.ao_fifo_depth
/ 2;
1278 ni_ao_fifo_load(dev
, s
, n
);
1280 s
->async
->events
|= COMEDI_CB_BLOCK
;
1285 static int ni_ao_prep_fifo(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
1290 devpriv
->stc_writew(dev
, 1, DAC_FIFO_Clear
);
1291 if (boardtype
.reg_type
& ni_reg_6xxx_mask
)
1292 ni_ao_win_outl(dev
, 0x6, AO_FIFO_Offset_Load_611x
);
1294 /* load some data */
1295 n
= comedi_buf_read_n_available(s
->async
);
1300 if (n
> boardtype
.ao_fifo_depth
)
1301 n
= boardtype
.ao_fifo_depth
;
1303 ni_ao_fifo_load(dev
, s
, n
);
1308 static void ni_ai_fifo_read(struct comedi_device
*dev
, struct comedi_subdevice
*s
, int n
)
1310 struct comedi_async
*async
= s
->async
;
1313 if (boardtype
.reg_type
== ni_reg_611x
) {
1317 for (i
= 0; i
< n
/ 2; i
++) {
1318 dl
= ni_readl(ADC_FIFO_Data_611x
);
1319 /* This may get the hi/lo data in the wrong order */
1320 data
[0] = (dl
>> 16) & 0xffff;
1321 data
[1] = dl
& 0xffff;
1322 cfc_write_array_to_buffer(s
, data
, sizeof(data
));
1324 /* Check if there's a single sample stuck in the FIFO */
1326 dl
= ni_readl(ADC_FIFO_Data_611x
);
1327 data
[0] = dl
& 0xffff;
1328 cfc_write_to_buffer(s
, data
[0]);
1330 } else if (boardtype
.reg_type
== ni_reg_6143
) {
1334 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1335 for (i
= 0; i
< n
/ 2; i
++) {
1336 dl
= ni_readl(AIFIFO_Data_6143
);
1338 data
[0] = (dl
>> 16) & 0xffff;
1339 data
[1] = dl
& 0xffff;
1340 cfc_write_array_to_buffer(s
, data
, sizeof(data
));
1343 /* Assume there is a single sample stuck in the FIFO */
1344 ni_writel(0x01, AIFIFO_Control_6143
); /* Get stranded sample into FIFO */
1345 dl
= ni_readl(AIFIFO_Data_6143
);
1346 data
[0] = (dl
>> 16) & 0xffff;
1347 cfc_write_to_buffer(s
, data
[0]);
1350 if (n
> sizeof(devpriv
->ai_fifo_buffer
) /
1351 sizeof(devpriv
->ai_fifo_buffer
[0])) {
1352 comedi_error(dev
, "bug! ai_fifo_buffer too small");
1353 async
->events
|= COMEDI_CB_ERROR
;
1356 for (i
= 0; i
< n
; i
++) {
1357 devpriv
->ai_fifo_buffer
[i
] =
1358 ni_readw(ADC_FIFO_Data_Register
);
1360 cfc_write_array_to_buffer(s
, devpriv
->ai_fifo_buffer
,
1361 n
* sizeof(devpriv
->ai_fifo_buffer
[0]));
1365 static void ni_handle_fifo_half_full(struct comedi_device
*dev
)
1368 struct comedi_subdevice
*s
= dev
->subdevices
+ NI_AI_SUBDEV
;
1370 n
= boardtype
.ai_fifo_depth
/ 2;
1372 ni_ai_fifo_read(dev
, s
, n
);
1377 static int ni_ai_drain_dma(struct comedi_device
*dev
)
1380 static const int timeout
= 10000;
1381 unsigned long flags
;
1384 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
1385 if (devpriv
->ai_mite_chan
) {
1386 for (i
= 0; i
< timeout
; i
++) {
1387 if ((devpriv
->stc_readw(dev
,
1388 AI_Status_1_Register
) &
1390 && mite_bytes_in_transit(devpriv
->
1397 ("ni_mio_common: wait for dma drain timed out\n");
1399 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1400 mite_bytes_in_transit(devpriv
->ai_mite_chan
),
1401 devpriv
->stc_readw(dev
, AI_Status_1_Register
));
1405 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
1407 ni_sync_ai_dma(dev
);
1415 static void ni_handle_fifo_dregs(struct comedi_device
*dev
)
1417 struct comedi_subdevice
*s
= dev
->subdevices
+ NI_AI_SUBDEV
;
1423 if (boardtype
.reg_type
== ni_reg_611x
) {
1424 while ((devpriv
->stc_readw(dev
,
1425 AI_Status_1_Register
) &
1426 AI_FIFO_Empty_St
) == 0) {
1427 dl
= ni_readl(ADC_FIFO_Data_611x
);
1429 /* This may get the hi/lo data in the wrong order */
1430 data
[0] = (dl
>> 16);
1431 data
[1] = (dl
& 0xffff);
1432 cfc_write_array_to_buffer(s
, data
, sizeof(data
));
1434 } else if (boardtype
.reg_type
== ni_reg_6143
) {
1436 while (ni_readl(AIFIFO_Status_6143
) & 0x04) {
1437 dl
= ni_readl(AIFIFO_Data_6143
);
1439 /* This may get the hi/lo data in the wrong order */
1440 data
[0] = (dl
>> 16);
1441 data
[1] = (dl
& 0xffff);
1442 cfc_write_array_to_buffer(s
, data
, sizeof(data
));
1445 /* Check if stranded sample is present */
1446 if (ni_readl(AIFIFO_Status_6143
) & 0x01) {
1447 ni_writel(0x01, AIFIFO_Control_6143
); /* Get stranded sample into FIFO */
1448 dl
= ni_readl(AIFIFO_Data_6143
);
1449 data
[0] = (dl
>> 16) & 0xffff;
1450 cfc_write_to_buffer(s
, data
[0]);
1455 devpriv
->stc_readw(dev
,
1456 AI_Status_1_Register
) & AI_FIFO_Empty_St
;
1457 while (fifo_empty
== 0) {
1460 sizeof(devpriv
->ai_fifo_buffer
) /
1461 sizeof(devpriv
->ai_fifo_buffer
[0]); i
++) {
1463 devpriv
->stc_readw(dev
,
1464 AI_Status_1_Register
) &
1468 devpriv
->ai_fifo_buffer
[i
] =
1469 ni_readw(ADC_FIFO_Data_Register
);
1471 cfc_write_array_to_buffer(s
, devpriv
->ai_fifo_buffer
,
1472 i
* sizeof(devpriv
->ai_fifo_buffer
[0]));
1477 static void get_last_sample_611x(struct comedi_device
*dev
)
1479 struct comedi_subdevice
*s
= dev
->subdevices
+ NI_AI_SUBDEV
;
1483 if (boardtype
.reg_type
!= ni_reg_611x
)
1486 /* Check if there's a single sample stuck in the FIFO */
1487 if (ni_readb(XXX_Status
) & 0x80) {
1488 dl
= ni_readl(ADC_FIFO_Data_611x
);
1489 data
= (dl
& 0xffff);
1490 cfc_write_to_buffer(s
, data
);
1494 static void get_last_sample_6143(struct comedi_device
*dev
)
1496 struct comedi_subdevice
*s
= dev
->subdevices
+ NI_AI_SUBDEV
;
1500 if (boardtype
.reg_type
!= ni_reg_6143
)
1503 /* Check if there's a single sample stuck in the FIFO */
1504 if (ni_readl(AIFIFO_Status_6143
) & 0x01) {
1505 ni_writel(0x01, AIFIFO_Control_6143
); /* Get stranded sample into FIFO */
1506 dl
= ni_readl(AIFIFO_Data_6143
);
1508 /* This may get the hi/lo data in the wrong order */
1509 data
= (dl
>> 16) & 0xffff;
1510 cfc_write_to_buffer(s
, data
);
1514 static void ni_ai_munge(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
1515 void *data
, unsigned int num_bytes
, unsigned int chan_index
)
1517 struct comedi_async
*async
= s
->async
;
1519 unsigned int length
= num_bytes
/ bytes_per_sample(s
);
1520 short *array
= data
;
1521 unsigned int *larray
= data
;
1522 for (i
= 0; i
< length
; i
++) {
1524 if (s
->subdev_flags
& SDF_LSAMPL
)
1525 larray
[i
] = le32_to_cpu(larray
[i
]);
1527 array
[i
] = le16_to_cpu(array
[i
]);
1529 if (s
->subdev_flags
& SDF_LSAMPL
)
1530 larray
[i
] += devpriv
->ai_offset
[chan_index
];
1532 array
[i
] += devpriv
->ai_offset
[chan_index
];
1534 chan_index
%= async
->cmd
.chanlist_len
;
1540 static int ni_ai_setup_MITE_dma(struct comedi_device
*dev
)
1542 struct comedi_subdevice
*s
= dev
->subdevices
+ NI_AI_SUBDEV
;
1544 unsigned long flags
;
1546 retval
= ni_request_ai_mite_channel(dev
);
1549 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1551 /* write alloc the entire buffer */
1552 comedi_buf_write_alloc(s
->async
, s
->async
->prealloc_bufsz
);
1554 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
1555 if (devpriv
->ai_mite_chan
== NULL
) {
1556 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
1560 switch (boardtype
.reg_type
) {
1563 mite_prep_dma(devpriv
->ai_mite_chan
, 32, 16);
1566 mite_prep_dma(devpriv
->ai_mite_chan
, 32, 32);
1569 mite_prep_dma(devpriv
->ai_mite_chan
, 16, 16);
1573 mite_dma_arm(devpriv
->ai_mite_chan
);
1574 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
1579 static int ni_ao_setup_MITE_dma(struct comedi_device
*dev
)
1581 struct comedi_subdevice
*s
= dev
->subdevices
+ NI_AO_SUBDEV
;
1583 unsigned long flags
;
1585 retval
= ni_request_ao_mite_channel(dev
);
1589 /* read alloc the entire buffer */
1590 comedi_buf_read_alloc(s
->async
, s
->async
->prealloc_bufsz
);
1592 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
1593 if (devpriv
->ao_mite_chan
) {
1594 if (boardtype
.reg_type
& (ni_reg_611x
| ni_reg_6713
)) {
1595 mite_prep_dma(devpriv
->ao_mite_chan
, 32, 32);
1597 /* doing 32 instead of 16 bit wide transfers from memory
1598 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1599 mite_prep_dma(devpriv
->ao_mite_chan
, 16, 32);
1601 mite_dma_arm(devpriv
->ao_mite_chan
);
1604 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
1612 used for both cancel ioctl and board initialization
1614 this is pretty harsh for a cancel, but it works...
1617 static int ni_ai_reset(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
1619 ni_release_ai_mite_channel(dev
);
1620 /* ai configuration */
1621 devpriv
->stc_writew(dev
, AI_Configuration_Start
| AI_Reset
,
1622 Joint_Reset_Register
);
1624 ni_set_bits(dev
, Interrupt_A_Enable_Register
,
1625 AI_SC_TC_Interrupt_Enable
| AI_START1_Interrupt_Enable
|
1626 AI_START2_Interrupt_Enable
| AI_START_Interrupt_Enable
|
1627 AI_STOP_Interrupt_Enable
| AI_Error_Interrupt_Enable
|
1628 AI_FIFO_Interrupt_Enable
, 0);
1630 ni_clear_ai_fifo(dev
);
1632 if (boardtype
.reg_type
!= ni_reg_6143
)
1633 ni_writeb(0, Misc_Command
);
1635 devpriv
->stc_writew(dev
, AI_Disarm
, AI_Command_1_Register
); /* reset pulses */
1636 devpriv
->stc_writew(dev
,
1637 AI_Start_Stop
| AI_Mode_1_Reserved
/*| AI_Trigger_Once */ ,
1638 AI_Mode_1_Register
);
1639 devpriv
->stc_writew(dev
, 0x0000, AI_Mode_2_Register
);
1640 /* generate FIFO interrupts on non-empty */
1641 devpriv
->stc_writew(dev
, (0 << 6) | 0x0000, AI_Mode_3_Register
);
1642 if (boardtype
.reg_type
== ni_reg_611x
) {
1643 devpriv
->stc_writew(dev
, AI_SHIFTIN_Pulse_Width
|
1645 AI_LOCALMUX_CLK_Pulse_Width
, AI_Personal_Register
);
1646 devpriv
->stc_writew(dev
, AI_SCAN_IN_PROG_Output_Select(3) |
1647 AI_EXTMUX_CLK_Output_Select(0) |
1648 AI_LOCALMUX_CLK_Output_Select(2) |
1649 AI_SC_TC_Output_Select(3) |
1650 AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_High
),
1651 AI_Output_Control_Register
);
1652 } else if (boardtype
.reg_type
== ni_reg_6143
) {
1653 devpriv
->stc_writew(dev
, AI_SHIFTIN_Pulse_Width
|
1655 AI_LOCALMUX_CLK_Pulse_Width
, AI_Personal_Register
);
1656 devpriv
->stc_writew(dev
, AI_SCAN_IN_PROG_Output_Select(3) |
1657 AI_EXTMUX_CLK_Output_Select(0) |
1658 AI_LOCALMUX_CLK_Output_Select(2) |
1659 AI_SC_TC_Output_Select(3) |
1660 AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_Low
),
1661 AI_Output_Control_Register
);
1663 unsigned ai_output_control_bits
;
1664 devpriv
->stc_writew(dev
, AI_SHIFTIN_Pulse_Width
|
1666 AI_CONVERT_Pulse_Width
|
1667 AI_LOCALMUX_CLK_Pulse_Width
, AI_Personal_Register
);
1668 ai_output_control_bits
= AI_SCAN_IN_PROG_Output_Select(3) |
1669 AI_EXTMUX_CLK_Output_Select(0) |
1670 AI_LOCALMUX_CLK_Output_Select(2) |
1671 AI_SC_TC_Output_Select(3);
1672 if (boardtype
.reg_type
== ni_reg_622x
)
1673 ai_output_control_bits
|=
1674 AI_CONVERT_Output_Select
1675 (AI_CONVERT_Output_Enable_High
);
1677 ai_output_control_bits
|=
1678 AI_CONVERT_Output_Select
1679 (AI_CONVERT_Output_Enable_Low
);
1680 devpriv
->stc_writew(dev
, ai_output_control_bits
,
1681 AI_Output_Control_Register
);
1683 /* the following registers should not be changed, because there
1684 * are no backup registers in devpriv. If you want to change
1685 * any of these, add a backup register and other appropriate code:
1686 * AI_Mode_1_Register
1687 * AI_Mode_3_Register
1688 * AI_Personal_Register
1689 * AI_Output_Control_Register
1691 devpriv
->stc_writew(dev
, AI_SC_TC_Error_Confirm
| AI_START_Interrupt_Ack
| AI_START2_Interrupt_Ack
| AI_START1_Interrupt_Ack
| AI_SC_TC_Interrupt_Ack
| AI_Error_Interrupt_Ack
| AI_STOP_Interrupt_Ack
, Interrupt_A_Ack_Register
); /* clear interrupts */
1693 devpriv
->stc_writew(dev
, AI_Configuration_End
, Joint_Reset_Register
);
1698 static int ni_ai_poll(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
1700 unsigned long flags
= 0;
1703 /* lock to avoid race with interrupt handler */
1704 if (in_interrupt() == 0)
1705 spin_lock_irqsave(&dev
->spinlock
, flags
);
1707 ni_handle_fifo_dregs(dev
);
1709 ni_sync_ai_dma(dev
);
1711 count
= s
->async
->buf_write_count
- s
->async
->buf_read_count
;
1712 if (in_interrupt() == 0)
1713 spin_unlock_irqrestore(&dev
->spinlock
, flags
);
1718 static int ni_ai_insn_read(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
1719 struct comedi_insn
*insn
, unsigned int *data
)
1722 const unsigned int mask
= (1 << boardtype
.adbits
) - 1;
1727 ni_load_channelgain_list(dev
, 1, &insn
->chanspec
);
1729 ni_clear_ai_fifo(dev
);
1731 signbits
= devpriv
->ai_offset
[0];
1732 if (boardtype
.reg_type
== ni_reg_611x
) {
1733 for (n
= 0; n
< num_adc_stages_611x
; n
++) {
1734 devpriv
->stc_writew(dev
, AI_CONVERT_Pulse
,
1735 AI_Command_1_Register
);
1738 for (n
= 0; n
< insn
->n
; n
++) {
1739 devpriv
->stc_writew(dev
, AI_CONVERT_Pulse
,
1740 AI_Command_1_Register
);
1741 /* The 611x has screwy 32-bit FIFOs. */
1743 for (i
= 0; i
< NI_TIMEOUT
; i
++) {
1744 if (ni_readb(XXX_Status
) & 0x80) {
1745 d
= (ni_readl(ADC_FIFO_Data_611x
) >> 16)
1749 if (!(devpriv
->stc_readw(dev
,
1750 AI_Status_1_Register
) &
1751 AI_FIFO_Empty_St
)) {
1752 d
= ni_readl(ADC_FIFO_Data_611x
) &
1757 if (i
== NI_TIMEOUT
) {
1759 ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1765 } else if (boardtype
.reg_type
== ni_reg_6143
) {
1766 for (n
= 0; n
< insn
->n
; n
++) {
1767 devpriv
->stc_writew(dev
, AI_CONVERT_Pulse
,
1768 AI_Command_1_Register
);
1770 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1772 for (i
= 0; i
< NI_TIMEOUT
; i
++) {
1773 if (ni_readl(AIFIFO_Status_6143
) & 0x01) {
1774 ni_writel(0x01, AIFIFO_Control_6143
); /* Get stranded sample into FIFO */
1775 dl
= ni_readl(AIFIFO_Data_6143
);
1779 if (i
== NI_TIMEOUT
) {
1781 ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1784 data
[n
] = (((dl
>> 16) & 0xFFFF) + signbits
) & 0xFFFF;
1787 for (n
= 0; n
< insn
->n
; n
++) {
1788 devpriv
->stc_writew(dev
, AI_CONVERT_Pulse
,
1789 AI_Command_1_Register
);
1790 for (i
= 0; i
< NI_TIMEOUT
; i
++) {
1791 if (!(devpriv
->stc_readw(dev
,
1792 AI_Status_1_Register
) &
1796 if (i
== NI_TIMEOUT
) {
1798 ("ni_mio_common: timeout in ni_ai_insn_read\n");
1801 if (boardtype
.reg_type
& ni_reg_m_series_mask
) {
1803 ni_readl(M_Offset_AI_FIFO_Data
) & mask
;
1805 d
= ni_readw(ADC_FIFO_Data_Register
);
1806 d
+= signbits
; /* subtle: needs to be short addition */
1814 void ni_prime_channelgain_list(struct comedi_device
*dev
)
1817 devpriv
->stc_writew(dev
, AI_CONVERT_Pulse
, AI_Command_1_Register
);
1818 for (i
= 0; i
< NI_TIMEOUT
; ++i
) {
1819 if (!(devpriv
->stc_readw(dev
,
1820 AI_Status_1_Register
) &
1821 AI_FIFO_Empty_St
)) {
1822 devpriv
->stc_writew(dev
, 1, ADC_FIFO_Clear
);
1827 printk("ni_mio_common: timeout loading channel/gain list\n");
1830 static void ni_m_series_load_channelgain_list(struct comedi_device
*dev
,
1831 unsigned int n_chan
, unsigned int *list
)
1833 unsigned int chan
, range
, aref
;
1836 unsigned int dither
;
1837 unsigned range_code
;
1839 devpriv
->stc_writew(dev
, 1, Configuration_Memory_Clear
);
1841 /* offset = 1 << (boardtype.adbits - 1); */
1842 if ((list
[0] & CR_ALT_SOURCE
)) {
1843 unsigned bypass_bits
;
1844 chan
= CR_CHAN(list
[0]);
1845 range
= CR_RANGE(list
[0]);
1846 range_code
= ni_gainlkup
[boardtype
.gainlkup
][range
];
1847 dither
= ((list
[0] & CR_ALT_FILTER
) != 0);
1848 bypass_bits
= MSeries_AI_Bypass_Config_FIFO_Bit
;
1849 bypass_bits
|= chan
;
1852 ai_calib_source
) & (MSeries_AI_Bypass_Cal_Sel_Pos_Mask
|
1853 MSeries_AI_Bypass_Cal_Sel_Neg_Mask
|
1854 MSeries_AI_Bypass_Mode_Mux_Mask
|
1855 MSeries_AO_Bypass_AO_Cal_Sel_Mask
);
1856 bypass_bits
|= MSeries_AI_Bypass_Gain_Bits(range_code
);
1858 bypass_bits
|= MSeries_AI_Bypass_Dither_Bit
;
1859 /* don't use 2's complement encoding */
1860 bypass_bits
|= MSeries_AI_Bypass_Polarity_Bit
;
1861 ni_writel(bypass_bits
, M_Offset_AI_Config_FIFO_Bypass
);
1863 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass
);
1866 for (i
= 0; i
< n_chan
; i
++) {
1867 unsigned config_bits
= 0;
1868 chan
= CR_CHAN(list
[i
]);
1869 aref
= CR_AREF(list
[i
]);
1870 range
= CR_RANGE(list
[i
]);
1871 dither
= ((list
[i
] & CR_ALT_FILTER
) != 0);
1873 range_code
= ni_gainlkup
[boardtype
.gainlkup
][range
];
1874 devpriv
->ai_offset
[i
] = offset
;
1878 MSeries_AI_Config_Channel_Type_Differential_Bits
;
1882 MSeries_AI_Config_Channel_Type_Common_Ref_Bits
;
1886 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits
;
1891 config_bits
|= MSeries_AI_Config_Channel_Bits(chan
);
1893 MSeries_AI_Config_Bank_Bits(boardtype
.reg_type
, chan
);
1894 config_bits
|= MSeries_AI_Config_Gain_Bits(range_code
);
1895 if (i
== n_chan
- 1)
1896 config_bits
|= MSeries_AI_Config_Last_Channel_Bit
;
1898 config_bits
|= MSeries_AI_Config_Dither_Bit
;
1899 /* don't use 2's complement encoding */
1900 config_bits
|= MSeries_AI_Config_Polarity_Bit
;
1901 ni_writew(config_bits
, M_Offset_AI_Config_FIFO_Data
);
1903 ni_prime_channelgain_list(dev
);
1907 * Notes on the 6110 and 6111:
1908 * These boards a slightly different than the rest of the series, since
1909 * they have multiple A/D converters.
1910 * From the driver side, the configuration memory is a
1912 * Configuration Memory Low:
1914 * bit 8: unipolar/bipolar (should be 0 for bipolar)
1915 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1916 * 1001 gain=0.1 (+/- 50)
1925 * Configuration Memory High:
1926 * bits 12-14: Channel Type
1927 * 001 for differential
1928 * 000 for calibration
1929 * bit 11: coupling (this is not currently handled)
1933 * valid channels are 0-3
1935 static void ni_load_channelgain_list(struct comedi_device
*dev
, unsigned int n_chan
,
1938 unsigned int chan
, range
, aref
;
1940 unsigned int hi
, lo
;
1942 unsigned int dither
;
1944 if (boardtype
.reg_type
& ni_reg_m_series_mask
) {
1945 ni_m_series_load_channelgain_list(dev
, n_chan
, list
);
1948 if (n_chan
== 1 && (boardtype
.reg_type
!= ni_reg_611x
)
1949 && (boardtype
.reg_type
!= ni_reg_6143
)) {
1950 if (devpriv
->changain_state
1951 && devpriv
->changain_spec
== list
[0]) {
1955 devpriv
->changain_state
= 1;
1956 devpriv
->changain_spec
= list
[0];
1958 devpriv
->changain_state
= 0;
1961 devpriv
->stc_writew(dev
, 1, Configuration_Memory_Clear
);
1963 /* Set up Calibration mode if required */
1964 if (boardtype
.reg_type
== ni_reg_6143
) {
1965 if ((list
[0] & CR_ALT_SOURCE
)
1966 && !devpriv
->ai_calib_source_enabled
) {
1967 /* Strobe Relay enable bit */
1970 Calibration_Channel_6143_RelayOn
,
1971 Calibration_Channel_6143
);
1972 ni_writew(devpriv
->ai_calib_source
,
1973 Calibration_Channel_6143
);
1974 devpriv
->ai_calib_source_enabled
= 1;
1975 msleep_interruptible(100); /* Allow relays to change */
1976 } else if (!(list
[0] & CR_ALT_SOURCE
)
1977 && devpriv
->ai_calib_source_enabled
) {
1978 /* Strobe Relay disable bit */
1981 Calibration_Channel_6143_RelayOff
,
1982 Calibration_Channel_6143
);
1983 ni_writew(devpriv
->ai_calib_source
,
1984 Calibration_Channel_6143
);
1985 devpriv
->ai_calib_source_enabled
= 0;
1986 msleep_interruptible(100); /* Allow relays to change */
1990 offset
= 1 << (boardtype
.adbits
- 1);
1991 for (i
= 0; i
< n_chan
; i
++) {
1992 if ((boardtype
.reg_type
!= ni_reg_6143
)
1993 && (list
[i
] & CR_ALT_SOURCE
)) {
1994 chan
= devpriv
->ai_calib_source
;
1996 chan
= CR_CHAN(list
[i
]);
1998 aref
= CR_AREF(list
[i
]);
1999 range
= CR_RANGE(list
[i
]);
2000 dither
= ((list
[i
] & CR_ALT_FILTER
) != 0);
2002 /* fix the external/internal range differences */
2003 range
= ni_gainlkup
[boardtype
.gainlkup
][range
];
2004 if (boardtype
.reg_type
== ni_reg_611x
)
2005 devpriv
->ai_offset
[i
] = offset
;
2007 devpriv
->ai_offset
[i
] = (range
& 0x100) ? 0 : offset
;
2010 if ((list
[i
] & CR_ALT_SOURCE
)) {
2011 if (boardtype
.reg_type
== ni_reg_611x
)
2012 ni_writew(CR_CHAN(list
[i
]) & 0x0003,
2013 Calibration_Channel_Select_611x
);
2015 if (boardtype
.reg_type
== ni_reg_611x
)
2017 else if (boardtype
.reg_type
== ni_reg_6143
)
2021 hi
|= AI_DIFFERENTIAL
;
2033 hi
|= AI_CONFIG_CHANNEL(chan
);
2035 ni_writew(hi
, Configuration_Memory_High
);
2037 if (boardtype
.reg_type
!= ni_reg_6143
) {
2039 if (i
== n_chan
- 1)
2040 lo
|= AI_LAST_CHANNEL
;
2044 ni_writew(lo
, Configuration_Memory_Low
);
2048 /* prime the channel/gain list */
2049 if ((boardtype
.reg_type
!= ni_reg_611x
)
2050 && (boardtype
.reg_type
!= ni_reg_6143
)) {
2051 ni_prime_channelgain_list(dev
);
2055 static int ni_ns_to_timer(const struct comedi_device
*dev
, unsigned nanosec
,
2059 switch (round_mode
) {
2060 case TRIG_ROUND_NEAREST
:
2062 divider
= (nanosec
+ devpriv
->clock_ns
/ 2) / devpriv
->clock_ns
;
2064 case TRIG_ROUND_DOWN
:
2065 divider
= (nanosec
) / devpriv
->clock_ns
;
2068 divider
= (nanosec
+ devpriv
->clock_ns
- 1) / devpriv
->clock_ns
;
2074 static unsigned ni_timer_to_ns(const struct comedi_device
*dev
, int timer
)
2076 return devpriv
->clock_ns
* (timer
+ 1);
2079 static unsigned ni_min_ai_scan_period_ns(struct comedi_device
*dev
,
2080 unsigned num_channels
)
2082 switch (boardtype
.reg_type
) {
2085 /* simultaneously-sampled inputs */
2086 return boardtype
.ai_speed
;
2089 /* multiplexed inputs */
2092 return boardtype
.ai_speed
* num_channels
;
2095 static int ni_ai_cmdtest(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
2096 struct comedi_cmd
*cmd
)
2102 /* step 1: make sure trigger sources are trivially valid */
2104 if ((cmd
->flags
& CMDF_WRITE
)) {
2105 cmd
->flags
&= ~CMDF_WRITE
;
2108 tmp
= cmd
->start_src
;
2109 cmd
->start_src
&= TRIG_NOW
| TRIG_INT
| TRIG_EXT
;
2110 if (!cmd
->start_src
|| tmp
!= cmd
->start_src
)
2113 tmp
= cmd
->scan_begin_src
;
2114 cmd
->scan_begin_src
&= TRIG_TIMER
| TRIG_EXT
;
2115 if (!cmd
->scan_begin_src
|| tmp
!= cmd
->scan_begin_src
)
2118 tmp
= cmd
->convert_src
;
2119 sources
= TRIG_TIMER
| TRIG_EXT
;
2120 if ((boardtype
.reg_type
== ni_reg_611x
)
2121 || (boardtype
.reg_type
== ni_reg_6143
))
2122 sources
|= TRIG_NOW
;
2123 cmd
->convert_src
&= sources
;
2124 if (!cmd
->convert_src
|| tmp
!= cmd
->convert_src
)
2127 tmp
= cmd
->scan_end_src
;
2128 cmd
->scan_end_src
&= TRIG_COUNT
;
2129 if (!cmd
->scan_end_src
|| tmp
!= cmd
->scan_end_src
)
2132 tmp
= cmd
->stop_src
;
2133 cmd
->stop_src
&= TRIG_COUNT
| TRIG_NONE
;
2134 if (!cmd
->stop_src
|| tmp
!= cmd
->stop_src
)
2140 /* step 2: make sure trigger sources are unique and mutually compatible */
2142 /* note that mutual compatiblity is not an issue here */
2143 if (cmd
->start_src
!= TRIG_NOW
&&
2144 cmd
->start_src
!= TRIG_INT
&& cmd
->start_src
!= TRIG_EXT
)
2146 if (cmd
->scan_begin_src
!= TRIG_TIMER
&&
2147 cmd
->scan_begin_src
!= TRIG_EXT
&&
2148 cmd
->scan_begin_src
!= TRIG_OTHER
)
2150 if (cmd
->convert_src
!= TRIG_TIMER
&&
2151 cmd
->convert_src
!= TRIG_EXT
&& cmd
->convert_src
!= TRIG_NOW
)
2153 if (cmd
->stop_src
!= TRIG_COUNT
&& cmd
->stop_src
!= TRIG_NONE
)
2159 /* step 3: make sure arguments are trivially compatible */
2161 if (cmd
->start_src
== TRIG_EXT
) {
2162 /* external trigger */
2163 unsigned int tmp
= CR_CHAN(cmd
->start_arg
);
2167 tmp
|= (cmd
->start_arg
& (CR_INVERT
| CR_EDGE
));
2168 if (cmd
->start_arg
!= tmp
) {
2169 cmd
->start_arg
= tmp
;
2173 if (cmd
->start_arg
!= 0) {
2174 /* true for both TRIG_NOW and TRIG_INT */
2179 if (cmd
->scan_begin_src
== TRIG_TIMER
) {
2180 if (cmd
->scan_begin_arg
< ni_min_ai_scan_period_ns(dev
,
2181 cmd
->chanlist_len
)) {
2182 cmd
->scan_begin_arg
=
2183 ni_min_ai_scan_period_ns(dev
,
2187 if (cmd
->scan_begin_arg
> devpriv
->clock_ns
* 0xffffff) {
2188 cmd
->scan_begin_arg
= devpriv
->clock_ns
* 0xffffff;
2191 } else if (cmd
->scan_begin_src
== TRIG_EXT
) {
2192 /* external trigger */
2193 unsigned int tmp
= CR_CHAN(cmd
->scan_begin_arg
);
2197 tmp
|= (cmd
->scan_begin_arg
& (CR_INVERT
| CR_EDGE
));
2198 if (cmd
->scan_begin_arg
!= tmp
) {
2199 cmd
->scan_begin_arg
= tmp
;
2202 } else { /* TRIG_OTHER */
2203 if (cmd
->scan_begin_arg
) {
2204 cmd
->scan_begin_arg
= 0;
2208 if (cmd
->convert_src
== TRIG_TIMER
) {
2209 if ((boardtype
.reg_type
== ni_reg_611x
)
2210 || (boardtype
.reg_type
== ni_reg_6143
)) {
2211 if (cmd
->convert_arg
!= 0) {
2212 cmd
->convert_arg
= 0;
2216 if (cmd
->convert_arg
< boardtype
.ai_speed
) {
2217 cmd
->convert_arg
= boardtype
.ai_speed
;
2220 if (cmd
->convert_arg
> devpriv
->clock_ns
* 0xffff) {
2221 cmd
->convert_arg
= devpriv
->clock_ns
* 0xffff;
2225 } else if (cmd
->convert_src
== TRIG_EXT
) {
2226 /* external trigger */
2227 unsigned int tmp
= CR_CHAN(cmd
->convert_arg
);
2231 tmp
|= (cmd
->convert_arg
& (CR_ALT_FILTER
| CR_INVERT
));
2232 if (cmd
->convert_arg
!= tmp
) {
2233 cmd
->convert_arg
= tmp
;
2236 } else if (cmd
->convert_src
== TRIG_NOW
) {
2237 if (cmd
->convert_arg
!= 0) {
2238 cmd
->convert_arg
= 0;
2243 if (cmd
->scan_end_arg
!= cmd
->chanlist_len
) {
2244 cmd
->scan_end_arg
= cmd
->chanlist_len
;
2247 if (cmd
->stop_src
== TRIG_COUNT
) {
2248 unsigned int max_count
= 0x01000000;
2250 if (boardtype
.reg_type
== ni_reg_611x
)
2251 max_count
-= num_adc_stages_611x
;
2252 if (cmd
->stop_arg
> max_count
) {
2253 cmd
->stop_arg
= max_count
;
2256 if (cmd
->stop_arg
< 1) {
2262 if (cmd
->stop_arg
!= 0) {
2271 /* step 4: fix up any arguments */
2273 if (cmd
->scan_begin_src
== TRIG_TIMER
) {
2274 tmp
= cmd
->scan_begin_arg
;
2275 cmd
->scan_begin_arg
=
2276 ni_timer_to_ns(dev
, ni_ns_to_timer(dev
,
2277 cmd
->scan_begin_arg
,
2278 cmd
->flags
& TRIG_ROUND_MASK
));
2279 if (tmp
!= cmd
->scan_begin_arg
)
2282 if (cmd
->convert_src
== TRIG_TIMER
) {
2283 if ((boardtype
.reg_type
!= ni_reg_611x
)
2284 && (boardtype
.reg_type
!= ni_reg_6143
)) {
2285 tmp
= cmd
->convert_arg
;
2287 ni_timer_to_ns(dev
, ni_ns_to_timer(dev
,
2289 cmd
->flags
& TRIG_ROUND_MASK
));
2290 if (tmp
!= cmd
->convert_arg
)
2292 if (cmd
->scan_begin_src
== TRIG_TIMER
&&
2293 cmd
->scan_begin_arg
<
2294 cmd
->convert_arg
* cmd
->scan_end_arg
) {
2295 cmd
->scan_begin_arg
=
2296 cmd
->convert_arg
* cmd
->scan_end_arg
;
2308 static int ni_ai_cmd(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
2310 const struct comedi_cmd
*cmd
= &s
->async
->cmd
;
2312 int mode1
= 0; /* mode1 is needed for both stop and convert */
2314 int start_stop_select
= 0;
2315 unsigned int stop_count
;
2316 int interrupt_a_enable
= 0;
2318 MDPRINTK("ni_ai_cmd\n");
2319 if (dev
->irq
== 0) {
2320 comedi_error(dev
, "cannot run command without an irq");
2323 ni_clear_ai_fifo(dev
);
2325 ni_load_channelgain_list(dev
, cmd
->chanlist_len
, cmd
->chanlist
);
2327 /* start configuration */
2328 devpriv
->stc_writew(dev
, AI_Configuration_Start
, Joint_Reset_Register
);
2330 /* disable analog triggering for now, since it
2331 * interferes with the use of pfi0 */
2332 devpriv
->an_trig_etc_reg
&= ~Analog_Trigger_Enable
;
2333 devpriv
->stc_writew(dev
, devpriv
->an_trig_etc_reg
,
2334 Analog_Trigger_Etc_Register
);
2336 switch (cmd
->start_src
) {
2339 devpriv
->stc_writew(dev
, AI_START2_Select(0) |
2340 AI_START1_Sync
| AI_START1_Edge
| AI_START1_Select(0),
2341 AI_Trigger_Select_Register
);
2345 int chan
= CR_CHAN(cmd
->start_arg
);
2346 unsigned int bits
= AI_START2_Select(0) |
2347 AI_START1_Sync
| AI_START1_Select(chan
+ 1);
2349 if (cmd
->start_arg
& CR_INVERT
)
2350 bits
|= AI_START1_Polarity
;
2351 if (cmd
->start_arg
& CR_EDGE
)
2352 bits
|= AI_START1_Edge
;
2353 devpriv
->stc_writew(dev
, bits
,
2354 AI_Trigger_Select_Register
);
2359 mode2
&= ~AI_Pre_Trigger
;
2360 mode2
&= ~AI_SC_Initial_Load_Source
;
2361 mode2
&= ~AI_SC_Reload_Mode
;
2362 devpriv
->stc_writew(dev
, mode2
, AI_Mode_2_Register
);
2364 if (cmd
->chanlist_len
== 1 || (boardtype
.reg_type
== ni_reg_611x
)
2365 || (boardtype
.reg_type
== ni_reg_6143
)) {
2366 start_stop_select
|= AI_STOP_Polarity
;
2367 start_stop_select
|= AI_STOP_Select(31); /* logic low */
2368 start_stop_select
|= AI_STOP_Sync
;
2370 start_stop_select
|= AI_STOP_Select(19); /* ai configuration memory */
2372 devpriv
->stc_writew(dev
, start_stop_select
,
2373 AI_START_STOP_Select_Register
);
2375 devpriv
->ai_cmd2
= 0;
2376 switch (cmd
->stop_src
) {
2378 stop_count
= cmd
->stop_arg
- 1;
2380 if (boardtype
.reg_type
== ni_reg_611x
) {
2381 /* have to take 3 stage adc pipeline into account */
2382 stop_count
+= num_adc_stages_611x
;
2384 /* stage number of scans */
2385 devpriv
->stc_writel(dev
, stop_count
, AI_SC_Load_A_Registers
);
2387 mode1
|= AI_Start_Stop
| AI_Mode_1_Reserved
| AI_Trigger_Once
;
2388 devpriv
->stc_writew(dev
, mode1
, AI_Mode_1_Register
);
2389 /* load SC (Scan Count) */
2390 devpriv
->stc_writew(dev
, AI_SC_Load
, AI_Command_1_Register
);
2392 devpriv
->ai_continuous
= 0;
2393 if (stop_count
== 0) {
2394 devpriv
->ai_cmd2
|= AI_End_On_End_Of_Scan
;
2395 interrupt_a_enable
|= AI_STOP_Interrupt_Enable
;
2396 /* this is required to get the last sample for chanlist_len > 1, not sure why */
2397 if (cmd
->chanlist_len
> 1)
2398 start_stop_select
|=
2399 AI_STOP_Polarity
| AI_STOP_Edge
;
2403 /* stage number of scans */
2404 devpriv
->stc_writel(dev
, 0, AI_SC_Load_A_Registers
);
2406 mode1
|= AI_Start_Stop
| AI_Mode_1_Reserved
| AI_Continuous
;
2407 devpriv
->stc_writew(dev
, mode1
, AI_Mode_1_Register
);
2409 /* load SC (Scan Count) */
2410 devpriv
->stc_writew(dev
, AI_SC_Load
, AI_Command_1_Register
);
2412 devpriv
->ai_continuous
= 1;
2417 switch (cmd
->scan_begin_src
) {
2420 stop bits for non 611x boards
2421 AI_SI_Special_Trigger_Delay=0
2423 AI_START_STOP_Select_Register:
2424 AI_START_Polarity=0 (?) rising edge
2425 AI_START_Edge=1 edge triggered
2427 AI_START_Select=0 SI_TC
2428 AI_STOP_Polarity=0 rising edge
2429 AI_STOP_Edge=0 level
2431 AI_STOP_Select=19 external pin (configuration mem)
2433 start_stop_select
|= AI_START_Edge
| AI_START_Sync
;
2434 devpriv
->stc_writew(dev
, start_stop_select
,
2435 AI_START_STOP_Select_Register
);
2437 mode2
|= AI_SI_Reload_Mode(0);
2438 /* AI_SI_Initial_Load_Source=A */
2439 mode2
&= ~AI_SI_Initial_Load_Source
;
2440 /* mode2 |= AI_SC_Reload_Mode; */
2441 devpriv
->stc_writew(dev
, mode2
, AI_Mode_2_Register
);
2444 timer
= ni_ns_to_timer(dev
, cmd
->scan_begin_arg
,
2445 TRIG_ROUND_NEAREST
);
2446 devpriv
->stc_writel(dev
, timer
, AI_SI_Load_A_Registers
);
2447 devpriv
->stc_writew(dev
, AI_SI_Load
, AI_Command_1_Register
);
2450 if (cmd
->scan_begin_arg
& CR_EDGE
)
2451 start_stop_select
|= AI_START_Edge
;
2452 /* AI_START_Polarity==1 is falling edge */
2453 if (cmd
->scan_begin_arg
& CR_INVERT
)
2454 start_stop_select
|= AI_START_Polarity
;
2455 if (cmd
->scan_begin_src
!= cmd
->convert_src
||
2456 (cmd
->scan_begin_arg
& ~CR_EDGE
) !=
2457 (cmd
->convert_arg
& ~CR_EDGE
))
2458 start_stop_select
|= AI_START_Sync
;
2459 start_stop_select
|=
2460 AI_START_Select(1 + CR_CHAN(cmd
->scan_begin_arg
));
2461 devpriv
->stc_writew(dev
, start_stop_select
,
2462 AI_START_STOP_Select_Register
);
2466 switch (cmd
->convert_src
) {
2469 if (cmd
->convert_arg
== 0 || cmd
->convert_src
== TRIG_NOW
)
2472 timer
= ni_ns_to_timer(dev
, cmd
->convert_arg
,
2473 TRIG_ROUND_NEAREST
);
2474 devpriv
->stc_writew(dev
, 1, AI_SI2_Load_A_Register
); /* 0,0 does not work. */
2475 devpriv
->stc_writew(dev
, timer
, AI_SI2_Load_B_Register
);
2477 /* AI_SI2_Reload_Mode = alternate */
2478 /* AI_SI2_Initial_Load_Source = A */
2479 mode2
&= ~AI_SI2_Initial_Load_Source
;
2480 mode2
|= AI_SI2_Reload_Mode
;
2481 devpriv
->stc_writew(dev
, mode2
, AI_Mode_2_Register
);
2484 devpriv
->stc_writew(dev
, AI_SI2_Load
, AI_Command_1_Register
);
2486 mode2
|= AI_SI2_Reload_Mode
; /* alternate */
2487 mode2
|= AI_SI2_Initial_Load_Source
; /* B */
2489 devpriv
->stc_writew(dev
, mode2
, AI_Mode_2_Register
);
2492 mode1
|= AI_CONVERT_Source_Select(1 + cmd
->convert_arg
);
2493 if ((cmd
->convert_arg
& CR_INVERT
) == 0)
2494 mode1
|= AI_CONVERT_Source_Polarity
;
2495 devpriv
->stc_writew(dev
, mode1
, AI_Mode_1_Register
);
2497 mode2
|= AI_Start_Stop_Gate_Enable
| AI_SC_Gate_Enable
;
2498 devpriv
->stc_writew(dev
, mode2
, AI_Mode_2_Register
);
2505 /* interrupt on FIFO, errors, SC_TC */
2506 interrupt_a_enable
|= AI_Error_Interrupt_Enable
|
2507 AI_SC_TC_Interrupt_Enable
;
2510 interrupt_a_enable
|= AI_FIFO_Interrupt_Enable
;
2513 if (cmd
->flags
& TRIG_WAKE_EOS
2514 || (devpriv
->ai_cmd2
& AI_End_On_End_Of_Scan
)) {
2515 /* wake on end-of-scan */
2516 devpriv
->aimode
= AIMODE_SCAN
;
2518 devpriv
->aimode
= AIMODE_HALF_FULL
;
2521 switch (devpriv
->aimode
) {
2522 case AIMODE_HALF_FULL
:
2523 /*generate FIFO interrupts and DMA requests on half-full */
2525 devpriv
->stc_writew(dev
, AI_FIFO_Mode_HF_to_E
,
2526 AI_Mode_3_Register
);
2528 devpriv
->stc_writew(dev
, AI_FIFO_Mode_HF
,
2529 AI_Mode_3_Register
);
2533 /*generate FIFO interrupts on non-empty */
2534 devpriv
->stc_writew(dev
, AI_FIFO_Mode_NE
,
2535 AI_Mode_3_Register
);
2539 devpriv
->stc_writew(dev
, AI_FIFO_Mode_NE
,
2540 AI_Mode_3_Register
);
2542 devpriv
->stc_writew(dev
, AI_FIFO_Mode_HF
,
2543 AI_Mode_3_Register
);
2545 interrupt_a_enable
|= AI_STOP_Interrupt_Enable
;
2551 devpriv
->stc_writew(dev
, AI_Error_Interrupt_Ack
| AI_STOP_Interrupt_Ack
| AI_START_Interrupt_Ack
| AI_START2_Interrupt_Ack
| AI_START1_Interrupt_Ack
| AI_SC_TC_Interrupt_Ack
| AI_SC_TC_Error_Confirm
, Interrupt_A_Ack_Register
); /* clear interrupts */
2553 ni_set_bits(dev
, Interrupt_A_Enable_Register
,
2554 interrupt_a_enable
, 1);
2556 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2557 devpriv
->int_a_enable_reg
);
2559 /* interrupt on nothing */
2560 ni_set_bits(dev
, Interrupt_A_Enable_Register
, ~0, 0);
2562 /* XXX start polling if necessary */
2563 MDPRINTK("interrupting on nothing\n");
2566 /* end configuration */
2567 devpriv
->stc_writew(dev
, AI_Configuration_End
, Joint_Reset_Register
);
2569 switch (cmd
->scan_begin_src
) {
2571 devpriv
->stc_writew(dev
,
2572 AI_SI2_Arm
| AI_SI_Arm
| AI_DIV_Arm
| AI_SC_Arm
,
2573 AI_Command_1_Register
);
2576 /* XXX AI_SI_Arm? */
2577 devpriv
->stc_writew(dev
,
2578 AI_SI2_Arm
| AI_SI_Arm
| AI_DIV_Arm
| AI_SC_Arm
,
2579 AI_Command_1_Register
);
2585 int retval
= ni_ai_setup_MITE_dma(dev
);
2589 /* mite_dump_regs(devpriv->mite); */
2592 switch (cmd
->start_src
) {
2594 /* AI_START1_Pulse */
2595 devpriv
->stc_writew(dev
, AI_START1_Pulse
| devpriv
->ai_cmd2
,
2596 AI_Command_2_Register
);
2597 s
->async
->inttrig
= NULL
;
2600 s
->async
->inttrig
= NULL
;
2603 s
->async
->inttrig
= &ni_ai_inttrig
;
2607 MDPRINTK("exit ni_ai_cmd\n");
2612 static int ni_ai_inttrig(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
2613 unsigned int trignum
)
2618 devpriv
->stc_writew(dev
, AI_START1_Pulse
| devpriv
->ai_cmd2
,
2619 AI_Command_2_Register
);
2620 s
->async
->inttrig
= NULL
;
2625 static int ni_ai_config_analog_trig(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
2626 struct comedi_insn
*insn
, unsigned int *data
);
2628 static int ni_ai_insn_config(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
2629 struct comedi_insn
*insn
, unsigned int *data
)
2635 case INSN_CONFIG_ANALOG_TRIG
:
2636 return ni_ai_config_analog_trig(dev
, s
, insn
, data
);
2637 case INSN_CONFIG_ALT_SOURCE
:
2638 if (boardtype
.reg_type
& ni_reg_m_series_mask
) {
2639 if (data
[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask
|
2640 MSeries_AI_Bypass_Cal_Sel_Neg_Mask
|
2641 MSeries_AI_Bypass_Mode_Mux_Mask
|
2642 MSeries_AO_Bypass_AO_Cal_Sel_Mask
)) {
2645 devpriv
->ai_calib_source
= data
[1];
2646 } else if (boardtype
.reg_type
== ni_reg_6143
) {
2647 unsigned int calib_source
;
2649 calib_source
= data
[1] & 0xf;
2651 if (calib_source
> 0xF)
2654 devpriv
->ai_calib_source
= calib_source
;
2655 ni_writew(calib_source
, Calibration_Channel_6143
);
2657 unsigned int calib_source
;
2658 unsigned int calib_source_adjust
;
2660 calib_source
= data
[1] & 0xf;
2661 calib_source_adjust
= (data
[1] >> 4) & 0xff;
2663 if (calib_source
>= 8)
2665 devpriv
->ai_calib_source
= calib_source
;
2666 if (boardtype
.reg_type
== ni_reg_611x
) {
2667 ni_writeb(calib_source_adjust
,
2668 Cal_Gain_Select_611x
);
2679 static int ni_ai_config_analog_trig(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
2680 struct comedi_insn
*insn
, unsigned int *data
)
2682 unsigned int a
, b
, modebits
;
2686 * data[2] is analog line
2687 * data[3] is set level
2688 * data[4] is reset level */
2689 if (!boardtype
.has_analog_trig
)
2691 if ((data
[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN
) {
2692 data
[1] &= (COMEDI_EV_SCAN_BEGIN
| 0xffff);
2695 if (data
[2] >= boardtype
.n_adchan
) {
2696 data
[2] = boardtype
.n_adchan
- 1;
2699 if (data
[3] > 255) { /* a */
2703 if (data
[4] > 255) { /* b */
2714 * high mode 00 00 01 10
2715 * low mode 00 00 10 01
2717 * hysteresis low mode 10 00 00 01
2718 * hysteresis high mode 01 00 00 10
2719 * middle mode 10 01 01 10
2724 modebits
= data
[1] & 0xff;
2725 if (modebits
& 0xf0) {
2726 /* two level mode */
2732 ((data
[1] & 0xf) << 4) | ((data
[1] & 0xf0) >>
2735 devpriv
->atrig_low
= a
;
2736 devpriv
->atrig_high
= b
;
2738 case 0x81: /* low hysteresis mode */
2739 devpriv
->atrig_mode
= 6;
2741 case 0x42: /* high hysteresis mode */
2742 devpriv
->atrig_mode
= 3;
2744 case 0x96: /* middle window mode */
2745 devpriv
->atrig_mode
= 2;
2752 /* one level mode */
2758 case 0x06: /* high window mode */
2759 devpriv
->atrig_high
= a
;
2760 devpriv
->atrig_mode
= 0;
2762 case 0x09: /* low window mode */
2763 devpriv
->atrig_low
= a
;
2764 devpriv
->atrig_mode
= 1;
2776 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2777 static void ni_ao_munge(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
2778 void *data
, unsigned int num_bytes
, unsigned int chan_index
)
2780 struct comedi_async
*async
= s
->async
;
2783 unsigned int offset
;
2784 unsigned int length
= num_bytes
/ sizeof(short);
2785 short *array
= data
;
2787 offset
= 1 << (boardtype
.aobits
- 1);
2788 for (i
= 0; i
< length
; i
++) {
2789 range
= CR_RANGE(async
->cmd
.chanlist
[chan_index
]);
2790 if (boardtype
.ao_unipolar
== 0 || (range
& 1) == 0)
2793 array
[i
] = cpu_to_le16(array
[i
]);
2796 chan_index
%= async
->cmd
.chanlist_len
;
2800 static int ni_m_series_ao_config_chanlist(struct comedi_device
*dev
,
2801 struct comedi_subdevice
*s
, unsigned int chanspec
[], unsigned int n_chans
,
2811 for (i
= 0; i
< boardtype
.n_aochan
; ++i
) {
2812 devpriv
->ao_conf
[i
] &= ~MSeries_AO_Update_Timed_Bit
;
2813 ni_writeb(devpriv
->ao_conf
[i
], M_Offset_AO_Config_Bank(i
));
2814 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i
));
2817 for (i
= 0; i
< n_chans
; i
++) {
2818 const struct comedi_krange
*krange
;
2819 chan
= CR_CHAN(chanspec
[i
]);
2820 range
= CR_RANGE(chanspec
[i
]);
2821 krange
= s
->range_table
->range
+ range
;
2824 switch (krange
->max
- krange
->min
) {
2826 conf
|= MSeries_AO_DAC_Reference_10V_Internal_Bits
;
2827 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan
));
2830 conf
|= MSeries_AO_DAC_Reference_5V_Internal_Bits
;
2831 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan
));
2834 conf
|= MSeries_AO_DAC_Reference_10V_Internal_Bits
;
2835 ni_writeb(MSeries_Attenuate_x5_Bit
,
2836 M_Offset_AO_Reference_Attenuation(chan
));
2839 conf
|= MSeries_AO_DAC_Reference_5V_Internal_Bits
;
2840 ni_writeb(MSeries_Attenuate_x5_Bit
,
2841 M_Offset_AO_Reference_Attenuation(chan
));
2844 printk("%s: bug! unhandled ao reference voltage\n",
2848 switch (krange
->max
+ krange
->min
) {
2850 conf
|= MSeries_AO_DAC_Offset_0V_Bits
;
2853 conf
|= MSeries_AO_DAC_Offset_5V_Bits
;
2856 printk("%s: bug! unhandled ao offset voltage\n",
2861 conf
|= MSeries_AO_Update_Timed_Bit
;
2862 ni_writeb(conf
, M_Offset_AO_Config_Bank(chan
));
2863 devpriv
->ao_conf
[chan
] = conf
;
2864 ni_writeb(i
, M_Offset_AO_Waveform_Order(chan
));
2869 static int ni_old_ao_config_chanlist(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
2870 unsigned int chanspec
[], unsigned int n_chans
)
2878 for (i
= 0; i
< n_chans
; i
++) {
2879 chan
= CR_CHAN(chanspec
[i
]);
2880 range
= CR_RANGE(chanspec
[i
]);
2881 conf
= AO_Channel(chan
);
2883 if (boardtype
.ao_unipolar
) {
2884 if ((range
& 1) == 0) {
2886 invert
= (1 << (boardtype
.aobits
- 1));
2894 invert
= (1 << (boardtype
.aobits
- 1));
2897 /* not all boards can deglitch, but this shouldn't hurt */
2898 if (chanspec
[i
] & CR_DEGLITCH
)
2899 conf
|= AO_Deglitch
;
2901 /* analog reference */
2902 /* AREF_OTHER connects AO ground to AI ground, i think */
2903 conf
|= (CR_AREF(chanspec
[i
]) ==
2904 AREF_OTHER
) ? AO_Ground_Ref
: 0;
2906 ni_writew(conf
, AO_Configuration
);
2907 devpriv
->ao_conf
[chan
] = conf
;
2912 static int ni_ao_config_chanlist(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
2913 unsigned int chanspec
[], unsigned int n_chans
, int timed
)
2915 if (boardtype
.reg_type
& ni_reg_m_series_mask
)
2916 return ni_m_series_ao_config_chanlist(dev
, s
, chanspec
, n_chans
,
2919 return ni_old_ao_config_chanlist(dev
, s
, chanspec
, n_chans
);
2921 static int ni_ao_insn_read(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
2922 struct comedi_insn
*insn
, unsigned int *data
)
2924 data
[0] = devpriv
->ao
[CR_CHAN(insn
->chanspec
)];
2929 static int ni_ao_insn_write(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
2930 struct comedi_insn
*insn
, unsigned int *data
)
2932 unsigned int chan
= CR_CHAN(insn
->chanspec
);
2933 unsigned int invert
;
2935 invert
= ni_ao_config_chanlist(dev
, s
, &insn
->chanspec
, 1, 0);
2937 devpriv
->ao
[chan
] = data
[0];
2939 if (boardtype
.reg_type
& ni_reg_m_series_mask
) {
2940 ni_writew(data
[0], M_Offset_DAC_Direct_Data(chan
));
2942 ni_writew(data
[0] ^ invert
,
2943 (chan
) ? DAC1_Direct_Data
: DAC0_Direct_Data
);
2948 static int ni_ao_insn_write_671x(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
2949 struct comedi_insn
*insn
, unsigned int *data
)
2951 unsigned int chan
= CR_CHAN(insn
->chanspec
);
2952 unsigned int invert
;
2954 ao_win_out(1 << chan
, AO_Immediate_671x
);
2955 invert
= 1 << (boardtype
.aobits
- 1);
2957 ni_ao_config_chanlist(dev
, s
, &insn
->chanspec
, 1, 0);
2959 devpriv
->ao
[chan
] = data
[0];
2960 ao_win_out(data
[0] ^ invert
, DACx_Direct_Data_671x(chan
));
2965 static int ni_ao_insn_config(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
2966 struct comedi_insn
*insn
, unsigned int *data
)
2969 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE
:
2973 data
[2] = 1 + boardtype
.ao_fifo_depth
* sizeof(short);
2974 if (devpriv
->mite
) data
[2] += devpriv
->mite
->fifo_size
;
2991 static int ni_ao_inttrig(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
2992 unsigned int trignum
)
2995 int interrupt_b_bits
;
2997 static const int timeout
= 1000;
3002 /* Null trig at beginning prevent ao start trigger from executing more than
3003 once per command (and doing things like trying to allocate the ao dma channel
3005 s
->async
->inttrig
= NULL
;
3007 ni_set_bits(dev
, Interrupt_B_Enable_Register
,
3008 AO_FIFO_Interrupt_Enable
| AO_Error_Interrupt_Enable
, 0);
3009 interrupt_b_bits
= AO_Error_Interrupt_Enable
;
3011 devpriv
->stc_writew(dev
, 1, DAC_FIFO_Clear
);
3012 if (boardtype
.reg_type
& ni_reg_6xxx_mask
)
3013 ni_ao_win_outl(dev
, 0x6, AO_FIFO_Offset_Load_611x
);
3014 ret
= ni_ao_setup_MITE_dma(dev
);
3017 ret
= ni_ao_wait_for_dma_load(dev
);
3021 ret
= ni_ao_prep_fifo(dev
, s
);
3025 interrupt_b_bits
|= AO_FIFO_Interrupt_Enable
;
3028 devpriv
->stc_writew(dev
, devpriv
->ao_mode3
| AO_Not_An_UPDATE
,
3029 AO_Mode_3_Register
);
3030 devpriv
->stc_writew(dev
, devpriv
->ao_mode3
, AO_Mode_3_Register
);
3031 /* wait for DACs to be loaded */
3032 for (i
= 0; i
< timeout
; i
++) {
3034 if ((devpriv
->stc_readw(dev
,
3035 Joint_Status_2_Register
) &
3036 AO_TMRDACWRs_In_Progress_St
) == 0)
3041 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3044 /* stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3045 devpriv
->stc_writew(dev
, AO_Error_Interrupt_Ack
,
3046 Interrupt_B_Ack_Register
);
3048 ni_set_bits(dev
, Interrupt_B_Enable_Register
, interrupt_b_bits
, 1);
3050 devpriv
->stc_writew(dev
,
3052 ao_cmd1
| AO_UI_Arm
| AO_UC_Arm
| AO_BC_Arm
|
3053 AO_DAC1_Update_Mode
| AO_DAC0_Update_Mode
,
3054 AO_Command_1_Register
);
3056 devpriv
->stc_writew(dev
, devpriv
->ao_cmd2
| AO_START1_Pulse
,
3057 AO_Command_2_Register
);
3062 static int ni_ao_cmd(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
3064 const struct comedi_cmd
*cmd
= &s
->async
->cmd
;
3069 if (dev
->irq
== 0) {
3070 comedi_error(dev
, "cannot run command without an irq");
3074 devpriv
->stc_writew(dev
, AO_Configuration_Start
, Joint_Reset_Register
);
3076 devpriv
->stc_writew(dev
, AO_Disarm
, AO_Command_1_Register
);
3078 if (boardtype
.reg_type
& ni_reg_6xxx_mask
) {
3079 ao_win_out(CLEAR_WG
, AO_Misc_611x
);
3082 for (i
= 0; i
< cmd
->chanlist_len
; i
++) {
3085 chan
= CR_CHAN(cmd
->chanlist
[i
]);
3087 ao_win_out(chan
, AO_Waveform_Generation_611x
);
3089 ao_win_out(bits
, AO_Timed_611x
);
3092 ni_ao_config_chanlist(dev
, s
, cmd
->chanlist
, cmd
->chanlist_len
, 1);
3094 if (cmd
->stop_src
== TRIG_NONE
) {
3095 devpriv
->ao_mode1
|= AO_Continuous
;
3096 devpriv
->ao_mode1
&= ~AO_Trigger_Once
;
3098 devpriv
->ao_mode1
&= ~AO_Continuous
;
3099 devpriv
->ao_mode1
|= AO_Trigger_Once
;
3101 devpriv
->stc_writew(dev
, devpriv
->ao_mode1
, AO_Mode_1_Register
);
3102 switch (cmd
->start_src
) {
3105 devpriv
->ao_trigger_select
&=
3106 ~(AO_START1_Polarity
| AO_START1_Select(-1));
3107 devpriv
->ao_trigger_select
|= AO_START1_Edge
| AO_START1_Sync
;
3108 devpriv
->stc_writew(dev
, devpriv
->ao_trigger_select
,
3109 AO_Trigger_Select_Register
);
3112 devpriv
->ao_trigger_select
= AO_START1_Select(CR_CHAN(cmd
->start_arg
)+1);
3113 if (cmd
->start_arg
& CR_INVERT
)
3114 devpriv
->ao_trigger_select
|= AO_START1_Polarity
; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
3115 if (cmd
->start_arg
& CR_EDGE
)
3116 devpriv
->ao_trigger_select
|= AO_START1_Edge
; /* 0=edge detection disabled, 1=enabled */
3117 devpriv
->stc_writew(dev
, devpriv
->ao_trigger_select
, AO_Trigger_Select_Register
);
3123 devpriv
->ao_mode3
&= ~AO_Trigger_Length
;
3124 devpriv
->stc_writew(dev
, devpriv
->ao_mode3
, AO_Mode_3_Register
);
3126 devpriv
->stc_writew(dev
, devpriv
->ao_mode1
, AO_Mode_1_Register
);
3127 devpriv
->ao_mode2
&= ~AO_BC_Initial_Load_Source
;
3128 devpriv
->stc_writew(dev
, devpriv
->ao_mode2
, AO_Mode_2_Register
);
3129 if (cmd
->stop_src
== TRIG_NONE
) {
3130 devpriv
->stc_writel(dev
, 0xffffff, AO_BC_Load_A_Register
);
3132 devpriv
->stc_writel(dev
, 0, AO_BC_Load_A_Register
);
3134 devpriv
->stc_writew(dev
, AO_BC_Load
, AO_Command_1_Register
);
3135 devpriv
->ao_mode2
&= ~AO_UC_Initial_Load_Source
;
3136 devpriv
->stc_writew(dev
, devpriv
->ao_mode2
, AO_Mode_2_Register
);
3137 switch (cmd
->stop_src
) {
3139 if (boardtype
.reg_type
& ni_reg_m_series_mask
)
3141 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
3142 devpriv
->stc_writel(dev
, cmd
->stop_arg
- 1, AO_UC_Load_A_Register
);
3143 devpriv
->stc_writew(dev
, AO_UC_Load
, AO_Command_1_Register
);
3146 devpriv
->stc_writel(dev
, cmd
->stop_arg
, AO_UC_Load_A_Register
);
3147 devpriv
->stc_writew(dev
, AO_UC_Load
, AO_Command_1_Register
);
3148 devpriv
->stc_writel(dev
, cmd
->stop_arg
- 1,
3149 AO_UC_Load_A_Register
);
3153 devpriv
->stc_writel(dev
, 0xffffff, AO_UC_Load_A_Register
);
3154 devpriv
->stc_writew(dev
, AO_UC_Load
, AO_Command_1_Register
);
3155 devpriv
->stc_writel(dev
, 0xffffff, AO_UC_Load_A_Register
);
3158 devpriv
->stc_writel(dev
, 0, AO_UC_Load_A_Register
);
3159 devpriv
->stc_writew(dev
, AO_UC_Load
, AO_Command_1_Register
);
3160 devpriv
->stc_writel(dev
, cmd
->stop_arg
, AO_UC_Load_A_Register
);
3163 devpriv
->ao_mode1
&=
3164 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity
|
3165 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity
);
3166 switch (cmd
->scan_begin_src
) {
3168 devpriv
->ao_cmd2
&= ~AO_BC_Gate_Enable
;
3170 ni_ns_to_timer(dev
, cmd
->scan_begin_arg
,
3171 TRIG_ROUND_NEAREST
);
3172 devpriv
->stc_writel(dev
, 1, AO_UI_Load_A_Register
);
3173 devpriv
->stc_writew(dev
, AO_UI_Load
, AO_Command_1_Register
);
3174 devpriv
->stc_writel(dev
, trigvar
, AO_UI_Load_A_Register
);
3177 devpriv
->ao_mode1
|=
3178 AO_UPDATE_Source_Select(cmd
->scan_begin_arg
);
3179 if (cmd
->scan_begin_arg
& CR_INVERT
)
3180 devpriv
->ao_mode1
|= AO_UPDATE_Source_Polarity
;
3181 devpriv
->ao_cmd2
|= AO_BC_Gate_Enable
;
3187 devpriv
->stc_writew(dev
, devpriv
->ao_cmd2
, AO_Command_2_Register
);
3188 devpriv
->stc_writew(dev
, devpriv
->ao_mode1
, AO_Mode_1_Register
);
3189 devpriv
->ao_mode2
&=
3190 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source
);
3191 devpriv
->stc_writew(dev
, devpriv
->ao_mode2
, AO_Mode_2_Register
);
3193 if (cmd
->scan_end_arg
> 1) {
3194 devpriv
->ao_mode1
|= AO_Multiple_Channels
;
3195 devpriv
->stc_writew(dev
,
3196 AO_Number_Of_Channels(cmd
->scan_end_arg
-
3198 AO_UPDATE_Output_Select
3199 (AO_Update_Output_High_Z
),
3200 AO_Output_Control_Register
);
3203 devpriv
->ao_mode1
&= ~AO_Multiple_Channels
;
3204 bits
= AO_UPDATE_Output_Select(AO_Update_Output_High_Z
);
3205 if (boardtype
.reg_type
& (ni_reg_m_series_mask
| ni_reg_6xxx_mask
)) {
3206 bits
|= AO_Number_Of_Channels(0);
3208 bits
|= AO_Number_Of_Channels(CR_CHAN(cmd
->
3211 devpriv
->stc_writew(dev
, bits
,
3212 AO_Output_Control_Register
);
3214 devpriv
->stc_writew(dev
, devpriv
->ao_mode1
, AO_Mode_1_Register
);
3216 devpriv
->stc_writew(dev
, AO_DAC0_Update_Mode
| AO_DAC1_Update_Mode
,
3217 AO_Command_1_Register
);
3219 devpriv
->ao_mode3
|= AO_Stop_On_Overrun_Error
;
3220 devpriv
->stc_writew(dev
, devpriv
->ao_mode3
, AO_Mode_3_Register
);
3222 devpriv
->ao_mode2
&= ~AO_FIFO_Mode_Mask
;
3224 devpriv
->ao_mode2
|= AO_FIFO_Mode_HF_to_F
;
3226 devpriv
->ao_mode2
|= AO_FIFO_Mode_HF
;
3228 devpriv
->ao_mode2
&= ~AO_FIFO_Retransmit_Enable
;
3229 devpriv
->stc_writew(dev
, devpriv
->ao_mode2
, AO_Mode_2_Register
);
3231 bits
= AO_BC_Source_Select
| AO_UPDATE_Pulse_Width
|
3232 AO_TMRDACWR_Pulse_Width
;
3233 if (boardtype
.ao_fifo_depth
)
3234 bits
|= AO_FIFO_Enable
;
3236 bits
|= AO_DMA_PIO_Control
;
3238 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3239 verified with bus analyzer. */
3240 if (boardtype
.reg_type
& ni_reg_m_series_mask
)
3241 bits
|= AO_Number_Of_DAC_Packages
;
3243 devpriv
->stc_writew(dev
, bits
, AO_Personal_Register
);
3244 /* enable sending of ao dma requests */
3245 devpriv
->stc_writew(dev
, AO_AOFREQ_Enable
, AO_Start_Select_Register
);
3247 devpriv
->stc_writew(dev
, AO_Configuration_End
, Joint_Reset_Register
);
3249 if (cmd
->stop_src
== TRIG_COUNT
) {
3250 devpriv
->stc_writew(dev
, AO_BC_TC_Interrupt_Ack
,
3251 Interrupt_B_Ack_Register
);
3252 ni_set_bits(dev
, Interrupt_B_Enable_Register
,
3253 AO_BC_TC_Interrupt_Enable
, 1);
3256 s
->async
->inttrig
= &ni_ao_inttrig
;
3261 static int ni_ao_cmdtest(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
3262 struct comedi_cmd
*cmd
)
3267 /* step 1: make sure trigger sources are trivially valid */
3269 if ((cmd
->flags
& CMDF_WRITE
) == 0) {
3270 cmd
->flags
|= CMDF_WRITE
;
3273 tmp
= cmd
->start_src
;
3274 cmd
->start_src
&= TRIG_INT
| TRIG_EXT
;
3275 if (!cmd
->start_src
|| tmp
!= cmd
->start_src
)
3278 tmp
= cmd
->scan_begin_src
;
3279 cmd
->scan_begin_src
&= TRIG_TIMER
| TRIG_EXT
;
3280 if (!cmd
->scan_begin_src
|| tmp
!= cmd
->scan_begin_src
)
3283 tmp
= cmd
->convert_src
;
3284 cmd
->convert_src
&= TRIG_NOW
;
3285 if (!cmd
->convert_src
|| tmp
!= cmd
->convert_src
)
3288 tmp
= cmd
->scan_end_src
;
3289 cmd
->scan_end_src
&= TRIG_COUNT
;
3290 if (!cmd
->scan_end_src
|| tmp
!= cmd
->scan_end_src
)
3293 tmp
= cmd
->stop_src
;
3294 cmd
->stop_src
&= TRIG_COUNT
| TRIG_NONE
;
3295 if (!cmd
->stop_src
|| tmp
!= cmd
->stop_src
)
3301 /* step 2: make sure trigger sources are unique and mutually compatible */
3303 if (cmd
->stop_src
!= TRIG_COUNT
&& cmd
->stop_src
!= TRIG_NONE
)
3309 /* step 3: make sure arguments are trivially compatible */
3311 if (cmd
->start_src
== TRIG_EXT
) {
3312 /* external trigger */
3313 unsigned int tmp
= CR_CHAN(cmd
->start_arg
);
3317 tmp
|= (cmd
->start_arg
& (CR_INVERT
| CR_EDGE
));
3318 if (cmd
->start_arg
!= tmp
) {
3319 cmd
->start_arg
= tmp
;
3323 if (cmd
->start_arg
!= 0) {
3324 /* true for both TRIG_NOW and TRIG_INT */
3329 if (cmd
->scan_begin_src
== TRIG_TIMER
) {
3330 if (cmd
->scan_begin_arg
< boardtype
.ao_speed
) {
3331 cmd
->scan_begin_arg
= boardtype
.ao_speed
;
3334 if (cmd
->scan_begin_arg
> devpriv
->clock_ns
* 0xffffff) { /* XXX check */
3335 cmd
->scan_begin_arg
= devpriv
->clock_ns
* 0xffffff;
3339 if (cmd
->convert_arg
!= 0) {
3340 cmd
->convert_arg
= 0;
3343 if (cmd
->scan_end_arg
!= cmd
->chanlist_len
) {
3344 cmd
->scan_end_arg
= cmd
->chanlist_len
;
3347 if (cmd
->stop_src
== TRIG_COUNT
) { /* XXX check */
3348 if (cmd
->stop_arg
> 0x00ffffff) {
3349 cmd
->stop_arg
= 0x00ffffff;
3354 if (cmd
->stop_arg
!= 0) {
3363 /* step 4: fix up any arguments */
3364 if (cmd
->scan_begin_src
== TRIG_TIMER
) {
3365 tmp
= cmd
->scan_begin_arg
;
3366 cmd
->scan_begin_arg
=
3367 ni_timer_to_ns(dev
, ni_ns_to_timer(dev
,
3368 cmd
->scan_begin_arg
,
3369 cmd
->flags
& TRIG_ROUND_MASK
));
3370 if (tmp
!= cmd
->scan_begin_arg
)
3376 /* step 5: fix up chanlist */
3384 static int ni_ao_reset(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
3386 /* devpriv->ao0p=0x0000; */
3387 /* ni_writew(devpriv->ao0p,AO_Configuration); */
3389 /* devpriv->ao1p=AO_Channel(1); */
3390 /* ni_writew(devpriv->ao1p,AO_Configuration); */
3392 ni_release_ao_mite_channel(dev
);
3394 devpriv
->stc_writew(dev
, AO_Configuration_Start
, Joint_Reset_Register
);
3395 devpriv
->stc_writew(dev
, AO_Disarm
, AO_Command_1_Register
);
3396 ni_set_bits(dev
, Interrupt_B_Enable_Register
, ~0, 0);
3397 devpriv
->stc_writew(dev
, AO_BC_Source_Select
, AO_Personal_Register
);
3398 devpriv
->stc_writew(dev
, 0x3f98, Interrupt_B_Ack_Register
);
3399 devpriv
->stc_writew(dev
, AO_BC_Source_Select
| AO_UPDATE_Pulse_Width
|
3400 AO_TMRDACWR_Pulse_Width
, AO_Personal_Register
);
3401 devpriv
->stc_writew(dev
, 0, AO_Output_Control_Register
);
3402 devpriv
->stc_writew(dev
, 0, AO_Start_Select_Register
);
3403 devpriv
->ao_cmd1
= 0;
3404 devpriv
->stc_writew(dev
, devpriv
->ao_cmd1
, AO_Command_1_Register
);
3405 devpriv
->ao_cmd2
= 0;
3406 devpriv
->stc_writew(dev
, devpriv
->ao_cmd2
, AO_Command_2_Register
);
3407 devpriv
->ao_mode1
= 0;
3408 devpriv
->stc_writew(dev
, devpriv
->ao_mode1
, AO_Mode_1_Register
);
3409 devpriv
->ao_mode2
= 0;
3410 devpriv
->stc_writew(dev
, devpriv
->ao_mode2
, AO_Mode_2_Register
);
3411 if (boardtype
.reg_type
& ni_reg_m_series_mask
)
3412 devpriv
->ao_mode3
= AO_Last_Gate_Disable
;
3414 devpriv
->ao_mode3
= 0;
3415 devpriv
->stc_writew(dev
, devpriv
->ao_mode3
, AO_Mode_3_Register
);
3416 devpriv
->ao_trigger_select
= 0;
3417 devpriv
->stc_writew(dev
, devpriv
->ao_trigger_select
,
3418 AO_Trigger_Select_Register
);
3419 if (boardtype
.reg_type
& ni_reg_6xxx_mask
) {
3420 unsigned immediate_bits
= 0;
3422 for (i
= 0; i
< s
->n_chan
; ++i
)
3424 immediate_bits
|= 1 << i
;
3426 ao_win_out(immediate_bits
, AO_Immediate_671x
);
3427 ao_win_out(CLEAR_WG
, AO_Misc_611x
);
3429 devpriv
->stc_writew(dev
, AO_Configuration_End
, Joint_Reset_Register
);
3436 static int ni_dio_insn_config(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
3437 struct comedi_insn
*insn
, unsigned int *data
)
3440 printk("ni_dio_insn_config() chan=%d io=%d\n",
3441 CR_CHAN(insn
->chanspec
), data
[0]);
3444 case INSN_CONFIG_DIO_OUTPUT
:
3445 s
->io_bits
|= 1 << CR_CHAN(insn
->chanspec
);
3447 case INSN_CONFIG_DIO_INPUT
:
3448 s
->io_bits
&= ~(1 << CR_CHAN(insn
->chanspec
));
3450 case INSN_CONFIG_DIO_QUERY
:
3452 (s
->io_bits
& (1 << CR_CHAN(insn
->
3453 chanspec
))) ? COMEDI_OUTPUT
:
3461 devpriv
->dio_control
&= ~DIO_Pins_Dir_Mask
;
3462 devpriv
->dio_control
|= DIO_Pins_Dir(s
->io_bits
);
3463 devpriv
->stc_writew(dev
, devpriv
->dio_control
, DIO_Control_Register
);
3468 static int ni_dio_insn_bits(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
3469 struct comedi_insn
*insn
, unsigned int *data
)
3472 printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data
[0], data
[1]);
3477 /* Perform check to make sure we're not using the
3478 serial part of the dio */
3479 if ((data
[0] & (DIO_SDIN
| DIO_SDOUT
))
3480 && devpriv
->serial_interval_ns
)
3483 s
->state
&= ~data
[0];
3484 s
->state
|= (data
[0] & data
[1]);
3485 devpriv
->dio_output
&= ~DIO_Parallel_Data_Mask
;
3486 devpriv
->dio_output
|= DIO_Parallel_Data_Out(s
->state
);
3487 devpriv
->stc_writew(dev
, devpriv
->dio_output
,
3488 DIO_Output_Register
);
3490 data
[1] = devpriv
->stc_readw(dev
, DIO_Parallel_Input_Register
);
3495 static int ni_m_series_dio_insn_config(struct comedi_device
*dev
,
3496 struct comedi_subdevice
*s
, struct comedi_insn
*insn
, unsigned int *data
)
3499 printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3500 CR_CHAN(insn
->chanspec
), data
[0]);
3503 case INSN_CONFIG_DIO_OUTPUT
:
3504 s
->io_bits
|= 1 << CR_CHAN(insn
->chanspec
);
3506 case INSN_CONFIG_DIO_INPUT
:
3507 s
->io_bits
&= ~(1 << CR_CHAN(insn
->chanspec
));
3509 case INSN_CONFIG_DIO_QUERY
:
3511 (s
->io_bits
& (1 << CR_CHAN(insn
->
3512 chanspec
))) ? COMEDI_OUTPUT
:
3520 ni_writel(s
->io_bits
, M_Offset_DIO_Direction
);
3525 static int ni_m_series_dio_insn_bits(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
3526 struct comedi_insn
*insn
, unsigned int *data
)
3529 printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data
[0],
3535 s
->state
&= ~data
[0];
3536 s
->state
|= (data
[0] & data
[1]);
3537 ni_writel(s
->state
, M_Offset_Static_Digital_Output
);
3539 data
[1] = ni_readl(M_Offset_Static_Digital_Input
);
3544 static int ni_cdio_cmdtest(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
3545 struct comedi_cmd
*cmd
)
3552 /* step 1: make sure trigger sources are trivially valid */
3554 tmp
= cmd
->start_src
;
3556 cmd
->start_src
&= sources
;
3557 if (!cmd
->start_src
|| tmp
!= cmd
->start_src
)
3560 tmp
= cmd
->scan_begin_src
;
3561 cmd
->scan_begin_src
&= TRIG_EXT
;
3562 if (!cmd
->scan_begin_src
|| tmp
!= cmd
->scan_begin_src
)
3565 tmp
= cmd
->convert_src
;
3566 cmd
->convert_src
&= TRIG_NOW
;
3567 if (!cmd
->convert_src
|| tmp
!= cmd
->convert_src
)
3570 tmp
= cmd
->scan_end_src
;
3571 cmd
->scan_end_src
&= TRIG_COUNT
;
3572 if (!cmd
->scan_end_src
|| tmp
!= cmd
->scan_end_src
)
3575 tmp
= cmd
->stop_src
;
3576 cmd
->stop_src
&= TRIG_NONE
;
3577 if (!cmd
->stop_src
|| tmp
!= cmd
->stop_src
)
3583 /* step 2: make sure trigger sources are unique... */
3585 if (cmd
->start_src
!= TRIG_INT
)
3587 if (cmd
->scan_begin_src
!= TRIG_EXT
)
3589 if (cmd
->convert_src
!= TRIG_NOW
)
3591 if (cmd
->stop_src
!= TRIG_NONE
)
3593 /* ... and mutually compatible */
3598 /* step 3: make sure arguments are trivially compatible */
3599 if (cmd
->start_src
== TRIG_INT
) {
3600 if (cmd
->start_arg
!= 0) {
3605 if (cmd
->scan_begin_src
== TRIG_EXT
) {
3606 tmp
= cmd
->scan_begin_arg
;
3607 tmp
&= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask
, 0, 0,
3609 if (tmp
!= cmd
->scan_begin_arg
) {
3613 if (cmd
->convert_src
== TRIG_NOW
) {
3614 if (cmd
->convert_arg
) {
3615 cmd
->convert_arg
= 0;
3620 if (cmd
->scan_end_arg
!= cmd
->chanlist_len
) {
3621 cmd
->scan_end_arg
= cmd
->chanlist_len
;
3625 if (cmd
->stop_src
== TRIG_NONE
) {
3626 if (cmd
->stop_arg
!= 0) {
3635 /* step 4: fix up any arguments */
3640 /* step 5: check chanlist */
3642 for (i
= 0; i
< cmd
->chanlist_len
; ++i
) {
3643 if (cmd
->chanlist
[i
] != i
)
3653 static int ni_cdio_cmd(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
3655 const struct comedi_cmd
*cmd
= &s
->async
->cmd
;
3656 unsigned cdo_mode_bits
= CDO_FIFO_Mode_Bit
| CDO_Halt_On_Error_Bit
;
3659 ni_writel(CDO_Reset_Bit
, M_Offset_CDIO_Command
);
3660 switch (cmd
->scan_begin_src
) {
3664 scan_begin_arg
) & CDO_Sample_Source_Select_Mask
;
3670 if (cmd
->scan_begin_arg
& CR_INVERT
)
3671 cdo_mode_bits
|= CDO_Polarity_Bit
;
3672 ni_writel(cdo_mode_bits
, M_Offset_CDO_Mode
);
3674 ni_writel(s
->state
, M_Offset_CDO_FIFO_Data
);
3675 ni_writel(CDO_SW_Update_Bit
, M_Offset_CDIO_Command
);
3676 ni_writel(s
->io_bits
, M_Offset_CDO_Mask_Enable
);
3679 "attempted to run digital output command with no lines configured as outputs");
3682 retval
= ni_request_cdo_mite_channel(dev
);
3686 s
->async
->inttrig
= &ni_cdo_inttrig
;
3690 static int ni_cdo_inttrig(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
3691 unsigned int trignum
)
3694 unsigned long flags
;
3698 const unsigned timeout
= 100;
3700 s
->async
->inttrig
= NULL
;
3702 /* read alloc the entire buffer */
3703 comedi_buf_read_alloc(s
->async
, s
->async
->prealloc_bufsz
);
3706 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
3707 if (devpriv
->cdo_mite_chan
) {
3708 mite_prep_dma(devpriv
->cdo_mite_chan
, 32, 32);
3709 mite_dma_arm(devpriv
->cdo_mite_chan
);
3711 comedi_error(dev
, "BUG: no cdo mite channel?");
3714 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
3719 * XXX not sure what interrupt C group does
3720 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3721 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3723 for (i
= 0; i
< timeout
; ++i
) {
3724 if (ni_readl(M_Offset_CDIO_Status
) & CDO_FIFO_Full_Bit
)
3729 comedi_error(dev
, "dma failed to fill cdo fifo!");
3730 ni_cdio_cancel(dev
, s
);
3733 ni_writel(CDO_Arm_Bit
| CDO_Error_Interrupt_Enable_Set_Bit
|
3734 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit
, M_Offset_CDIO_Command
);
3738 static int ni_cdio_cancel(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
3740 ni_writel(CDO_Disarm_Bit
| CDO_Error_Interrupt_Enable_Clear_Bit
|
3741 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit
|
3742 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit
,
3743 M_Offset_CDIO_Command
);
3745 * XXX not sure what interrupt C group does ni_writeb(0,
3746 * M_Offset_Interrupt_C_Enable);
3748 ni_writel(0, M_Offset_CDO_Mask_Enable
);
3749 ni_release_cdo_mite_channel(dev
);
3753 static void handle_cdio_interrupt(struct comedi_device
*dev
)
3755 unsigned cdio_status
;
3756 struct comedi_subdevice
*s
= dev
->subdevices
+ NI_DIO_SUBDEV
;
3758 unsigned long flags
;
3761 if ((boardtype
.reg_type
& ni_reg_m_series_mask
) == 0) {
3765 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
3766 if (devpriv
->cdo_mite_chan
) {
3767 unsigned cdo_mite_status
=
3768 mite_get_status(devpriv
->cdo_mite_chan
);
3769 if (cdo_mite_status
& CHSR_LINKC
) {
3771 devpriv
->mite
->mite_io_addr
+
3772 MITE_CHOR(devpriv
->cdo_mite_chan
->channel
));
3774 mite_sync_output_dma(devpriv
->cdo_mite_chan
, s
->async
);
3776 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
3779 cdio_status
= ni_readl(M_Offset_CDIO_Status
);
3780 if (cdio_status
& (CDO_Overrun_Bit
| CDO_Underflow_Bit
)) {
3781 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3782 ni_writel(CDO_Error_Interrupt_Confirm_Bit
, M_Offset_CDIO_Command
); /* XXX just guessing this is needed and does something useful */
3783 s
->async
->events
|= COMEDI_CB_OVERFLOW
;
3785 if (cdio_status
& CDO_FIFO_Empty_Bit
) {
3786 /* printk("cdio fifo empty\n"); */
3787 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit
,
3788 M_Offset_CDIO_Command
);
3789 /* s->async->events |= COMEDI_CB_EOA; */
3794 static int ni_serial_insn_config(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
3795 struct comedi_insn
*insn
, unsigned int *data
)
3798 unsigned char byte_out
, byte_in
= 0;
3804 case INSN_CONFIG_SERIAL_CLOCK
:
3807 printk("SPI serial clock Config cd\n", data
[1]);
3809 devpriv
->serial_hw_mode
= 1;
3810 devpriv
->dio_control
|= DIO_HW_Serial_Enable
;
3812 if (data
[1] == SERIAL_DISABLED
) {
3813 devpriv
->serial_hw_mode
= 0;
3814 devpriv
->dio_control
&= ~(DIO_HW_Serial_Enable
|
3815 DIO_Software_Serial_Control
);
3816 data
[1] = SERIAL_DISABLED
;
3817 devpriv
->serial_interval_ns
= data
[1];
3818 } else if (data
[1] <= SERIAL_600NS
) {
3819 /* Warning: this clock speed is too fast to reliably
3821 devpriv
->dio_control
&= ~DIO_HW_Serial_Timebase
;
3822 devpriv
->clock_and_fout
|= Slow_Internal_Timebase
;
3823 devpriv
->clock_and_fout
&= ~DIO_Serial_Out_Divide_By_2
;
3824 data
[1] = SERIAL_600NS
;
3825 devpriv
->serial_interval_ns
= data
[1];
3826 } else if (data
[1] <= SERIAL_1_2US
) {
3827 devpriv
->dio_control
&= ~DIO_HW_Serial_Timebase
;
3828 devpriv
->clock_and_fout
|= Slow_Internal_Timebase
|
3829 DIO_Serial_Out_Divide_By_2
;
3830 data
[1] = SERIAL_1_2US
;
3831 devpriv
->serial_interval_ns
= data
[1];
3832 } else if (data
[1] <= SERIAL_10US
) {
3833 devpriv
->dio_control
|= DIO_HW_Serial_Timebase
;
3834 devpriv
->clock_and_fout
|= Slow_Internal_Timebase
|
3835 DIO_Serial_Out_Divide_By_2
;
3836 /* Note: DIO_Serial_Out_Divide_By_2 only affects
3837 600ns/1.2us. If you turn divide_by_2 off with the
3838 slow clock, you will still get 10us, except then
3839 all your delays are wrong. */
3840 data
[1] = SERIAL_10US
;
3841 devpriv
->serial_interval_ns
= data
[1];
3843 devpriv
->dio_control
&= ~(DIO_HW_Serial_Enable
|
3844 DIO_Software_Serial_Control
);
3845 devpriv
->serial_hw_mode
= 0;
3846 data
[1] = (data
[1] / 1000) * 1000;
3847 devpriv
->serial_interval_ns
= data
[1];
3850 devpriv
->stc_writew(dev
, devpriv
->dio_control
,
3851 DIO_Control_Register
);
3852 devpriv
->stc_writew(dev
, devpriv
->clock_and_fout
,
3853 Clock_and_FOUT_Register
);
3858 case INSN_CONFIG_BIDIRECTIONAL_DATA
:
3860 if (devpriv
->serial_interval_ns
== 0) {
3864 byte_out
= data
[1] & 0xFF;
3866 if (devpriv
->serial_hw_mode
) {
3867 err
= ni_serial_hw_readwrite8(dev
, s
, byte_out
,
3869 } else if (devpriv
->serial_interval_ns
> 0) {
3870 err
= ni_serial_sw_readwrite8(dev
, s
, byte_out
,
3873 printk("ni_serial_insn_config: serial disabled!\n");
3878 data
[1] = byte_in
& 0xFF;
3888 static int ni_serial_hw_readwrite8(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
3889 unsigned char data_out
, unsigned char *data_in
)
3891 unsigned int status1
;
3892 int err
= 0, count
= 20;
3895 printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out
);
3898 devpriv
->dio_output
&= ~DIO_Serial_Data_Mask
;
3899 devpriv
->dio_output
|= DIO_Serial_Data_Out(data_out
);
3900 devpriv
->stc_writew(dev
, devpriv
->dio_output
, DIO_Output_Register
);
3902 status1
= devpriv
->stc_readw(dev
, Joint_Status_1_Register
);
3903 if (status1
& DIO_Serial_IO_In_Progress_St
) {
3908 devpriv
->dio_control
|= DIO_HW_Serial_Start
;
3909 devpriv
->stc_writew(dev
, devpriv
->dio_control
, DIO_Control_Register
);
3910 devpriv
->dio_control
&= ~DIO_HW_Serial_Start
;
3912 /* Wait until STC says we're done, but don't loop infinitely. */
3914 devpriv
->stc_readw(dev
,
3915 Joint_Status_1_Register
)) &
3916 DIO_Serial_IO_In_Progress_St
) {
3917 /* Delay one bit per loop */
3918 udelay((devpriv
->serial_interval_ns
+ 999) / 1000);
3921 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3927 /* Delay for last bit. This delay is absolutely necessary, because
3928 DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3929 udelay((devpriv
->serial_interval_ns
+ 999) / 1000);
3931 if (data_in
!= NULL
) {
3932 *data_in
= devpriv
->stc_readw(dev
, DIO_Serial_Input_Register
);
3934 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in
);
3939 devpriv
->stc_writew(dev
, devpriv
->dio_control
, DIO_Control_Register
);
3944 static int ni_serial_sw_readwrite8(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
3945 unsigned char data_out
, unsigned char *data_in
)
3947 unsigned char mask
, input
= 0;
3950 printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out
);
3953 /* Wait for one bit before transfer */
3954 udelay((devpriv
->serial_interval_ns
+ 999) / 1000);
3956 for (mask
= 0x80; mask
; mask
>>= 1) {
3957 /* Output current bit; note that we cannot touch s->state
3958 because it is a per-subdevice field, and serial is
3959 a separate subdevice from DIO. */
3960 devpriv
->dio_output
&= ~DIO_SDOUT
;
3961 if (data_out
& mask
) {
3962 devpriv
->dio_output
|= DIO_SDOUT
;
3964 devpriv
->stc_writew(dev
, devpriv
->dio_output
,
3965 DIO_Output_Register
);
3967 /* Assert SDCLK (active low, inverted), wait for half of
3968 the delay, deassert SDCLK, and wait for the other half. */
3969 devpriv
->dio_control
|= DIO_Software_Serial_Control
;
3970 devpriv
->stc_writew(dev
, devpriv
->dio_control
,
3971 DIO_Control_Register
);
3973 udelay((devpriv
->serial_interval_ns
+ 999) / 2000);
3975 devpriv
->dio_control
&= ~DIO_Software_Serial_Control
;
3976 devpriv
->stc_writew(dev
, devpriv
->dio_control
,
3977 DIO_Control_Register
);
3979 udelay((devpriv
->serial_interval_ns
+ 999) / 2000);
3981 /* Input current bit */
3982 if (devpriv
->stc_readw(dev
,
3983 DIO_Parallel_Input_Register
) & DIO_SDIN
) {
3984 /* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
3989 printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input
);
3997 static void mio_common_detach(struct comedi_device
*dev
)
4000 if (devpriv
->counter_dev
) {
4001 ni_gpct_device_destroy(devpriv
->counter_dev
);
4004 if (dev
->subdevices
&& boardtype
.has_8255
)
4005 subdev_8255_cleanup(dev
, dev
->subdevices
+ NI_8255_DIO_SUBDEV
);
4008 static void init_ao_67xx(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
4012 for (i
= 0; i
< s
->n_chan
; i
++)
4014 ni_ao_win_outw(dev
, AO_Channel(i
) | 0x0,
4015 AO_Configuration_2_67xx
);
4017 ao_win_out(0x0, AO_Later_Single_Point_Updates
);
4020 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg
)
4022 unsigned stc_register
;
4024 case NITIO_G0_Autoincrement_Reg
:
4025 stc_register
= G_Autoincrement_Register(0);
4027 case NITIO_G1_Autoincrement_Reg
:
4028 stc_register
= G_Autoincrement_Register(1);
4030 case NITIO_G0_Command_Reg
:
4031 stc_register
= G_Command_Register(0);
4033 case NITIO_G1_Command_Reg
:
4034 stc_register
= G_Command_Register(1);
4036 case NITIO_G0_HW_Save_Reg
:
4037 stc_register
= G_HW_Save_Register(0);
4039 case NITIO_G1_HW_Save_Reg
:
4040 stc_register
= G_HW_Save_Register(1);
4042 case NITIO_G0_SW_Save_Reg
:
4043 stc_register
= G_Save_Register(0);
4045 case NITIO_G1_SW_Save_Reg
:
4046 stc_register
= G_Save_Register(1);
4048 case NITIO_G0_Mode_Reg
:
4049 stc_register
= G_Mode_Register(0);
4051 case NITIO_G1_Mode_Reg
:
4052 stc_register
= G_Mode_Register(1);
4054 case NITIO_G0_LoadA_Reg
:
4055 stc_register
= G_Load_A_Register(0);
4057 case NITIO_G1_LoadA_Reg
:
4058 stc_register
= G_Load_A_Register(1);
4060 case NITIO_G0_LoadB_Reg
:
4061 stc_register
= G_Load_B_Register(0);
4063 case NITIO_G1_LoadB_Reg
:
4064 stc_register
= G_Load_B_Register(1);
4066 case NITIO_G0_Input_Select_Reg
:
4067 stc_register
= G_Input_Select_Register(0);
4069 case NITIO_G1_Input_Select_Reg
:
4070 stc_register
= G_Input_Select_Register(1);
4072 case NITIO_G01_Status_Reg
:
4073 stc_register
= G_Status_Register
;
4075 case NITIO_G01_Joint_Reset_Reg
:
4076 stc_register
= Joint_Reset_Register
;
4078 case NITIO_G01_Joint_Status1_Reg
:
4079 stc_register
= Joint_Status_1_Register
;
4081 case NITIO_G01_Joint_Status2_Reg
:
4082 stc_register
= Joint_Status_2_Register
;
4084 case NITIO_G0_Interrupt_Acknowledge_Reg
:
4085 stc_register
= Interrupt_A_Ack_Register
;
4087 case NITIO_G1_Interrupt_Acknowledge_Reg
:
4088 stc_register
= Interrupt_B_Ack_Register
;
4090 case NITIO_G0_Status_Reg
:
4091 stc_register
= AI_Status_1_Register
;
4093 case NITIO_G1_Status_Reg
:
4094 stc_register
= AO_Status_1_Register
;
4096 case NITIO_G0_Interrupt_Enable_Reg
:
4097 stc_register
= Interrupt_A_Enable_Register
;
4099 case NITIO_G1_Interrupt_Enable_Reg
:
4100 stc_register
= Interrupt_B_Enable_Register
;
4103 printk("%s: unhandled register 0x%x in switch.\n",
4109 return stc_register
;
4112 static void ni_gpct_write_register(struct ni_gpct
*counter
, unsigned bits
,
4113 enum ni_gpct_register reg
)
4115 struct comedi_device
*dev
= counter
->counter_dev
->dev
;
4116 unsigned stc_register
;
4117 /* bits in the join reset register which are relevant to counters */
4118 static const unsigned gpct_joint_reset_mask
= G0_Reset
| G1_Reset
;
4119 static const unsigned gpct_interrupt_a_enable_mask
=
4120 G0_Gate_Interrupt_Enable
| G0_TC_Interrupt_Enable
;
4121 static const unsigned gpct_interrupt_b_enable_mask
=
4122 G1_Gate_Interrupt_Enable
| G1_TC_Interrupt_Enable
;
4125 /* m-series-only registers */
4126 case NITIO_G0_Counting_Mode_Reg
:
4127 ni_writew(bits
, M_Offset_G0_Counting_Mode
);
4129 case NITIO_G1_Counting_Mode_Reg
:
4130 ni_writew(bits
, M_Offset_G1_Counting_Mode
);
4132 case NITIO_G0_Second_Gate_Reg
:
4133 ni_writew(bits
, M_Offset_G0_Second_Gate
);
4135 case NITIO_G1_Second_Gate_Reg
:
4136 ni_writew(bits
, M_Offset_G1_Second_Gate
);
4138 case NITIO_G0_DMA_Config_Reg
:
4139 ni_writew(bits
, M_Offset_G0_DMA_Config
);
4141 case NITIO_G1_DMA_Config_Reg
:
4142 ni_writew(bits
, M_Offset_G1_DMA_Config
);
4144 case NITIO_G0_ABZ_Reg
:
4145 ni_writew(bits
, M_Offset_G0_MSeries_ABZ
);
4147 case NITIO_G1_ABZ_Reg
:
4148 ni_writew(bits
, M_Offset_G1_MSeries_ABZ
);
4151 /* 32 bit registers */
4152 case NITIO_G0_LoadA_Reg
:
4153 case NITIO_G1_LoadA_Reg
:
4154 case NITIO_G0_LoadB_Reg
:
4155 case NITIO_G1_LoadB_Reg
:
4156 stc_register
= ni_gpct_to_stc_register(reg
);
4157 devpriv
->stc_writel(dev
, bits
, stc_register
);
4160 /* 16 bit registers */
4161 case NITIO_G0_Interrupt_Enable_Reg
:
4162 BUG_ON(bits
& ~gpct_interrupt_a_enable_mask
);
4163 ni_set_bitfield(dev
, Interrupt_A_Enable_Register
,
4164 gpct_interrupt_a_enable_mask
, bits
);
4166 case NITIO_G1_Interrupt_Enable_Reg
:
4167 BUG_ON(bits
& ~gpct_interrupt_b_enable_mask
);
4168 ni_set_bitfield(dev
, Interrupt_B_Enable_Register
,
4169 gpct_interrupt_b_enable_mask
, bits
);
4171 case NITIO_G01_Joint_Reset_Reg
:
4172 BUG_ON(bits
& ~gpct_joint_reset_mask
);
4175 stc_register
= ni_gpct_to_stc_register(reg
);
4176 devpriv
->stc_writew(dev
, bits
, stc_register
);
4180 static unsigned ni_gpct_read_register(struct ni_gpct
*counter
,
4181 enum ni_gpct_register reg
)
4183 struct comedi_device
*dev
= counter
->counter_dev
->dev
;
4184 unsigned stc_register
;
4186 /* m-series only registers */
4187 case NITIO_G0_DMA_Status_Reg
:
4188 return ni_readw(M_Offset_G0_DMA_Status
);
4190 case NITIO_G1_DMA_Status_Reg
:
4191 return ni_readw(M_Offset_G1_DMA_Status
);
4194 /* 32 bit registers */
4195 case NITIO_G0_HW_Save_Reg
:
4196 case NITIO_G1_HW_Save_Reg
:
4197 case NITIO_G0_SW_Save_Reg
:
4198 case NITIO_G1_SW_Save_Reg
:
4199 stc_register
= ni_gpct_to_stc_register(reg
);
4200 return devpriv
->stc_readl(dev
, stc_register
);
4203 /* 16 bit registers */
4205 stc_register
= ni_gpct_to_stc_register(reg
);
4206 return devpriv
->stc_readw(dev
, stc_register
);
4212 static int ni_freq_out_insn_read(struct comedi_device
*dev
,
4213 struct comedi_subdevice
*s
, struct comedi_insn
*insn
, unsigned int *data
)
4215 data
[0] = devpriv
->clock_and_fout
& FOUT_Divider_mask
;
4219 static int ni_freq_out_insn_write(struct comedi_device
*dev
,
4220 struct comedi_subdevice
*s
, struct comedi_insn
*insn
, unsigned int *data
)
4222 devpriv
->clock_and_fout
&= ~FOUT_Enable
;
4223 devpriv
->stc_writew(dev
, devpriv
->clock_and_fout
,
4224 Clock_and_FOUT_Register
);
4225 devpriv
->clock_and_fout
&= ~FOUT_Divider_mask
;
4226 devpriv
->clock_and_fout
|= FOUT_Divider(data
[0]);
4227 devpriv
->clock_and_fout
|= FOUT_Enable
;
4228 devpriv
->stc_writew(dev
, devpriv
->clock_and_fout
,
4229 Clock_and_FOUT_Register
);
4233 static int ni_set_freq_out_clock(struct comedi_device
*dev
, unsigned int clock_source
)
4235 switch (clock_source
) {
4236 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC
:
4237 devpriv
->clock_and_fout
&= ~FOUT_Timebase_Select
;
4239 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC
:
4240 devpriv
->clock_and_fout
|= FOUT_Timebase_Select
;
4245 devpriv
->stc_writew(dev
, devpriv
->clock_and_fout
,
4246 Clock_and_FOUT_Register
);
4250 static void ni_get_freq_out_clock(struct comedi_device
*dev
, unsigned int *clock_source
,
4251 unsigned int *clock_period_ns
)
4253 if (devpriv
->clock_and_fout
& FOUT_Timebase_Select
) {
4254 *clock_source
= NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC
;
4255 *clock_period_ns
= TIMEBASE_2_NS
;
4257 *clock_source
= NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC
;
4258 *clock_period_ns
= TIMEBASE_1_NS
* 2;
4262 static int ni_freq_out_insn_config(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
4263 struct comedi_insn
*insn
, unsigned int *data
)
4266 case INSN_CONFIG_SET_CLOCK_SRC
:
4267 return ni_set_freq_out_clock(dev
, data
[1]);
4269 case INSN_CONFIG_GET_CLOCK_SRC
:
4270 ni_get_freq_out_clock(dev
, &data
[1], &data
[2]);
4278 static int ni_alloc_private(struct comedi_device
*dev
)
4282 ret
= alloc_private(dev
, sizeof(struct ni_private
));
4286 spin_lock_init(&devpriv
->window_lock
);
4287 spin_lock_init(&devpriv
->soft_reg_copy_lock
);
4288 spin_lock_init(&devpriv
->mite_channel_lock
);
4293 static int ni_E_init(struct comedi_device
*dev
, struct comedi_devconfig
*it
)
4295 struct comedi_subdevice
*s
;
4297 enum ni_gpct_variant counter_variant
;
4299 if (boardtype
.n_aochan
> MAX_N_AO_CHAN
) {
4300 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
4304 if (alloc_subdevices(dev
, NI_NUM_SUBDEVICES
) < 0)
4307 /* analog input subdevice */
4309 s
= dev
->subdevices
+ NI_AI_SUBDEV
;
4310 dev
->read_subdev
= s
;
4311 if (boardtype
.n_adchan
) {
4312 s
->type
= COMEDI_SUBD_AI
;
4314 SDF_READABLE
| SDF_DIFF
| SDF_DITHER
| SDF_CMD_READ
;
4315 if (boardtype
.reg_type
!= ni_reg_611x
)
4316 s
->subdev_flags
|= SDF_GROUND
| SDF_COMMON
| SDF_OTHER
;
4317 if (boardtype
.adbits
> 16)
4318 s
->subdev_flags
|= SDF_LSAMPL
;
4319 if (boardtype
.reg_type
& ni_reg_m_series_mask
)
4320 s
->subdev_flags
|= SDF_SOFT_CALIBRATED
;
4321 s
->n_chan
= boardtype
.n_adchan
;
4322 s
->len_chanlist
= 512;
4323 s
->maxdata
= (1 << boardtype
.adbits
) - 1;
4324 s
->range_table
= ni_range_lkup
[boardtype
.gainlkup
];
4325 s
->insn_read
= &ni_ai_insn_read
;
4326 s
->insn_config
= &ni_ai_insn_config
;
4327 s
->do_cmdtest
= &ni_ai_cmdtest
;
4328 s
->do_cmd
= &ni_ai_cmd
;
4329 s
->cancel
= &ni_ai_reset
;
4330 s
->poll
= &ni_ai_poll
;
4331 s
->munge
= &ni_ai_munge
;
4333 s
->async_dma_dir
= DMA_FROM_DEVICE
;
4336 s
->type
= COMEDI_SUBD_UNUSED
;
4339 /* analog output subdevice */
4341 s
= dev
->subdevices
+ NI_AO_SUBDEV
;
4342 if (boardtype
.n_aochan
) {
4343 s
->type
= COMEDI_SUBD_AO
;
4344 s
->subdev_flags
= SDF_WRITABLE
| SDF_DEGLITCH
| SDF_GROUND
;
4345 if (boardtype
.reg_type
& ni_reg_m_series_mask
)
4346 s
->subdev_flags
|= SDF_SOFT_CALIBRATED
;
4347 s
->n_chan
= boardtype
.n_aochan
;
4348 s
->maxdata
= (1 << boardtype
.aobits
) - 1;
4349 s
->range_table
= boardtype
.ao_range_table
;
4350 s
->insn_read
= &ni_ao_insn_read
;
4351 if (boardtype
.reg_type
& ni_reg_6xxx_mask
) {
4352 s
->insn_write
= &ni_ao_insn_write_671x
;
4354 s
->insn_write
= &ni_ao_insn_write
;
4356 s
->insn_config
= &ni_ao_insn_config
;
4358 if (boardtype
.n_aochan
) {
4359 s
->async_dma_dir
= DMA_TO_DEVICE
;
4361 if (boardtype
.ao_fifo_depth
) {
4363 dev
->write_subdev
= s
;
4364 s
->subdev_flags
|= SDF_CMD_WRITE
;
4365 s
->do_cmd
= &ni_ao_cmd
;
4366 s
->do_cmdtest
= &ni_ao_cmdtest
;
4367 s
->len_chanlist
= boardtype
.n_aochan
;
4368 if ((boardtype
.reg_type
& ni_reg_m_series_mask
) == 0)
4369 s
->munge
= ni_ao_munge
;
4371 s
->cancel
= &ni_ao_reset
;
4373 s
->type
= COMEDI_SUBD_UNUSED
;
4375 if ((boardtype
.reg_type
& ni_reg_67xx_mask
))
4376 init_ao_67xx(dev
, s
);
4378 /* digital i/o subdevice */
4380 s
= dev
->subdevices
+ NI_DIO_SUBDEV
;
4381 s
->type
= COMEDI_SUBD_DIO
;
4382 s
->subdev_flags
= SDF_WRITABLE
| SDF_READABLE
;
4384 s
->io_bits
= 0; /* all bits input */
4385 s
->range_table
= &range_digital
;
4386 s
->n_chan
= boardtype
.num_p0_dio_channels
;
4387 if (boardtype
.reg_type
& ni_reg_m_series_mask
) {
4389 SDF_LSAMPL
| SDF_CMD_WRITE
/* | SDF_CMD_READ */ ;
4390 s
->insn_bits
= &ni_m_series_dio_insn_bits
;
4391 s
->insn_config
= &ni_m_series_dio_insn_config
;
4392 s
->do_cmd
= &ni_cdio_cmd
;
4393 s
->do_cmdtest
= &ni_cdio_cmdtest
;
4394 s
->cancel
= &ni_cdio_cancel
;
4395 s
->async_dma_dir
= DMA_BIDIRECTIONAL
;
4396 s
->len_chanlist
= s
->n_chan
;
4398 ni_writel(CDO_Reset_Bit
| CDI_Reset_Bit
, M_Offset_CDIO_Command
);
4399 ni_writel(s
->io_bits
, M_Offset_DIO_Direction
);
4401 s
->insn_bits
= &ni_dio_insn_bits
;
4402 s
->insn_config
= &ni_dio_insn_config
;
4403 devpriv
->dio_control
= DIO_Pins_Dir(s
->io_bits
);
4404 ni_writew(devpriv
->dio_control
, DIO_Control_Register
);
4408 s
= dev
->subdevices
+ NI_8255_DIO_SUBDEV
;
4409 if (boardtype
.has_8255
) {
4410 subdev_8255_init(dev
, s
, ni_8255_callback
, (unsigned long)dev
);
4412 s
->type
= COMEDI_SUBD_UNUSED
;
4415 /* formerly general purpose counter/timer device, but no longer used */
4416 s
= dev
->subdevices
+ NI_UNUSED_SUBDEV
;
4417 s
->type
= COMEDI_SUBD_UNUSED
;
4419 /* calibration subdevice -- ai and ao */
4420 s
= dev
->subdevices
+ NI_CALIBRATION_SUBDEV
;
4421 s
->type
= COMEDI_SUBD_CALIB
;
4422 if (boardtype
.reg_type
& ni_reg_m_series_mask
) {
4423 /* internal PWM analog output used for AI nonlinearity calibration */
4424 s
->subdev_flags
= SDF_INTERNAL
;
4425 s
->insn_config
= &ni_m_series_pwm_config
;
4428 ni_writel(0x0, M_Offset_Cal_PWM
);
4429 } else if (boardtype
.reg_type
== ni_reg_6143
) {
4430 /* internal PWM analog output used for AI nonlinearity calibration */
4431 s
->subdev_flags
= SDF_INTERNAL
;
4432 s
->insn_config
= &ni_6143_pwm_config
;
4436 s
->subdev_flags
= SDF_WRITABLE
| SDF_INTERNAL
;
4437 s
->insn_read
= &ni_calib_insn_read
;
4438 s
->insn_write
= &ni_calib_insn_write
;
4439 caldac_setup(dev
, s
);
4443 s
= dev
->subdevices
+ NI_EEPROM_SUBDEV
;
4444 s
->type
= COMEDI_SUBD_MEMORY
;
4445 s
->subdev_flags
= SDF_READABLE
| SDF_INTERNAL
;
4447 if (boardtype
.reg_type
& ni_reg_m_series_mask
) {
4448 s
->n_chan
= M_SERIES_EEPROM_SIZE
;
4449 s
->insn_read
= &ni_m_series_eeprom_insn_read
;
4452 s
->insn_read
= &ni_eeprom_insn_read
;
4456 s
= dev
->subdevices
+ NI_PFI_DIO_SUBDEV
;
4457 s
->type
= COMEDI_SUBD_DIO
;
4458 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
| SDF_INTERNAL
;
4459 if (boardtype
.reg_type
& ni_reg_m_series_mask
) {
4462 ni_writew(s
->state
, M_Offset_PFI_DO
);
4463 for (i
= 0; i
< NUM_PFI_OUTPUT_SELECT_REGS
; ++i
) {
4464 ni_writew(devpriv
->pfi_output_select_reg
[i
],
4465 M_Offset_PFI_Output_Select(i
+ 1));
4471 if (boardtype
.reg_type
& ni_reg_m_series_mask
) {
4472 s
->insn_bits
= &ni_pfi_insn_bits
;
4474 s
->insn_config
= &ni_pfi_insn_config
;
4475 ni_set_bits(dev
, IO_Bidirection_Pin_Register
, ~0, 0);
4477 /* cs5529 calibration adc */
4478 s
= dev
->subdevices
+ NI_CS5529_CALIBRATION_SUBDEV
;
4479 if (boardtype
.reg_type
& ni_reg_67xx_mask
) {
4480 s
->type
= COMEDI_SUBD_AI
;
4481 s
->subdev_flags
= SDF_READABLE
| SDF_DIFF
| SDF_INTERNAL
;
4482 /* one channel for each analog output channel */
4483 s
->n_chan
= boardtype
.n_aochan
;
4484 s
->maxdata
= (1 << 16) - 1;
4485 s
->range_table
= &range_unknown
; /* XXX */
4486 s
->insn_read
= cs5529_ai_insn_read
;
4487 s
->insn_config
= NULL
;
4490 s
->type
= COMEDI_SUBD_UNUSED
;
4494 s
= dev
->subdevices
+ NI_SERIAL_SUBDEV
;
4495 s
->type
= COMEDI_SUBD_SERIAL
;
4496 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
| SDF_INTERNAL
;
4499 s
->insn_config
= ni_serial_insn_config
;
4500 devpriv
->serial_interval_ns
= 0;
4501 devpriv
->serial_hw_mode
= 0;
4504 s
= dev
->subdevices
+ NI_RTSI_SUBDEV
;
4505 s
->type
= COMEDI_SUBD_DIO
;
4506 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
| SDF_INTERNAL
;
4509 s
->insn_bits
= ni_rtsi_insn_bits
;
4510 s
->insn_config
= ni_rtsi_insn_config
;
4513 if (boardtype
.reg_type
& ni_reg_m_series_mask
) {
4514 counter_variant
= ni_gpct_variant_m_series
;
4516 counter_variant
= ni_gpct_variant_e_series
;
4518 devpriv
->counter_dev
= ni_gpct_device_construct(dev
,
4519 &ni_gpct_write_register
, &ni_gpct_read_register
,
4520 counter_variant
, NUM_GPCT
);
4521 /* General purpose counters */
4522 for (j
= 0; j
< NUM_GPCT
; ++j
) {
4523 s
= dev
->subdevices
+ NI_GPCT_SUBDEV(j
);
4524 s
->type
= COMEDI_SUBD_COUNTER
;
4526 SDF_READABLE
| SDF_WRITABLE
| SDF_LSAMPL
| SDF_CMD_READ
4527 /* | SDF_CMD_WRITE */ ;
4529 if (boardtype
.reg_type
& ni_reg_m_series_mask
)
4530 s
->maxdata
= 0xffffffff;
4532 s
->maxdata
= 0xffffff;
4533 s
->insn_read
= &ni_gpct_insn_read
;
4534 s
->insn_write
= &ni_gpct_insn_write
;
4535 s
->insn_config
= &ni_gpct_insn_config
;
4536 s
->do_cmd
= &ni_gpct_cmd
;
4537 s
->len_chanlist
= 1;
4538 s
->do_cmdtest
= &ni_gpct_cmdtest
;
4539 s
->cancel
= &ni_gpct_cancel
;
4540 s
->async_dma_dir
= DMA_BIDIRECTIONAL
;
4541 s
->private = &devpriv
->counter_dev
->counters
[j
];
4543 devpriv
->counter_dev
->counters
[j
].chip_index
= 0;
4544 devpriv
->counter_dev
->counters
[j
].counter_index
= j
;
4545 ni_tio_init_counter(&devpriv
->counter_dev
->counters
[j
]);
4548 /* Frequency output */
4549 s
= dev
->subdevices
+ NI_FREQ_OUT_SUBDEV
;
4550 s
->type
= COMEDI_SUBD_COUNTER
;
4551 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
;
4554 s
->insn_read
= &ni_freq_out_insn_read
;
4555 s
->insn_write
= &ni_freq_out_insn_write
;
4556 s
->insn_config
= &ni_freq_out_insn_config
;
4558 /* ai configuration */
4559 ni_ai_reset(dev
, dev
->subdevices
+ NI_AI_SUBDEV
);
4560 if ((boardtype
.reg_type
& ni_reg_6xxx_mask
) == 0) {
4561 /* BEAM is this needed for PCI-6143 ?? */
4562 devpriv
->clock_and_fout
=
4563 Slow_Internal_Time_Divide_By_2
|
4564 Slow_Internal_Timebase
|
4565 Clock_To_Board_Divide_By_2
|
4567 AI_Output_Divide_By_2
| AO_Output_Divide_By_2
;
4569 devpriv
->clock_and_fout
=
4570 Slow_Internal_Time_Divide_By_2
|
4571 Slow_Internal_Timebase
|
4572 Clock_To_Board_Divide_By_2
| Clock_To_Board
;
4574 devpriv
->stc_writew(dev
, devpriv
->clock_and_fout
,
4575 Clock_and_FOUT_Register
);
4577 /* analog output configuration */
4578 ni_ao_reset(dev
, dev
->subdevices
+ NI_AO_SUBDEV
);
4581 devpriv
->stc_writew(dev
,
4582 (IRQ_POLARITY
? Interrupt_Output_Polarity
: 0) |
4583 (Interrupt_Output_On_3_Pins
& 0) | Interrupt_A_Enable
|
4584 Interrupt_B_Enable
|
4585 Interrupt_A_Output_Select(interrupt_pin(dev
->
4587 Interrupt_B_Output_Select(interrupt_pin(dev
->irq
)),
4588 Interrupt_Control_Register
);
4592 ni_writeb(devpriv
->ai_ao_select_reg
, AI_AO_Select
);
4593 ni_writeb(devpriv
->g0_g1_select_reg
, G0_G1_Select
);
4595 if (boardtype
.reg_type
& ni_reg_6xxx_mask
) {
4596 ni_writeb(0, Magic_611x
);
4597 } else if (boardtype
.reg_type
& ni_reg_m_series_mask
) {
4599 for (channel
= 0; channel
< boardtype
.n_aochan
; ++channel
) {
4600 ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel
));
4602 M_Offset_AO_Reference_Attenuation(channel
));
4604 ni_writeb(0x0, M_Offset_AO_Calibration
);
4611 static int ni_8255_callback(int dir
, int port
, int data
, unsigned long arg
)
4613 struct comedi_device
*dev
= (struct comedi_device
*) arg
;
4616 ni_writeb(data
, Port_A
+ 2 * port
);
4619 return ni_readb(Port_A
+ 2 * port
);
4624 presents the EEPROM as a subdevice
4627 static int ni_eeprom_insn_read(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
4628 struct comedi_insn
*insn
, unsigned int *data
)
4630 data
[0] = ni_read_eeprom(dev
, CR_CHAN(insn
->chanspec
));
4636 reads bytes out of eeprom
4639 static int ni_read_eeprom(struct comedi_device
*dev
, int addr
)
4644 bitstring
= 0x0300 | ((addr
& 0x100) << 3) | (addr
& 0xff);
4645 ni_writeb(0x04, Serial_Command
);
4646 for (bit
= 0x8000; bit
; bit
>>= 1) {
4647 ni_writeb(0x04 | ((bit
& bitstring
) ? 0x02 : 0),
4649 ni_writeb(0x05 | ((bit
& bitstring
) ? 0x02 : 0),
4653 for (bit
= 0x80; bit
; bit
>>= 1) {
4654 ni_writeb(0x04, Serial_Command
);
4655 ni_writeb(0x05, Serial_Command
);
4656 bitstring
|= ((ni_readb(XXX_Status
) & PROMOUT
) ? bit
: 0);
4658 ni_writeb(0x00, Serial_Command
);
4663 static int ni_m_series_eeprom_insn_read(struct comedi_device
*dev
,
4664 struct comedi_subdevice
*s
, struct comedi_insn
*insn
, unsigned int *data
)
4666 data
[0] = devpriv
->eeprom_buffer
[CR_CHAN(insn
->chanspec
)];
4671 static int ni_get_pwm_config(struct comedi_device
*dev
, unsigned int *data
)
4673 data
[1] = devpriv
->pwm_up_count
* devpriv
->clock_ns
;
4674 data
[2] = devpriv
->pwm_down_count
* devpriv
->clock_ns
;
4678 static int ni_m_series_pwm_config(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
4679 struct comedi_insn
*insn
, unsigned int *data
)
4681 unsigned up_count
, down_count
;
4683 case INSN_CONFIG_PWM_OUTPUT
:
4685 case TRIG_ROUND_NEAREST
:
4688 devpriv
->clock_ns
/ 2) / devpriv
->clock_ns
;
4690 case TRIG_ROUND_DOWN
:
4691 up_count
= data
[2] / devpriv
->clock_ns
;
4695 (data
[2] + devpriv
->clock_ns
-
4696 1) / devpriv
->clock_ns
;
4703 case TRIG_ROUND_NEAREST
:
4706 devpriv
->clock_ns
/ 2) / devpriv
->clock_ns
;
4708 case TRIG_ROUND_DOWN
:
4709 down_count
= data
[4] / devpriv
->clock_ns
;
4713 (data
[4] + devpriv
->clock_ns
-
4714 1) / devpriv
->clock_ns
;
4720 if (up_count
* devpriv
->clock_ns
!= data
[2] ||
4721 down_count
* devpriv
->clock_ns
!= data
[4]) {
4722 data
[2] = up_count
* devpriv
->clock_ns
;
4723 data
[4] = down_count
* devpriv
->clock_ns
;
4726 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count
) |
4727 MSeries_Cal_PWM_Low_Time_Bits(down_count
),
4729 devpriv
->pwm_up_count
= up_count
;
4730 devpriv
->pwm_down_count
= down_count
;
4733 case INSN_CONFIG_GET_PWM_OUTPUT
:
4734 return ni_get_pwm_config(dev
, data
);
4743 static int ni_6143_pwm_config(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
4744 struct comedi_insn
*insn
, unsigned int *data
)
4746 unsigned up_count
, down_count
;
4748 case INSN_CONFIG_PWM_OUTPUT
:
4750 case TRIG_ROUND_NEAREST
:
4753 devpriv
->clock_ns
/ 2) / devpriv
->clock_ns
;
4755 case TRIG_ROUND_DOWN
:
4756 up_count
= data
[2] / devpriv
->clock_ns
;
4760 (data
[2] + devpriv
->clock_ns
-
4761 1) / devpriv
->clock_ns
;
4768 case TRIG_ROUND_NEAREST
:
4771 devpriv
->clock_ns
/ 2) / devpriv
->clock_ns
;
4773 case TRIG_ROUND_DOWN
:
4774 down_count
= data
[4] / devpriv
->clock_ns
;
4778 (data
[4] + devpriv
->clock_ns
-
4779 1) / devpriv
->clock_ns
;
4785 if (up_count
* devpriv
->clock_ns
!= data
[2] ||
4786 down_count
* devpriv
->clock_ns
!= data
[4]) {
4787 data
[2] = up_count
* devpriv
->clock_ns
;
4788 data
[4] = down_count
* devpriv
->clock_ns
;
4791 ni_writel(up_count
, Calibration_HighTime_6143
);
4792 devpriv
->pwm_up_count
= up_count
;
4793 ni_writel(down_count
, Calibration_LowTime_6143
);
4794 devpriv
->pwm_down_count
= down_count
;
4797 case INSN_CONFIG_GET_PWM_OUTPUT
:
4798 return ni_get_pwm_config(dev
, data
);
4806 static void ni_write_caldac(struct comedi_device
*dev
, int addr
, int val
);
4808 calibration subdevice
4810 static int ni_calib_insn_write(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
4811 struct comedi_insn
*insn
, unsigned int *data
)
4813 ni_write_caldac(dev
, CR_CHAN(insn
->chanspec
), data
[0]);
4818 static int ni_calib_insn_read(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
4819 struct comedi_insn
*insn
, unsigned int *data
)
4821 data
[0] = devpriv
->caldacs
[CR_CHAN(insn
->chanspec
)];
4826 static int pack_mb88341(int addr
, int val
, int *bitstring
);
4827 static int pack_dac8800(int addr
, int val
, int *bitstring
);
4828 static int pack_dac8043(int addr
, int val
, int *bitstring
);
4829 static int pack_ad8522(int addr
, int val
, int *bitstring
);
4830 static int pack_ad8804(int addr
, int val
, int *bitstring
);
4831 static int pack_ad8842(int addr
, int val
, int *bitstring
);
4833 struct caldac_struct
{
4836 int (*packbits
) (int, int, int *);
4839 static struct caldac_struct caldacs
[] = {
4840 [mb88341
] = {12, 8, pack_mb88341
},
4841 [dac8800
] = {8, 8, pack_dac8800
},
4842 [dac8043
] = {1, 12, pack_dac8043
},
4843 [ad8522
] = {2, 12, pack_ad8522
},
4844 [ad8804
] = {12, 8, pack_ad8804
},
4845 [ad8842
] = {8, 8, pack_ad8842
},
4846 [ad8804_debug
] = {16, 8, pack_ad8804
},
4849 static void caldac_setup(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
4859 type
= boardtype
.caldac
[0];
4860 if (type
== caldac_none
)
4862 n_bits
= caldacs
[type
].n_bits
;
4863 for (i
= 0; i
< 3; i
++) {
4864 type
= boardtype
.caldac
[i
];
4865 if (type
== caldac_none
)
4867 if (caldacs
[type
].n_bits
!= n_bits
)
4869 n_chans
+= caldacs
[type
].n_chans
;
4872 s
->n_chan
= n_chans
;
4875 unsigned int *maxdata_list
;
4877 if (n_chans
> MAX_N_CALDACS
) {
4878 printk("BUG! MAX_N_CALDACS too small\n");
4880 s
->maxdata_list
= maxdata_list
= devpriv
->caldac_maxdata_list
;
4882 for (i
= 0; i
< n_dacs
; i
++) {
4883 type
= boardtype
.caldac
[i
];
4884 for (j
= 0; j
< caldacs
[type
].n_chans
; j
++) {
4885 maxdata_list
[chan
] =
4886 (1 << caldacs
[type
].n_bits
) - 1;
4891 for (chan
= 0; chan
< s
->n_chan
; chan
++)
4892 ni_write_caldac(dev
, i
, s
->maxdata_list
[i
] / 2);
4894 type
= boardtype
.caldac
[0];
4895 s
->maxdata
= (1 << caldacs
[type
].n_bits
) - 1;
4897 for (chan
= 0; chan
< s
->n_chan
; chan
++)
4898 ni_write_caldac(dev
, i
, s
->maxdata
/ 2);
4902 static void ni_write_caldac(struct comedi_device
*dev
, int addr
, int val
)
4904 unsigned int loadbit
= 0, bits
= 0, bit
, bitstring
= 0;
4908 /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
4909 if (devpriv
->caldacs
[addr
] == val
)
4911 devpriv
->caldacs
[addr
] = val
;
4913 for (i
= 0; i
< 3; i
++) {
4914 type
= boardtype
.caldac
[i
];
4915 if (type
== caldac_none
)
4917 if (addr
< caldacs
[type
].n_chans
) {
4918 bits
= caldacs
[type
].packbits(addr
, val
, &bitstring
);
4919 loadbit
= SerDacLd(i
);
4920 /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
4923 addr
-= caldacs
[type
].n_chans
;
4926 for (bit
= 1 << (bits
- 1); bit
; bit
>>= 1) {
4927 ni_writeb(((bit
& bitstring
) ? 0x02 : 0), Serial_Command
);
4929 ni_writeb(1 | ((bit
& bitstring
) ? 0x02 : 0), Serial_Command
);
4932 ni_writeb(loadbit
, Serial_Command
);
4934 ni_writeb(0, Serial_Command
);
4937 static int pack_mb88341(int addr
, int val
, int *bitstring
)
4941 Note that address bits are reversed. Thanks to
4942 Ingo Keen for noticing this.
4944 Note also that the 88341 expects address values from
4945 1-12, whereas we use channel numbers 0-11. The NI
4946 docs use 1-12, also, so be careful here.
4949 *bitstring
= ((addr
& 0x1) << 11) |
4950 ((addr
& 0x2) << 9) |
4951 ((addr
& 0x4) << 7) | ((addr
& 0x8) << 5) | (val
& 0xff);
4955 static int pack_dac8800(int addr
, int val
, int *bitstring
)
4957 *bitstring
= ((addr
& 0x7) << 8) | (val
& 0xff);
4961 static int pack_dac8043(int addr
, int val
, int *bitstring
)
4963 *bitstring
= val
& 0xfff;
4967 static int pack_ad8522(int addr
, int val
, int *bitstring
)
4969 *bitstring
= (val
& 0xfff) | (addr
? 0xc000 : 0xa000);
4973 static int pack_ad8804(int addr
, int val
, int *bitstring
)
4975 *bitstring
= ((addr
& 0xf) << 8) | (val
& 0xff);
4979 static int pack_ad8842(int addr
, int val
, int *bitstring
)
4981 *bitstring
= ((addr
+ 1) << 8) | (val
& 0xff);
4987 * Read the GPCTs current value.
4989 static int GPCT_G_Watch(struct comedi_device
*dev
, int chan
)
4991 unsigned int hi1
, hi2
, lo
;
4993 devpriv
->gpct_command
[chan
] &= ~G_Save_Trace
;
4994 devpriv
->stc_writew(dev
, devpriv
->gpct_command
[chan
],
4995 G_Command_Register(chan
));
4997 devpriv
->gpct_command
[chan
] |= G_Save_Trace
;
4998 devpriv
->stc_writew(dev
, devpriv
->gpct_command
[chan
],
4999 G_Command_Register(chan
));
5001 /* This procedure is used because the two registers cannot
5002 * be read atomically. */
5004 hi1
= devpriv
->stc_readw(dev
, G_Save_Register_High(chan
));
5005 lo
= devpriv
->stc_readw(dev
, G_Save_Register_Low(chan
));
5006 hi2
= devpriv
->stc_readw(dev
, G_Save_Register_High(chan
));
5007 } while (hi1
!= hi2
);
5009 return (hi1
<< 16) | lo
;
5012 static void GPCT_Reset(struct comedi_device
*dev
, int chan
)
5014 int temp_ack_reg
= 0;
5016 /* printk("GPCT_Reset..."); */
5017 devpriv
->gpct_cur_operation
[chan
] = GPCT_RESET
;
5021 devpriv
->stc_writew(dev
, G0_Reset
, Joint_Reset_Register
);
5022 ni_set_bits(dev
, Interrupt_A_Enable_Register
,
5023 G0_TC_Interrupt_Enable
, 0);
5024 ni_set_bits(dev
, Interrupt_A_Enable_Register
,
5025 G0_Gate_Interrupt_Enable
, 0);
5026 temp_ack_reg
|= G0_Gate_Error_Confirm
;
5027 temp_ack_reg
|= G0_TC_Error_Confirm
;
5028 temp_ack_reg
|= G0_TC_Interrupt_Ack
;
5029 temp_ack_reg
|= G0_Gate_Interrupt_Ack
;
5030 devpriv
->stc_writew(dev
, temp_ack_reg
,
5031 Interrupt_A_Ack_Register
);
5033 /* problem...this interferes with the other ctr... */
5034 devpriv
->an_trig_etc_reg
|= GPFO_0_Output_Enable
;
5035 devpriv
->stc_writew(dev
, devpriv
->an_trig_etc_reg
,
5036 Analog_Trigger_Etc_Register
);
5039 devpriv
->stc_writew(dev
, G1_Reset
, Joint_Reset_Register
);
5040 ni_set_bits(dev
, Interrupt_B_Enable_Register
,
5041 G1_TC_Interrupt_Enable
, 0);
5042 ni_set_bits(dev
, Interrupt_B_Enable_Register
,
5043 G0_Gate_Interrupt_Enable
, 0);
5044 temp_ack_reg
|= G1_Gate_Error_Confirm
;
5045 temp_ack_reg
|= G1_TC_Error_Confirm
;
5046 temp_ack_reg
|= G1_TC_Interrupt_Ack
;
5047 temp_ack_reg
|= G1_Gate_Interrupt_Ack
;
5048 devpriv
->stc_writew(dev
, temp_ack_reg
,
5049 Interrupt_B_Ack_Register
);
5051 devpriv
->an_trig_etc_reg
|= GPFO_1_Output_Enable
;
5052 devpriv
->stc_writew(dev
, devpriv
->an_trig_etc_reg
,
5053 Analog_Trigger_Etc_Register
);
5057 devpriv
->gpct_mode
[chan
] = 0;
5058 devpriv
->gpct_input_select
[chan
] = 0;
5059 devpriv
->gpct_command
[chan
] = 0;
5061 devpriv
->gpct_command
[chan
] |= G_Synchronized_Gate
;
5063 devpriv
->stc_writew(dev
, devpriv
->gpct_mode
[chan
],
5064 G_Mode_Register(chan
));
5065 devpriv
->stc_writew(dev
, devpriv
->gpct_input_select
[chan
],
5066 G_Input_Select_Register(chan
));
5067 devpriv
->stc_writew(dev
, 0, G_Autoincrement_Register(chan
));
5069 /* printk("exit GPCT_Reset\n"); */
5074 static int ni_gpct_insn_config(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
5075 struct comedi_insn
*insn
, unsigned int *data
)
5077 struct ni_gpct
*counter
= s
->private;
5078 return ni_tio_insn_config(counter
, insn
, data
);
5081 static int ni_gpct_insn_read(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
5082 struct comedi_insn
*insn
, unsigned int *data
)
5084 struct ni_gpct
*counter
= s
->private;
5085 return ni_tio_rinsn(counter
, insn
, data
);
5088 static int ni_gpct_insn_write(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
5089 struct comedi_insn
*insn
, unsigned int *data
)
5091 struct ni_gpct
*counter
= s
->private;
5092 return ni_tio_winsn(counter
, insn
, data
);
5095 static int ni_gpct_cmd(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
5099 struct ni_gpct
*counter
= s
->private;
5100 /* const struct comedi_cmd *cmd = &s->async->cmd; */
5102 retval
= ni_request_gpct_mite_channel(dev
, counter
->counter_index
,
5106 "no dma channel available for use by counter");
5109 ni_tio_acknowledge_and_confirm(counter
, NULL
, NULL
, NULL
, NULL
);
5110 ni_e_series_enable_second_irq(dev
, counter
->counter_index
, 1);
5111 retval
= ni_tio_cmd(counter
, s
->async
);
5118 static int ni_gpct_cmdtest(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
5119 struct comedi_cmd
*cmd
)
5122 struct ni_gpct
*counter
= s
->private;
5124 return ni_tio_cmdtest(counter
, cmd
);
5130 static int ni_gpct_cancel(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
5133 struct ni_gpct
*counter
= s
->private;
5136 retval
= ni_tio_cancel(counter
);
5137 ni_e_series_enable_second_irq(dev
, counter
->counter_index
, 0);
5138 ni_release_gpct_mite_channel(dev
, counter
->counter_index
);
5147 * Programmable Function Inputs
5151 static int ni_m_series_set_pfi_routing(struct comedi_device
*dev
, unsigned chan
,
5154 unsigned pfi_reg_index
;
5155 unsigned array_offset
;
5156 if ((source
& 0x1f) != source
)
5158 pfi_reg_index
= 1 + chan
/ 3;
5159 array_offset
= pfi_reg_index
- 1;
5160 devpriv
->pfi_output_select_reg
[array_offset
] &=
5161 ~MSeries_PFI_Output_Select_Mask(chan
);
5162 devpriv
->pfi_output_select_reg
[array_offset
] |=
5163 MSeries_PFI_Output_Select_Bits(chan
, source
);
5164 ni_writew(devpriv
->pfi_output_select_reg
[array_offset
],
5165 M_Offset_PFI_Output_Select(pfi_reg_index
));
5169 static int ni_old_set_pfi_routing(struct comedi_device
*dev
, unsigned chan
,
5172 /* pre-m-series boards have fixed signals on pfi pins */
5173 if (source
!= ni_old_get_pfi_routing(dev
, chan
))
5178 static int ni_set_pfi_routing(struct comedi_device
*dev
, unsigned chan
,
5181 if (boardtype
.reg_type
& ni_reg_m_series_mask
)
5182 return ni_m_series_set_pfi_routing(dev
, chan
, source
);
5184 return ni_old_set_pfi_routing(dev
, chan
, source
);
5187 static unsigned ni_m_series_get_pfi_routing(struct comedi_device
*dev
, unsigned chan
)
5189 const unsigned array_offset
= chan
/ 3;
5190 return MSeries_PFI_Output_Select_Source(chan
,
5191 devpriv
->pfi_output_select_reg
[array_offset
]);
5194 static unsigned ni_old_get_pfi_routing(struct comedi_device
*dev
, unsigned chan
)
5196 /* pre-m-series boards have fixed signals on pfi pins */
5199 return NI_PFI_OUTPUT_AI_START1
;
5202 return NI_PFI_OUTPUT_AI_START2
;
5205 return NI_PFI_OUTPUT_AI_CONVERT
;
5208 return NI_PFI_OUTPUT_G_SRC1
;
5211 return NI_PFI_OUTPUT_G_GATE1
;
5214 return NI_PFI_OUTPUT_AO_UPDATE_N
;
5217 return NI_PFI_OUTPUT_AO_START1
;
5220 return NI_PFI_OUTPUT_AI_START_PULSE
;
5223 return NI_PFI_OUTPUT_G_SRC0
;
5226 return NI_PFI_OUTPUT_G_GATE0
;
5229 printk("%s: bug, unhandled case in switch.\n", __func__
);
5235 static unsigned ni_get_pfi_routing(struct comedi_device
*dev
, unsigned chan
)
5237 if (boardtype
.reg_type
& ni_reg_m_series_mask
)
5238 return ni_m_series_get_pfi_routing(dev
, chan
);
5240 return ni_old_get_pfi_routing(dev
, chan
);
5243 static int ni_config_filter(struct comedi_device
*dev
, unsigned pfi_channel
,
5244 enum ni_pfi_filter_select filter
)
5247 if ((boardtype
.reg_type
& ni_reg_m_series_mask
) == 0) {
5250 bits
= ni_readl(M_Offset_PFI_Filter
);
5251 bits
&= ~MSeries_PFI_Filter_Select_Mask(pfi_channel
);
5252 bits
|= MSeries_PFI_Filter_Select_Bits(pfi_channel
, filter
);
5253 ni_writel(bits
, M_Offset_PFI_Filter
);
5257 static int ni_pfi_insn_bits(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
5258 struct comedi_insn
*insn
, unsigned int *data
)
5260 if ((boardtype
.reg_type
& ni_reg_m_series_mask
) == 0) {
5264 s
->state
&= ~data
[0];
5265 s
->state
|= (data
[0] & data
[1]);
5266 ni_writew(s
->state
, M_Offset_PFI_DO
);
5268 data
[1] = ni_readw(M_Offset_PFI_DI
);
5272 static int ni_pfi_insn_config(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
5273 struct comedi_insn
*insn
, unsigned int *data
)
5280 chan
= CR_CHAN(insn
->chanspec
);
5284 ni_set_bits(dev
, IO_Bidirection_Pin_Register
, 1 << chan
, 1);
5287 ni_set_bits(dev
, IO_Bidirection_Pin_Register
, 1 << chan
, 0);
5289 case INSN_CONFIG_DIO_QUERY
:
5292 io_bidirection_pin_reg
& (1 << chan
)) ? COMEDI_OUTPUT
:
5296 case INSN_CONFIG_SET_ROUTING
:
5297 return ni_set_pfi_routing(dev
, chan
, data
[1]);
5299 case INSN_CONFIG_GET_ROUTING
:
5300 data
[1] = ni_get_pfi_routing(dev
, chan
);
5302 case INSN_CONFIG_FILTER
:
5303 return ni_config_filter(dev
, chan
, data
[1]);
5313 * NI RTSI Bus Functions
5316 static void ni_rtsi_init(struct comedi_device
*dev
)
5318 /* Initialises the RTSI bus signal switch to a default state */
5320 /* Set clock mode to internal */
5321 devpriv
->clock_and_fout2
= MSeries_RTSI_10MHz_Bit
;
5322 if (ni_set_master_clock(dev
, NI_MIO_INTERNAL_CLOCK
, 0) < 0) {
5323 printk("ni_set_master_clock failed, bug?");
5325 /* default internal lines routing to RTSI bus lines */
5326 devpriv
->rtsi_trig_a_output_reg
=
5327 RTSI_Trig_Output_Bits(0,
5328 NI_RTSI_OUTPUT_ADR_START1
) | RTSI_Trig_Output_Bits(1,
5329 NI_RTSI_OUTPUT_ADR_START2
) | RTSI_Trig_Output_Bits(2,
5330 NI_RTSI_OUTPUT_SCLKG
) | RTSI_Trig_Output_Bits(3,
5331 NI_RTSI_OUTPUT_DACUPDN
);
5332 devpriv
->stc_writew(dev
, devpriv
->rtsi_trig_a_output_reg
,
5333 RTSI_Trig_A_Output_Register
);
5334 devpriv
->rtsi_trig_b_output_reg
=
5335 RTSI_Trig_Output_Bits(4,
5336 NI_RTSI_OUTPUT_DA_START1
) | RTSI_Trig_Output_Bits(5,
5337 NI_RTSI_OUTPUT_G_SRC0
) | RTSI_Trig_Output_Bits(6,
5338 NI_RTSI_OUTPUT_G_GATE0
);
5339 if (boardtype
.reg_type
& ni_reg_m_series_mask
)
5340 devpriv
->rtsi_trig_b_output_reg
|=
5341 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC
);
5342 devpriv
->stc_writew(dev
, devpriv
->rtsi_trig_b_output_reg
,
5343 RTSI_Trig_B_Output_Register
);
5346 * Sets the source and direction of the 4 on board lines
5347 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5351 static int ni_rtsi_insn_bits(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
5352 struct comedi_insn
*insn
, unsigned int *data
)
5362 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5363 * given an arbitrary frequency input clock */
5364 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns
,
5365 unsigned *freq_divider
, unsigned *freq_multiplier
,
5366 unsigned *actual_period_ns
)
5369 unsigned best_div
= 1;
5370 static const unsigned max_div
= 0x10;
5372 unsigned best_mult
= 1;
5373 static const unsigned max_mult
= 0x100;
5374 static const unsigned pico_per_nano
= 1000;
5376 const unsigned reference_picosec
= reference_period_ns
* pico_per_nano
;
5377 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5378 * 20 MHz for most timing clocks */
5379 static const unsigned target_picosec
= 12500;
5380 static const unsigned fudge_factor_80_to_20Mhz
= 4;
5381 int best_period_picosec
= 0;
5382 for (div
= 1; div
<= max_div
; ++div
) {
5383 for (mult
= 1; mult
<= max_mult
; ++mult
) {
5384 unsigned new_period_ps
=
5385 (reference_picosec
* div
) / mult
;
5386 if (abs(new_period_ps
- target_picosec
) <
5387 abs(best_period_picosec
- target_picosec
)) {
5388 best_period_picosec
= new_period_ps
;
5394 if (best_period_picosec
== 0) {
5395 printk("%s: bug, failed to find pll parameters\n",
5399 *freq_divider
= best_div
;
5400 *freq_multiplier
= best_mult
;
5402 (best_period_picosec
* fudge_factor_80_to_20Mhz
+
5403 (pico_per_nano
/ 2)) / pico_per_nano
;
5407 static inline unsigned num_configurable_rtsi_channels(struct comedi_device
*dev
)
5409 if (boardtype
.reg_type
& ni_reg_m_series_mask
)
5415 static int ni_mseries_set_pll_master_clock(struct comedi_device
*dev
, unsigned source
,
5418 static const unsigned min_period_ns
= 50;
5419 static const unsigned max_period_ns
= 1000;
5420 static const unsigned timeout
= 1000;
5421 unsigned pll_control_bits
;
5422 unsigned freq_divider
;
5423 unsigned freq_multiplier
;
5426 if (source
== NI_MIO_PLL_PXI10_CLOCK
)
5428 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5429 if (period_ns
< min_period_ns
|| period_ns
> max_period_ns
) {
5431 ("%s: you must specify an input clock frequency between %i and %i nanosec "
5432 "for the phased-lock loop.\n", __func__
,
5433 min_period_ns
, max_period_ns
);
5436 devpriv
->rtsi_trig_direction_reg
&= ~Use_RTSI_Clock_Bit
;
5437 devpriv
->stc_writew(dev
, devpriv
->rtsi_trig_direction_reg
,
5438 RTSI_Trig_Direction_Register
);
5440 MSeries_PLL_Enable_Bit
| MSeries_PLL_VCO_Mode_75_150MHz_Bits
;
5441 devpriv
->clock_and_fout2
|=
5442 MSeries_Timebase1_Select_Bit
| MSeries_Timebase3_Select_Bit
;
5443 devpriv
->clock_and_fout2
&= ~MSeries_PLL_In_Source_Select_Mask
;
5445 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK
:
5446 devpriv
->clock_and_fout2
|=
5447 MSeries_PLL_In_Source_Select_Star_Trigger_Bits
;
5448 retval
= ni_mseries_get_pll_parameters(period_ns
, &freq_divider
,
5449 &freq_multiplier
, &devpriv
->clock_ns
);
5453 case NI_MIO_PLL_PXI10_CLOCK
:
5454 /* pxi clock is 10MHz */
5455 devpriv
->clock_and_fout2
|=
5456 MSeries_PLL_In_Source_Select_PXI_Clock10
;
5457 retval
= ni_mseries_get_pll_parameters(period_ns
, &freq_divider
,
5458 &freq_multiplier
, &devpriv
->clock_ns
);
5464 unsigned rtsi_channel
;
5465 static const unsigned max_rtsi_channel
= 7;
5466 for (rtsi_channel
= 0; rtsi_channel
<= max_rtsi_channel
;
5469 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel
)) {
5470 devpriv
->clock_and_fout2
|=
5471 MSeries_PLL_In_Source_Select_RTSI_Bits
5476 if (rtsi_channel
> max_rtsi_channel
)
5478 retval
= ni_mseries_get_pll_parameters(period_ns
,
5479 &freq_divider
, &freq_multiplier
,
5480 &devpriv
->clock_ns
);
5486 ni_writew(devpriv
->clock_and_fout2
, M_Offset_Clock_and_Fout2
);
5488 MSeries_PLL_Divisor_Bits(freq_divider
) |
5489 MSeries_PLL_Multiplier_Bits(freq_multiplier
);
5491 /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5492 * freq_divider, freq_multiplier, pll_control_bits); */
5493 /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5494 ni_writew(pll_control_bits
, M_Offset_PLL_Control
);
5495 devpriv
->clock_source
= source
;
5496 /* it seems to typically take a few hundred microseconds for PLL to lock */
5497 for (i
= 0; i
< timeout
; ++i
) {
5498 if (ni_readw(M_Offset_PLL_Status
) & MSeries_PLL_Locked_Bit
) {
5505 ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5506 __func__
, source
, period_ns
);
5512 static int ni_set_master_clock(struct comedi_device
*dev
, unsigned source
,
5515 if (source
== NI_MIO_INTERNAL_CLOCK
) {
5516 devpriv
->rtsi_trig_direction_reg
&= ~Use_RTSI_Clock_Bit
;
5517 devpriv
->stc_writew(dev
, devpriv
->rtsi_trig_direction_reg
,
5518 RTSI_Trig_Direction_Register
);
5519 devpriv
->clock_ns
= TIMEBASE_1_NS
;
5520 if (boardtype
.reg_type
& ni_reg_m_series_mask
) {
5521 devpriv
->clock_and_fout2
&=
5522 ~(MSeries_Timebase1_Select_Bit
|
5523 MSeries_Timebase3_Select_Bit
);
5524 ni_writew(devpriv
->clock_and_fout2
,
5525 M_Offset_Clock_and_Fout2
);
5526 ni_writew(0, M_Offset_PLL_Control
);
5528 devpriv
->clock_source
= source
;
5530 if (boardtype
.reg_type
& ni_reg_m_series_mask
) {
5531 return ni_mseries_set_pll_master_clock(dev
, source
,
5534 if (source
== NI_MIO_RTSI_CLOCK
) {
5535 devpriv
->rtsi_trig_direction_reg
|=
5537 devpriv
->stc_writew(dev
,
5538 devpriv
->rtsi_trig_direction_reg
,
5539 RTSI_Trig_Direction_Register
);
5540 if (period_ns
== 0) {
5542 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5546 devpriv
->clock_ns
= period_ns
;
5548 devpriv
->clock_source
= source
;
5556 static int ni_valid_rtsi_output_source(struct comedi_device
*dev
, unsigned chan
,
5559 if (chan
>= num_configurable_rtsi_channels(dev
)) {
5560 if (chan
== old_RTSI_clock_channel
) {
5561 if (source
== NI_RTSI_OUTPUT_RTSI_OSC
)
5565 ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5567 old_RTSI_clock_channel
);
5574 case NI_RTSI_OUTPUT_ADR_START1
:
5575 case NI_RTSI_OUTPUT_ADR_START2
:
5576 case NI_RTSI_OUTPUT_SCLKG
:
5577 case NI_RTSI_OUTPUT_DACUPDN
:
5578 case NI_RTSI_OUTPUT_DA_START1
:
5579 case NI_RTSI_OUTPUT_G_SRC0
:
5580 case NI_RTSI_OUTPUT_G_GATE0
:
5581 case NI_RTSI_OUTPUT_RGOUT0
:
5582 case NI_RTSI_OUTPUT_RTSI_BRD_0
:
5585 case NI_RTSI_OUTPUT_RTSI_OSC
:
5586 if (boardtype
.reg_type
& ni_reg_m_series_mask
)
5597 static int ni_set_rtsi_routing(struct comedi_device
*dev
, unsigned chan
,
5600 if (ni_valid_rtsi_output_source(dev
, chan
, source
) == 0)
5603 devpriv
->rtsi_trig_a_output_reg
&= ~RTSI_Trig_Output_Mask(chan
);
5604 devpriv
->rtsi_trig_a_output_reg
|=
5605 RTSI_Trig_Output_Bits(chan
, source
);
5606 devpriv
->stc_writew(dev
, devpriv
->rtsi_trig_a_output_reg
,
5607 RTSI_Trig_A_Output_Register
);
5608 } else if (chan
< 8) {
5609 devpriv
->rtsi_trig_b_output_reg
&= ~RTSI_Trig_Output_Mask(chan
);
5610 devpriv
->rtsi_trig_b_output_reg
|=
5611 RTSI_Trig_Output_Bits(chan
, source
);
5612 devpriv
->stc_writew(dev
, devpriv
->rtsi_trig_b_output_reg
,
5613 RTSI_Trig_B_Output_Register
);
5618 static unsigned ni_get_rtsi_routing(struct comedi_device
*dev
, unsigned chan
)
5621 return RTSI_Trig_Output_Source(chan
,
5622 devpriv
->rtsi_trig_a_output_reg
);
5623 } else if (chan
< num_configurable_rtsi_channels(dev
)) {
5624 return RTSI_Trig_Output_Source(chan
,
5625 devpriv
->rtsi_trig_b_output_reg
);
5627 if (chan
== old_RTSI_clock_channel
)
5628 return NI_RTSI_OUTPUT_RTSI_OSC
;
5629 printk("%s: bug! should never get here?\n", __func__
);
5634 static int ni_rtsi_insn_config(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
5635 struct comedi_insn
*insn
, unsigned int *data
)
5637 unsigned int chan
= CR_CHAN(insn
->chanspec
);
5639 case INSN_CONFIG_DIO_OUTPUT
:
5640 if (chan
< num_configurable_rtsi_channels(dev
)) {
5641 devpriv
->rtsi_trig_direction_reg
|=
5642 RTSI_Output_Bit(chan
,
5643 (boardtype
.reg_type
& ni_reg_m_series_mask
) !=
5645 } else if (chan
== old_RTSI_clock_channel
) {
5646 devpriv
->rtsi_trig_direction_reg
|=
5647 Drive_RTSI_Clock_Bit
;
5649 devpriv
->stc_writew(dev
, devpriv
->rtsi_trig_direction_reg
,
5650 RTSI_Trig_Direction_Register
);
5652 case INSN_CONFIG_DIO_INPUT
:
5653 if (chan
< num_configurable_rtsi_channels(dev
)) {
5654 devpriv
->rtsi_trig_direction_reg
&=
5655 ~RTSI_Output_Bit(chan
,
5656 (boardtype
.reg_type
& ni_reg_m_series_mask
) !=
5658 } else if (chan
== old_RTSI_clock_channel
) {
5659 devpriv
->rtsi_trig_direction_reg
&=
5660 ~Drive_RTSI_Clock_Bit
;
5662 devpriv
->stc_writew(dev
, devpriv
->rtsi_trig_direction_reg
,
5663 RTSI_Trig_Direction_Register
);
5665 case INSN_CONFIG_DIO_QUERY
:
5666 if (chan
< num_configurable_rtsi_channels(dev
)) {
5669 rtsi_trig_direction_reg
& RTSI_Output_Bit(chan
,
5671 reg_type
& ni_reg_m_series_mask
)
5673 0)) ? INSN_CONFIG_DIO_OUTPUT
:
5674 INSN_CONFIG_DIO_INPUT
;
5675 } else if (chan
== old_RTSI_clock_channel
) {
5678 rtsi_trig_direction_reg
& Drive_RTSI_Clock_Bit
)
5679 ? INSN_CONFIG_DIO_OUTPUT
:
5680 INSN_CONFIG_DIO_INPUT
;
5684 case INSN_CONFIG_SET_CLOCK_SRC
:
5685 return ni_set_master_clock(dev
, data
[1], data
[2]);
5687 case INSN_CONFIG_GET_CLOCK_SRC
:
5688 data
[1] = devpriv
->clock_source
;
5689 data
[2] = devpriv
->clock_ns
;
5692 case INSN_CONFIG_SET_ROUTING
:
5693 return ni_set_rtsi_routing(dev
, chan
, data
[1]);
5695 case INSN_CONFIG_GET_ROUTING
:
5696 data
[1] = ni_get_rtsi_routing(dev
, chan
);
5706 static int cs5529_wait_for_idle(struct comedi_device
*dev
)
5708 unsigned short status
;
5709 const int timeout
= HZ
;
5712 for (i
= 0; i
< timeout
; i
++) {
5713 status
= ni_ao_win_inw(dev
, CAL_ADC_Status_67xx
);
5714 if ((status
& CSS_ADC_BUSY
) == 0) {
5717 set_current_state(TASK_INTERRUPTIBLE
);
5718 if (schedule_timeout(1)) {
5722 /* printk("looped %i times waiting for idle\n", i); */
5724 printk("%s: %s: timeout\n", __FILE__
, __func__
);
5730 static void cs5529_command(struct comedi_device
*dev
, unsigned short value
)
5732 static const int timeout
= 100;
5735 ni_ao_win_outw(dev
, value
, CAL_ADC_Command_67xx
);
5736 /* give time for command to start being serially clocked into cs5529.
5737 * this insures that the CSS_ADC_BUSY bit will get properly
5738 * set before we exit this function.
5740 for (i
= 0; i
< timeout
; i
++) {
5741 if ((ni_ao_win_inw(dev
, CAL_ADC_Status_67xx
) & CSS_ADC_BUSY
))
5745 /* printk("looped %i times writing command to cs5529\n", i); */
5747 comedi_error(dev
, "possible problem - never saw adc go busy?");
5751 /* write to cs5529 register */
5752 static void cs5529_config_write(struct comedi_device
*dev
, unsigned int value
,
5753 unsigned int reg_select_bits
)
5755 ni_ao_win_outw(dev
, ((value
>> 16) & 0xff),
5756 CAL_ADC_Config_Data_High_Word_67xx
);
5757 ni_ao_win_outw(dev
, (value
& 0xffff),
5758 CAL_ADC_Config_Data_Low_Word_67xx
);
5759 reg_select_bits
&= CSCMD_REGISTER_SELECT_MASK
;
5760 cs5529_command(dev
, CSCMD_COMMAND
| reg_select_bits
);
5761 if (cs5529_wait_for_idle(dev
))
5762 comedi_error(dev
, "time or signal in cs5529_config_write()");
5765 #ifdef NI_CS5529_DEBUG
5766 /* read from cs5529 register */
5767 static unsigned int cs5529_config_read(struct comedi_device
*dev
,
5768 unsigned int reg_select_bits
)
5772 reg_select_bits
&= CSCMD_REGISTER_SELECT_MASK
;
5773 cs5529_command(dev
, CSCMD_COMMAND
| CSCMD_READ
| reg_select_bits
);
5774 if (cs5529_wait_for_idle(dev
))
5775 comedi_error(dev
, "timeout or signal in cs5529_config_read()");
5776 value
= (ni_ao_win_inw(dev
,
5777 CAL_ADC_Config_Data_High_Word_67xx
) << 16) & 0xff0000;
5778 value
|= ni_ao_win_inw(dev
, CAL_ADC_Config_Data_Low_Word_67xx
) & 0xffff;
5783 static int cs5529_do_conversion(struct comedi_device
*dev
, unsigned short *data
)
5786 unsigned short status
;
5788 cs5529_command(dev
, CSCMD_COMMAND
| CSCMD_SINGLE_CONVERSION
);
5789 retval
= cs5529_wait_for_idle(dev
);
5792 "timeout or signal in cs5529_do_conversion()");
5795 status
= ni_ao_win_inw(dev
, CAL_ADC_Status_67xx
);
5796 if (status
& CSS_OSC_DETECT
) {
5798 ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5801 if (status
& CSS_OVERRANGE
) {
5803 ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5806 *data
= ni_ao_win_inw(dev
, CAL_ADC_Data_67xx
);
5807 /* cs5529 returns 16 bit signed data in bipolar mode */
5813 static int cs5529_ai_insn_read(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
5814 struct comedi_insn
*insn
, unsigned int *data
)
5817 unsigned short sample
;
5818 unsigned int channel_select
;
5819 const unsigned int INTERNAL_REF
= 0x1000;
5821 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
5822 * do nothing. bit 12 seems to chooses internal reference voltage, bit
5823 * 13 causes the adc input to go overrange (maybe reads external reference?) */
5824 if (insn
->chanspec
& CR_ALT_SOURCE
)
5825 channel_select
= INTERNAL_REF
;
5827 channel_select
= CR_CHAN(insn
->chanspec
);
5828 ni_ao_win_outw(dev
, channel_select
, AO_Calibration_Channel_Select_67xx
);
5830 for (n
= 0; n
< insn
->n
; n
++) {
5831 retval
= cs5529_do_conversion(dev
, &sample
);
5839 static int init_cs5529(struct comedi_device
*dev
)
5841 unsigned int config_bits
=
5842 CSCFG_PORT_MODE
| CSCFG_WORD_RATE_2180_CYCLES
;
5845 /* do self-calibration */
5846 cs5529_config_write(dev
, config_bits
| CSCFG_SELF_CAL_OFFSET_GAIN
,
5847 CSCMD_CONFIG_REGISTER
);
5848 /* need to force a conversion for calibration to run */
5849 cs5529_do_conversion(dev
, NULL
);
5851 /* force gain calibration to 1 */
5852 cs5529_config_write(dev
, 0x400000, CSCMD_GAIN_REGISTER
);
5853 cs5529_config_write(dev
, config_bits
| CSCFG_SELF_CAL_OFFSET
,
5854 CSCMD_CONFIG_REGISTER
);
5855 if (cs5529_wait_for_idle(dev
))
5856 comedi_error(dev
, "timeout or signal in init_cs5529()\n");
5858 #ifdef NI_CS5529_DEBUG
5859 printk("config: 0x%x\n", cs5529_config_read(dev
,
5860 CSCMD_CONFIG_REGISTER
));
5861 printk("gain: 0x%x\n", cs5529_config_read(dev
,
5862 CSCMD_GAIN_REGISTER
));
5863 printk("offset: 0x%x\n", cs5529_config_read(dev
,
5864 CSCMD_OFFSET_REGISTER
));