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usb: musb: introduce api for dma code to check compatibility with usb request
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / usb / musb / musb_gadget.c
blob2fe304611dcfe2c07bfbb2b8ab054a15501ab3d9
1 /*
2 * MUSB OTG driver peripheral support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/moduleparam.h>
44 #include <linux/stat.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/slab.h>
47
48 #include "musb_core.h"
49
50
51 /* MUSB PERIPHERAL status 3-mar-2006:
52 *
53 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
54 * Minor glitches:
55 *
56 * + remote wakeup to Linux hosts work, but saw USBCV failures;
57 * in one test run (operator error?)
58 * + endpoint halt tests -- in both usbtest and usbcv -- seem
59 * to break when dma is enabled ... is something wrongly
60 * clearing SENDSTALL?
61 *
62 * - Mass storage behaved ok when last tested. Network traffic patterns
63 * (with lots of short transfers etc) need retesting; they turn up the
64 * worst cases of the DMA, since short packets are typical but are not
65 * required.
66 *
67 * - TX/IN
68 * + both pio and dma behave in with network and g_zero tests
69 * + no cppi throughput issues other than no-hw-queueing
70 * + failed with FLAT_REG (DaVinci)
71 * + seems to behave with double buffering, PIO -and- CPPI
72 * + with gadgetfs + AIO, requests got lost?
73 *
74 * - RX/OUT
75 * + both pio and dma behave in with network and g_zero tests
76 * + dma is slow in typical case (short_not_ok is clear)
77 * + double buffering ok with PIO
78 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
79 * + request lossage observed with gadgetfs
80 *
81 * - ISO not tested ... might work, but only weakly isochronous
82 *
83 * - Gadget driver disabling of softconnect during bind() is ignored; so
84 * drivers can't hold off host requests until userspace is ready.
85 * (Workaround: they can turn it off later.)
86 *
87 * - PORTABILITY (assumes PIO works):
88 * + DaVinci, basically works with cppi dma
89 * + OMAP 2430, ditto with mentor dma
90 * + TUSB 6010, platform-specific dma in the works
91 */
92
93 /* ----------------------------------------------------------------------- */
94
95 #define is_buffer_mapped(req) (is_dma_capable() && \
96 (req->map_state != UN_MAPPED))
97
98 /* Maps the buffer to dma */
99
100 static inline void map_dma_buffer(struct musb_request *request,
101 struct musb *musb, struct musb_ep *musb_ep)
102 {
103 int compatible = true;
104 struct dma_controller *dma = musb->dma_controller;
105
106 request->map_state = UN_MAPPED;
107
108 if (!is_dma_capable() || !musb_ep->dma)
109 return;
110
111 /* Check if DMA engine can handle this request.
112 * DMA code must reject the USB request explicitly.
113 * Default behaviour is to map the request.
114 */
115 if (dma->is_compatible)
116 compatible = dma->is_compatible(musb_ep->dma,
117 musb_ep->packet_sz, request->request.buf,
118 request->request.length);
119 if (!compatible)
120 return;
121
122 if (request->request.dma == DMA_ADDR_INVALID) {
123 request->request.dma = dma_map_single(
124 musb->controller,
125 request->request.buf,
126 request->request.length,
127 request->tx
128 ? DMA_TO_DEVICE
129 : DMA_FROM_DEVICE);
130 request->map_state = MUSB_MAPPED;
131 } else {
132 dma_sync_single_for_device(musb->controller,
133 request->request.dma,
134 request->request.length,
135 request->tx
136 ? DMA_TO_DEVICE
137 : DMA_FROM_DEVICE);
138 request->map_state = PRE_MAPPED;
139 }
140 }
141
142 /* Unmap the buffer from dma and maps it back to cpu */
143 static inline void unmap_dma_buffer(struct musb_request *request,
144 struct musb *musb)
145 {
146 if (!is_buffer_mapped(request))
147 return;
148
149 if (request->request.dma == DMA_ADDR_INVALID) {
150 DBG(20, "not unmapping a never mapped buffer\n");
151 return;
152 }
153 if (request->map_state == MUSB_MAPPED) {
154 dma_unmap_single(musb->controller,
155 request->request.dma,
156 request->request.length,
157 request->tx
158 ? DMA_TO_DEVICE
159 : DMA_FROM_DEVICE);
160 request->request.dma = DMA_ADDR_INVALID;
161 } else { /* PRE_MAPPED */
162 dma_sync_single_for_cpu(musb->controller,
163 request->request.dma,
164 request->request.length,
165 request->tx
166 ? DMA_TO_DEVICE
167 : DMA_FROM_DEVICE);
168 }
169 request->map_state = UN_MAPPED;
170 }
171
172 /*
173 * Immediately complete a request.
174 *
175 * @param request the request to complete
176 * @param status the status to complete the request with
177 * Context: controller locked, IRQs blocked.
178 */
179 void musb_g_giveback(
180 struct musb_ep *ep,
181 struct usb_request *request,
182 int status)
183 __releases(ep->musb->lock)
184 __acquires(ep->musb->lock)
185 {
186 struct musb_request *req;
187 struct musb *musb;
188 int busy = ep->busy;
189
190 req = to_musb_request(request);
191
192 list_del(&request->list);
193 if (req->request.status == -EINPROGRESS)
194 req->request.status = status;
195 musb = req->musb;
196
197 ep->busy = 1;
198 spin_unlock(&musb->lock);
199 unmap_dma_buffer(req, musb);
200 if (request->status == 0)
201 DBG(5, "%s done request %p, %d/%d\n",
202 ep->end_point.name, request,
203 req->request.actual, req->request.length);
204 else
205 DBG(2, "%s request %p, %d/%d fault %d\n",
206 ep->end_point.name, request,
207 req->request.actual, req->request.length,
208 request->status);
209 req->request.complete(&req->ep->end_point, &req->request);
210 spin_lock(&musb->lock);
211 ep->busy = busy;
212 }
213
214 /* ----------------------------------------------------------------------- */
215
216 /*
217 * Abort requests queued to an endpoint using the status. Synchronous.
218 * caller locked controller and blocked irqs, and selected this ep.
219 */
220 static void nuke(struct musb_ep *ep, const int status)
221 {
222 struct musb_request *req = NULL;
223 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
224
225 ep->busy = 1;
226
227 if (is_dma_capable() && ep->dma) {
228 struct dma_controller *c = ep->musb->dma_controller;
229 int value;
230
231 if (ep->is_in) {
232 /*
233 * The programming guide says that we must not clear
234 * the DMAMODE bit before DMAENAB, so we only
235 * clear it in the second write...
236 */
237 musb_writew(epio, MUSB_TXCSR,
238 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
239 musb_writew(epio, MUSB_TXCSR,
240 0 | MUSB_TXCSR_FLUSHFIFO);
241 } else {
242 musb_writew(epio, MUSB_RXCSR,
243 0 | MUSB_RXCSR_FLUSHFIFO);
244 musb_writew(epio, MUSB_RXCSR,
245 0 | MUSB_RXCSR_FLUSHFIFO);
246 }
247
248 value = c->channel_abort(ep->dma);
249 DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value);
250 c->channel_release(ep->dma);
251 ep->dma = NULL;
252 }
253
254 while (!list_empty(&(ep->req_list))) {
255 req = container_of(ep->req_list.next, struct musb_request,
256 request.list);
257 musb_g_giveback(ep, &req->request, status);
258 }
259 }
260
261 /* ----------------------------------------------------------------------- */
262
263 /* Data transfers - pure PIO, pure DMA, or mixed mode */
264
265 /*
266 * This assumes the separate CPPI engine is responding to DMA requests
267 * from the usb core ... sequenced a bit differently from mentor dma.
268 */
269
270 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
271 {
272 if (can_bulk_split(musb, ep->type))
273 return ep->hw_ep->max_packet_sz_tx;
274 else
275 return ep->packet_sz;
276 }
277
278
279 #ifdef CONFIG_USB_INVENTRA_DMA
280
281 /* Peripheral tx (IN) using Mentor DMA works as follows:
282 Only mode 0 is used for transfers <= wPktSize,
283 mode 1 is used for larger transfers,
284
285 One of the following happens:
286 - Host sends IN token which causes an endpoint interrupt
287 -> TxAvail
288 -> if DMA is currently busy, exit.
289 -> if queue is non-empty, txstate().
290
291 - Request is queued by the gadget driver.
292 -> if queue was previously empty, txstate()
293
294 txstate()
295 -> start
296 /\ -> setup DMA
297 | (data is transferred to the FIFO, then sent out when
298 | IN token(s) are recd from Host.
299 | -> DMA interrupt on completion
300 | calls TxAvail.
301 | -> stop DMA, ~DMAENAB,
302 | -> set TxPktRdy for last short pkt or zlp
303 | -> Complete Request
304 | -> Continue next request (call txstate)
305 |___________________________________|
306
307 * Non-Mentor DMA engines can of course work differently, such as by
308 * upleveling from irq-per-packet to irq-per-buffer.
309 */
310
311 #endif
312
313 /*
314 * An endpoint is transmitting data. This can be called either from
315 * the IRQ routine or from ep.queue() to kickstart a request on an
316 * endpoint.
317 *
318 * Context: controller locked, IRQs blocked, endpoint selected
319 */
320 static void txstate(struct musb *musb, struct musb_request *req)
321 {
322 u8 epnum = req->epnum;
323 struct musb_ep *musb_ep;
324 void __iomem *epio = musb->endpoints[epnum].regs;
325 struct usb_request *request;
326 u16 fifo_count = 0, csr;
327 int use_dma = 0;
328
329 musb_ep = req->ep;
330
331 /* we shouldn't get here while DMA is active ... but we do ... */
332 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
333 DBG(4, "dma pending...\n");
334 return;
335 }
336
337 /* read TXCSR before */
338 csr = musb_readw(epio, MUSB_TXCSR);
339
340 request = &req->request;
341 fifo_count = min(max_ep_writesize(musb, musb_ep),
342 (int)(request->length - request->actual));
343
344 if (csr & MUSB_TXCSR_TXPKTRDY) {
345 DBG(5, "%s old packet still ready , txcsr %03x\n",
346 musb_ep->end_point.name, csr);
347 return;
348 }
349
350 if (csr & MUSB_TXCSR_P_SENDSTALL) {
351 DBG(5, "%s stalling, txcsr %03x\n",
352 musb_ep->end_point.name, csr);
353 return;
354 }
355
356 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
357 epnum, musb_ep->packet_sz, fifo_count,
358 csr);
359
360 #ifndef CONFIG_MUSB_PIO_ONLY
361 if (is_buffer_mapped(req)) {
362 struct dma_controller *c = musb->dma_controller;
363 size_t request_size;
364
365 /* setup DMA, then program endpoint CSR */
366 request_size = min_t(size_t, request->length - request->actual,
367 musb_ep->dma->max_len);
368
369 use_dma = (request->dma != DMA_ADDR_INVALID);
370
371 /* MUSB_TXCSR_P_ISO is still set correctly */
372
373 #ifdef CONFIG_USB_INVENTRA_DMA
374 {
375 if (request_size < musb_ep->packet_sz)
376 musb_ep->dma->desired_mode = 0;
377 else
378 musb_ep->dma->desired_mode = 1;
379
380 use_dma = use_dma && c->channel_program(
381 musb_ep->dma, musb_ep->packet_sz,
382 musb_ep->dma->desired_mode,
383 request->dma + request->actual, request_size);
384 if (use_dma) {
385 if (musb_ep->dma->desired_mode == 0) {
386 /*
387 * We must not clear the DMAMODE bit
388 * before the DMAENAB bit -- and the
389 * latter doesn't always get cleared
390 * before we get here...
391 */
392 csr &= ~(MUSB_TXCSR_AUTOSET
393 | MUSB_TXCSR_DMAENAB);
394 musb_writew(epio, MUSB_TXCSR, csr
395 | MUSB_TXCSR_P_WZC_BITS);
396 csr &= ~MUSB_TXCSR_DMAMODE;
397 csr |= (MUSB_TXCSR_DMAENAB |
398 MUSB_TXCSR_MODE);
399 /* against programming guide */
400 } else {
401 csr |= (MUSB_TXCSR_DMAENAB
402 | MUSB_TXCSR_DMAMODE
403 | MUSB_TXCSR_MODE);
404 if (!musb_ep->hb_mult)
405 csr |= MUSB_TXCSR_AUTOSET;
406 }
407 csr &= ~MUSB_TXCSR_P_UNDERRUN;
408
409 musb_writew(epio, MUSB_TXCSR, csr);
410 }
411 }
412
413 #elif defined(CONFIG_USB_TI_CPPI_DMA)
414 /* program endpoint CSR first, then setup DMA */
415 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
416 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
417 MUSB_TXCSR_MODE;
418 musb_writew(epio, MUSB_TXCSR,
419 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
420 | csr);
421
422 /* ensure writebuffer is empty */
423 csr = musb_readw(epio, MUSB_TXCSR);
424
425 /* NOTE host side sets DMAENAB later than this; both are
426 * OK since the transfer dma glue (between CPPI and Mentor
427 * fifos) just tells CPPI it could start. Data only moves
428 * to the USB TX fifo when both fifos are ready.
429 */
430
431 /* "mode" is irrelevant here; handle terminating ZLPs like
432 * PIO does, since the hardware RNDIS mode seems unreliable
433 * except for the last-packet-is-already-short case.
434 */
435 use_dma = use_dma && c->channel_program(
436 musb_ep->dma, musb_ep->packet_sz,
437 0,
438 request->dma + request->actual,
439 request_size);
440 if (!use_dma) {
441 c->channel_release(musb_ep->dma);
442 musb_ep->dma = NULL;
443 csr &= ~MUSB_TXCSR_DMAENAB;
444 musb_writew(epio, MUSB_TXCSR, csr);
445 /* invariant: prequest->buf is non-null */
446 }
447 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
448 use_dma = use_dma && c->channel_program(
449 musb_ep->dma, musb_ep->packet_sz,
450 request->zero,
451 request->dma + request->actual,
452 request_size);
453 #endif
454 }
455 #endif
456
457 if (!use_dma) {
458 /*
459 * Unmap the dma buffer back to cpu if dma channel
460 * programming fails
461 */
462 unmap_dma_buffer(req, musb);
463
464 musb_write_fifo(musb_ep->hw_ep, fifo_count,
465 (u8 *) (request->buf + request->actual));
466 request->actual += fifo_count;
467 csr |= MUSB_TXCSR_TXPKTRDY;
468 csr &= ~MUSB_TXCSR_P_UNDERRUN;
469 musb_writew(epio, MUSB_TXCSR, csr);
470 }
471
472 /* host may already have the data when this message shows... */
473 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
474 musb_ep->end_point.name, use_dma ? "dma" : "pio",
475 request->actual, request->length,
476 musb_readw(epio, MUSB_TXCSR),
477 fifo_count,
478 musb_readw(epio, MUSB_TXMAXP));
479 }
480
481 /*
482 * FIFO state update (e.g. data ready).
483 * Called from IRQ, with controller locked.
484 */
485 void musb_g_tx(struct musb *musb, u8 epnum)
486 {
487 u16 csr;
488 struct usb_request *request;
489 u8 __iomem *mbase = musb->mregs;
490 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
491 void __iomem *epio = musb->endpoints[epnum].regs;
492 struct dma_channel *dma;
493
494 musb_ep_select(mbase, epnum);
495 request = next_request(musb_ep);
496
497 csr = musb_readw(epio, MUSB_TXCSR);
498 DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
499
500 dma = is_dma_capable() ? musb_ep->dma : NULL;
501
502 /*
503 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
504 * probably rates reporting as a host error.
505 */
506 if (csr & MUSB_TXCSR_P_SENTSTALL) {
507 csr |= MUSB_TXCSR_P_WZC_BITS;
508 csr &= ~MUSB_TXCSR_P_SENTSTALL;
509 musb_writew(epio, MUSB_TXCSR, csr);
510 return;
511 }
512
513 if (csr & MUSB_TXCSR_P_UNDERRUN) {
514 /* We NAKed, no big deal... little reason to care. */
515 csr |= MUSB_TXCSR_P_WZC_BITS;
516 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
517 musb_writew(epio, MUSB_TXCSR, csr);
518 DBG(20, "underrun on ep%d, req %p\n", epnum, request);
519 }
520
521 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
522 /*
523 * SHOULD NOT HAPPEN... has with CPPI though, after
524 * changing SENDSTALL (and other cases); harmless?
525 */
526 DBG(5, "%s dma still busy?\n", musb_ep->end_point.name);
527 return;
528 }
529
530 if (request) {
531 u8 is_dma = 0;
532
533 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
534 is_dma = 1;
535 csr |= MUSB_TXCSR_P_WZC_BITS;
536 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
537 MUSB_TXCSR_TXPKTRDY);
538 musb_writew(epio, MUSB_TXCSR, csr);
539 /* Ensure writebuffer is empty. */
540 csr = musb_readw(epio, MUSB_TXCSR);
541 request->actual += musb_ep->dma->actual_len;
542 DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
543 epnum, csr, musb_ep->dma->actual_len, request);
544 }
545
546 /*
547 * First, maybe a terminating short packet. Some DMA
548 * engines might handle this by themselves.
549 */
550 if ((request->zero && request->length
551 && (request->length % musb_ep->packet_sz == 0)
552 && (request->actual == request->length))
553 #ifdef CONFIG_USB_INVENTRA_DMA
554 || (is_dma && (!dma->desired_mode ||
555 (request->actual &
556 (musb_ep->packet_sz - 1))))
557 #endif
558 ) {
559 /*
560 * On DMA completion, FIFO may not be
561 * available yet...
562 */
563 if (csr & MUSB_TXCSR_TXPKTRDY)
564 return;
565
566 DBG(4, "sending zero pkt\n");
567 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
568 | MUSB_TXCSR_TXPKTRDY);
569 request->zero = 0;
570 }
571
572 if (request->actual == request->length) {
573 musb_g_giveback(musb_ep, request, 0);
574 request = musb_ep->desc ? next_request(musb_ep) : NULL;
575 if (!request) {
576 DBG(4, "%s idle now\n",
577 musb_ep->end_point.name);
578 return;
579 }
580 }
581
582 txstate(musb, to_musb_request(request));
583 }
584 }
585
586 /* ------------------------------------------------------------ */
587
588 #ifdef CONFIG_USB_INVENTRA_DMA
589
590 /* Peripheral rx (OUT) using Mentor DMA works as follows:
591 - Only mode 0 is used.
592
593 - Request is queued by the gadget class driver.
594 -> if queue was previously empty, rxstate()
595
596 - Host sends OUT token which causes an endpoint interrupt
597 /\ -> RxReady
598 | -> if request queued, call rxstate
599 | /\ -> setup DMA
600 | | -> DMA interrupt on completion
601 | | -> RxReady
602 | | -> stop DMA
603 | | -> ack the read
604 | | -> if data recd = max expected
605 | | by the request, or host
606 | | sent a short packet,
607 | | complete the request,
608 | | and start the next one.
609 | |_____________________________________|
610 | else just wait for the host
611 | to send the next OUT token.
612 |__________________________________________________|
613
614 * Non-Mentor DMA engines can of course work differently.
615 */
616
617 #endif
618
619 /*
620 * Context: controller locked, IRQs blocked, endpoint selected
621 */
622 static void rxstate(struct musb *musb, struct musb_request *req)
623 {
624 const u8 epnum = req->epnum;
625 struct usb_request *request = &req->request;
626 struct musb_ep *musb_ep;
627 void __iomem *epio = musb->endpoints[epnum].regs;
628 unsigned fifo_count = 0;
629 u16 len;
630 u16 csr = musb_readw(epio, MUSB_RXCSR);
631 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
632
633 if (hw_ep->is_shared_fifo)
634 musb_ep = &hw_ep->ep_in;
635 else
636 musb_ep = &hw_ep->ep_out;
637
638 len = musb_ep->packet_sz;
639
640 /* We shouldn't get here while DMA is active, but we do... */
641 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
642 DBG(4, "DMA pending...\n");
643 return;
644 }
645
646 if (csr & MUSB_RXCSR_P_SENDSTALL) {
647 DBG(5, "%s stalling, RXCSR %04x\n",
648 musb_ep->end_point.name, csr);
649 return;
650 }
651
652 if (is_cppi_enabled() && is_buffer_mapped(req)) {
653 struct dma_controller *c = musb->dma_controller;
654 struct dma_channel *channel = musb_ep->dma;
655
656 /* NOTE: CPPI won't actually stop advancing the DMA
657 * queue after short packet transfers, so this is almost
658 * always going to run as IRQ-per-packet DMA so that
659 * faults will be handled correctly.
660 */
661 if (c->channel_program(channel,
662 musb_ep->packet_sz,
663 !request->short_not_ok,
664 request->dma + request->actual,
665 request->length - request->actual)) {
666
667 /* make sure that if an rxpkt arrived after the irq,
668 * the cppi engine will be ready to take it as soon
669 * as DMA is enabled
670 */
671 csr &= ~(MUSB_RXCSR_AUTOCLEAR
672 | MUSB_RXCSR_DMAMODE);
673 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
674 musb_writew(epio, MUSB_RXCSR, csr);
675 return;
676 }
677 }
678
679 if (csr & MUSB_RXCSR_RXPKTRDY) {
680 len = musb_readw(epio, MUSB_RXCOUNT);
681 if (request->actual < request->length) {
682 #ifdef CONFIG_USB_INVENTRA_DMA
683 if (is_buffer_mapped(req)) {
684 struct dma_controller *c;
685 struct dma_channel *channel;
686 int use_dma = 0;
687
688 c = musb->dma_controller;
689 channel = musb_ep->dma;
690
691 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
692 * mode 0 only. So we do not get endpoint interrupts due to DMA
693 * completion. We only get interrupts from DMA controller.
694 *
695 * We could operate in DMA mode 1 if we knew the size of the tranfer
696 * in advance. For mass storage class, request->length = what the host
697 * sends, so that'd work. But for pretty much everything else,
698 * request->length is routinely more than what the host sends. For
699 * most these gadgets, end of is signified either by a short packet,
700 * or filling the last byte of the buffer. (Sending extra data in
701 * that last pckate should trigger an overflow fault.) But in mode 1,
702 * we don't get DMA completion interrrupt for short packets.
703 *
704 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
705 * to get endpoint interrupt on every DMA req, but that didn't seem
706 * to work reliably.
707 *
708 * REVISIT an updated g_file_storage can set req->short_not_ok, which
709 * then becomes usable as a runtime "use mode 1" hint...
710 */
711
712 csr |= MUSB_RXCSR_DMAENAB;
713 #ifdef USE_MODE1
714 csr |= MUSB_RXCSR_AUTOCLEAR;
715 /* csr |= MUSB_RXCSR_DMAMODE; */
716
717 /* this special sequence (enabling and then
718 * disabling MUSB_RXCSR_DMAMODE) is required
719 * to get DMAReq to activate
720 */
721 musb_writew(epio, MUSB_RXCSR,
722 csr | MUSB_RXCSR_DMAMODE);
723 #else
724 if (!musb_ep->hb_mult &&
725 musb_ep->hw_ep->rx_double_buffered)
726 csr |= MUSB_RXCSR_AUTOCLEAR;
727 #endif
728 musb_writew(epio, MUSB_RXCSR, csr);
729
730 if (request->actual < request->length) {
731 int transfer_size = 0;
732 #ifdef USE_MODE1
733 transfer_size = min(request->length - request->actual,
734 channel->max_len);
735 #else
736 transfer_size = min(request->length - request->actual,
737 (unsigned)len);
738 #endif
739 if (transfer_size <= musb_ep->packet_sz)
740 musb_ep->dma->desired_mode = 0;
741 else
742 musb_ep->dma->desired_mode = 1;
743
744 use_dma = c->channel_program(
745 channel,
746 musb_ep->packet_sz,
747 channel->desired_mode,
748 request->dma
749 + request->actual,
750 transfer_size);
751 }
752
753 if (use_dma)
754 return;
755 }
756 #endif /* Mentor's DMA */
757
758 fifo_count = request->length - request->actual;
759 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
760 musb_ep->end_point.name,
761 len, fifo_count,
762 musb_ep->packet_sz);
763
764 fifo_count = min_t(unsigned, len, fifo_count);
765
766 #ifdef CONFIG_USB_TUSB_OMAP_DMA
767 if (tusb_dma_omap() && is_buffer_mapped(req)) {
768 struct dma_controller *c = musb->dma_controller;
769 struct dma_channel *channel = musb_ep->dma;
770 u32 dma_addr = request->dma + request->actual;
771 int ret;
772
773 ret = c->channel_program(channel,
774 musb_ep->packet_sz,
775 channel->desired_mode,
776 dma_addr,
777 fifo_count);
778 if (ret)
779 return;
780 }
781 #endif
782 /*
783 * Unmap the dma buffer back to cpu if dma channel
784 * programming fails. This buffer is mapped if the
785 * channel allocation is successful
786 */
787 if (is_buffer_mapped(req)) {
788 unmap_dma_buffer(req, musb);
789
790 /*
791 * Clear DMAENAB and AUTOCLEAR for the
792 * PIO mode transfer
793 */
794 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
795 musb_writew(epio, MUSB_RXCSR, csr);
796 }
797
798 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
799 (request->buf + request->actual));
800 request->actual += fifo_count;
801
802 /* REVISIT if we left anything in the fifo, flush
803 * it and report -EOVERFLOW
804 */
805
806 /* ack the read! */
807 csr |= MUSB_RXCSR_P_WZC_BITS;
808 csr &= ~MUSB_RXCSR_RXPKTRDY;
809 musb_writew(epio, MUSB_RXCSR, csr);
810 }
811 }
812
813 /* reach the end or short packet detected */
814 if (request->actual == request->length || len < musb_ep->packet_sz)
815 musb_g_giveback(musb_ep, request, 0);
816 }
817
818 /*
819 * Data ready for a request; called from IRQ
820 */
821 void musb_g_rx(struct musb *musb, u8 epnum)
822 {
823 u16 csr;
824 struct usb_request *request;
825 void __iomem *mbase = musb->mregs;
826 struct musb_ep *musb_ep;
827 void __iomem *epio = musb->endpoints[epnum].regs;
828 struct dma_channel *dma;
829 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
830
831 if (hw_ep->is_shared_fifo)
832 musb_ep = &hw_ep->ep_in;
833 else
834 musb_ep = &hw_ep->ep_out;
835
836 musb_ep_select(mbase, epnum);
837
838 request = next_request(musb_ep);
839 if (!request)
840 return;
841
842 csr = musb_readw(epio, MUSB_RXCSR);
843 dma = is_dma_capable() ? musb_ep->dma : NULL;
844
845 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
846 csr, dma ? " (dma)" : "", request);
847
848 if (csr & MUSB_RXCSR_P_SENTSTALL) {
849 csr |= MUSB_RXCSR_P_WZC_BITS;
850 csr &= ~MUSB_RXCSR_P_SENTSTALL;
851 musb_writew(epio, MUSB_RXCSR, csr);
852 return;
853 }
854
855 if (csr & MUSB_RXCSR_P_OVERRUN) {
856 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
857 csr &= ~MUSB_RXCSR_P_OVERRUN;
858 musb_writew(epio, MUSB_RXCSR, csr);
859
860 DBG(3, "%s iso overrun on %p\n", musb_ep->name, request);
861 if (request->status == -EINPROGRESS)
862 request->status = -EOVERFLOW;
863 }
864 if (csr & MUSB_RXCSR_INCOMPRX) {
865 /* REVISIT not necessarily an error */
866 DBG(4, "%s, incomprx\n", musb_ep->end_point.name);
867 }
868
869 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
870 /* "should not happen"; likely RXPKTRDY pending for DMA */
871 DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1,
872 "%s busy, csr %04x\n",
873 musb_ep->end_point.name, csr);
874 return;
875 }
876
877 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
878 csr &= ~(MUSB_RXCSR_AUTOCLEAR
879 | MUSB_RXCSR_DMAENAB
880 | MUSB_RXCSR_DMAMODE);
881 musb_writew(epio, MUSB_RXCSR,
882 MUSB_RXCSR_P_WZC_BITS | csr);
883
884 request->actual += musb_ep->dma->actual_len;
885
886 DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
887 epnum, csr,
888 musb_readw(epio, MUSB_RXCSR),
889 musb_ep->dma->actual_len, request);
890
891 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
892 /* Autoclear doesn't clear RxPktRdy for short packets */
893 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
894 || (dma->actual_len
895 & (musb_ep->packet_sz - 1))) {
896 /* ack the read! */
897 csr &= ~MUSB_RXCSR_RXPKTRDY;
898 musb_writew(epio, MUSB_RXCSR, csr);
899 }
900
901 /* incomplete, and not short? wait for next IN packet */
902 if ((request->actual < request->length)
903 && (musb_ep->dma->actual_len
904 == musb_ep->packet_sz)) {
905 /* In double buffer case, continue to unload fifo if
906 * there is Rx packet in FIFO.
907 **/
908 csr = musb_readw(epio, MUSB_RXCSR);
909 if ((csr & MUSB_RXCSR_RXPKTRDY) &&
910 hw_ep->rx_double_buffered)
911 goto exit;
912 return;
913 }
914 #endif
915 musb_g_giveback(musb_ep, request, 0);
916
917 request = next_request(musb_ep);
918 if (!request)
919 return;
920 }
921 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
922 exit:
923 #endif
924 /* Analyze request */
925 rxstate(musb, to_musb_request(request));
926 }
927
928 /* ------------------------------------------------------------ */
929
930 static int musb_gadget_enable(struct usb_ep *ep,
931 const struct usb_endpoint_descriptor *desc)
932 {
933 unsigned long flags;
934 struct musb_ep *musb_ep;
935 struct musb_hw_ep *hw_ep;
936 void __iomem *regs;
937 struct musb *musb;
938 void __iomem *mbase;
939 u8 epnum;
940 u16 csr;
941 unsigned tmp;
942 int status = -EINVAL;
943
944 if (!ep || !desc)
945 return -EINVAL;
946
947 musb_ep = to_musb_ep(ep);
948 hw_ep = musb_ep->hw_ep;
949 regs = hw_ep->regs;
950 musb = musb_ep->musb;
951 mbase = musb->mregs;
952 epnum = musb_ep->current_epnum;
953
954 spin_lock_irqsave(&musb->lock, flags);
955
956 if (musb_ep->desc) {
957 status = -EBUSY;
958 goto fail;
959 }
960 musb_ep->type = usb_endpoint_type(desc);
961
962 /* check direction and (later) maxpacket size against endpoint */
963 if (usb_endpoint_num(desc) != epnum)
964 goto fail;
965
966 /* REVISIT this rules out high bandwidth periodic transfers */
967 tmp = le16_to_cpu(desc->wMaxPacketSize);
968 if (tmp & ~0x07ff) {
969 int ok;
970
971 if (usb_endpoint_dir_in(desc))
972 ok = musb->hb_iso_tx;
973 else
974 ok = musb->hb_iso_rx;
975
976 if (!ok) {
977 DBG(4, "%s: not support ISO high bandwidth\n", __func__);
978 goto fail;
979 }
980 musb_ep->hb_mult = (tmp >> 11) & 3;
981 } else {
982 musb_ep->hb_mult = 0;
983 }
984
985 musb_ep->packet_sz = tmp & 0x7ff;
986 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
987
988 /* enable the interrupts for the endpoint, set the endpoint
989 * packet size (or fail), set the mode, clear the fifo
990 */
991 musb_ep_select(mbase, epnum);
992 if (usb_endpoint_dir_in(desc)) {
993 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
994
995 if (hw_ep->is_shared_fifo)
996 musb_ep->is_in = 1;
997 if (!musb_ep->is_in)
998 goto fail;
999
1000 if (tmp > hw_ep->max_packet_sz_tx) {
1001 DBG(4, "%s: packet size beyond hw fifo size\n", __func__);
1002 goto fail;
1003 }
1004
1005 int_txe |= (1 << epnum);
1006 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1007
1008 /* REVISIT if can_bulk_split(), use by updating "tmp";
1009 * likewise high bandwidth periodic tx
1010 */
1011 /* Set TXMAXP with the FIFO size of the endpoint
1012 * to disable double buffering mode.
1013 */
1014 if (musb->double_buffer_not_ok)
1015 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
1016 else
1017 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
1018 | (musb_ep->hb_mult << 11));
1019
1020 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
1021 if (musb_readw(regs, MUSB_TXCSR)
1022 & MUSB_TXCSR_FIFONOTEMPTY)
1023 csr |= MUSB_TXCSR_FLUSHFIFO;
1024 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1025 csr |= MUSB_TXCSR_P_ISO;
1026
1027 /* set twice in case of double buffering */
1028 musb_writew(regs, MUSB_TXCSR, csr);
1029 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1030 musb_writew(regs, MUSB_TXCSR, csr);
1031
1032 } else {
1033 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
1034
1035 if (hw_ep->is_shared_fifo)
1036 musb_ep->is_in = 0;
1037 if (musb_ep->is_in)
1038 goto fail;
1039
1040 if (tmp > hw_ep->max_packet_sz_rx) {
1041 DBG(4, "%s: packet size beyond hw fifo size\n", __func__);
1042 goto fail;
1043 }
1044
1045 int_rxe |= (1 << epnum);
1046 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
1047
1048 /* REVISIT if can_bulk_combine() use by updating "tmp"
1049 * likewise high bandwidth periodic rx
1050 */
1051 /* Set RXMAXP with the FIFO size of the endpoint
1052 * to disable double buffering mode.
1053 */
1054 if (musb->double_buffer_not_ok)
1055 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
1056 else
1057 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1058 | (musb_ep->hb_mult << 11));
1059
1060 /* force shared fifo to OUT-only mode */
1061 if (hw_ep->is_shared_fifo) {
1062 csr = musb_readw(regs, MUSB_TXCSR);
1063 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1064 musb_writew(regs, MUSB_TXCSR, csr);
1065 }
1066
1067 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1068 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1069 csr |= MUSB_RXCSR_P_ISO;
1070 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1071 csr |= MUSB_RXCSR_DISNYET;
1072
1073 /* set twice in case of double buffering */
1074 musb_writew(regs, MUSB_RXCSR, csr);
1075 musb_writew(regs, MUSB_RXCSR, csr);
1076 }
1077
1078 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1079 * for some reason you run out of channels here.
1080 */
1081 if (is_dma_capable() && musb->dma_controller) {
1082 struct dma_controller *c = musb->dma_controller;
1083
1084 musb_ep->dma = c->channel_alloc(c, hw_ep,
1085 (desc->bEndpointAddress & USB_DIR_IN));
1086 } else
1087 musb_ep->dma = NULL;
1088
1089 musb_ep->desc = desc;
1090 musb_ep->busy = 0;
1091 musb_ep->wedged = 0;
1092 status = 0;
1093
1094 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1095 musb_driver_name, musb_ep->end_point.name,
1096 ({ char *s; switch (musb_ep->type) {
1097 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
1098 case USB_ENDPOINT_XFER_INT: s = "int"; break;
1099 default: s = "iso"; break;
1100 }; s; }),
1101 musb_ep->is_in ? "IN" : "OUT",
1102 musb_ep->dma ? "dma, " : "",
1103 musb_ep->packet_sz);
1104
1105 schedule_work(&musb->irq_work);
1106
1107 fail:
1108 spin_unlock_irqrestore(&musb->lock, flags);
1109 return status;
1110 }
1111
1112 /*
1113 * Disable an endpoint flushing all requests queued.
1114 */
1115 static int musb_gadget_disable(struct usb_ep *ep)
1116 {
1117 unsigned long flags;
1118 struct musb *musb;
1119 u8 epnum;
1120 struct musb_ep *musb_ep;
1121 void __iomem *epio;
1122 int status = 0;
1123
1124 musb_ep = to_musb_ep(ep);
1125 musb = musb_ep->musb;
1126 epnum = musb_ep->current_epnum;
1127 epio = musb->endpoints[epnum].regs;
1128
1129 spin_lock_irqsave(&musb->lock, flags);
1130 musb_ep_select(musb->mregs, epnum);
1131
1132 /* zero the endpoint sizes */
1133 if (musb_ep->is_in) {
1134 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
1135 int_txe &= ~(1 << epnum);
1136 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
1137 musb_writew(epio, MUSB_TXMAXP, 0);
1138 } else {
1139 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
1140 int_rxe &= ~(1 << epnum);
1141 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
1142 musb_writew(epio, MUSB_RXMAXP, 0);
1143 }
1144
1145 musb_ep->desc = NULL;
1146
1147 /* abort all pending DMA and requests */
1148 nuke(musb_ep, -ESHUTDOWN);
1149
1150 schedule_work(&musb->irq_work);
1151
1152 spin_unlock_irqrestore(&(musb->lock), flags);
1153
1154 DBG(2, "%s\n", musb_ep->end_point.name);
1155
1156 return status;
1157 }
1158
1159 /*
1160 * Allocate a request for an endpoint.
1161 * Reused by ep0 code.
1162 */
1163 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1164 {
1165 struct musb_ep *musb_ep = to_musb_ep(ep);
1166 struct musb_request *request = NULL;
1167
1168 request = kzalloc(sizeof *request, gfp_flags);
1169 if (!request) {
1170 DBG(4, "not enough memory\n");
1171 return NULL;
1172 }
1173
1174 INIT_LIST_HEAD(&request->request.list);
1175 request->request.dma = DMA_ADDR_INVALID;
1176 request->epnum = musb_ep->current_epnum;
1177 request->ep = musb_ep;
1178
1179 return &request->request;
1180 }
1181
1182 /*
1183 * Free a request
1184 * Reused by ep0 code.
1185 */
1186 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1187 {
1188 kfree(to_musb_request(req));
1189 }
1190
1191 static LIST_HEAD(buffers);
1192
1193 struct free_record {
1194 struct list_head list;
1195 struct device *dev;
1196 unsigned bytes;
1197 dma_addr_t dma;
1198 };
1199
1200 /*
1201 * Context: controller locked, IRQs blocked.
1202 */
1203 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1204 {
1205 DBG(3, "<== %s request %p len %u on hw_ep%d\n",
1206 req->tx ? "TX/IN" : "RX/OUT",
1207 &req->request, req->request.length, req->epnum);
1208
1209 musb_ep_select(musb->mregs, req->epnum);
1210 if (req->tx)
1211 txstate(musb, req);
1212 else
1213 rxstate(musb, req);
1214 }
1215
1216 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1217 gfp_t gfp_flags)
1218 {
1219 struct musb_ep *musb_ep;
1220 struct musb_request *request;
1221 struct musb *musb;
1222 int status = 0;
1223 unsigned long lockflags;
1224
1225 if (!ep || !req)
1226 return -EINVAL;
1227 if (!req->buf)
1228 return -ENODATA;
1229
1230 musb_ep = to_musb_ep(ep);
1231 musb = musb_ep->musb;
1232
1233 request = to_musb_request(req);
1234 request->musb = musb;
1235
1236 if (request->ep != musb_ep)
1237 return -EINVAL;
1238
1239 DBG(4, "<== to %s request=%p\n", ep->name, req);
1240
1241 /* request is mine now... */
1242 request->request.actual = 0;
1243 request->request.status = -EINPROGRESS;
1244 request->epnum = musb_ep->current_epnum;
1245 request->tx = musb_ep->is_in;
1246
1247 map_dma_buffer(request, musb, musb_ep);
1248
1249 spin_lock_irqsave(&musb->lock, lockflags);
1250
1251 /* don't queue if the ep is down */
1252 if (!musb_ep->desc) {
1253 DBG(4, "req %p queued to %s while ep %s\n",
1254 req, ep->name, "disabled");
1255 status = -ESHUTDOWN;
1256 goto cleanup;
1257 }
1258
1259 /* add request to the list */
1260 list_add_tail(&(request->request.list), &(musb_ep->req_list));
1261
1262 /* it this is the head of the queue, start i/o ... */
1263 if (!musb_ep->busy && &request->request.list == musb_ep->req_list.next)
1264 musb_ep_restart(musb, request);
1265
1266 cleanup:
1267 spin_unlock_irqrestore(&musb->lock, lockflags);
1268 return status;
1269 }
1270
1271 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1272 {
1273 struct musb_ep *musb_ep = to_musb_ep(ep);
1274 struct usb_request *r;
1275 unsigned long flags;
1276 int status = 0;
1277 struct musb *musb = musb_ep->musb;
1278
1279 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1280 return -EINVAL;
1281
1282 spin_lock_irqsave(&musb->lock, flags);
1283
1284 list_for_each_entry(r, &musb_ep->req_list, list) {
1285 if (r == request)
1286 break;
1287 }
1288 if (r != request) {
1289 DBG(3, "request %p not queued to %s\n", request, ep->name);
1290 status = -EINVAL;
1291 goto done;
1292 }
1293
1294 /* if the hardware doesn't have the request, easy ... */
1295 if (musb_ep->req_list.next != &request->list || musb_ep->busy)
1296 musb_g_giveback(musb_ep, request, -ECONNRESET);
1297
1298 /* ... else abort the dma transfer ... */
1299 else if (is_dma_capable() && musb_ep->dma) {
1300 struct dma_controller *c = musb->dma_controller;
1301
1302 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1303 if (c->channel_abort)
1304 status = c->channel_abort(musb_ep->dma);
1305 else
1306 status = -EBUSY;
1307 if (status == 0)
1308 musb_g_giveback(musb_ep, request, -ECONNRESET);
1309 } else {
1310 /* NOTE: by sticking to easily tested hardware/driver states,
1311 * we leave counting of in-flight packets imprecise.
1312 */
1313 musb_g_giveback(musb_ep, request, -ECONNRESET);
1314 }
1315
1316 done:
1317 spin_unlock_irqrestore(&musb->lock, flags);
1318 return status;
1319 }
1320
1321 /*
1322 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1323 * data but will queue requests.
1324 *
1325 * exported to ep0 code
1326 */
1327 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1328 {
1329 struct musb_ep *musb_ep = to_musb_ep(ep);
1330 u8 epnum = musb_ep->current_epnum;
1331 struct musb *musb = musb_ep->musb;
1332 void __iomem *epio = musb->endpoints[epnum].regs;
1333 void __iomem *mbase;
1334 unsigned long flags;
1335 u16 csr;
1336 struct musb_request *request;
1337 int status = 0;
1338
1339 if (!ep)
1340 return -EINVAL;
1341 mbase = musb->mregs;
1342
1343 spin_lock_irqsave(&musb->lock, flags);
1344
1345 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1346 status = -EINVAL;
1347 goto done;
1348 }
1349
1350 musb_ep_select(mbase, epnum);
1351
1352 request = to_musb_request(next_request(musb_ep));
1353 if (value) {
1354 if (request) {
1355 DBG(3, "request in progress, cannot halt %s\n",
1356 ep->name);
1357 status = -EAGAIN;
1358 goto done;
1359 }
1360 /* Cannot portably stall with non-empty FIFO */
1361 if (musb_ep->is_in) {
1362 csr = musb_readw(epio, MUSB_TXCSR);
1363 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1364 DBG(3, "FIFO busy, cannot halt %s\n", ep->name);
1365 status = -EAGAIN;
1366 goto done;
1367 }
1368 }
1369 } else
1370 musb_ep->wedged = 0;
1371
1372 /* set/clear the stall and toggle bits */
1373 DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1374 if (musb_ep->is_in) {
1375 csr = musb_readw(epio, MUSB_TXCSR);
1376 csr |= MUSB_TXCSR_P_WZC_BITS
1377 | MUSB_TXCSR_CLRDATATOG;
1378 if (value)
1379 csr |= MUSB_TXCSR_P_SENDSTALL;
1380 else
1381 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1382 | MUSB_TXCSR_P_SENTSTALL);
1383 csr &= ~MUSB_TXCSR_TXPKTRDY;
1384 musb_writew(epio, MUSB_TXCSR, csr);
1385 } else {
1386 csr = musb_readw(epio, MUSB_RXCSR);
1387 csr |= MUSB_RXCSR_P_WZC_BITS
1388 | MUSB_RXCSR_FLUSHFIFO
1389 | MUSB_RXCSR_CLRDATATOG;
1390 if (value)
1391 csr |= MUSB_RXCSR_P_SENDSTALL;
1392 else
1393 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1394 | MUSB_RXCSR_P_SENTSTALL);
1395 musb_writew(epio, MUSB_RXCSR, csr);
1396 }
1397
1398 /* maybe start the first request in the queue */
1399 if (!musb_ep->busy && !value && request) {
1400 DBG(3, "restarting the request\n");
1401 musb_ep_restart(musb, request);
1402 }
1403
1404 done:
1405 spin_unlock_irqrestore(&musb->lock, flags);
1406 return status;
1407 }
1408
1409 /*
1410 * Sets the halt feature with the clear requests ignored
1411 */
1412 static int musb_gadget_set_wedge(struct usb_ep *ep)
1413 {
1414 struct musb_ep *musb_ep = to_musb_ep(ep);
1415
1416 if (!ep)
1417 return -EINVAL;
1418
1419 musb_ep->wedged = 1;
1420
1421 return usb_ep_set_halt(ep);
1422 }
1423
1424 static int musb_gadget_fifo_status(struct usb_ep *ep)
1425 {
1426 struct musb_ep *musb_ep = to_musb_ep(ep);
1427 void __iomem *epio = musb_ep->hw_ep->regs;
1428 int retval = -EINVAL;
1429
1430 if (musb_ep->desc && !musb_ep->is_in) {
1431 struct musb *musb = musb_ep->musb;
1432 int epnum = musb_ep->current_epnum;
1433 void __iomem *mbase = musb->mregs;
1434 unsigned long flags;
1435
1436 spin_lock_irqsave(&musb->lock, flags);
1437
1438 musb_ep_select(mbase, epnum);
1439 /* FIXME return zero unless RXPKTRDY is set */
1440 retval = musb_readw(epio, MUSB_RXCOUNT);
1441
1442 spin_unlock_irqrestore(&musb->lock, flags);
1443 }
1444 return retval;
1445 }
1446
1447 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1448 {
1449 struct musb_ep *musb_ep = to_musb_ep(ep);
1450 struct musb *musb = musb_ep->musb;
1451 u8 epnum = musb_ep->current_epnum;
1452 void __iomem *epio = musb->endpoints[epnum].regs;
1453 void __iomem *mbase;
1454 unsigned long flags;
1455 u16 csr, int_txe;
1456
1457 mbase = musb->mregs;
1458
1459 spin_lock_irqsave(&musb->lock, flags);
1460 musb_ep_select(mbase, (u8) epnum);
1461
1462 /* disable interrupts */
1463 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1464 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
1465
1466 if (musb_ep->is_in) {
1467 csr = musb_readw(epio, MUSB_TXCSR);
1468 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1469 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1470 musb_writew(epio, MUSB_TXCSR, csr);
1471 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1472 musb_writew(epio, MUSB_TXCSR, csr);
1473 }
1474 } else {
1475 csr = musb_readw(epio, MUSB_RXCSR);
1476 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1477 musb_writew(epio, MUSB_RXCSR, csr);
1478 musb_writew(epio, MUSB_RXCSR, csr);
1479 }
1480
1481 /* re-enable interrupt */
1482 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1483 spin_unlock_irqrestore(&musb->lock, flags);
1484 }
1485
1486 static const struct usb_ep_ops musb_ep_ops = {
1487 .enable = musb_gadget_enable,
1488 .disable = musb_gadget_disable,
1489 .alloc_request = musb_alloc_request,
1490 .free_request = musb_free_request,
1491 .queue = musb_gadget_queue,
1492 .dequeue = musb_gadget_dequeue,
1493 .set_halt = musb_gadget_set_halt,
1494 .set_wedge = musb_gadget_set_wedge,
1495 .fifo_status = musb_gadget_fifo_status,
1496 .fifo_flush = musb_gadget_fifo_flush
1497 };
1498
1499 /* ----------------------------------------------------------------------- */
1500
1501 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1502 {
1503 struct musb *musb = gadget_to_musb(gadget);
1504
1505 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1506 }
1507
1508 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1509 {
1510 struct musb *musb = gadget_to_musb(gadget);
1511 void __iomem *mregs = musb->mregs;
1512 unsigned long flags;
1513 int status = -EINVAL;
1514 u8 power, devctl;
1515 int retries;
1516
1517 spin_lock_irqsave(&musb->lock, flags);
1518
1519 switch (musb->xceiv->state) {
1520 case OTG_STATE_B_PERIPHERAL:
1521 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1522 * that's part of the standard usb 1.1 state machine, and
1523 * doesn't affect OTG transitions.
1524 */
1525 if (musb->may_wakeup && musb->is_suspended)
1526 break;
1527 goto done;
1528 case OTG_STATE_B_IDLE:
1529 /* Start SRP ... OTG not required. */
1530 devctl = musb_readb(mregs, MUSB_DEVCTL);
1531 DBG(2, "Sending SRP: devctl: %02x\n", devctl);
1532 devctl |= MUSB_DEVCTL_SESSION;
1533 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1534 devctl = musb_readb(mregs, MUSB_DEVCTL);
1535 retries = 100;
1536 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1537 devctl = musb_readb(mregs, MUSB_DEVCTL);
1538 if (retries-- < 1)
1539 break;
1540 }
1541 retries = 10000;
1542 while (devctl & MUSB_DEVCTL_SESSION) {
1543 devctl = musb_readb(mregs, MUSB_DEVCTL);
1544 if (retries-- < 1)
1545 break;
1546 }
1547
1548 /* Block idling for at least 1s */
1549 musb_platform_try_idle(musb,
1550 jiffies + msecs_to_jiffies(1 * HZ));
1551
1552 status = 0;
1553 goto done;
1554 default:
1555 DBG(2, "Unhandled wake: %s\n", otg_state_string(musb));
1556 goto done;
1557 }
1558
1559 status = 0;
1560
1561 power = musb_readb(mregs, MUSB_POWER);
1562 power |= MUSB_POWER_RESUME;
1563 musb_writeb(mregs, MUSB_POWER, power);
1564 DBG(2, "issue wakeup\n");
1565
1566 /* FIXME do this next chunk in a timer callback, no udelay */
1567 mdelay(2);
1568
1569 power = musb_readb(mregs, MUSB_POWER);
1570 power &= ~MUSB_POWER_RESUME;
1571 musb_writeb(mregs, MUSB_POWER, power);
1572 done:
1573 spin_unlock_irqrestore(&musb->lock, flags);
1574 return status;
1575 }
1576
1577 static int
1578 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1579 {
1580 struct musb *musb = gadget_to_musb(gadget);
1581
1582 musb->is_self_powered = !!is_selfpowered;
1583 return 0;
1584 }
1585
1586 static void musb_pullup(struct musb *musb, int is_on)
1587 {
1588 u8 power;
1589
1590 power = musb_readb(musb->mregs, MUSB_POWER);
1591 if (is_on)
1592 power |= MUSB_POWER_SOFTCONN;
1593 else
1594 power &= ~MUSB_POWER_SOFTCONN;
1595
1596 /* FIXME if on, HdrcStart; if off, HdrcStop */
1597
1598 DBG(3, "gadget %s D+ pullup %s\n",
1599 musb->gadget_driver->function, is_on ? "on" : "off");
1600 musb_writeb(musb->mregs, MUSB_POWER, power);
1601 }
1602
1603 #if 0
1604 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1605 {
1606 DBG(2, "<= %s =>\n", __func__);
1607
1608 /*
1609 * FIXME iff driver's softconnect flag is set (as it is during probe,
1610 * though that can clear it), just musb_pullup().
1611 */
1612
1613 return -EINVAL;
1614 }
1615 #endif
1616
1617 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1618 {
1619 struct musb *musb = gadget_to_musb(gadget);
1620
1621 if (!musb->xceiv->set_power)
1622 return -EOPNOTSUPP;
1623 return otg_set_power(musb->xceiv, mA);
1624 }
1625
1626 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1627 {
1628 struct musb *musb = gadget_to_musb(gadget);
1629 unsigned long flags;
1630
1631 is_on = !!is_on;
1632
1633 /* NOTE: this assumes we are sensing vbus; we'd rather
1634 * not pullup unless the B-session is active.
1635 */
1636 spin_lock_irqsave(&musb->lock, flags);
1637 if (is_on != musb->softconnect) {
1638 musb->softconnect = is_on;
1639 musb_pullup(musb, is_on);
1640 }
1641 spin_unlock_irqrestore(&musb->lock, flags);
1642 return 0;
1643 }
1644
1645 static const struct usb_gadget_ops musb_gadget_operations = {
1646 .get_frame = musb_gadget_get_frame,
1647 .wakeup = musb_gadget_wakeup,
1648 .set_selfpowered = musb_gadget_set_self_powered,
1649 /* .vbus_session = musb_gadget_vbus_session, */
1650 .vbus_draw = musb_gadget_vbus_draw,
1651 .pullup = musb_gadget_pullup,
1652 };
1653
1654 /* ----------------------------------------------------------------------- */
1655
1656 /* Registration */
1657
1658 /* Only this registration code "knows" the rule (from USB standards)
1659 * about there being only one external upstream port. It assumes
1660 * all peripheral ports are external...
1661 */
1662 static struct musb *the_gadget;
1663
1664 static void musb_gadget_release(struct device *dev)
1665 {
1666 /* kref_put(WHAT) */
1667 dev_dbg(dev, "%s\n", __func__);
1668 }
1669
1670
1671 static void __init
1672 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1673 {
1674 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1675
1676 memset(ep, 0, sizeof *ep);
1677
1678 ep->current_epnum = epnum;
1679 ep->musb = musb;
1680 ep->hw_ep = hw_ep;
1681 ep->is_in = is_in;
1682
1683 INIT_LIST_HEAD(&ep->req_list);
1684
1685 sprintf(ep->name, "ep%d%s", epnum,
1686 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1687 is_in ? "in" : "out"));
1688 ep->end_point.name = ep->name;
1689 INIT_LIST_HEAD(&ep->end_point.ep_list);
1690 if (!epnum) {
1691 ep->end_point.maxpacket = 64;
1692 ep->end_point.ops = &musb_g_ep0_ops;
1693 musb->g.ep0 = &ep->end_point;
1694 } else {
1695 if (is_in)
1696 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1697 else
1698 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1699 ep->end_point.ops = &musb_ep_ops;
1700 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1701 }
1702 }
1703
1704 /*
1705 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1706 * to the rest of the driver state.
1707 */
1708 static inline void __init musb_g_init_endpoints(struct musb *musb)
1709 {
1710 u8 epnum;
1711 struct musb_hw_ep *hw_ep;
1712 unsigned count = 0;
1713
1714 /* initialize endpoint list just once */
1715 INIT_LIST_HEAD(&(musb->g.ep_list));
1716
1717 for (epnum = 0, hw_ep = musb->endpoints;
1718 epnum < musb->nr_endpoints;
1719 epnum++, hw_ep++) {
1720 if (hw_ep->is_shared_fifo /* || !epnum */) {
1721 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1722 count++;
1723 } else {
1724 if (hw_ep->max_packet_sz_tx) {
1725 init_peripheral_ep(musb, &hw_ep->ep_in,
1726 epnum, 1);
1727 count++;
1728 }
1729 if (hw_ep->max_packet_sz_rx) {
1730 init_peripheral_ep(musb, &hw_ep->ep_out,
1731 epnum, 0);
1732 count++;
1733 }
1734 }
1735 }
1736 }
1737
1738 /* called once during driver setup to initialize and link into
1739 * the driver model; memory is zeroed.
1740 */
1741 int __init musb_gadget_setup(struct musb *musb)
1742 {
1743 int status;
1744
1745 /* REVISIT minor race: if (erroneously) setting up two
1746 * musb peripherals at the same time, only the bus lock
1747 * is probably held.
1748 */
1749 if (the_gadget)
1750 return -EBUSY;
1751 the_gadget = musb;
1752
1753 musb->g.ops = &musb_gadget_operations;
1754 musb->g.is_dualspeed = 1;
1755 musb->g.speed = USB_SPEED_UNKNOWN;
1756
1757 /* this "gadget" abstracts/virtualizes the controller */
1758 dev_set_name(&musb->g.dev, "gadget");
1759 musb->g.dev.parent = musb->controller;
1760 musb->g.dev.dma_mask = musb->controller->dma_mask;
1761 musb->g.dev.release = musb_gadget_release;
1762 musb->g.name = musb_driver_name;
1763
1764 if (is_otg_enabled(musb))
1765 musb->g.is_otg = 1;
1766
1767 musb_g_init_endpoints(musb);
1768
1769 musb->is_active = 0;
1770 musb_platform_try_idle(musb, 0);
1771
1772 status = device_register(&musb->g.dev);
1773 if (status != 0) {
1774 put_device(&musb->g.dev);
1775 the_gadget = NULL;
1776 }
1777 return status;
1778 }
1779
1780 void musb_gadget_cleanup(struct musb *musb)
1781 {
1782 if (musb != the_gadget)
1783 return;
1784
1785 device_unregister(&musb->g.dev);
1786 the_gadget = NULL;
1787 }
1788
1789 /*
1790 * Register the gadget driver. Used by gadget drivers when
1791 * registering themselves with the controller.
1792 *
1793 * -EINVAL something went wrong (not driver)
1794 * -EBUSY another gadget is already using the controller
1795 * -ENOMEM no memory to perform the operation
1796 *
1797 * @param driver the gadget driver
1798 * @param bind the driver's bind function
1799 * @return <0 if error, 0 if everything is fine
1800 */
1801 int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1802 int (*bind)(struct usb_gadget *))
1803 {
1804 int retval;
1805 unsigned long flags;
1806 struct musb *musb = the_gadget;
1807
1808 if (!driver
1809 || driver->speed != USB_SPEED_HIGH
1810 || !bind || !driver->setup)
1811 return -EINVAL;
1812
1813 /* driver must be initialized to support peripheral mode */
1814 if (!musb) {
1815 DBG(1, "%s, no dev??\n", __func__);
1816 return -ENODEV;
1817 }
1818
1819 DBG(3, "registering driver %s\n", driver->function);
1820 spin_lock_irqsave(&musb->lock, flags);
1821
1822 if (musb->gadget_driver) {
1823 DBG(1, "%s is already bound to %s\n",
1824 musb_driver_name,
1825 musb->gadget_driver->driver.name);
1826 retval = -EBUSY;
1827 } else {
1828 musb->gadget_driver = driver;
1829 musb->g.dev.driver = &driver->driver;
1830 driver->driver.bus = NULL;
1831 musb->softconnect = 1;
1832 retval = 0;
1833 }
1834
1835 spin_unlock_irqrestore(&musb->lock, flags);
1836
1837 if (retval == 0) {
1838 retval = bind(&musb->g);
1839 if (retval != 0) {
1840 DBG(3, "bind to driver %s failed --> %d\n",
1841 driver->driver.name, retval);
1842 musb->gadget_driver = NULL;
1843 musb->g.dev.driver = NULL;
1844 }
1845
1846 spin_lock_irqsave(&musb->lock, flags);
1847
1848 otg_set_peripheral(musb->xceiv, &musb->g);
1849 musb->xceiv->state = OTG_STATE_B_IDLE;
1850 musb->is_active = 1;
1851
1852 /* FIXME this ignores the softconnect flag. Drivers are
1853 * allowed hold the peripheral inactive until for example
1854 * userspace hooks up printer hardware or DSP codecs, so
1855 * hosts only see fully functional devices.
1856 */
1857
1858 if (!is_otg_enabled(musb))
1859 musb_start(musb);
1860
1861 otg_set_peripheral(musb->xceiv, &musb->g);
1862
1863 spin_unlock_irqrestore(&musb->lock, flags);
1864
1865 if (is_otg_enabled(musb)) {
1866 struct usb_hcd *hcd = musb_to_hcd(musb);
1867
1868 DBG(3, "OTG startup...\n");
1869
1870 /* REVISIT: funcall to other code, which also
1871 * handles power budgeting ... this way also
1872 * ensures HdrcStart is indirectly called.
1873 */
1874 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1875 if (retval < 0) {
1876 DBG(1, "add_hcd failed, %d\n", retval);
1877 spin_lock_irqsave(&musb->lock, flags);
1878 otg_set_peripheral(musb->xceiv, NULL);
1879 musb->gadget_driver = NULL;
1880 musb->g.dev.driver = NULL;
1881 spin_unlock_irqrestore(&musb->lock, flags);
1882 } else {
1883 hcd->self.uses_pio_for_control = 1;
1884 }
1885 }
1886 }
1887
1888 return retval;
1889 }
1890 EXPORT_SYMBOL(usb_gadget_probe_driver);
1891
1892 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1893 {
1894 int i;
1895 struct musb_hw_ep *hw_ep;
1896
1897 /* don't disconnect if it's not connected */
1898 if (musb->g.speed == USB_SPEED_UNKNOWN)
1899 driver = NULL;
1900 else
1901 musb->g.speed = USB_SPEED_UNKNOWN;
1902
1903 /* deactivate the hardware */
1904 if (musb->softconnect) {
1905 musb->softconnect = 0;
1906 musb_pullup(musb, 0);
1907 }
1908 musb_stop(musb);
1909
1910 /* killing any outstanding requests will quiesce the driver;
1911 * then report disconnect
1912 */
1913 if (driver) {
1914 for (i = 0, hw_ep = musb->endpoints;
1915 i < musb->nr_endpoints;
1916 i++, hw_ep++) {
1917 musb_ep_select(musb->mregs, i);
1918 if (hw_ep->is_shared_fifo /* || !epnum */) {
1919 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1920 } else {
1921 if (hw_ep->max_packet_sz_tx)
1922 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1923 if (hw_ep->max_packet_sz_rx)
1924 nuke(&hw_ep->ep_out, -ESHUTDOWN);
1925 }
1926 }
1927
1928 spin_unlock(&musb->lock);
1929 driver->disconnect(&musb->g);
1930 spin_lock(&musb->lock);
1931 }
1932 }
1933
1934 /*
1935 * Unregister the gadget driver. Used by gadget drivers when
1936 * unregistering themselves from the controller.
1937 *
1938 * @param driver the gadget driver to unregister
1939 */
1940 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1941 {
1942 unsigned long flags;
1943 int retval = 0;
1944 struct musb *musb = the_gadget;
1945
1946 if (!driver || !driver->unbind || !musb)
1947 return -EINVAL;
1948
1949 /* REVISIT always use otg_set_peripheral() here too;
1950 * this needs to shut down the OTG engine.
1951 */
1952
1953 spin_lock_irqsave(&musb->lock, flags);
1954
1955 #ifdef CONFIG_USB_MUSB_OTG
1956 musb_hnp_stop(musb);
1957 #endif
1958
1959 if (musb->gadget_driver == driver) {
1960
1961 (void) musb_gadget_vbus_draw(&musb->g, 0);
1962
1963 musb->xceiv->state = OTG_STATE_UNDEFINED;
1964 stop_activity(musb, driver);
1965 otg_set_peripheral(musb->xceiv, NULL);
1966
1967 DBG(3, "unregistering driver %s\n", driver->function);
1968 spin_unlock_irqrestore(&musb->lock, flags);
1969 driver->unbind(&musb->g);
1970 spin_lock_irqsave(&musb->lock, flags);
1971
1972 musb->gadget_driver = NULL;
1973 musb->g.dev.driver = NULL;
1974
1975 musb->is_active = 0;
1976 musb_platform_try_idle(musb, 0);
1977 } else
1978 retval = -EINVAL;
1979 spin_unlock_irqrestore(&musb->lock, flags);
1980
1981 if (is_otg_enabled(musb) && retval == 0) {
1982 usb_remove_hcd(musb_to_hcd(musb));
1983 /* FIXME we need to be able to register another
1984 * gadget driver here and have everything work;
1985 * that currently misbehaves.
1986 */
1987 }
1988
1989 return retval;
1990 }
1991 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1992
1993
1994 /* ----------------------------------------------------------------------- */
1995
1996 /* lifecycle operations called through plat_uds.c */
1997
1998 void musb_g_resume(struct musb *musb)
1999 {
2000 musb->is_suspended = 0;
2001 switch (musb->xceiv->state) {
2002 case OTG_STATE_B_IDLE:
2003 break;
2004 case OTG_STATE_B_WAIT_ACON:
2005 case OTG_STATE_B_PERIPHERAL:
2006 musb->is_active = 1;
2007 if (musb->gadget_driver && musb->gadget_driver->resume) {
2008 spin_unlock(&musb->lock);
2009 musb->gadget_driver->resume(&musb->g);
2010 spin_lock(&musb->lock);
2011 }
2012 break;
2013 default:
2014 WARNING("unhandled RESUME transition (%s)\n",
2015 otg_state_string(musb));
2016 }
2017 }
2018
2019 /* called when SOF packets stop for 3+ msec */
2020 void musb_g_suspend(struct musb *musb)
2021 {
2022 u8 devctl;
2023
2024 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2025 DBG(3, "devctl %02x\n", devctl);
2026
2027 switch (musb->xceiv->state) {
2028 case OTG_STATE_B_IDLE:
2029 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2030 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2031 break;
2032 case OTG_STATE_B_PERIPHERAL:
2033 musb->is_suspended = 1;
2034 if (musb->gadget_driver && musb->gadget_driver->suspend) {
2035 spin_unlock(&musb->lock);
2036 musb->gadget_driver->suspend(&musb->g);
2037 spin_lock(&musb->lock);
2038 }
2039 break;
2040 default:
2041 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
2042 * A_PERIPHERAL may need care too
2043 */
2044 WARNING("unhandled SUSPEND transition (%s)\n",
2045 otg_state_string(musb));
2046 }
2047 }
2048
2049 /* Called during SRP */
2050 void musb_g_wakeup(struct musb *musb)
2051 {
2052 musb_gadget_wakeup(&musb->g);
2053 }
2054
2055 /* called when VBUS drops below session threshold, and in other cases */
2056 void musb_g_disconnect(struct musb *musb)
2057 {
2058 void __iomem *mregs = musb->mregs;
2059 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2060
2061 DBG(3, "devctl %02x\n", devctl);
2062
2063 /* clear HR */
2064 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
2065
2066 /* don't draw vbus until new b-default session */
2067 (void) musb_gadget_vbus_draw(&musb->g, 0);
2068
2069 musb->g.speed = USB_SPEED_UNKNOWN;
2070 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
2071 spin_unlock(&musb->lock);
2072 musb->gadget_driver->disconnect(&musb->g);
2073 spin_lock(&musb->lock);
2074 }
2075
2076 switch (musb->xceiv->state) {
2077 default:
2078 #ifdef CONFIG_USB_MUSB_OTG
2079 DBG(2, "Unhandled disconnect %s, setting a_idle\n",
2080 otg_state_string(musb));
2081 musb->xceiv->state = OTG_STATE_A_IDLE;
2082 MUSB_HST_MODE(musb);
2083 break;
2084 case OTG_STATE_A_PERIPHERAL:
2085 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2086 MUSB_HST_MODE(musb);
2087 break;
2088 case OTG_STATE_B_WAIT_ACON:
2089 case OTG_STATE_B_HOST:
2090 #endif
2091 case OTG_STATE_B_PERIPHERAL:
2092 case OTG_STATE_B_IDLE:
2093 musb->xceiv->state = OTG_STATE_B_IDLE;
2094 break;
2095 case OTG_STATE_B_SRP_INIT:
2096 break;
2097 }
2098
2099 musb->is_active = 0;
2100 }
2101
2102 void musb_g_reset(struct musb *musb)
2103 __releases(musb->lock)
2104 __acquires(musb->lock)
2105 {
2106 void __iomem *mbase = musb->mregs;
2107 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2108 u8 power;
2109
2110 DBG(3, "<== %s addr=%x driver '%s'\n",
2111 (devctl & MUSB_DEVCTL_BDEVICE)
2112 ? "B-Device" : "A-Device",
2113 musb_readb(mbase, MUSB_FADDR),
2114 musb->gadget_driver
2115 ? musb->gadget_driver->driver.name
2116 : NULL
2117 );
2118
2119 /* report disconnect, if we didn't already (flushing EP state) */
2120 if (musb->g.speed != USB_SPEED_UNKNOWN)
2121 musb_g_disconnect(musb);
2122
2123 /* clear HR */
2124 else if (devctl & MUSB_DEVCTL_HR)
2125 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2126
2127
2128 /* what speed did we negotiate? */
2129 power = musb_readb(mbase, MUSB_POWER);
2130 musb->g.speed = (power & MUSB_POWER_HSMODE)
2131 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2132
2133 /* start in USB_STATE_DEFAULT */
2134 musb->is_active = 1;
2135 musb->is_suspended = 0;
2136 MUSB_DEV_MODE(musb);
2137 musb->address = 0;
2138 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2139
2140 musb->may_wakeup = 0;
2141 musb->g.b_hnp_enable = 0;
2142 musb->g.a_alt_hnp_support = 0;
2143 musb->g.a_hnp_support = 0;
2144
2145 /* Normal reset, as B-Device;
2146 * or else after HNP, as A-Device
2147 */
2148 if (devctl & MUSB_DEVCTL_BDEVICE) {
2149 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2150 musb->g.is_a_peripheral = 0;
2151 } else if (is_otg_enabled(musb)) {
2152 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
2153 musb->g.is_a_peripheral = 1;
2154 } else
2155 WARN_ON(1);
2156
2157 /* start with default limits on VBUS power draw */
2158 (void) musb_gadget_vbus_draw(&musb->g,
2159 is_otg_enabled(musb) ? 8 : 100);
2160 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree