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mmc: tmio: use PIO for short transfers
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / mmc / host / tmio_mmc.c
blob32ab1452d97d7af89e2a7dcd3356ca23fc3d575a
1 /*
2 * linux/drivers/mmc/tmio_mmc.c
3 *
4 * Copyright (C) 2004 Ian Molton
5 * Copyright (C) 2007 Ian Molton
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Driver for the MMC / SD / SDIO cell found in:
12 *
13 * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
14 *
15 * This driver draws mainly on scattered spec sheets, Reverse engineering
16 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
17 * support). (Further 4 bit support from a later datasheet).
18 *
19 * TODO:
20 * Investigate using a workqueue for PIO transfers
21 * Eliminate FIXMEs
22 * SDIO support
23 * Better Power management
24 * Handle MMC errors better
25 * double buffer support
26 *
27 */
28
29 #include <linux/delay.h>
30 #include <linux/device.h>
31 #include <linux/dmaengine.h>
32 #include <linux/highmem.h>
33 #include <linux/interrupt.h>
34 #include <linux/io.h>
35 #include <linux/irq.h>
36 #include <linux/mfd/core.h>
37 #include <linux/mfd/tmio.h>
38 #include <linux/mmc/host.h>
39 #include <linux/module.h>
40 #include <linux/pagemap.h>
41 #include <linux/scatterlist.h>
42 #include <linux/workqueue.h>
43 #include <linux/spinlock.h>
44
45 #define CTL_SD_CMD 0x00
46 #define CTL_ARG_REG 0x04
47 #define CTL_STOP_INTERNAL_ACTION 0x08
48 #define CTL_XFER_BLK_COUNT 0xa
49 #define CTL_RESPONSE 0x0c
50 #define CTL_STATUS 0x1c
51 #define CTL_IRQ_MASK 0x20
52 #define CTL_SD_CARD_CLK_CTL 0x24
53 #define CTL_SD_XFER_LEN 0x26
54 #define CTL_SD_MEM_CARD_OPT 0x28
55 #define CTL_SD_ERROR_DETAIL_STATUS 0x2c
56 #define CTL_SD_DATA_PORT 0x30
57 #define CTL_TRANSACTION_CTL 0x34
58 #define CTL_SDIO_STATUS 0x36
59 #define CTL_SDIO_IRQ_MASK 0x38
60 #define CTL_RESET_SD 0xe0
61 #define CTL_SDIO_REGS 0x100
62 #define CTL_CLK_AND_WAIT_CTL 0x138
63 #define CTL_RESET_SDIO 0x1e0
64
65 /* Definitions for values the CTRL_STATUS register can take. */
66 #define TMIO_STAT_CMDRESPEND 0x00000001
67 #define TMIO_STAT_DATAEND 0x00000004
68 #define TMIO_STAT_CARD_REMOVE 0x00000008
69 #define TMIO_STAT_CARD_INSERT 0x00000010
70 #define TMIO_STAT_SIGSTATE 0x00000020
71 #define TMIO_STAT_WRPROTECT 0x00000080
72 #define TMIO_STAT_CARD_REMOVE_A 0x00000100
73 #define TMIO_STAT_CARD_INSERT_A 0x00000200
74 #define TMIO_STAT_SIGSTATE_A 0x00000400
75 #define TMIO_STAT_CMD_IDX_ERR 0x00010000
76 #define TMIO_STAT_CRCFAIL 0x00020000
77 #define TMIO_STAT_STOPBIT_ERR 0x00040000
78 #define TMIO_STAT_DATATIMEOUT 0x00080000
79 #define TMIO_STAT_RXOVERFLOW 0x00100000
80 #define TMIO_STAT_TXUNDERRUN 0x00200000
81 #define TMIO_STAT_CMDTIMEOUT 0x00400000
82 #define TMIO_STAT_RXRDY 0x01000000
83 #define TMIO_STAT_TXRQ 0x02000000
84 #define TMIO_STAT_ILL_FUNC 0x20000000
85 #define TMIO_STAT_CMD_BUSY 0x40000000
86 #define TMIO_STAT_ILL_ACCESS 0x80000000
87
88 /* Definitions for values the CTRL_SDIO_STATUS register can take. */
89 #define TMIO_SDIO_STAT_IOIRQ 0x0001
90 #define TMIO_SDIO_STAT_EXPUB52 0x4000
91 #define TMIO_SDIO_STAT_EXWT 0x8000
92 #define TMIO_SDIO_MASK_ALL 0xc007
93
94 /* Define some IRQ masks */
95 /* This is the mask used at reset by the chip */
96 #define TMIO_MASK_ALL 0x837f031d
97 #define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND)
98 #define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND)
99 #define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \
100 TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
101 #define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)
102
103 #define TMIO_MIN_DMA_LEN 8
104
105 #define enable_mmc_irqs(host, i) \
106 do { \
107 u32 mask;\
108 mask = sd_ctrl_read32((host), CTL_IRQ_MASK); \
109 mask &= ~((i) & TMIO_MASK_IRQ); \
110 sd_ctrl_write32((host), CTL_IRQ_MASK, mask); \
111 } while (0)
112
113 #define disable_mmc_irqs(host, i) \
114 do { \
115 u32 mask;\
116 mask = sd_ctrl_read32((host), CTL_IRQ_MASK); \
117 mask |= ((i) & TMIO_MASK_IRQ); \
118 sd_ctrl_write32((host), CTL_IRQ_MASK, mask); \
119 } while (0)
120
121 #define ack_mmc_irqs(host, i) \
122 do { \
123 sd_ctrl_write32((host), CTL_STATUS, ~(i)); \
124 } while (0)
125
126 /* This is arbitrary, just noone needed any higher alignment yet */
127 #define MAX_ALIGN 4
128
129 struct tmio_mmc_host {
130 void __iomem *ctl;
131 unsigned long bus_shift;
132 struct mmc_command *cmd;
133 struct mmc_request *mrq;
134 struct mmc_data *data;
135 struct mmc_host *mmc;
136 int irq;
137 unsigned int sdio_irq_enabled;
138
139 /* Callbacks for clock / power control */
140 void (*set_pwr)(struct platform_device *host, int state);
141 void (*set_clk_div)(struct platform_device *host, int state);
142
143 /* pio related stuff */
144 struct scatterlist *sg_ptr;
145 struct scatterlist *sg_orig;
146 unsigned int sg_len;
147 unsigned int sg_off;
148
149 struct platform_device *pdev;
150
151 /* DMA support */
152 bool force_pio;
153 struct dma_chan *chan_rx;
154 struct dma_chan *chan_tx;
155 struct tasklet_struct dma_complete;
156 struct tasklet_struct dma_issue;
157 #ifdef CONFIG_TMIO_MMC_DMA
158 u8 bounce_buf[PAGE_CACHE_SIZE] __attribute__((aligned(MAX_ALIGN)));
159 struct scatterlist bounce_sg;
160 #endif
161
162 /* Track lost interrupts */
163 struct delayed_work delayed_reset_work;
164 spinlock_t lock;
165 unsigned long last_req_ts;
166 };
167
168 static void tmio_check_bounce_buffer(struct tmio_mmc_host *host);
169
170 static u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
171 {
172 return readw(host->ctl + (addr << host->bus_shift));
173 }
174
175 static void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
176 u16 *buf, int count)
177 {
178 readsw(host->ctl + (addr << host->bus_shift), buf, count);
179 }
180
181 static u32 sd_ctrl_read32(struct tmio_mmc_host *host, int addr)
182 {
183 return readw(host->ctl + (addr << host->bus_shift)) |
184 readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
185 }
186
187 static void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, u16 val)
188 {
189 writew(val, host->ctl + (addr << host->bus_shift));
190 }
191
192 static void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
193 u16 *buf, int count)
194 {
195 writesw(host->ctl + (addr << host->bus_shift), buf, count);
196 }
197
198 static void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val)
199 {
200 writew(val, host->ctl + (addr << host->bus_shift));
201 writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
202 }
203
204 static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)
205 {
206 host->sg_len = data->sg_len;
207 host->sg_ptr = data->sg;
208 host->sg_orig = data->sg;
209 host->sg_off = 0;
210 }
211
212 static int tmio_mmc_next_sg(struct tmio_mmc_host *host)
213 {
214 host->sg_ptr = sg_next(host->sg_ptr);
215 host->sg_off = 0;
216 return --host->sg_len;
217 }
218
219 static char *tmio_mmc_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
220 {
221 local_irq_save(*flags);
222 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
223 }
224
225 static void tmio_mmc_kunmap_atomic(struct scatterlist *sg, unsigned long *flags, void *virt)
226 {
227 kunmap_atomic(virt - sg->offset, KM_BIO_SRC_IRQ);
228 local_irq_restore(*flags);
229 }
230
231 #ifdef CONFIG_MMC_DEBUG
232
233 #define STATUS_TO_TEXT(a, status, i) \
234 do { \
235 if (status & TMIO_STAT_##a) { \
236 if (i++) \
237 printk(" | "); \
238 printk(#a); \
239 } \
240 } while (0)
241
242 void pr_debug_status(u32 status)
243 {
244 int i = 0;
245 printk(KERN_DEBUG "status: %08x = ", status);
246 STATUS_TO_TEXT(CARD_REMOVE, status, i);
247 STATUS_TO_TEXT(CARD_INSERT, status, i);
248 STATUS_TO_TEXT(SIGSTATE, status, i);
249 STATUS_TO_TEXT(WRPROTECT, status, i);
250 STATUS_TO_TEXT(CARD_REMOVE_A, status, i);
251 STATUS_TO_TEXT(CARD_INSERT_A, status, i);
252 STATUS_TO_TEXT(SIGSTATE_A, status, i);
253 STATUS_TO_TEXT(CMD_IDX_ERR, status, i);
254 STATUS_TO_TEXT(STOPBIT_ERR, status, i);
255 STATUS_TO_TEXT(ILL_FUNC, status, i);
256 STATUS_TO_TEXT(CMD_BUSY, status, i);
257 STATUS_TO_TEXT(CMDRESPEND, status, i);
258 STATUS_TO_TEXT(DATAEND, status, i);
259 STATUS_TO_TEXT(CRCFAIL, status, i);
260 STATUS_TO_TEXT(DATATIMEOUT, status, i);
261 STATUS_TO_TEXT(CMDTIMEOUT, status, i);
262 STATUS_TO_TEXT(RXOVERFLOW, status, i);
263 STATUS_TO_TEXT(TXUNDERRUN, status, i);
264 STATUS_TO_TEXT(RXRDY, status, i);
265 STATUS_TO_TEXT(TXRQ, status, i);
266 STATUS_TO_TEXT(ILL_ACCESS, status, i);
267 printk("\n");
268 }
269
270 #else
271 #define pr_debug_status(s) do { } while (0)
272 #endif
273
274 static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
275 {
276 struct tmio_mmc_host *host = mmc_priv(mmc);
277
278 if (enable) {
279 host->sdio_irq_enabled = 1;
280 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
281 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK,
282 (TMIO_SDIO_MASK_ALL & ~TMIO_SDIO_STAT_IOIRQ));
283 } else {
284 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, TMIO_SDIO_MASK_ALL);
285 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000);
286 host->sdio_irq_enabled = 0;
287 }
288 }
289
290 static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
291 {
292 u32 clk = 0, clock;
293
294 if (new_clock) {
295 for (clock = host->mmc->f_min, clk = 0x80000080;
296 new_clock >= (clock<<1); clk >>= 1)
297 clock <<= 1;
298 clk |= 0x100;
299 }
300
301 if (host->set_clk_div)
302 host->set_clk_div(host->pdev, (clk>>22) & 1);
303
304 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
305 }
306
307 static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
308 {
309 struct tmio_mmc_data *pdata = mfd_get_data(host->pdev);
310
311 /*
312 * Testing on sh-mobile showed that SDIO IRQs are unmasked when
313 * CTL_CLK_AND_WAIT_CTL gets written, so we have to disable the
314 * device IRQ here and restore the SDIO IRQ mask before
315 * re-enabling the device IRQ.
316 */
317 if (pdata->flags & TMIO_MMC_SDIO_IRQ)
318 disable_irq(host->irq);
319 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
320 msleep(10);
321 if (pdata->flags & TMIO_MMC_SDIO_IRQ) {
322 tmio_mmc_enable_sdio_irq(host->mmc, host->sdio_irq_enabled);
323 enable_irq(host->irq);
324 }
325 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
326 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
327 msleep(10);
328 }
329
330 static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
331 {
332 struct tmio_mmc_data *pdata = mfd_get_data(host->pdev);
333
334 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
335 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
336 msleep(10);
337 /* see comment in tmio_mmc_clk_stop above */
338 if (pdata->flags & TMIO_MMC_SDIO_IRQ)
339 disable_irq(host->irq);
340 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
341 msleep(10);
342 if (pdata->flags & TMIO_MMC_SDIO_IRQ) {
343 tmio_mmc_enable_sdio_irq(host->mmc, host->sdio_irq_enabled);
344 enable_irq(host->irq);
345 }
346 }
347
348 static void reset(struct tmio_mmc_host *host)
349 {
350 /* FIXME - should we set stop clock reg here */
351 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
352 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
353 msleep(10);
354 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
355 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
356 msleep(10);
357 }
358
359 static void tmio_mmc_reset_work(struct work_struct *work)
360 {
361 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
362 delayed_reset_work.work);
363 struct mmc_request *mrq;
364 unsigned long flags;
365
366 spin_lock_irqsave(&host->lock, flags);
367 mrq = host->mrq;
368
369 /* request already finished */
370 if (!mrq
371 || time_is_after_jiffies(host->last_req_ts +
372 msecs_to_jiffies(2000))) {
373 spin_unlock_irqrestore(&host->lock, flags);
374 return;
375 }
376
377 dev_warn(&host->pdev->dev,
378 "timeout waiting for hardware interrupt (CMD%u)\n",
379 mrq->cmd->opcode);
380
381 if (host->data)
382 host->data->error = -ETIMEDOUT;
383 else if (host->cmd)
384 host->cmd->error = -ETIMEDOUT;
385 else
386 mrq->cmd->error = -ETIMEDOUT;
387
388 host->cmd = NULL;
389 host->data = NULL;
390 host->mrq = NULL;
391 host->force_pio = false;
392
393 spin_unlock_irqrestore(&host->lock, flags);
394
395 reset(host);
396
397 mmc_request_done(host->mmc, mrq);
398 }
399
400 static void
401 tmio_mmc_finish_request(struct tmio_mmc_host *host)
402 {
403 struct mmc_request *mrq = host->mrq;
404
405 if (!mrq)
406 return;
407
408 host->mrq = NULL;
409 host->cmd = NULL;
410 host->data = NULL;
411 host->force_pio = false;
412
413 cancel_delayed_work(&host->delayed_reset_work);
414
415 mmc_request_done(host->mmc, mrq);
416 }
417
418 /* These are the bitmasks the tmio chip requires to implement the MMC response
419 * types. Note that R1 and R6 are the same in this scheme. */
420 #define APP_CMD 0x0040
421 #define RESP_NONE 0x0300
422 #define RESP_R1 0x0400
423 #define RESP_R1B 0x0500
424 #define RESP_R2 0x0600
425 #define RESP_R3 0x0700
426 #define DATA_PRESENT 0x0800
427 #define TRANSFER_READ 0x1000
428 #define TRANSFER_MULTI 0x2000
429 #define SECURITY_CMD 0x4000
430
431 static int
432 tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
433 {
434 struct mmc_data *data = host->data;
435 int c = cmd->opcode;
436
437 /* Command 12 is handled by hardware */
438 if (cmd->opcode == 12 && !cmd->arg) {
439 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
440 return 0;
441 }
442
443 switch (mmc_resp_type(cmd)) {
444 case MMC_RSP_NONE: c |= RESP_NONE; break;
445 case MMC_RSP_R1: c |= RESP_R1; break;
446 case MMC_RSP_R1B: c |= RESP_R1B; break;
447 case MMC_RSP_R2: c |= RESP_R2; break;
448 case MMC_RSP_R3: c |= RESP_R3; break;
449 default:
450 pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
451 return -EINVAL;
452 }
453
454 host->cmd = cmd;
455
456 /* FIXME - this seems to be ok commented out but the spec suggest this bit
457 * should be set when issuing app commands.
458 * if(cmd->flags & MMC_FLAG_ACMD)
459 * c |= APP_CMD;
460 */
461 if (data) {
462 c |= DATA_PRESENT;
463 if (data->blocks > 1) {
464 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
465 c |= TRANSFER_MULTI;
466 }
467 if (data->flags & MMC_DATA_READ)
468 c |= TRANSFER_READ;
469 }
470
471 enable_mmc_irqs(host, TMIO_MASK_CMD);
472
473 /* Fire off the command */
474 sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg);
475 sd_ctrl_write16(host, CTL_SD_CMD, c);
476
477 return 0;
478 }
479
480 /*
481 * This chip always returns (at least?) as much data as you ask for.
482 * I'm unsure what happens if you ask for less than a block. This should be
483 * looked into to ensure that a funny length read doesnt hose the controller.
484 */
485 static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
486 {
487 struct mmc_data *data = host->data;
488 void *sg_virt;
489 unsigned short *buf;
490 unsigned int count;
491 unsigned long flags;
492
493 if ((host->chan_tx || host->chan_rx) && !host->force_pio) {
494 pr_err("PIO IRQ in DMA mode!\n");
495 return;
496 } else if (!data) {
497 pr_debug("Spurious PIO IRQ\n");
498 return;
499 }
500
501 sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags);
502 buf = (unsigned short *)(sg_virt + host->sg_off);
503
504 count = host->sg_ptr->length - host->sg_off;
505 if (count > data->blksz)
506 count = data->blksz;
507
508 pr_debug("count: %08x offset: %08x flags %08x\n",
509 count, host->sg_off, data->flags);
510
511 /* Transfer the data */
512 if (data->flags & MMC_DATA_READ)
513 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
514 else
515 sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
516
517 host->sg_off += count;
518
519 tmio_mmc_kunmap_atomic(host->sg_ptr, &flags, sg_virt);
520
521 if (host->sg_off == host->sg_ptr->length)
522 tmio_mmc_next_sg(host);
523
524 return;
525 }
526
527 /* needs to be called with host->lock held */
528 static void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
529 {
530 struct mmc_data *data = host->data;
531 struct mmc_command *stop;
532
533 host->data = NULL;
534
535 if (!data) {
536 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
537 return;
538 }
539 stop = data->stop;
540
541 /* FIXME - return correct transfer count on errors */
542 if (!data->error)
543 data->bytes_xfered = data->blocks * data->blksz;
544 else
545 data->bytes_xfered = 0;
546
547 pr_debug("Completed data request\n");
548
549 /*
550 * FIXME: other drivers allow an optional stop command of any given type
551 * which we dont do, as the chip can auto generate them.
552 * Perhaps we can be smarter about when to use auto CMD12 and
553 * only issue the auto request when we know this is the desired
554 * stop command, allowing fallback to the stop command the
555 * upper layers expect. For now, we do what works.
556 */
557
558 if (data->flags & MMC_DATA_READ) {
559 if (host->chan_rx && !host->force_pio)
560 tmio_check_bounce_buffer(host);
561 dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
562 host->mrq);
563 } else {
564 dev_dbg(&host->pdev->dev, "Complete Tx request %p\n",
565 host->mrq);
566 }
567
568 if (stop) {
569 if (stop->opcode == 12 && !stop->arg)
570 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
571 else
572 BUG();
573 }
574
575 tmio_mmc_finish_request(host);
576 }
577
578 static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
579 {
580 struct mmc_data *data;
581 spin_lock(&host->lock);
582 data = host->data;
583
584 if (!data)
585 goto out;
586
587 if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) {
588 /*
589 * Has all data been written out yet? Testing on SuperH showed,
590 * that in most cases the first interrupt comes already with the
591 * BUSY status bit clear, but on some operations, like mount or
592 * in the beginning of a write / sync / umount, there is one
593 * DATAEND interrupt with the BUSY bit set, in this cases
594 * waiting for one more interrupt fixes the problem.
595 */
596 if (!(sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_CMD_BUSY)) {
597 disable_mmc_irqs(host, TMIO_STAT_DATAEND);
598 tasklet_schedule(&host->dma_complete);
599 }
600 } else if (host->chan_rx && (data->flags & MMC_DATA_READ) && !host->force_pio) {
601 disable_mmc_irqs(host, TMIO_STAT_DATAEND);
602 tasklet_schedule(&host->dma_complete);
603 } else {
604 tmio_mmc_do_data_irq(host);
605 disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP);
606 }
607 out:
608 spin_unlock(&host->lock);
609 }
610
611 static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
612 unsigned int stat)
613 {
614 struct mmc_command *cmd = host->cmd;
615 int i, addr;
616
617 spin_lock(&host->lock);
618
619 if (!host->cmd) {
620 pr_debug("Spurious CMD irq\n");
621 goto out;
622 }
623
624 host->cmd = NULL;
625
626 /* This controller is sicker than the PXA one. Not only do we need to
627 * drop the top 8 bits of the first response word, we also need to
628 * modify the order of the response for short response command types.
629 */
630
631 for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
632 cmd->resp[i] = sd_ctrl_read32(host, addr);
633
634 if (cmd->flags & MMC_RSP_136) {
635 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
636 cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
637 cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
638 cmd->resp[3] <<= 8;
639 } else if (cmd->flags & MMC_RSP_R3) {
640 cmd->resp[0] = cmd->resp[3];
641 }
642
643 if (stat & TMIO_STAT_CMDTIMEOUT)
644 cmd->error = -ETIMEDOUT;
645 else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
646 cmd->error = -EILSEQ;
647
648 /* If there is data to handle we enable data IRQs here, and
649 * we will ultimatley finish the request in the data_end handler.
650 * If theres no data or we encountered an error, finish now.
651 */
652 if (host->data && !cmd->error) {
653 if (host->data->flags & MMC_DATA_READ) {
654 if (host->force_pio || !host->chan_rx)
655 enable_mmc_irqs(host, TMIO_MASK_READOP);
656 else
657 tasklet_schedule(&host->dma_issue);
658 } else {
659 if (host->force_pio || !host->chan_tx)
660 enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
661 else
662 tasklet_schedule(&host->dma_issue);
663 }
664 } else {
665 tmio_mmc_finish_request(host);
666 }
667
668 out:
669 spin_unlock(&host->lock);
670
671 return;
672 }
673
674 static irqreturn_t tmio_mmc_irq(int irq, void *devid)
675 {
676 struct tmio_mmc_host *host = devid;
677 struct tmio_mmc_data *pdata = mfd_get_data(host->pdev);
678 unsigned int ireg, irq_mask, status;
679 unsigned int sdio_ireg, sdio_irq_mask, sdio_status;
680
681 pr_debug("MMC IRQ begin\n");
682
683 status = sd_ctrl_read32(host, CTL_STATUS);
684 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
685 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
686
687 sdio_ireg = 0;
688 if (!ireg && pdata->flags & TMIO_MMC_SDIO_IRQ) {
689 sdio_status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
690 sdio_irq_mask = sd_ctrl_read16(host, CTL_SDIO_IRQ_MASK);
691 sdio_ireg = sdio_status & TMIO_SDIO_MASK_ALL & ~sdio_irq_mask;
692
693 sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status & ~TMIO_SDIO_MASK_ALL);
694
695 if (sdio_ireg && !host->sdio_irq_enabled) {
696 pr_warning("tmio_mmc: Spurious SDIO IRQ, disabling! 0x%04x 0x%04x 0x%04x\n",
697 sdio_status, sdio_irq_mask, sdio_ireg);
698 tmio_mmc_enable_sdio_irq(host->mmc, 0);
699 goto out;
700 }
701
702 if (host->mmc->caps & MMC_CAP_SDIO_IRQ &&
703 sdio_ireg & TMIO_SDIO_STAT_IOIRQ)
704 mmc_signal_sdio_irq(host->mmc);
705
706 if (sdio_ireg)
707 goto out;
708 }
709
710 pr_debug_status(status);
711 pr_debug_status(ireg);
712
713 if (!ireg) {
714 disable_mmc_irqs(host, status & ~irq_mask);
715
716 pr_warning("tmio_mmc: Spurious irq, disabling! "
717 "0x%08x 0x%08x 0x%08x\n", status, irq_mask, ireg);
718 pr_debug_status(status);
719
720 goto out;
721 }
722
723 while (ireg) {
724 /* Card insert / remove attempts */
725 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
726 ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
727 TMIO_STAT_CARD_REMOVE);
728 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
729 }
730
731 /* CRC and other errors */
732 /* if (ireg & TMIO_STAT_ERR_IRQ)
733 * handled |= tmio_error_irq(host, irq, stat);
734 */
735
736 /* Command completion */
737 if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) {
738 ack_mmc_irqs(host,
739 TMIO_STAT_CMDRESPEND |
740 TMIO_STAT_CMDTIMEOUT);
741 tmio_mmc_cmd_irq(host, status);
742 }
743
744 /* Data transfer */
745 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
746 ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
747 tmio_mmc_pio_irq(host);
748 }
749
750 /* Data transfer completion */
751 if (ireg & TMIO_STAT_DATAEND) {
752 ack_mmc_irqs(host, TMIO_STAT_DATAEND);
753 tmio_mmc_data_irq(host);
754 }
755
756 /* Check status - keep going until we've handled it all */
757 status = sd_ctrl_read32(host, CTL_STATUS);
758 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
759 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
760
761 pr_debug("Status at end of loop: %08x\n", status);
762 pr_debug_status(status);
763 }
764 pr_debug("MMC IRQ end\n");
765
766 out:
767 return IRQ_HANDLED;
768 }
769
770 #ifdef CONFIG_TMIO_MMC_DMA
771 static void tmio_check_bounce_buffer(struct tmio_mmc_host *host)
772 {
773 if (host->sg_ptr == &host->bounce_sg) {
774 unsigned long flags;
775 void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags);
776 memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length);
777 tmio_mmc_kunmap_atomic(host->sg_orig, &flags, sg_vaddr);
778 }
779 }
780
781 static void tmio_mmc_enable_dma(struct tmio_mmc_host *host, bool enable)
782 {
783 #if defined(CONFIG_SUPERH) || defined(CONFIG_ARCH_SHMOBILE)
784 /* Switch DMA mode on or off - SuperH specific? */
785 sd_ctrl_write16(host, 0xd8, enable ? 2 : 0);
786 #endif
787 }
788
789 static void tmio_mmc_start_dma_rx(struct tmio_mmc_host *host)
790 {
791 struct scatterlist *sg = host->sg_ptr, *sg_tmp;
792 struct dma_async_tx_descriptor *desc = NULL;
793 struct dma_chan *chan = host->chan_rx;
794 struct tmio_mmc_data *pdata = mfd_get_data(host->pdev);
795 dma_cookie_t cookie;
796 int ret, i;
797 bool aligned = true, multiple = true;
798 unsigned int align = (1 << pdata->dma->alignment_shift) - 1;
799
800 for_each_sg(sg, sg_tmp, host->sg_len, i) {
801 if (sg_tmp->offset & align)
802 aligned = false;
803 if (sg_tmp->length & align) {
804 multiple = false;
805 break;
806 }
807 }
808
809 if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_CACHE_SIZE ||
810 align >= MAX_ALIGN)) || !multiple) {
811 ret = -EINVAL;
812 goto pio;
813 }
814
815 if (sg->length < TMIO_MIN_DMA_LEN) {
816 host->force_pio = true;
817 return;
818 }
819
820 disable_mmc_irqs(host, TMIO_STAT_RXRDY);
821
822 /* The only sg element can be unaligned, use our bounce buffer then */
823 if (!aligned) {
824 sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
825 host->sg_ptr = &host->bounce_sg;
826 sg = host->sg_ptr;
827 }
828
829 ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_FROM_DEVICE);
830 if (ret > 0)
831 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
832 DMA_FROM_DEVICE, DMA_CTRL_ACK);
833
834 if (desc)
835 cookie = dmaengine_submit(desc);
836
837 dev_dbg(&host->pdev->dev, "%s(): mapped %d -> %d, cookie %d, rq %p\n",
838 __func__, host->sg_len, ret, cookie, host->mrq);
839
840 pio:
841 if (!desc) {
842 /* DMA failed, fall back to PIO */
843 if (ret >= 0)
844 ret = -EIO;
845 host->chan_rx = NULL;
846 dma_release_channel(chan);
847 /* Free the Tx channel too */
848 chan = host->chan_tx;
849 if (chan) {
850 host->chan_tx = NULL;
851 dma_release_channel(chan);
852 }
853 dev_warn(&host->pdev->dev,
854 "DMA failed: %d, falling back to PIO\n", ret);
855 tmio_mmc_enable_dma(host, false);
856 }
857
858 dev_dbg(&host->pdev->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
859 desc, cookie, host->sg_len);
860 }
861
862 static void tmio_mmc_start_dma_tx(struct tmio_mmc_host *host)
863 {
864 struct scatterlist *sg = host->sg_ptr, *sg_tmp;
865 struct dma_async_tx_descriptor *desc = NULL;
866 struct dma_chan *chan = host->chan_tx;
867 struct tmio_mmc_data *pdata = mfd_get_data(host->pdev);
868 dma_cookie_t cookie;
869 int ret, i;
870 bool aligned = true, multiple = true;
871 unsigned int align = (1 << pdata->dma->alignment_shift) - 1;
872
873 for_each_sg(sg, sg_tmp, host->sg_len, i) {
874 if (sg_tmp->offset & align)
875 aligned = false;
876 if (sg_tmp->length & align) {
877 multiple = false;
878 break;
879 }
880 }
881
882 if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_CACHE_SIZE ||
883 align >= MAX_ALIGN)) || !multiple) {
884 ret = -EINVAL;
885 goto pio;
886 }
887
888 if (sg->length < TMIO_MIN_DMA_LEN) {
889 host->force_pio = true;
890 return;
891 }
892
893 disable_mmc_irqs(host, TMIO_STAT_TXRQ);
894
895 /* The only sg element can be unaligned, use our bounce buffer then */
896 if (!aligned) {
897 unsigned long flags;
898 void *sg_vaddr = tmio_mmc_kmap_atomic(sg, &flags);
899 sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
900 memcpy(host->bounce_buf, sg_vaddr, host->bounce_sg.length);
901 tmio_mmc_kunmap_atomic(sg, &flags, sg_vaddr);
902 host->sg_ptr = &host->bounce_sg;
903 sg = host->sg_ptr;
904 }
905
906 ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_TO_DEVICE);
907 if (ret > 0)
908 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
909 DMA_TO_DEVICE, DMA_CTRL_ACK);
910
911 if (desc)
912 cookie = dmaengine_submit(desc);
913
914 dev_dbg(&host->pdev->dev, "%s(): mapped %d -> %d, cookie %d, rq %p\n",
915 __func__, host->sg_len, ret, cookie, host->mrq);
916
917 pio:
918 if (!desc) {
919 /* DMA failed, fall back to PIO */
920 if (ret >= 0)
921 ret = -EIO;
922 host->chan_tx = NULL;
923 dma_release_channel(chan);
924 /* Free the Rx channel too */
925 chan = host->chan_rx;
926 if (chan) {
927 host->chan_rx = NULL;
928 dma_release_channel(chan);
929 }
930 dev_warn(&host->pdev->dev,
931 "DMA failed: %d, falling back to PIO\n", ret);
932 tmio_mmc_enable_dma(host, false);
933 }
934
935 dev_dbg(&host->pdev->dev, "%s(): desc %p, cookie %d\n", __func__,
936 desc, cookie);
937 }
938
939 static void tmio_mmc_start_dma(struct tmio_mmc_host *host,
940 struct mmc_data *data)
941 {
942 if (data->flags & MMC_DATA_READ) {
943 if (host->chan_rx)
944 tmio_mmc_start_dma_rx(host);
945 } else {
946 if (host->chan_tx)
947 tmio_mmc_start_dma_tx(host);
948 }
949 }
950
951 static void tmio_issue_tasklet_fn(unsigned long priv)
952 {
953 struct tmio_mmc_host *host = (struct tmio_mmc_host *)priv;
954 struct dma_chan *chan = NULL;
955
956 spin_lock_irq(&host->lock);
957
958 if (host && host->data) {
959 if (host->data->flags & MMC_DATA_READ)
960 chan = host->chan_rx;
961 else
962 chan = host->chan_tx;
963 }
964
965 spin_unlock_irq(&host->lock);
966
967 enable_mmc_irqs(host, TMIO_STAT_DATAEND);
968
969 if (chan)
970 dma_async_issue_pending(chan);
971 }
972
973 static void tmio_tasklet_fn(unsigned long arg)
974 {
975 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
976
977 spin_lock_irq(&host->lock);
978
979 if (!host->data)
980 goto out;
981
982 if (host->data->flags & MMC_DATA_READ)
983 dma_unmap_sg(host->chan_rx->device->dev,
984 host->sg_ptr, host->sg_len,
985 DMA_FROM_DEVICE);
986 else
987 dma_unmap_sg(host->chan_tx->device->dev,
988 host->sg_ptr, host->sg_len,
989 DMA_TO_DEVICE);
990
991 tmio_mmc_do_data_irq(host);
992 out:
993 spin_unlock_irq(&host->lock);
994 }
995
996 /* It might be necessary to make filter MFD specific */
997 static bool tmio_mmc_filter(struct dma_chan *chan, void *arg)
998 {
999 dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg);
1000 chan->private = arg;
1001 return true;
1002 }
1003
1004 static void tmio_mmc_request_dma(struct tmio_mmc_host *host,
1005 struct tmio_mmc_data *pdata)
1006 {
1007 /* We can only either use DMA for both Tx and Rx or not use it at all */
1008 if (pdata->dma) {
1009 dma_cap_mask_t mask;
1010
1011 dma_cap_zero(mask);
1012 dma_cap_set(DMA_SLAVE, mask);
1013
1014 host->chan_tx = dma_request_channel(mask, tmio_mmc_filter,
1015 pdata->dma->chan_priv_tx);
1016 dev_dbg(&host->pdev->dev, "%s: TX: got channel %p\n", __func__,
1017 host->chan_tx);
1018
1019 if (!host->chan_tx)
1020 return;
1021
1022 host->chan_rx = dma_request_channel(mask, tmio_mmc_filter,
1023 pdata->dma->chan_priv_rx);
1024 dev_dbg(&host->pdev->dev, "%s: RX: got channel %p\n", __func__,
1025 host->chan_rx);
1026
1027 if (!host->chan_rx) {
1028 dma_release_channel(host->chan_tx);
1029 host->chan_tx = NULL;
1030 return;
1031 }
1032
1033 tasklet_init(&host->dma_complete, tmio_tasklet_fn, (unsigned long)host);
1034 tasklet_init(&host->dma_issue, tmio_issue_tasklet_fn, (unsigned long)host);
1035
1036 tmio_mmc_enable_dma(host, true);
1037 }
1038 }
1039
1040 static void tmio_mmc_release_dma(struct tmio_mmc_host *host)
1041 {
1042 if (host->chan_tx) {
1043 struct dma_chan *chan = host->chan_tx;
1044 host->chan_tx = NULL;
1045 dma_release_channel(chan);
1046 }
1047 if (host->chan_rx) {
1048 struct dma_chan *chan = host->chan_rx;
1049 host->chan_rx = NULL;
1050 dma_release_channel(chan);
1051 }
1052 }
1053 #else
1054 static void tmio_check_bounce_buffer(struct tmio_mmc_host *host)
1055 {
1056 }
1057
1058 static void tmio_mmc_start_dma(struct tmio_mmc_host *host,
1059 struct mmc_data *data)
1060 {
1061 }
1062
1063 static void tmio_mmc_request_dma(struct tmio_mmc_host *host,
1064 struct tmio_mmc_data *pdata)
1065 {
1066 host->chan_tx = NULL;
1067 host->chan_rx = NULL;
1068 }
1069
1070 static void tmio_mmc_release_dma(struct tmio_mmc_host *host)
1071 {
1072 }
1073 #endif
1074
1075 static int tmio_mmc_start_data(struct tmio_mmc_host *host,
1076 struct mmc_data *data)
1077 {
1078 struct tmio_mmc_data *pdata = mfd_get_data(host->pdev);
1079
1080 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
1081 data->blksz, data->blocks);
1082
1083 /* Some hardware cannot perform 2 byte requests in 4 bit mode */
1084 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
1085 int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES;
1086
1087 if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) {
1088 pr_err("%s: %d byte block unsupported in 4 bit mode\n",
1089 mmc_hostname(host->mmc), data->blksz);
1090 return -EINVAL;
1091 }
1092 }
1093
1094 tmio_mmc_init_sg(host, data);
1095 host->data = data;
1096
1097 /* Set transfer length / blocksize */
1098 sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
1099 sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
1100
1101 tmio_mmc_start_dma(host, data);
1102
1103 return 0;
1104 }
1105
1106 /* Process requests from the MMC layer */
1107 static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
1108 {
1109 struct tmio_mmc_host *host = mmc_priv(mmc);
1110 int ret;
1111
1112 if (host->mrq)
1113 pr_debug("request not null\n");
1114
1115 host->last_req_ts = jiffies;
1116 wmb();
1117 host->mrq = mrq;
1118
1119 if (mrq->data) {
1120 ret = tmio_mmc_start_data(host, mrq->data);
1121 if (ret)
1122 goto fail;
1123 }
1124
1125 ret = tmio_mmc_start_command(host, mrq->cmd);
1126 if (!ret) {
1127 schedule_delayed_work(&host->delayed_reset_work,
1128 msecs_to_jiffies(2000));
1129 return;
1130 }
1131
1132 fail:
1133 host->mrq = NULL;
1134 host->force_pio = false;
1135 mrq->cmd->error = ret;
1136 mmc_request_done(mmc, mrq);
1137 }
1138
1139 /* Set MMC clock / power.
1140 * Note: This controller uses a simple divider scheme therefore it cannot
1141 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
1142 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
1143 * slowest setting.
1144 */
1145 static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1146 {
1147 struct tmio_mmc_host *host = mmc_priv(mmc);
1148
1149 if (ios->clock)
1150 tmio_mmc_set_clock(host, ios->clock);
1151
1152 /* Power sequence - OFF -> ON -> UP */
1153 switch (ios->power_mode) {
1154 case MMC_POWER_OFF: /* power down SD bus */
1155 if (host->set_pwr)
1156 host->set_pwr(host->pdev, 0);
1157 tmio_mmc_clk_stop(host);
1158 break;
1159 case MMC_POWER_ON: /* power up SD bus */
1160 if (host->set_pwr)
1161 host->set_pwr(host->pdev, 1);
1162 break;
1163 case MMC_POWER_UP: /* start bus clock */
1164 tmio_mmc_clk_start(host);
1165 break;
1166 }
1167
1168 switch (ios->bus_width) {
1169 case MMC_BUS_WIDTH_1:
1170 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0);
1171 break;
1172 case MMC_BUS_WIDTH_4:
1173 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0);
1174 break;
1175 }
1176
1177 /* Let things settle. delay taken from winCE driver */
1178 udelay(140);
1179 }
1180
1181 static int tmio_mmc_get_ro(struct mmc_host *mmc)
1182 {
1183 struct tmio_mmc_host *host = mmc_priv(mmc);
1184 struct tmio_mmc_data *pdata = mfd_get_data(host->pdev);
1185
1186 return ((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
1187 (sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT)) ? 0 : 1;
1188 }
1189
1190 static int tmio_mmc_get_cd(struct mmc_host *mmc)
1191 {
1192 struct tmio_mmc_host *host = mmc_priv(mmc);
1193 struct tmio_mmc_data *pdata = mfd_get_data(host->pdev);
1194
1195 if (!pdata->get_cd)
1196 return -ENOSYS;
1197 else
1198 return pdata->get_cd(host->pdev);
1199 }
1200
1201 static const struct mmc_host_ops tmio_mmc_ops = {
1202 .request = tmio_mmc_request,
1203 .set_ios = tmio_mmc_set_ios,
1204 .get_ro = tmio_mmc_get_ro,
1205 .get_cd = tmio_mmc_get_cd,
1206 .enable_sdio_irq = tmio_mmc_enable_sdio_irq,
1207 };
1208
1209 #ifdef CONFIG_PM
1210 static int tmio_mmc_suspend(struct platform_device *dev, pm_message_t state)
1211 {
1212 const struct mfd_cell *cell = mfd_get_cell(dev);
1213 struct mmc_host *mmc = platform_get_drvdata(dev);
1214 int ret;
1215
1216 ret = mmc_suspend_host(mmc);
1217
1218 /* Tell MFD core it can disable us now.*/
1219 if (!ret && cell->disable)
1220 cell->disable(dev);
1221
1222 return ret;
1223 }
1224
1225 static int tmio_mmc_resume(struct platform_device *dev)
1226 {
1227 const struct mfd_cell *cell = mfd_get_cell(dev);
1228 struct mmc_host *mmc = platform_get_drvdata(dev);
1229 int ret = 0;
1230
1231 /* Tell the MFD core we are ready to be enabled */
1232 if (cell->resume) {
1233 ret = cell->resume(dev);
1234 if (ret)
1235 goto out;
1236 }
1237
1238 mmc_resume_host(mmc);
1239
1240 out:
1241 return ret;
1242 }
1243 #else
1244 #define tmio_mmc_suspend NULL
1245 #define tmio_mmc_resume NULL
1246 #endif
1247
1248 static int __devinit tmio_mmc_probe(struct platform_device *dev)
1249 {
1250 const struct mfd_cell *cell = mfd_get_cell(dev);
1251 struct tmio_mmc_data *pdata;
1252 struct resource *res_ctl;
1253 struct tmio_mmc_host *host;
1254 struct mmc_host *mmc;
1255 int ret = -EINVAL;
1256 u32 irq_mask = TMIO_MASK_CMD;
1257
1258 if (dev->num_resources != 2)
1259 goto out;
1260
1261 res_ctl = platform_get_resource(dev, IORESOURCE_MEM, 0);
1262 if (!res_ctl)
1263 goto out;
1264
1265 pdata = mfd_get_data(dev);
1266 if (!pdata || !pdata->hclk)
1267 goto out;
1268
1269 ret = -ENOMEM;
1270
1271 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &dev->dev);
1272 if (!mmc)
1273 goto out;
1274
1275 host = mmc_priv(mmc);
1276 host->mmc = mmc;
1277 host->pdev = dev;
1278 platform_set_drvdata(dev, mmc);
1279
1280 host->set_pwr = pdata->set_pwr;
1281 host->set_clk_div = pdata->set_clk_div;
1282
1283 /* SD control register space size is 0x200, 0x400 for bus_shift=1 */
1284 host->bus_shift = resource_size(res_ctl) >> 10;
1285
1286 host->ctl = ioremap(res_ctl->start, resource_size(res_ctl));
1287 if (!host->ctl)
1288 goto host_free;
1289
1290 mmc->ops = &tmio_mmc_ops;
1291 mmc->caps = MMC_CAP_4_BIT_DATA | pdata->capabilities;
1292 mmc->f_max = pdata->hclk;
1293 mmc->f_min = mmc->f_max / 512;
1294 mmc->max_segs = 32;
1295 mmc->max_blk_size = 512;
1296 mmc->max_blk_count = (PAGE_CACHE_SIZE / mmc->max_blk_size) *
1297 mmc->max_segs;
1298 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1299 mmc->max_seg_size = mmc->max_req_size;
1300 if (pdata->ocr_mask)
1301 mmc->ocr_avail = pdata->ocr_mask;
1302 else
1303 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1304
1305 /* Tell the MFD core we are ready to be enabled */
1306 if (cell->enable) {
1307 ret = cell->enable(dev);
1308 if (ret)
1309 goto unmap_ctl;
1310 }
1311
1312 tmio_mmc_clk_stop(host);
1313 reset(host);
1314
1315 ret = platform_get_irq(dev, 0);
1316 if (ret >= 0)
1317 host->irq = ret;
1318 else
1319 goto cell_disable;
1320
1321 disable_mmc_irqs(host, TMIO_MASK_ALL);
1322 if (pdata->flags & TMIO_MMC_SDIO_IRQ)
1323 tmio_mmc_enable_sdio_irq(mmc, 0);
1324
1325 ret = request_irq(host->irq, tmio_mmc_irq, IRQF_DISABLED |
1326 IRQF_TRIGGER_FALLING, dev_name(&dev->dev), host);
1327 if (ret)
1328 goto cell_disable;
1329
1330 spin_lock_init(&host->lock);
1331
1332 /* Init delayed work for request timeouts */
1333 INIT_DELAYED_WORK(&host->delayed_reset_work, tmio_mmc_reset_work);
1334
1335 /* See if we also get DMA */
1336 tmio_mmc_request_dma(host, pdata);
1337
1338 mmc_add_host(mmc);
1339
1340 pr_info("%s at 0x%08lx irq %d\n", mmc_hostname(host->mmc),
1341 (unsigned long)host->ctl, host->irq);
1342
1343 /* Unmask the IRQs we want to know about */
1344 if (!host->chan_rx)
1345 irq_mask |= TMIO_MASK_READOP;
1346 if (!host->chan_tx)
1347 irq_mask |= TMIO_MASK_WRITEOP;
1348 enable_mmc_irqs(host, irq_mask);
1349
1350 return 0;
1351
1352 cell_disable:
1353 if (cell->disable)
1354 cell->disable(dev);
1355 unmap_ctl:
1356 iounmap(host->ctl);
1357 host_free:
1358 mmc_free_host(mmc);
1359 out:
1360 return ret;
1361 }
1362
1363 static int __devexit tmio_mmc_remove(struct platform_device *dev)
1364 {
1365 const struct mfd_cell *cell = mfd_get_cell(dev);
1366 struct mmc_host *mmc = platform_get_drvdata(dev);
1367
1368 platform_set_drvdata(dev, NULL);
1369
1370 if (mmc) {
1371 struct tmio_mmc_host *host = mmc_priv(mmc);
1372 mmc_remove_host(mmc);
1373 cancel_delayed_work_sync(&host->delayed_reset_work);
1374 tmio_mmc_release_dma(host);
1375 free_irq(host->irq, host);
1376 if (cell->disable)
1377 cell->disable(dev);
1378 iounmap(host->ctl);
1379 mmc_free_host(mmc);
1380 }
1381
1382 return 0;
1383 }
1384
1385 /* ------------------- device registration ----------------------- */
1386
1387 static struct platform_driver tmio_mmc_driver = {
1388 .driver = {
1389 .name = "tmio-mmc",
1390 .owner = THIS_MODULE,
1391 },
1392 .probe = tmio_mmc_probe,
1393 .remove = __devexit_p(tmio_mmc_remove),
1394 .suspend = tmio_mmc_suspend,
1395 .resume = tmio_mmc_resume,
1396 };
1397
1398
1399 static int __init tmio_mmc_init(void)
1400 {
1401 return platform_driver_register(&tmio_mmc_driver);
1402 }
1403
1404 static void __exit tmio_mmc_exit(void)
1405 {
1406 platform_driver_unregister(&tmio_mmc_driver);
1407 }
1408
1409 module_init(tmio_mmc_init);
1410 module_exit(tmio_mmc_exit);
1411
1412 MODULE_DESCRIPTION("Toshiba TMIO SD/MMC driver");
1413 MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
1414 MODULE_LICENSE("GPL v2");
1415 MODULE_ALIAS("platform:tmio-mmc");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree