2 * Performance counter x86 architecture code
4 * Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright(C) 2008 Red Hat, Inc., Ingo Molnar
6 * Copyright(C) 2009 Jaswinder Singh Rajput
8 * For licencing details see kernel-base/COPYING
11 #include <linux/perf_counter.h>
12 #include <linux/capability.h>
13 #include <linux/notifier.h>
14 #include <linux/hardirq.h>
15 #include <linux/kprobes.h>
16 #include <linux/module.h>
17 #include <linux/kdebug.h>
18 #include <linux/sched.h>
19 #include <linux/uaccess.h>
22 #include <asm/stacktrace.h>
25 static bool perf_counters_initialized __read_mostly
;
28 * Number of (generic) HW counters:
30 static int nr_counters_generic __read_mostly
;
31 static u64 perf_counter_mask __read_mostly
;
32 static u64 counter_value_mask __read_mostly
;
33 static int counter_value_bits __read_mostly
;
35 static int nr_counters_fixed __read_mostly
;
37 struct cpu_hw_counters
{
38 struct perf_counter
*counters
[X86_PMC_IDX_MAX
];
39 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
40 unsigned long interrupts
;
42 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
47 * struct x86_pmu - generic x86 pmu
50 u64 (*save_disable_all
)(void);
51 void (*restore_all
)(u64
);
52 u64 (*get_status
)(u64
);
53 void (*ack_status
)(u64
);
54 void (*enable
)(int, u64
);
55 void (*disable
)(int, u64
);
58 u64 (*event_map
)(int);
59 u64 (*raw_event
)(u64
);
63 static struct x86_pmu
*x86_pmu __read_mostly
;
65 static DEFINE_PER_CPU(struct cpu_hw_counters
, cpu_hw_counters
) = {
69 static __read_mostly
int intel_perfmon_version
;
72 * Intel PerfMon v3. Used on Core2 and later.
74 static const u64 intel_perfmon_event_map
[] =
76 [PERF_COUNT_CPU_CYCLES
] = 0x003c,
77 [PERF_COUNT_INSTRUCTIONS
] = 0x00c0,
78 [PERF_COUNT_CACHE_REFERENCES
] = 0x4f2e,
79 [PERF_COUNT_CACHE_MISSES
] = 0x412e,
80 [PERF_COUNT_BRANCH_INSTRUCTIONS
] = 0x00c4,
81 [PERF_COUNT_BRANCH_MISSES
] = 0x00c5,
82 [PERF_COUNT_BUS_CYCLES
] = 0x013c,
85 static u64
intel_pmu_event_map(int event
)
87 return intel_perfmon_event_map
[event
];
90 static u64
intel_pmu_raw_event(u64 event
)
92 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
93 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
94 #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
96 #define CORE_EVNTSEL_MASK \
97 (CORE_EVNTSEL_EVENT_MASK | \
98 CORE_EVNTSEL_UNIT_MASK | \
99 CORE_EVNTSEL_COUNTER_MASK)
101 return event
& CORE_EVNTSEL_MASK
;
105 * AMD Performance Monitor K7 and later.
107 static const u64 amd_perfmon_event_map
[] =
109 [PERF_COUNT_CPU_CYCLES
] = 0x0076,
110 [PERF_COUNT_INSTRUCTIONS
] = 0x00c0,
111 [PERF_COUNT_CACHE_REFERENCES
] = 0x0080,
112 [PERF_COUNT_CACHE_MISSES
] = 0x0081,
113 [PERF_COUNT_BRANCH_INSTRUCTIONS
] = 0x00c4,
114 [PERF_COUNT_BRANCH_MISSES
] = 0x00c5,
117 static u64
amd_pmu_event_map(int event
)
119 return amd_perfmon_event_map
[event
];
122 static u64
amd_pmu_raw_event(u64 event
)
124 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
125 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
126 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
128 #define K7_EVNTSEL_MASK \
129 (K7_EVNTSEL_EVENT_MASK | \
130 K7_EVNTSEL_UNIT_MASK | \
131 K7_EVNTSEL_COUNTER_MASK)
133 return event
& K7_EVNTSEL_MASK
;
137 * Propagate counter elapsed time into the generic counter.
138 * Can only be executed on the CPU where the counter is active.
139 * Returns the delta events processed.
142 x86_perf_counter_update(struct perf_counter
*counter
,
143 struct hw_perf_counter
*hwc
, int idx
)
145 u64 prev_raw_count
, new_raw_count
, delta
;
148 * Careful: an NMI might modify the previous counter value.
150 * Our tactic to handle this is to first atomically read and
151 * exchange a new raw count - then add that new-prev delta
152 * count to the generic counter atomically:
155 prev_raw_count
= atomic64_read(&hwc
->prev_count
);
156 rdmsrl(hwc
->counter_base
+ idx
, new_raw_count
);
158 if (atomic64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
159 new_raw_count
) != prev_raw_count
)
163 * Now we have the new raw value and have updated the prev
164 * timestamp already. We can now calculate the elapsed delta
165 * (counter-)time and add that to the generic counter.
167 * Careful, not all hw sign-extends above the physical width
168 * of the count, so we do that by clipping the delta to 32 bits:
170 delta
= (u64
)(u32
)((s32
)new_raw_count
- (s32
)prev_raw_count
);
172 atomic64_add(delta
, &counter
->count
);
173 atomic64_sub(delta
, &hwc
->period_left
);
176 static atomic_t num_counters
;
177 static DEFINE_MUTEX(pmc_reserve_mutex
);
179 static bool reserve_pmc_hardware(void)
183 if (nmi_watchdog
== NMI_LOCAL_APIC
)
184 disable_lapic_nmi_watchdog();
186 for (i
= 0; i
< nr_counters_generic
; i
++) {
187 if (!reserve_perfctr_nmi(x86_pmu
->perfctr
+ i
))
191 for (i
= 0; i
< nr_counters_generic
; i
++) {
192 if (!reserve_evntsel_nmi(x86_pmu
->eventsel
+ i
))
199 for (i
--; i
>= 0; i
--)
200 release_evntsel_nmi(x86_pmu
->eventsel
+ i
);
202 i
= nr_counters_generic
;
205 for (i
--; i
>= 0; i
--)
206 release_perfctr_nmi(x86_pmu
->perfctr
+ i
);
208 if (nmi_watchdog
== NMI_LOCAL_APIC
)
209 enable_lapic_nmi_watchdog();
214 static void release_pmc_hardware(void)
218 for (i
= 0; i
< nr_counters_generic
; i
++) {
219 release_perfctr_nmi(x86_pmu
->perfctr
+ i
);
220 release_evntsel_nmi(x86_pmu
->eventsel
+ i
);
223 if (nmi_watchdog
== NMI_LOCAL_APIC
)
224 enable_lapic_nmi_watchdog();
227 static void hw_perf_counter_destroy(struct perf_counter
*counter
)
229 if (atomic_dec_and_mutex_lock(&num_counters
, &pmc_reserve_mutex
)) {
230 release_pmc_hardware();
231 mutex_unlock(&pmc_reserve_mutex
);
236 * Setup the hardware configuration for a given hw_event_type
238 static int __hw_perf_counter_init(struct perf_counter
*counter
)
240 struct perf_counter_hw_event
*hw_event
= &counter
->hw_event
;
241 struct hw_perf_counter
*hwc
= &counter
->hw
;
244 if (unlikely(!perf_counters_initialized
))
248 if (atomic_inc_not_zero(&num_counters
)) {
249 mutex_lock(&pmc_reserve_mutex
);
250 if (atomic_read(&num_counters
) == 0 && !reserve_pmc_hardware())
253 atomic_inc(&num_counters
);
254 mutex_unlock(&pmc_reserve_mutex
);
261 * (keep 'enabled' bit clear for now)
263 hwc
->config
= ARCH_PERFMON_EVENTSEL_INT
;
266 * Count user and OS events unless requested not to.
268 if (!hw_event
->exclude_user
)
269 hwc
->config
|= ARCH_PERFMON_EVENTSEL_USR
;
270 if (!hw_event
->exclude_kernel
)
271 hwc
->config
|= ARCH_PERFMON_EVENTSEL_OS
;
274 * If privileged enough, allow NMI events:
277 if (capable(CAP_SYS_ADMIN
) && hw_event
->nmi
)
280 hwc
->irq_period
= hw_event
->irq_period
;
282 * Intel PMCs cannot be accessed sanely above 32 bit width,
283 * so we install an artificial 1<<31 period regardless of
284 * the generic counter period:
286 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
287 if ((s64
)hwc
->irq_period
<= 0 || hwc
->irq_period
> 0x7FFFFFFF)
288 hwc
->irq_period
= 0x7FFFFFFF;
290 atomic64_set(&hwc
->period_left
, hwc
->irq_period
);
293 * Raw event type provide the config in the event structure
295 if (perf_event_raw(hw_event
)) {
296 hwc
->config
|= x86_pmu
->raw_event(perf_event_config(hw_event
));
298 if (perf_event_id(hw_event
) >= x86_pmu
->max_events
)
303 hwc
->config
|= x86_pmu
->event_map(perf_event_id(hw_event
));
306 counter
->destroy
= hw_perf_counter_destroy
;
311 static u64
intel_pmu_save_disable_all(void)
315 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
316 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
321 static u64
amd_pmu_save_disable_all(void)
323 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
326 enabled
= cpuc
->enabled
;
329 * ensure we write the disable before we start disabling the
330 * counters proper, so that amd_pmu_enable_counter() does the
335 for (idx
= 0; idx
< nr_counters_generic
; idx
++) {
338 if (!test_bit(idx
, cpuc
->active_mask
))
340 rdmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
341 if (!(val
& ARCH_PERFMON_EVENTSEL0_ENABLE
))
343 val
&= ~ARCH_PERFMON_EVENTSEL0_ENABLE
;
344 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
350 u64
hw_perf_save_disable(void)
352 if (unlikely(!perf_counters_initialized
))
355 return x86_pmu
->save_disable_all();
358 * Exported because of ACPI idle
360 EXPORT_SYMBOL_GPL(hw_perf_save_disable
);
362 static void intel_pmu_restore_all(u64 ctrl
)
364 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
367 static void amd_pmu_restore_all(u64 ctrl
)
369 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
372 cpuc
->enabled
= ctrl
;
377 for (idx
= 0; idx
< nr_counters_generic
; idx
++) {
380 if (!test_bit(idx
, cpuc
->active_mask
))
382 rdmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
383 if (val
& ARCH_PERFMON_EVENTSEL0_ENABLE
)
385 val
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
386 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
390 void hw_perf_restore(u64 ctrl
)
392 if (unlikely(!perf_counters_initialized
))
395 x86_pmu
->restore_all(ctrl
);
398 * Exported because of ACPI idle
400 EXPORT_SYMBOL_GPL(hw_perf_restore
);
402 static u64
intel_pmu_get_status(u64 mask
)
406 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
411 static u64
amd_pmu_get_status(u64 mask
)
416 for (idx
= 0; idx
< nr_counters_generic
; idx
++) {
419 if (!(mask
& (1 << idx
)))
422 rdmsrl(MSR_K7_PERFCTR0
+ idx
, val
);
423 val
<<= (64 - counter_value_bits
);
425 status
|= (1 << idx
);
431 static u64
hw_perf_get_status(u64 mask
)
433 if (unlikely(!perf_counters_initialized
))
436 return x86_pmu
->get_status(mask
);
439 static void intel_pmu_ack_status(u64 ack
)
441 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, ack
);
444 static void amd_pmu_ack_status(u64 ack
)
448 static void hw_perf_ack_status(u64 ack
)
450 if (unlikely(!perf_counters_initialized
))
453 x86_pmu
->ack_status(ack
);
456 static void intel_pmu_enable_counter(int idx
, u64 config
)
458 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0
+ idx
,
459 config
| ARCH_PERFMON_EVENTSEL0_ENABLE
);
462 static void amd_pmu_enable_counter(int idx
, u64 config
)
464 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
466 set_bit(idx
, cpuc
->active_mask
);
468 config
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
470 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, config
);
473 static void hw_perf_enable(int idx
, u64 config
)
475 if (unlikely(!perf_counters_initialized
))
478 x86_pmu
->enable(idx
, config
);
481 static void intel_pmu_disable_counter(int idx
, u64 config
)
483 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0
+ idx
, config
);
486 static void amd_pmu_disable_counter(int idx
, u64 config
)
488 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
490 clear_bit(idx
, cpuc
->active_mask
);
491 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, config
);
495 static void hw_perf_disable(int idx
, u64 config
)
497 if (unlikely(!perf_counters_initialized
))
500 x86_pmu
->disable(idx
, config
);
504 __pmc_fixed_disable(struct perf_counter
*counter
,
505 struct hw_perf_counter
*hwc
, unsigned int __idx
)
507 int idx
= __idx
- X86_PMC_IDX_FIXED
;
511 mask
= 0xfULL
<< (idx
* 4);
513 rdmsrl(hwc
->config_base
, ctrl_val
);
515 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
519 __x86_pmu_disable(struct perf_counter
*counter
,
520 struct hw_perf_counter
*hwc
, unsigned int idx
)
522 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
))
523 __pmc_fixed_disable(counter
, hwc
, idx
);
525 hw_perf_disable(idx
, hwc
->config
);
528 static DEFINE_PER_CPU(u64
, prev_left
[X86_PMC_IDX_MAX
]);
531 * Set the next IRQ period, based on the hwc->period_left value.
532 * To be called with the counter disabled in hw:
535 __hw_perf_counter_set_period(struct perf_counter
*counter
,
536 struct hw_perf_counter
*hwc
, int idx
)
538 s64 left
= atomic64_read(&hwc
->period_left
);
539 s64 period
= hwc
->irq_period
;
543 * If we are way outside a reasoable range then just skip forward:
545 if (unlikely(left
<= -period
)) {
547 atomic64_set(&hwc
->period_left
, left
);
550 if (unlikely(left
<= 0)) {
552 atomic64_set(&hwc
->period_left
, left
);
555 per_cpu(prev_left
[idx
], smp_processor_id()) = left
;
558 * The hw counter starts counting from this counter offset,
559 * mark it to be able to extra future deltas:
561 atomic64_set(&hwc
->prev_count
, (u64
)-left
);
563 err
= checking_wrmsrl(hwc
->counter_base
+ idx
,
564 (u64
)(-left
) & counter_value_mask
);
568 __pmc_fixed_enable(struct perf_counter
*counter
,
569 struct hw_perf_counter
*hwc
, unsigned int __idx
)
571 int idx
= __idx
- X86_PMC_IDX_FIXED
;
572 u64 ctrl_val
, bits
, mask
;
576 * Enable IRQ generation (0x8),
577 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
581 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_USR
)
583 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_OS
)
586 mask
= 0xfULL
<< (idx
* 4);
588 rdmsrl(hwc
->config_base
, ctrl_val
);
591 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
595 __x86_pmu_enable(struct perf_counter
*counter
,
596 struct hw_perf_counter
*hwc
, int idx
)
598 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
))
599 __pmc_fixed_enable(counter
, hwc
, idx
);
601 hw_perf_enable(idx
, hwc
->config
);
605 fixed_mode_idx(struct perf_counter
*counter
, struct hw_perf_counter
*hwc
)
609 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
612 if (unlikely(hwc
->nmi
))
615 event
= hwc
->config
& ARCH_PERFMON_EVENT_MASK
;
617 if (unlikely(event
== x86_pmu
->event_map(PERF_COUNT_INSTRUCTIONS
)))
618 return X86_PMC_IDX_FIXED_INSTRUCTIONS
;
619 if (unlikely(event
== x86_pmu
->event_map(PERF_COUNT_CPU_CYCLES
)))
620 return X86_PMC_IDX_FIXED_CPU_CYCLES
;
621 if (unlikely(event
== x86_pmu
->event_map(PERF_COUNT_BUS_CYCLES
)))
622 return X86_PMC_IDX_FIXED_BUS_CYCLES
;
628 * Find a PMC slot for the freshly enabled / scheduled in counter:
630 static int x86_pmu_enable(struct perf_counter
*counter
)
632 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
633 struct hw_perf_counter
*hwc
= &counter
->hw
;
636 idx
= fixed_mode_idx(counter
, hwc
);
639 * Try to get the fixed counter, if that is already taken
640 * then try to get a generic counter:
642 if (test_and_set_bit(idx
, cpuc
->used
))
645 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
647 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
648 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
651 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
655 /* Try to get the previous generic counter again */
656 if (test_and_set_bit(idx
, cpuc
->used
)) {
658 idx
= find_first_zero_bit(cpuc
->used
, nr_counters_generic
);
659 if (idx
== nr_counters_generic
)
662 set_bit(idx
, cpuc
->used
);
665 hwc
->config_base
= x86_pmu
->eventsel
;
666 hwc
->counter_base
= x86_pmu
->perfctr
;
669 perf_counters_lapic_init(hwc
->nmi
);
671 __x86_pmu_disable(counter
, hwc
, idx
);
673 cpuc
->counters
[idx
] = counter
;
675 * Make it visible before enabling the hw:
679 __hw_perf_counter_set_period(counter
, hwc
, idx
);
680 __x86_pmu_enable(counter
, hwc
, idx
);
685 void perf_counter_print_debug(void)
687 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
688 struct cpu_hw_counters
*cpuc
;
691 if (!nr_counters_generic
)
696 cpu
= smp_processor_id();
697 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
699 if (intel_perfmon_version
>= 2) {
700 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
701 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
702 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
703 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
706 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
707 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
708 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
709 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
711 pr_info("CPU#%d: used: %016llx\n", cpu
, *(u64
*)cpuc
->used
);
713 for (idx
= 0; idx
< nr_counters_generic
; idx
++) {
714 rdmsrl(x86_pmu
->eventsel
+ idx
, pmc_ctrl
);
715 rdmsrl(x86_pmu
->perfctr
+ idx
, pmc_count
);
717 prev_left
= per_cpu(prev_left
[idx
], cpu
);
719 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
721 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
722 cpu
, idx
, pmc_count
);
723 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
724 cpu
, idx
, prev_left
);
726 for (idx
= 0; idx
< nr_counters_fixed
; idx
++) {
727 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
729 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
730 cpu
, idx
, pmc_count
);
735 static void x86_pmu_disable(struct perf_counter
*counter
)
737 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
738 struct hw_perf_counter
*hwc
= &counter
->hw
;
739 unsigned int idx
= hwc
->idx
;
741 __x86_pmu_disable(counter
, hwc
, idx
);
743 clear_bit(idx
, cpuc
->used
);
744 cpuc
->counters
[idx
] = NULL
;
746 * Make sure the cleared pointer becomes visible before we
747 * (potentially) free the counter:
752 * Drain the remaining delta count out of a counter
753 * that we are disabling:
755 x86_perf_counter_update(counter
, hwc
, idx
);
759 * Save and restart an expired counter. Called by NMI contexts,
760 * so it has to be careful about preempting normal counter ops:
762 static void perf_save_and_restart(struct perf_counter
*counter
)
764 struct hw_perf_counter
*hwc
= &counter
->hw
;
767 x86_perf_counter_update(counter
, hwc
, idx
);
768 __hw_perf_counter_set_period(counter
, hwc
, idx
);
770 if (counter
->state
== PERF_COUNTER_STATE_ACTIVE
)
771 __x86_pmu_enable(counter
, hwc
, idx
);
775 * Maximum interrupt frequency of 100KHz per CPU
777 #define PERFMON_MAX_INTERRUPTS (100000/HZ)
780 * This handler is triggered by the local APIC, so the APIC IRQ handling
783 static int __smp_perf_counter_interrupt(struct pt_regs
*regs
, int nmi
)
785 int bit
, cpu
= smp_processor_id();
787 struct cpu_hw_counters
*cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
790 cpuc
->throttle_ctrl
= hw_perf_save_disable();
792 status
= hw_perf_get_status(cpuc
->throttle_ctrl
);
798 inc_irq_stat(apic_perf_irqs
);
800 for_each_bit(bit
, (unsigned long *)&status
, X86_PMC_IDX_MAX
) {
801 struct perf_counter
*counter
= cpuc
->counters
[bit
];
803 clear_bit(bit
, (unsigned long *) &status
);
807 perf_save_and_restart(counter
);
808 if (perf_counter_overflow(counter
, nmi
, regs
, 0))
809 __x86_pmu_disable(counter
, &counter
->hw
, bit
);
812 hw_perf_ack_status(ack
);
815 * Repeat if there is more work to be done:
817 status
= hw_perf_get_status(cpuc
->throttle_ctrl
);
822 * Restore - do not reenable when global enable is off or throttled:
824 if (++cpuc
->interrupts
< PERFMON_MAX_INTERRUPTS
)
825 hw_perf_restore(cpuc
->throttle_ctrl
);
830 void perf_counter_unthrottle(void)
832 struct cpu_hw_counters
*cpuc
;
834 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
))
837 if (unlikely(!perf_counters_initialized
))
840 cpuc
= &__get_cpu_var(cpu_hw_counters
);
841 if (cpuc
->interrupts
>= PERFMON_MAX_INTERRUPTS
) {
842 if (printk_ratelimit())
843 printk(KERN_WARNING
"PERFMON: max interrupts exceeded!\n");
844 hw_perf_restore(cpuc
->throttle_ctrl
);
846 cpuc
->interrupts
= 0;
849 void smp_perf_counter_interrupt(struct pt_regs
*regs
)
852 apic_write(APIC_LVTPC
, LOCAL_PERF_VECTOR
);
854 __smp_perf_counter_interrupt(regs
, 0);
858 void smp_perf_pending_interrupt(struct pt_regs
*regs
)
862 inc_irq_stat(apic_pending_irqs
);
863 perf_counter_do_pending();
867 void set_perf_counter_pending(void)
869 apic
->send_IPI_self(LOCAL_PENDING_VECTOR
);
872 void perf_counters_lapic_init(int nmi
)
876 if (!perf_counters_initialized
)
879 * Enable the performance counter vector in the APIC LVT:
881 apic_val
= apic_read(APIC_LVTERR
);
883 apic_write(APIC_LVTERR
, apic_val
| APIC_LVT_MASKED
);
885 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
887 apic_write(APIC_LVTPC
, LOCAL_PERF_VECTOR
);
888 apic_write(APIC_LVTERR
, apic_val
);
892 perf_counter_nmi_handler(struct notifier_block
*self
,
893 unsigned long cmd
, void *__args
)
895 struct die_args
*args
= __args
;
896 struct pt_regs
*regs
;
910 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
911 ret
= __smp_perf_counter_interrupt(regs
, 1);
913 return ret
? NOTIFY_STOP
: NOTIFY_OK
;
916 static __read_mostly
struct notifier_block perf_counter_nmi_notifier
= {
917 .notifier_call
= perf_counter_nmi_handler
,
922 static struct x86_pmu intel_pmu
= {
923 .save_disable_all
= intel_pmu_save_disable_all
,
924 .restore_all
= intel_pmu_restore_all
,
925 .get_status
= intel_pmu_get_status
,
926 .ack_status
= intel_pmu_ack_status
,
927 .enable
= intel_pmu_enable_counter
,
928 .disable
= intel_pmu_disable_counter
,
929 .eventsel
= MSR_ARCH_PERFMON_EVENTSEL0
,
930 .perfctr
= MSR_ARCH_PERFMON_PERFCTR0
,
931 .event_map
= intel_pmu_event_map
,
932 .raw_event
= intel_pmu_raw_event
,
933 .max_events
= ARRAY_SIZE(intel_perfmon_event_map
),
936 static struct x86_pmu amd_pmu
= {
937 .save_disable_all
= amd_pmu_save_disable_all
,
938 .restore_all
= amd_pmu_restore_all
,
939 .get_status
= amd_pmu_get_status
,
940 .ack_status
= amd_pmu_ack_status
,
941 .enable
= amd_pmu_enable_counter
,
942 .disable
= amd_pmu_disable_counter
,
943 .eventsel
= MSR_K7_EVNTSEL0
,
944 .perfctr
= MSR_K7_PERFCTR0
,
945 .event_map
= amd_pmu_event_map
,
946 .raw_event
= amd_pmu_raw_event
,
947 .max_events
= ARRAY_SIZE(amd_perfmon_event_map
),
950 static struct x86_pmu
*intel_pmu_init(void)
952 union cpuid10_edx edx
;
953 union cpuid10_eax eax
;
957 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
))
961 * Check whether the Architectural PerfMon supports
962 * Branch Misses Retired Event or not.
964 cpuid(10, &eax
.full
, &ebx
, &unused
, &edx
.full
);
965 if (eax
.split
.mask_length
<= ARCH_PERFMON_BRANCH_MISSES_RETIRED
)
968 intel_perfmon_version
= eax
.split
.version_id
;
969 if (intel_perfmon_version
< 2)
972 pr_info("Intel Performance Monitoring support detected.\n");
973 pr_info("... version: %d\n", intel_perfmon_version
);
974 pr_info("... bit width: %d\n", eax
.split
.bit_width
);
975 pr_info("... mask length: %d\n", eax
.split
.mask_length
);
977 nr_counters_generic
= eax
.split
.num_counters
;
978 nr_counters_fixed
= edx
.split
.num_counters_fixed
;
979 counter_value_mask
= (1ULL << eax
.split
.bit_width
) - 1;
984 static struct x86_pmu
*amd_pmu_init(void)
986 nr_counters_generic
= 4;
987 nr_counters_fixed
= 0;
988 counter_value_mask
= 0x0000FFFFFFFFFFFFULL
;
989 counter_value_bits
= 48;
991 pr_info("AMD Performance Monitoring support detected.\n");
996 void __init
init_hw_perf_counters(void)
998 switch (boot_cpu_data
.x86_vendor
) {
999 case X86_VENDOR_INTEL
:
1000 x86_pmu
= intel_pmu_init();
1002 case X86_VENDOR_AMD
:
1003 x86_pmu
= amd_pmu_init();
1011 pr_info("... num counters: %d\n", nr_counters_generic
);
1012 if (nr_counters_generic
> X86_PMC_MAX_GENERIC
) {
1013 nr_counters_generic
= X86_PMC_MAX_GENERIC
;
1014 WARN(1, KERN_ERR
"hw perf counters %d > max(%d), clipping!",
1015 nr_counters_generic
, X86_PMC_MAX_GENERIC
);
1017 perf_counter_mask
= (1 << nr_counters_generic
) - 1;
1018 perf_max_counters
= nr_counters_generic
;
1020 pr_info("... value mask: %016Lx\n", counter_value_mask
);
1022 if (nr_counters_fixed
> X86_PMC_MAX_FIXED
) {
1023 nr_counters_fixed
= X86_PMC_MAX_FIXED
;
1024 WARN(1, KERN_ERR
"hw perf counters fixed %d > max(%d), clipping!",
1025 nr_counters_fixed
, X86_PMC_MAX_FIXED
);
1027 pr_info("... fixed counters: %d\n", nr_counters_fixed
);
1029 perf_counter_mask
|= ((1LL << nr_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
1031 pr_info("... counter mask: %016Lx\n", perf_counter_mask
);
1032 perf_counters_initialized
= true;
1034 perf_counters_lapic_init(0);
1035 register_die_notifier(&perf_counter_nmi_notifier
);
1038 static void x86_pmu_read(struct perf_counter
*counter
)
1040 x86_perf_counter_update(counter
, &counter
->hw
, counter
->hw
.idx
);
1043 static const struct pmu pmu
= {
1044 .enable
= x86_pmu_enable
,
1045 .disable
= x86_pmu_disable
,
1046 .read
= x86_pmu_read
,
1049 const struct pmu
*hw_perf_counter_init(struct perf_counter
*counter
)
1053 err
= __hw_perf_counter_init(counter
);
1055 return ERR_PTR(err
);
1065 void callchain_store(struct perf_callchain_entry
*entry
, unsigned long ip
)
1067 if (entry
->nr
< MAX_STACK_DEPTH
)
1068 entry
->ip
[entry
->nr
++] = ip
;
1071 static DEFINE_PER_CPU(struct perf_callchain_entry
, irq_entry
);
1072 static DEFINE_PER_CPU(struct perf_callchain_entry
, nmi_entry
);
1076 backtrace_warning_symbol(void *data
, char *msg
, unsigned long symbol
)
1078 /* Ignore warnings */
1081 static void backtrace_warning(void *data
, char *msg
)
1083 /* Ignore warnings */
1086 static int backtrace_stack(void *data
, char *name
)
1088 /* Don't bother with IRQ stacks for now */
1092 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1094 struct perf_callchain_entry
*entry
= data
;
1097 callchain_store(entry
, addr
);
1100 static const struct stacktrace_ops backtrace_ops
= {
1101 .warning
= backtrace_warning
,
1102 .warning_symbol
= backtrace_warning_symbol
,
1103 .stack
= backtrace_stack
,
1104 .address
= backtrace_address
,
1108 perf_callchain_kernel(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1114 callchain_store(entry
, instruction_pointer(regs
));
1116 stack
= ((char *)regs
+ sizeof(struct pt_regs
));
1117 #ifdef CONFIG_FRAME_POINTER
1118 bp
= frame_pointer(regs
);
1123 dump_trace(NULL
, regs
, (void *)stack
, bp
, &backtrace_ops
, entry
);
1125 entry
->kernel
= entry
->nr
- nr
;
1129 struct stack_frame
{
1130 const void __user
*next_fp
;
1131 unsigned long return_address
;
1134 static int copy_stack_frame(const void __user
*fp
, struct stack_frame
*frame
)
1138 if (!access_ok(VERIFY_READ
, fp
, sizeof(*frame
)))
1142 pagefault_disable();
1143 if (__copy_from_user_inatomic(frame
, fp
, sizeof(*frame
)))
1151 perf_callchain_user(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1153 struct stack_frame frame
;
1154 const void __user
*fp
;
1157 regs
= (struct pt_regs
*)current
->thread
.sp0
- 1;
1158 fp
= (void __user
*)regs
->bp
;
1160 callchain_store(entry
, regs
->ip
);
1162 while (entry
->nr
< MAX_STACK_DEPTH
) {
1163 frame
.next_fp
= NULL
;
1164 frame
.return_address
= 0;
1166 if (!copy_stack_frame(fp
, &frame
))
1169 if ((unsigned long)fp
< user_stack_pointer(regs
))
1172 callchain_store(entry
, frame
.return_address
);
1176 entry
->user
= entry
->nr
- nr
;
1180 perf_do_callchain(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1187 is_user
= user_mode(regs
);
1189 if (!current
|| current
->pid
== 0)
1192 if (is_user
&& current
->state
!= TASK_RUNNING
)
1196 perf_callchain_kernel(regs
, entry
);
1199 perf_callchain_user(regs
, entry
);
1202 struct perf_callchain_entry
*perf_callchain(struct pt_regs
*regs
)
1204 struct perf_callchain_entry
*entry
;
1207 entry
= &__get_cpu_var(nmi_entry
);
1209 entry
= &__get_cpu_var(irq_entry
);
1216 perf_do_callchain(regs
, entry
);