drivers/ide/pci/pdc202xx_new.c

   1 /*
   2  *  Promise TX2/TX4/TX2000/133 IDE driver
   3  *
   4  *  This program is free software; you can redistribute it and/or
   5  *  modify it under the terms of the GNU General Public License
   6  *  as published by the Free Software Foundation; either version
   7  *  2 of the License, or (at your option) any later version.
   8  *
   9  *  Split from:
  10  *  linux/drivers/ide/pdc202xx.c        Version 0.35    Mar. 30, 2002
  11  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
  12  *  Copyright (C) 2005-2007             MontaVista Software, Inc.
  13  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  14  *  Author: Frank Tiernan (frankt@promise.com)
  15  *  Released under terms of General Public License
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/types.h>
  20 #include <linux/kernel.h>
  21 #include <linux/delay.h>
  22 #include <linux/timer.h>
  23 #include <linux/mm.h>
  24 #include <linux/ioport.h>
  25 #include <linux/blkdev.h>
  26 #include <linux/hdreg.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/pci.h>
  29 #include <linux/init.h>
  30 #include <linux/ide.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #ifdef CONFIG_PPC_PMAC
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif
  39
  40 #undef DEBUG
  41
  42 #ifdef DEBUG
  43 #define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
  44 #else
  45 #define DBG(fmt, args...)
  46 #endif
  47
  48 static const char *pdc_quirk_drives[] = {
  49         "QUANTUM FIREBALLlct08 08",
  50         "QUANTUM FIREBALLP KA6.4",
  51         "QUANTUM FIREBALLP KA9.1",
  52         "QUANTUM FIREBALLP LM20.4",
  53         "QUANTUM FIREBALLP KX13.6",
  54         "QUANTUM FIREBALLP KX20.5",
  55         "QUANTUM FIREBALLP KX27.3",
  56         "QUANTUM FIREBALLP LM20.5",
  57         NULL
  58 };
  59
  60 static u8 max_dma_rate(struct pci_dev *pdev)
  61 {
  62         u8 mode;
  63
  64         switch(pdev->device) {
  65                 case PCI_DEVICE_ID_PROMISE_20277:
  66                 case PCI_DEVICE_ID_PROMISE_20276:
  67                 case PCI_DEVICE_ID_PROMISE_20275:
  68                 case PCI_DEVICE_ID_PROMISE_20271:
  69                 case PCI_DEVICE_ID_PROMISE_20269:
  70                         mode = 4;
  71                         break;
  72                 case PCI_DEVICE_ID_PROMISE_20270:
  73                 case PCI_DEVICE_ID_PROMISE_20268:
  74                         mode = 3;
  75                         break;
  76                 default:
  77                         return 0;
  78         }
  79
  80         return mode;
  81 }
  82
  83 /**
  84  * get_indexed_reg - Get indexed register
  85  * @hwif: for the port address
  86  * @index: index of the indexed register
  87  */
  88 static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
  89 {
  90         u8 value;
  91
  92         outb(index, hwif->dma_vendor1);
  93         value = inb(hwif->dma_vendor3);
  94
  95         DBG("index[%02X] value[%02X]\n", index, value);
  96         return value;
  97 }
  98
  99 /**
 100  * set_indexed_reg - Set indexed register
 101  * @hwif: for the port address
 102  * @index: index of the indexed register
 103  */
 104 static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
 105 {
 106         outb(index, hwif->dma_vendor1);
 107         outb(value, hwif->dma_vendor3);
 108         DBG("index[%02X] value[%02X]\n", index, value);
 109 }
 110
 111 /*
 112  * ATA Timing Tables based on 133 MHz PLL output clock.
 113  *
 114  * If the PLL outputs 100 MHz clock, the ASIC hardware will set
 115  * the timing registers automatically when "set features" command is
 116  * issued to the device. However, if the PLL output clock is 133 MHz,
 117  * the following tables must be used.
 118  */
 119 static struct pio_timing {
 120         u8 reg0c, reg0d, reg13;
 121 } pio_timings [] = {
 122         { 0xfb, 0x2b, 0xac },   /* PIO mode 0, IORDY off, Prefetch off */
 123         { 0x46, 0x29, 0xa4 },   /* PIO mode 1, IORDY off, Prefetch off */
 124         { 0x23, 0x26, 0x64 },   /* PIO mode 2, IORDY off, Prefetch off */
 125         { 0x27, 0x0d, 0x35 },   /* PIO mode 3, IORDY on,  Prefetch off */
 126         { 0x23, 0x09, 0x25 },   /* PIO mode 4, IORDY on,  Prefetch off */
 127 };
 128
 129 static struct mwdma_timing {
 130         u8 reg0e, reg0f;
 131 } mwdma_timings [] = {
 132         { 0xdf, 0x5f },         /* MWDMA mode 0 */
 133         { 0x6b, 0x27 },         /* MWDMA mode 1 */
 134         { 0x69, 0x25 },         /* MWDMA mode 2 */
 135 };
 136
 137 static struct udma_timing {
 138         u8 reg10, reg11, reg12;
 139 } udma_timings [] = {
 140         { 0x4a, 0x0f, 0xd5 },   /* UDMA mode 0 */
 141         { 0x3a, 0x0a, 0xd0 },   /* UDMA mode 1 */
 142         { 0x2a, 0x07, 0xcd },   /* UDMA mode 2 */
 143         { 0x1a, 0x05, 0xcd },   /* UDMA mode 3 */
 144         { 0x1a, 0x03, 0xcd },   /* UDMA mode 4 */
 145         { 0x1a, 0x02, 0xcb },   /* UDMA mode 5 */
 146         { 0x1a, 0x01, 0xcb },   /* UDMA mode 6 */
 147 };
 148
 149 static void pdcnew_set_mode(ide_drive_t *drive, const u8 speed)
 150 {
 151         ide_hwif_t *hwif        = HWIF(drive);
 152         u8 adj                  = (drive->dn & 1) ? 0x08 : 0x00;
 153
 154         /*
 155          * IDE core issues SETFEATURES_XFER to the drive first (thanks to
 156          * IDE_HFLAG_POST_SET_MODE in ->host_flags).  PDC202xx hardware will
 157          * automatically set the timing registers based on 100 MHz PLL output.
 158          *
 159          * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
 160          * chips, we must override the default register settings...
 161          */
 162         if (max_dma_rate(hwif->pci_dev) == 4) {
 163                 u8 mode = speed & 0x07;
 164
 165                 switch (speed) {
 166                         case XFER_UDMA_6:
 167                         case XFER_UDMA_5:
 168                         case XFER_UDMA_4:
 169                         case XFER_UDMA_3:
 170                         case XFER_UDMA_2:
 171                         case XFER_UDMA_1:
 172                         case XFER_UDMA_0:
 173                                 set_indexed_reg(hwif, 0x10 + adj,
 174                                                 udma_timings[mode].reg10);
 175                                 set_indexed_reg(hwif, 0x11 + adj,
 176                                                 udma_timings[mode].reg11);
 177                                 set_indexed_reg(hwif, 0x12 + adj,
 178                                                 udma_timings[mode].reg12);
 179                                 break;
 180
 181                         case XFER_MW_DMA_2:
 182                         case XFER_MW_DMA_1:
 183                         case XFER_MW_DMA_0:
 184                                 set_indexed_reg(hwif, 0x0e + adj,
 185                                                 mwdma_timings[mode].reg0e);
 186                                 set_indexed_reg(hwif, 0x0f + adj,
 187                                                 mwdma_timings[mode].reg0f);
 188                                 break;
 189                         case XFER_PIO_4:
 190                         case XFER_PIO_3:
 191                         case XFER_PIO_2:
 192                         case XFER_PIO_1:
 193                         case XFER_PIO_0:
 194                                 set_indexed_reg(hwif, 0x0c + adj,
 195                                                 pio_timings[mode].reg0c);
 196                                 set_indexed_reg(hwif, 0x0d + adj,
 197                                                 pio_timings[mode].reg0d);
 198                                 set_indexed_reg(hwif, 0x13 + adj,
 199                                                 pio_timings[mode].reg13);
 200                                 break;
 201                         default:
 202                                 printk(KERN_ERR "pdc202xx_new: "
 203                                        "Unknown speed %d ignored\n", speed);
 204                 }
 205         } else if (speed == XFER_UDMA_2) {
 206                 /* Set tHOLD bit to 0 if using UDMA mode 2 */
 207                 u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
 208
 209                 set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
 210         }
 211 }
 212
 213 static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
 214 {
 215         pdcnew_set_mode(drive, XFER_PIO_0 + pio);
 216 }
 217
 218 static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
 219 {
 220         if (get_indexed_reg(hwif, 0x0b) & 0x04)
 221                 return ATA_CBL_PATA40;
 222         else
 223                 return ATA_CBL_PATA80;
 224 }
 225
 226 static int pdcnew_quirkproc(ide_drive_t *drive)
 227 {
 228         const char **list, *model = drive->id->model;
 229
 230         for (list = pdc_quirk_drives; *list != NULL; list++)
 231                 if (strstr(model, *list) != NULL)
 232                         return 2;
 233         return 0;
 234 }
 235
 236 static void pdcnew_reset(ide_drive_t *drive)
 237 {
 238         /*
 239          * Deleted this because it is redundant from the caller.
 240          */
 241         printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
 242                 HWIF(drive)->channel ? "Secondary" : "Primary");
 243 }
 244
 245 /**
 246  * read_counter - Read the byte count registers
 247  * @dma_base: for the port address
 248  */
 249 static long __devinit read_counter(u32 dma_base)
 250 {
 251         u32  pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
 252         u8   cnt0, cnt1, cnt2, cnt3;
 253         long count = 0, last;
 254         int  retry = 3;
 255
 256         do {
 257                 last = count;
 258
 259                 /* Read the current count */
 260                 outb(0x20, pri_dma_base + 0x01);
 261                 cnt0 = inb(pri_dma_base + 0x03);
 262                 outb(0x21, pri_dma_base + 0x01);
 263                 cnt1 = inb(pri_dma_base + 0x03);
 264                 outb(0x20, sec_dma_base + 0x01);
 265                 cnt2 = inb(sec_dma_base + 0x03);
 266                 outb(0x21, sec_dma_base + 0x01);
 267                 cnt3 = inb(sec_dma_base + 0x03);
 268
 269                 count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
 270
 271                 /*
 272                  * The 30-bit decrementing counter is read in 4 pieces.
 273                  * Incorrect value may be read when the most significant bytes
 274                  * are changing...
 275                  */
 276         } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
 277
 278         DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
 279                   cnt0, cnt1, cnt2, cnt3);
 280
 281         return count;
 282 }
 283
 284 /**
 285  * detect_pll_input_clock - Detect the PLL input clock in Hz.
 286  * @dma_base: for the port address
 287  * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
 288  */
 289 static long __devinit detect_pll_input_clock(unsigned long dma_base)
 290 {
 291         struct timeval start_time, end_time;
 292         long start_count, end_count;
 293         long pll_input, usec_elapsed;
 294         u8 scr1;
 295
 296         start_count = read_counter(dma_base);
 297         do_gettimeofday(&start_time);
 298
 299         /* Start the test mode */
 300         outb(0x01, dma_base + 0x01);
 301         scr1 = inb(dma_base + 0x03);
 302         DBG("scr1[%02X]\n", scr1);
 303         outb(scr1 | 0x40, dma_base + 0x03);
 304
 305         /* Let the counter run for 10 ms. */
 306         mdelay(10);
 307
 308         end_count = read_counter(dma_base);
 309         do_gettimeofday(&end_time);
 310
 311         /* Stop the test mode */
 312         outb(0x01, dma_base + 0x01);
 313         scr1 = inb(dma_base + 0x03);
 314         DBG("scr1[%02X]\n", scr1);
 315         outb(scr1 & ~0x40, dma_base + 0x03);
 316
 317         /*
 318          * Calculate the input clock in Hz
 319          * (the clock counter is 30 bit wide and counts down)
 320          */
 321         usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
 322                 (end_time.tv_usec - start_time.tv_usec);
 323         pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
 324                 (10000000 / usec_elapsed);
 325
 326         DBG("start[%ld] end[%ld]\n", start_count, end_count);
 327
 328         return pll_input;
 329 }
 330
 331 #ifdef CONFIG_PPC_PMAC
 332 static void __devinit apple_kiwi_init(struct pci_dev *pdev)
 333 {
 334         struct device_node *np = pci_device_to_OF_node(pdev);
 335         u8 conf;
 336
 337         if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
 338                 return;
 339
 340         if (pdev->revision >= 0x03) {
 341                 /* Setup chip magic config stuff (from darwin) */
 342                 pci_read_config_byte (pdev, 0x40, &conf);
 343                 pci_write_config_byte(pdev, 0x40, (conf | 0x01));
 344         }
 345 }
 346 #endif /* CONFIG_PPC_PMAC */
 347
 348 static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
 349 {
 350         unsigned long dma_base = pci_resource_start(dev, 4);
 351         unsigned long sec_dma_base = dma_base + 0x08;
 352         long pll_input, pll_output, ratio;
 353         int f, r;
 354         u8 pll_ctl0, pll_ctl1;
 355
 356         if (dma_base == 0)
 357                 return -EFAULT;
 358
 359 #ifdef CONFIG_PPC_PMAC
 360         apple_kiwi_init(dev);
 361 #endif
 362
 363         /* Calculate the required PLL output frequency */
 364         switch(max_dma_rate(dev)) {
 365                 case 4: /* it's 133 MHz for Ultra133 chips */
 366                         pll_output = 133333333;
 367                         break;
 368                 case 3: /* and  100 MHz for Ultra100 chips */
 369                 default:
 370                         pll_output = 100000000;
 371                         break;
 372         }
 373
 374         /*
 375          * Detect PLL input clock.
 376          * On some systems, where PCI bus is running at non-standard clock rate
 377          * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
 378          * PDC20268 and newer chips employ PLL circuit to help correct timing
 379          * registers setting.
 380          */
 381         pll_input = detect_pll_input_clock(dma_base);
 382         printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
 383
 384         /* Sanity check */
 385         if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
 386                 printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
 387                        name, pll_input);
 388                 goto out;
 389         }
 390
 391 #ifdef DEBUG
 392         DBG("pll_output is %ld Hz\n", pll_output);
 393
 394         /* Show the current clock value of PLL control register
 395          * (maybe already configured by the BIOS)
 396          */
 397         outb(0x02, sec_dma_base + 0x01);
 398         pll_ctl0 = inb(sec_dma_base + 0x03);
 399         outb(0x03, sec_dma_base + 0x01);
 400         pll_ctl1 = inb(sec_dma_base + 0x03);
 401
 402         DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
 403 #endif
 404
 405         /*
 406          * Calculate the ratio of F, R and NO
 407          * POUT = (F + 2) / (( R + 2) * NO)
 408          */
 409         ratio = pll_output / (pll_input / 1000);
 410         if (ratio < 8600L) { /* 8.6x */
 411                 /* Using NO = 0x01, R = 0x0d */
 412                 r = 0x0d;
 413         } else if (ratio < 12900L) { /* 12.9x */
 414                 /* Using NO = 0x01, R = 0x08 */
 415                 r = 0x08;
 416         } else if (ratio < 16100L) { /* 16.1x */
 417                 /* Using NO = 0x01, R = 0x06 */
 418                 r = 0x06;
 419         } else if (ratio < 64000L) { /* 64x */
 420                 r = 0x00;
 421         } else {
 422                 /* Invalid ratio */
 423                 printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
 424                 goto out;
 425         }
 426
 427         f = (ratio * (r + 2)) / 1000 - 2;
 428
 429         DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
 430
 431         if (unlikely(f < 0 || f > 127)) {
 432                 /* Invalid F */
 433                 printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
 434                 goto out;
 435         }
 436
 437         pll_ctl0 = (u8) f;
 438         pll_ctl1 = (u8) r;
 439
 440         DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
 441
 442         outb(0x02,     sec_dma_base + 0x01);
 443         outb(pll_ctl0, sec_dma_base + 0x03);
 444         outb(0x03,     sec_dma_base + 0x01);
 445         outb(pll_ctl1, sec_dma_base + 0x03);
 446
 447         /* Wait the PLL circuit to be stable */
 448         mdelay(30);
 449
 450 #ifdef DEBUG
 451         /*
 452          *  Show the current clock value of PLL control register
 453          */
 454         outb(0x02, sec_dma_base + 0x01);
 455         pll_ctl0 = inb(sec_dma_base + 0x03);
 456         outb(0x03, sec_dma_base + 0x01);
 457         pll_ctl1 = inb(sec_dma_base + 0x03);
 458
 459         DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
 460 #endif
 461
 462  out:
 463         return dev->irq;
 464 }
 465
 466 static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
 467 {
 468         hwif->set_pio_mode = &pdcnew_set_pio_mode;
 469         hwif->set_dma_mode = &pdcnew_set_mode;
 470
 471         hwif->quirkproc = &pdcnew_quirkproc;
 472         hwif->resetproc = &pdcnew_reset;
 473
 474         if (hwif->dma_base == 0)
 475                 return;
 476
 477         if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 478                 hwif->cbl = pdcnew_cable_detect(hwif);
 479 }
 480
 481 static struct pci_dev * __devinit pdc20270_get_dev2(struct pci_dev *dev)
 482 {
 483         struct pci_dev *dev2;
 484
 485         dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 1,
 486                                                 PCI_FUNC(dev->devfn)));
 487
 488         if (dev2 &&
 489             dev2->vendor == dev->vendor &&
 490             dev2->device == dev->device) {
 491
 492                 if (dev2->irq != dev->irq) {
 493                         dev2->irq = dev->irq;
 494                         printk(KERN_INFO "PDC20270: PCI config space "
 495                                          "interrupt fixed\n");
 496                 }
 497
 498                 return dev2;
 499         }
 500
 501         return NULL;
 502 }
 503
 504 #define DECLARE_PDCNEW_DEV(name_str, udma) \
 505         { \
 506                 .name           = name_str, \
 507                 .init_chipset   = init_chipset_pdcnew, \
 508                 .init_hwif      = init_hwif_pdc202new, \
 509                 .host_flags     = IDE_HFLAG_POST_SET_MODE | \
 510                                   IDE_HFLAG_ERROR_STOPS_FIFO | \
 511                                   IDE_HFLAG_OFF_BOARD, \
 512                 .pio_mask       = ATA_PIO4, \
 513                 .mwdma_mask     = ATA_MWDMA2, \
 514                 .udma_mask      = udma, \
 515         }
 516
 517 static const struct ide_port_info pdcnew_chipsets[] __devinitdata = {
 518         /* 0 */ DECLARE_PDCNEW_DEV("PDC20268", ATA_UDMA5),
 519         /* 1 */ DECLARE_PDCNEW_DEV("PDC20269", ATA_UDMA6),
 520         /* 2 */ DECLARE_PDCNEW_DEV("PDC20270", ATA_UDMA5),
 521         /* 3 */ DECLARE_PDCNEW_DEV("PDC20271", ATA_UDMA6),
 522         /* 4 */ DECLARE_PDCNEW_DEV("PDC20275", ATA_UDMA6),
 523         /* 5 */ DECLARE_PDCNEW_DEV("PDC20276", ATA_UDMA6),
 524         /* 6 */ DECLARE_PDCNEW_DEV("PDC20277", ATA_UDMA6),
 525 };
 526
 527 /**
 528  *      pdc202new_init_one      -       called when a pdc202xx is found
 529  *      @dev: the pdc202new device
 530  *      @id: the matching pci id
 531  *
 532  *      Called when the PCI registration layer (or the IDE initialization)
 533  *      finds a device matching our IDE device tables.
 534  */
 535
 536 static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 537 {
 538         const struct ide_port_info *d;
 539         struct pci_dev *bridge = dev->bus->self;
 540         u8 idx = id->driver_data;
 541
 542         d = &pdcnew_chipsets[idx];
 543
 544         if (idx == 2 && bridge &&
 545             bridge->vendor == PCI_VENDOR_ID_DEC &&
 546             bridge->device == PCI_DEVICE_ID_DEC_21150) {
 547                 struct pci_dev *dev2;
 548
 549                 if (PCI_SLOT(dev->devfn) & 2)
 550                         return -ENODEV;
 551
 552                 dev2 = pdc20270_get_dev2(dev);
 553
 554                 if (dev2) {
 555                         int ret = ide_setup_pci_devices(dev, dev2, d);
 556                         if (ret < 0)
 557                                 pci_dev_put(dev2);
 558                         return ret;
 559                 }
 560         }
 561
 562         if (idx == 5 && bridge &&
 563             bridge->vendor == PCI_VENDOR_ID_INTEL &&
 564             (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
 565              bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
 566                 printk(KERN_INFO "PDC20276: attached to I2O RAID controller, "
 567                                  "skipping\n");
 568                 return -ENODEV;
 569         }
 570
 571         return ide_setup_pci_device(dev, d);
 572 }
 573
 574 static const struct pci_device_id pdc202new_pci_tbl[] = {
 575         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
 576         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
 577         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 2 },
 578         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 3 },
 579         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 4 },
 580         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 5 },
 581         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 6 },
 582         { 0, },
 583 };
 584 MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
 585
 586 static struct pci_driver driver = {
 587         .name           = "Promise_IDE",
 588         .id_table       = pdc202new_pci_tbl,
 589         .probe          = pdc202new_init_one,
 590 };
 591
 592 static int __init pdc202new_ide_init(void)
 593 {
 594         return ide_pci_register_driver(&driver);
 595 }
 596
 597 module_init(pdc202new_ide_init);
 598
 599 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 600 MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
 601 MODULE_LICENSE("GPL");