2 * TI DaVinci DM365 chip specific setup
4 * Copyright (C) 2009 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/init.h>
16 #include <linux/clk.h>
17 #include <linux/serial_8250.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/gpio.h>
21 #include <linux/spi/spi.h>
23 #include <asm/mach/map.h>
25 #include <mach/dm365.h>
26 #include <mach/cputype.h>
27 #include <mach/edma.h>
30 #include <mach/irqs.h>
31 #include <mach/time.h>
32 #include <mach/serial.h>
33 #include <mach/common.h>
35 #include <mach/keyscan.h>
42 #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
44 static struct pll_data pll1_data
= {
46 .phys_base
= DAVINCI_PLL1_BASE
,
47 .flags
= PLL_HAS_POSTDIV
| PLL_HAS_PREDIV
,
50 static struct pll_data pll2_data
= {
52 .phys_base
= DAVINCI_PLL2_BASE
,
53 .flags
= PLL_HAS_POSTDIV
| PLL_HAS_PREDIV
,
56 static struct clk ref_clk
= {
58 .rate
= DM365_REF_FREQ
,
61 static struct clk pll1_clk
= {
65 .pll_data
= &pll1_data
,
68 static struct clk pll1_aux_clk
= {
69 .name
= "pll1_aux_clk",
71 .flags
= CLK_PLL
| PRE_PLL
,
74 static struct clk pll1_sysclkbp
= {
75 .name
= "pll1_sysclkbp",
77 .flags
= CLK_PLL
| PRE_PLL
,
81 static struct clk clkout0_clk
= {
84 .flags
= CLK_PLL
| PRE_PLL
,
87 static struct clk pll1_sysclk1
= {
88 .name
= "pll1_sysclk1",
94 static struct clk pll1_sysclk2
= {
95 .name
= "pll1_sysclk2",
101 static struct clk pll1_sysclk3
= {
102 .name
= "pll1_sysclk3",
108 static struct clk pll1_sysclk4
= {
109 .name
= "pll1_sysclk4",
115 static struct clk pll1_sysclk5
= {
116 .name
= "pll1_sysclk5",
122 static struct clk pll1_sysclk6
= {
123 .name
= "pll1_sysclk6",
129 static struct clk pll1_sysclk7
= {
130 .name
= "pll1_sysclk7",
136 static struct clk pll1_sysclk8
= {
137 .name
= "pll1_sysclk8",
143 static struct clk pll1_sysclk9
= {
144 .name
= "pll1_sysclk9",
150 static struct clk pll2_clk
= {
154 .pll_data
= &pll2_data
,
157 static struct clk pll2_aux_clk
= {
158 .name
= "pll2_aux_clk",
160 .flags
= CLK_PLL
| PRE_PLL
,
163 static struct clk clkout1_clk
= {
166 .flags
= CLK_PLL
| PRE_PLL
,
169 static struct clk pll2_sysclk1
= {
170 .name
= "pll2_sysclk1",
176 static struct clk pll2_sysclk2
= {
177 .name
= "pll2_sysclk2",
183 static struct clk pll2_sysclk3
= {
184 .name
= "pll2_sysclk3",
190 static struct clk pll2_sysclk4
= {
191 .name
= "pll2_sysclk4",
197 static struct clk pll2_sysclk5
= {
198 .name
= "pll2_sysclk5",
204 static struct clk pll2_sysclk6
= {
205 .name
= "pll2_sysclk6",
211 static struct clk pll2_sysclk7
= {
212 .name
= "pll2_sysclk7",
218 static struct clk pll2_sysclk8
= {
219 .name
= "pll2_sysclk8",
225 static struct clk pll2_sysclk9
= {
226 .name
= "pll2_sysclk9",
232 static struct clk vpss_dac_clk
= {
234 .parent
= &pll1_sysclk3
,
235 .lpsc
= DM365_LPSC_DAC_CLK
,
238 static struct clk vpss_master_clk
= {
239 .name
= "vpss_master",
240 .parent
= &pll1_sysclk5
,
241 .lpsc
= DM365_LPSC_VPSSMSTR
,
245 static struct clk arm_clk
= {
247 .parent
= &pll2_sysclk2
,
248 .lpsc
= DAVINCI_LPSC_ARM
,
249 .flags
= ALWAYS_ENABLED
,
252 static struct clk uart0_clk
= {
254 .parent
= &pll1_aux_clk
,
255 .lpsc
= DAVINCI_LPSC_UART0
,
258 static struct clk uart1_clk
= {
260 .parent
= &pll1_sysclk4
,
261 .lpsc
= DAVINCI_LPSC_UART1
,
264 static struct clk i2c_clk
= {
266 .parent
= &pll1_aux_clk
,
267 .lpsc
= DAVINCI_LPSC_I2C
,
270 static struct clk mmcsd0_clk
= {
272 .parent
= &pll1_sysclk8
,
273 .lpsc
= DAVINCI_LPSC_MMC_SD
,
276 static struct clk mmcsd1_clk
= {
278 .parent
= &pll1_sysclk4
,
279 .lpsc
= DM365_LPSC_MMC_SD1
,
282 static struct clk spi0_clk
= {
284 .parent
= &pll1_sysclk4
,
285 .lpsc
= DAVINCI_LPSC_SPI
,
288 static struct clk spi1_clk
= {
290 .parent
= &pll1_sysclk4
,
291 .lpsc
= DM365_LPSC_SPI1
,
294 static struct clk spi2_clk
= {
296 .parent
= &pll1_sysclk4
,
297 .lpsc
= DM365_LPSC_SPI2
,
300 static struct clk spi3_clk
= {
302 .parent
= &pll1_sysclk4
,
303 .lpsc
= DM365_LPSC_SPI3
,
306 static struct clk spi4_clk
= {
308 .parent
= &pll1_aux_clk
,
309 .lpsc
= DM365_LPSC_SPI4
,
312 static struct clk gpio_clk
= {
314 .parent
= &pll1_sysclk4
,
315 .lpsc
= DAVINCI_LPSC_GPIO
,
318 static struct clk aemif_clk
= {
320 .parent
= &pll1_sysclk4
,
321 .lpsc
= DAVINCI_LPSC_AEMIF
,
324 static struct clk pwm0_clk
= {
326 .parent
= &pll1_aux_clk
,
327 .lpsc
= DAVINCI_LPSC_PWM0
,
330 static struct clk pwm1_clk
= {
332 .parent
= &pll1_aux_clk
,
333 .lpsc
= DAVINCI_LPSC_PWM1
,
336 static struct clk pwm2_clk
= {
338 .parent
= &pll1_aux_clk
,
339 .lpsc
= DAVINCI_LPSC_PWM2
,
342 static struct clk pwm3_clk
= {
345 .lpsc
= DM365_LPSC_PWM3
,
348 static struct clk timer0_clk
= {
350 .parent
= &pll1_aux_clk
,
351 .lpsc
= DAVINCI_LPSC_TIMER0
,
354 static struct clk timer1_clk
= {
356 .parent
= &pll1_aux_clk
,
357 .lpsc
= DAVINCI_LPSC_TIMER1
,
360 static struct clk timer2_clk
= {
362 .parent
= &pll1_aux_clk
,
363 .lpsc
= DAVINCI_LPSC_TIMER2
,
367 static struct clk timer3_clk
= {
369 .parent
= &pll1_aux_clk
,
370 .lpsc
= DM365_LPSC_TIMER3
,
373 static struct clk usb_clk
= {
375 .parent
= &pll1_aux_clk
,
376 .lpsc
= DAVINCI_LPSC_USB
,
379 static struct clk emac_clk
= {
381 .parent
= &pll1_sysclk4
,
382 .lpsc
= DM365_LPSC_EMAC
,
385 static struct clk voicecodec_clk
= {
386 .name
= "voice_codec",
387 .parent
= &pll2_sysclk4
,
388 .lpsc
= DM365_LPSC_VOICE_CODEC
,
391 static struct clk asp0_clk
= {
393 .parent
= &pll1_sysclk4
,
394 .lpsc
= DM365_LPSC_McBSP1
,
397 static struct clk rto_clk
= {
399 .parent
= &pll1_sysclk4
,
400 .lpsc
= DM365_LPSC_RTO
,
403 static struct clk mjcp_clk
= {
405 .parent
= &pll1_sysclk3
,
406 .lpsc
= DM365_LPSC_MJCP
,
409 static struct clk_lookup dm365_clks
[] = {
410 CLK(NULL
, "ref", &ref_clk
),
411 CLK(NULL
, "pll1", &pll1_clk
),
412 CLK(NULL
, "pll1_aux", &pll1_aux_clk
),
413 CLK(NULL
, "pll1_sysclkbp", &pll1_sysclkbp
),
414 CLK(NULL
, "clkout0", &clkout0_clk
),
415 CLK(NULL
, "pll1_sysclk1", &pll1_sysclk1
),
416 CLK(NULL
, "pll1_sysclk2", &pll1_sysclk2
),
417 CLK(NULL
, "pll1_sysclk3", &pll1_sysclk3
),
418 CLK(NULL
, "pll1_sysclk4", &pll1_sysclk4
),
419 CLK(NULL
, "pll1_sysclk5", &pll1_sysclk5
),
420 CLK(NULL
, "pll1_sysclk6", &pll1_sysclk6
),
421 CLK(NULL
, "pll1_sysclk7", &pll1_sysclk7
),
422 CLK(NULL
, "pll1_sysclk8", &pll1_sysclk8
),
423 CLK(NULL
, "pll1_sysclk9", &pll1_sysclk9
),
424 CLK(NULL
, "pll2", &pll2_clk
),
425 CLK(NULL
, "pll2_aux", &pll2_aux_clk
),
426 CLK(NULL
, "clkout1", &clkout1_clk
),
427 CLK(NULL
, "pll2_sysclk1", &pll2_sysclk1
),
428 CLK(NULL
, "pll2_sysclk2", &pll2_sysclk2
),
429 CLK(NULL
, "pll2_sysclk3", &pll2_sysclk3
),
430 CLK(NULL
, "pll2_sysclk4", &pll2_sysclk4
),
431 CLK(NULL
, "pll2_sysclk5", &pll2_sysclk5
),
432 CLK(NULL
, "pll2_sysclk6", &pll2_sysclk6
),
433 CLK(NULL
, "pll2_sysclk7", &pll2_sysclk7
),
434 CLK(NULL
, "pll2_sysclk8", &pll2_sysclk8
),
435 CLK(NULL
, "pll2_sysclk9", &pll2_sysclk9
),
436 CLK(NULL
, "vpss_dac", &vpss_dac_clk
),
437 CLK(NULL
, "vpss_master", &vpss_master_clk
),
438 CLK(NULL
, "arm", &arm_clk
),
439 CLK(NULL
, "uart0", &uart0_clk
),
440 CLK(NULL
, "uart1", &uart1_clk
),
441 CLK("i2c_davinci.1", NULL
, &i2c_clk
),
442 CLK("davinci_mmc.0", NULL
, &mmcsd0_clk
),
443 CLK("davinci_mmc.1", NULL
, &mmcsd1_clk
),
444 CLK("spi_davinci.0", NULL
, &spi0_clk
),
445 CLK("spi_davinci.1", NULL
, &spi1_clk
),
446 CLK("spi_davinci.2", NULL
, &spi2_clk
),
447 CLK("spi_davinci.3", NULL
, &spi3_clk
),
448 CLK("spi_davinci.4", NULL
, &spi4_clk
),
449 CLK(NULL
, "gpio", &gpio_clk
),
450 CLK(NULL
, "aemif", &aemif_clk
),
451 CLK(NULL
, "pwm0", &pwm0_clk
),
452 CLK(NULL
, "pwm1", &pwm1_clk
),
453 CLK(NULL
, "pwm2", &pwm2_clk
),
454 CLK(NULL
, "pwm3", &pwm3_clk
),
455 CLK(NULL
, "timer0", &timer0_clk
),
456 CLK(NULL
, "timer1", &timer1_clk
),
457 CLK("watchdog", NULL
, &timer2_clk
),
458 CLK(NULL
, "timer3", &timer3_clk
),
459 CLK(NULL
, "usb", &usb_clk
),
460 CLK("davinci_emac.1", NULL
, &emac_clk
),
461 CLK("davinci_voicecodec", NULL
, &voicecodec_clk
),
462 CLK("davinci-asp.0", NULL
, &asp0_clk
),
463 CLK(NULL
, "rto", &rto_clk
),
464 CLK(NULL
, "mjcp", &mjcp_clk
),
465 CLK(NULL
, NULL
, NULL
),
468 /*----------------------------------------------------------------------*/
479 static const struct mux_config dm365_pins
[] = {
480 #ifdef CONFIG_DAVINCI_MUX
481 MUX_CFG(DM365
, MMCSD0
, 0, 24, 1, 0, false)
483 MUX_CFG(DM365
, SD1_CLK
, 0, 16, 3, 1, false)
484 MUX_CFG(DM365
, SD1_CMD
, 4, 30, 3, 1, false)
485 MUX_CFG(DM365
, SD1_DATA3
, 4, 28, 3, 1, false)
486 MUX_CFG(DM365
, SD1_DATA2
, 4, 26, 3, 1, false)
487 MUX_CFG(DM365
, SD1_DATA1
, 4, 24, 3, 1, false)
488 MUX_CFG(DM365
, SD1_DATA0
, 4, 22, 3, 1, false)
490 MUX_CFG(DM365
, I2C_SDA
, 3, 23, 3, 2, false)
491 MUX_CFG(DM365
, I2C_SCL
, 3, 21, 3, 2, false)
493 MUX_CFG(DM365
, AEMIF_AR
, 2, 0, 3, 1, false)
494 MUX_CFG(DM365
, AEMIF_A3
, 2, 2, 3, 1, false)
495 MUX_CFG(DM365
, AEMIF_A7
, 2, 4, 3, 1, false)
496 MUX_CFG(DM365
, AEMIF_D15_8
, 2, 6, 1, 1, false)
497 MUX_CFG(DM365
, AEMIF_CE0
, 2, 7, 1, 0, false)
499 MUX_CFG(DM365
, MCBSP0_BDX
, 0, 23, 1, 1, false)
500 MUX_CFG(DM365
, MCBSP0_X
, 0, 22, 1, 1, false)
501 MUX_CFG(DM365
, MCBSP0_BFSX
, 0, 21, 1, 1, false)
502 MUX_CFG(DM365
, MCBSP0_BDR
, 0, 20, 1, 1, false)
503 MUX_CFG(DM365
, MCBSP0_R
, 0, 19, 1, 1, false)
504 MUX_CFG(DM365
, MCBSP0_BFSR
, 0, 18, 1, 1, false)
506 MUX_CFG(DM365
, SPI0_SCLK
, 3, 28, 1, 1, false)
507 MUX_CFG(DM365
, SPI0_SDI
, 3, 26, 3, 1, false)
508 MUX_CFG(DM365
, SPI0_SDO
, 3, 25, 1, 1, false)
509 MUX_CFG(DM365
, SPI0_SDENA0
, 3, 29, 3, 1, false)
510 MUX_CFG(DM365
, SPI0_SDENA1
, 3, 26, 3, 2, false)
512 MUX_CFG(DM365
, UART0_RXD
, 3, 20, 1, 1, false)
513 MUX_CFG(DM365
, UART0_TXD
, 3, 19, 1, 1, false)
514 MUX_CFG(DM365
, UART1_RXD
, 3, 17, 3, 2, false)
515 MUX_CFG(DM365
, UART1_TXD
, 3, 15, 3, 2, false)
516 MUX_CFG(DM365
, UART1_RTS
, 3, 23, 3, 1, false)
517 MUX_CFG(DM365
, UART1_CTS
, 3, 21, 3, 1, false)
519 MUX_CFG(DM365
, EMAC_TX_EN
, 3, 17, 3, 1, false)
520 MUX_CFG(DM365
, EMAC_TX_CLK
, 3, 15, 3, 1, false)
521 MUX_CFG(DM365
, EMAC_COL
, 3, 14, 1, 1, false)
522 MUX_CFG(DM365
, EMAC_TXD3
, 3, 13, 1, 1, false)
523 MUX_CFG(DM365
, EMAC_TXD2
, 3, 12, 1, 1, false)
524 MUX_CFG(DM365
, EMAC_TXD1
, 3, 11, 1, 1, false)
525 MUX_CFG(DM365
, EMAC_TXD0
, 3, 10, 1, 1, false)
526 MUX_CFG(DM365
, EMAC_RXD3
, 3, 9, 1, 1, false)
527 MUX_CFG(DM365
, EMAC_RXD2
, 3, 8, 1, 1, false)
528 MUX_CFG(DM365
, EMAC_RXD1
, 3, 7, 1, 1, false)
529 MUX_CFG(DM365
, EMAC_RXD0
, 3, 6, 1, 1, false)
530 MUX_CFG(DM365
, EMAC_RX_CLK
, 3, 5, 1, 1, false)
531 MUX_CFG(DM365
, EMAC_RX_DV
, 3, 4, 1, 1, false)
532 MUX_CFG(DM365
, EMAC_RX_ER
, 3, 3, 1, 1, false)
533 MUX_CFG(DM365
, EMAC_CRS
, 3, 2, 1, 1, false)
534 MUX_CFG(DM365
, EMAC_MDIO
, 3, 1, 1, 1, false)
535 MUX_CFG(DM365
, EMAC_MDCLK
, 3, 0, 1, 1, false)
537 MUX_CFG(DM365
, KEYSCAN
, 2, 0, 0x3f, 0x3f, false)
539 MUX_CFG(DM365
, PWM0
, 1, 0, 3, 2, false)
540 MUX_CFG(DM365
, PWM0_G23
, 3, 26, 3, 3, false)
541 MUX_CFG(DM365
, PWM1
, 1, 2, 3, 2, false)
542 MUX_CFG(DM365
, PWM1_G25
, 3, 29, 3, 2, false)
543 MUX_CFG(DM365
, PWM2_G87
, 1, 10, 3, 2, false)
544 MUX_CFG(DM365
, PWM2_G88
, 1, 8, 3, 2, false)
545 MUX_CFG(DM365
, PWM2_G89
, 1, 6, 3, 2, false)
546 MUX_CFG(DM365
, PWM2_G90
, 1, 4, 3, 2, false)
547 MUX_CFG(DM365
, PWM3_G80
, 1, 20, 3, 3, false)
548 MUX_CFG(DM365
, PWM3_G81
, 1, 18, 3, 3, false)
549 MUX_CFG(DM365
, PWM3_G85
, 1, 14, 3, 2, false)
550 MUX_CFG(DM365
, PWM3_G86
, 1, 12, 3, 2, false)
552 MUX_CFG(DM365
, SPI1_SCLK
, 4, 2, 3, 1, false)
553 MUX_CFG(DM365
, SPI1_SDI
, 3, 31, 1, 1, false)
554 MUX_CFG(DM365
, SPI1_SDO
, 4, 0, 3, 1, false)
555 MUX_CFG(DM365
, SPI1_SDENA0
, 4, 4, 3, 1, false)
556 MUX_CFG(DM365
, SPI1_SDENA1
, 4, 0, 3, 2, false)
558 MUX_CFG(DM365
, SPI2_SCLK
, 4, 10, 3, 1, false)
559 MUX_CFG(DM365
, SPI2_SDI
, 4, 6, 3, 1, false)
560 MUX_CFG(DM365
, SPI2_SDO
, 4, 8, 3, 1, false)
561 MUX_CFG(DM365
, SPI2_SDENA0
, 4, 12, 3, 1, false)
562 MUX_CFG(DM365
, SPI2_SDENA1
, 4, 8, 3, 2, false)
564 MUX_CFG(DM365
, SPI3_SCLK
, 0, 0, 3, 2, false)
565 MUX_CFG(DM365
, SPI3_SDI
, 0, 2, 3, 2, false)
566 MUX_CFG(DM365
, SPI3_SDO
, 0, 6, 3, 2, false)
567 MUX_CFG(DM365
, SPI3_SDENA0
, 0, 4, 3, 2, false)
568 MUX_CFG(DM365
, SPI3_SDENA1
, 0, 6, 3, 3, false)
570 MUX_CFG(DM365
, SPI4_SCLK
, 4, 18, 3, 1, false)
571 MUX_CFG(DM365
, SPI4_SDI
, 4, 14, 3, 1, false)
572 MUX_CFG(DM365
, SPI4_SDO
, 4, 16, 3, 1, false)
573 MUX_CFG(DM365
, SPI4_SDENA0
, 4, 20, 3, 1, false)
574 MUX_CFG(DM365
, SPI4_SDENA1
, 4, 16, 3, 2, false)
576 MUX_CFG(DM365
, GPIO20
, 3, 21, 3, 0, false)
577 MUX_CFG(DM365
, GPIO33
, 4, 12, 3, 0, false)
578 MUX_CFG(DM365
, GPIO40
, 4, 26, 3, 0, false)
580 MUX_CFG(DM365
, VOUT_FIELD
, 1, 18, 3, 1, false)
581 MUX_CFG(DM365
, VOUT_FIELD_G81
, 1, 18, 3, 0, false)
582 MUX_CFG(DM365
, VOUT_HVSYNC
, 1, 16, 1, 0, false)
583 MUX_CFG(DM365
, VOUT_COUTL_EN
, 1, 0, 0xff, 0x55, false)
584 MUX_CFG(DM365
, VOUT_COUTH_EN
, 1, 8, 0xff, 0x55, false)
585 MUX_CFG(DM365
, VIN_CAM_WEN
, 0, 14, 3, 0, false)
586 MUX_CFG(DM365
, VIN_CAM_VD
, 0, 13, 1, 0, false)
587 MUX_CFG(DM365
, VIN_CAM_HD
, 0, 12, 1, 0, false)
588 MUX_CFG(DM365
, VIN_YIN4_7_EN
, 0, 0, 0xff, 0, false)
589 MUX_CFG(DM365
, VIN_YIN0_3_EN
, 0, 8, 0xf, 0, false)
591 INT_CFG(DM365
, INT_EDMA_CC
, 2, 1, 1, false)
592 INT_CFG(DM365
, INT_EDMA_TC0_ERR
, 3, 1, 1, false)
593 INT_CFG(DM365
, INT_EDMA_TC1_ERR
, 4, 1, 1, false)
594 INT_CFG(DM365
, INT_EDMA_TC2_ERR
, 22, 1, 1, false)
595 INT_CFG(DM365
, INT_EDMA_TC3_ERR
, 23, 1, 1, false)
596 INT_CFG(DM365
, INT_PRTCSS
, 10, 1, 1, false)
597 INT_CFG(DM365
, INT_EMAC_RXTHRESH
, 14, 1, 1, false)
598 INT_CFG(DM365
, INT_EMAC_RXPULSE
, 15, 1, 1, false)
599 INT_CFG(DM365
, INT_EMAC_TXPULSE
, 16, 1, 1, false)
600 INT_CFG(DM365
, INT_EMAC_MISCPULSE
, 17, 1, 1, false)
601 INT_CFG(DM365
, INT_IMX0_ENABLE
, 0, 1, 0, false)
602 INT_CFG(DM365
, INT_IMX0_DISABLE
, 0, 1, 1, false)
603 INT_CFG(DM365
, INT_HDVICP_ENABLE
, 0, 1, 1, false)
604 INT_CFG(DM365
, INT_HDVICP_DISABLE
, 0, 1, 0, false)
605 INT_CFG(DM365
, INT_IMX1_ENABLE
, 24, 1, 1, false)
606 INT_CFG(DM365
, INT_IMX1_DISABLE
, 24, 1, 0, false)
607 INT_CFG(DM365
, INT_NSF_ENABLE
, 25, 1, 1, false)
608 INT_CFG(DM365
, INT_NSF_DISABLE
, 25, 1, 0, false)
610 EVT_CFG(DM365
, EVT2_ASP_TX
, 0, 1, 0, false)
611 EVT_CFG(DM365
, EVT3_ASP_RX
, 1, 1, 0, false)
612 EVT_CFG(DM365
, EVT2_VC_TX
, 0, 1, 1, false)
613 EVT_CFG(DM365
, EVT3_VC_RX
, 1, 1, 1, false)
617 static u64 dm365_spi0_dma_mask
= DMA_BIT_MASK(32);
619 static struct davinci_spi_platform_data dm365_spi0_pdata
= {
620 .version
= SPI_VERSION_1
,
625 .poll_mode
= 1, /* 0 -> interrupt mode 1-> polling mode */
630 static struct resource dm365_spi0_resources
[] = {
634 .flags
= IORESOURCE_MEM
,
637 .start
= IRQ_DM365_SPIINT0_0
,
638 .flags
= IORESOURCE_IRQ
,
642 .flags
= IORESOURCE_DMA
,
646 .flags
= IORESOURCE_DMA
,
650 .flags
= IORESOURCE_DMA
,
654 static struct platform_device dm365_spi0_device
= {
655 .name
= "spi_davinci",
658 .dma_mask
= &dm365_spi0_dma_mask
,
659 .coherent_dma_mask
= DMA_BIT_MASK(32),
660 .platform_data
= &dm365_spi0_pdata
,
662 .num_resources
= ARRAY_SIZE(dm365_spi0_resources
),
663 .resource
= dm365_spi0_resources
,
666 void __init
dm365_init_spi0(unsigned chipselect_mask
,
667 struct spi_board_info
*info
, unsigned len
)
669 davinci_cfg_reg(DM365_SPI0_SCLK
);
670 davinci_cfg_reg(DM365_SPI0_SDI
);
671 davinci_cfg_reg(DM365_SPI0_SDO
);
673 /* not all slaves will be wired up */
674 if (chipselect_mask
& BIT(0))
675 davinci_cfg_reg(DM365_SPI0_SDENA0
);
676 if (chipselect_mask
& BIT(1))
677 davinci_cfg_reg(DM365_SPI0_SDENA1
);
679 spi_register_board_info(info
, len
);
681 platform_device_register(&dm365_spi0_device
);
684 static struct emac_platform_data dm365_emac_pdata
= {
685 .ctrl_reg_offset
= DM365_EMAC_CNTRL_OFFSET
,
686 .ctrl_mod_reg_offset
= DM365_EMAC_CNTRL_MOD_OFFSET
,
687 .ctrl_ram_offset
= DM365_EMAC_CNTRL_RAM_OFFSET
,
688 .mdio_reg_offset
= DM365_EMAC_MDIO_OFFSET
,
689 .ctrl_ram_size
= DM365_EMAC_CNTRL_RAM_SIZE
,
690 .version
= EMAC_VERSION_2
,
693 static struct resource dm365_emac_resources
[] = {
695 .start
= DM365_EMAC_BASE
,
696 .end
= DM365_EMAC_BASE
+ 0x47ff,
697 .flags
= IORESOURCE_MEM
,
700 .start
= IRQ_DM365_EMAC_RXTHRESH
,
701 .end
= IRQ_DM365_EMAC_RXTHRESH
,
702 .flags
= IORESOURCE_IRQ
,
705 .start
= IRQ_DM365_EMAC_RXPULSE
,
706 .end
= IRQ_DM365_EMAC_RXPULSE
,
707 .flags
= IORESOURCE_IRQ
,
710 .start
= IRQ_DM365_EMAC_TXPULSE
,
711 .end
= IRQ_DM365_EMAC_TXPULSE
,
712 .flags
= IORESOURCE_IRQ
,
715 .start
= IRQ_DM365_EMAC_MISCPULSE
,
716 .end
= IRQ_DM365_EMAC_MISCPULSE
,
717 .flags
= IORESOURCE_IRQ
,
721 static struct platform_device dm365_emac_device
= {
722 .name
= "davinci_emac",
725 .platform_data
= &dm365_emac_pdata
,
727 .num_resources
= ARRAY_SIZE(dm365_emac_resources
),
728 .resource
= dm365_emac_resources
,
731 static u8 dm365_default_priorities
[DAVINCI_N_AINTC_IRQ
] = {
739 [IRQ_DM365_INSFINT
] = 7,
743 [IRQ_DM365_IMCOPINT
] = 4,
745 [IRQ_DM365_RTOINT
] = 7,
746 [IRQ_DM365_TINT5
] = 7,
747 [IRQ_DM365_TINT6
] = 5,
753 [IRQ_DM365_SPINT2_1
] = 7,
754 [IRQ_DM365_TINT7
] = 7,
755 [IRQ_DM365_SDIOINT0
] = 7,
759 [IRQ_DM365_MMCINT1
] = 7,
760 [IRQ_DM365_PWMINT3
] = 7,
763 [IRQ_DM365_SDIOINT1
] = 2,
764 [IRQ_TINT0_TINT12
] = 7,
765 [IRQ_TINT0_TINT34
] = 7,
766 [IRQ_TINT1_TINT12
] = 7,
767 [IRQ_TINT1_TINT34
] = 7,
774 [IRQ_DM365_RTCINT
] = 3,
775 [IRQ_DM365_SPIINT0_0
] = 3,
776 [IRQ_DM365_SPIINT3_0
] = 3,
777 [IRQ_DM365_GPIO0
] = 3,
778 [IRQ_DM365_GPIO1
] = 7,
779 [IRQ_DM365_GPIO2
] = 4,
780 [IRQ_DM365_GPIO3
] = 4,
781 [IRQ_DM365_GPIO4
] = 7,
782 [IRQ_DM365_GPIO5
] = 7,
783 [IRQ_DM365_GPIO6
] = 7,
784 [IRQ_DM365_GPIO7
] = 7,
785 [IRQ_DM365_EMAC_RXTHRESH
] = 7,
786 [IRQ_DM365_EMAC_RXPULSE
] = 7,
787 [IRQ_DM365_EMAC_TXPULSE
] = 7,
788 [IRQ_DM365_EMAC_MISCPULSE
] = 7,
789 [IRQ_DM365_GPIO12
] = 7,
790 [IRQ_DM365_GPIO13
] = 7,
791 [IRQ_DM365_GPIO14
] = 7,
792 [IRQ_DM365_GPIO15
] = 7,
793 [IRQ_DM365_KEYINT
] = 7,
794 [IRQ_DM365_TCERRINT2
] = 7,
795 [IRQ_DM365_TCERRINT3
] = 7,
796 [IRQ_DM365_EMUINT
] = 7,
799 /* Four Transfer Controllers on DM365 */
801 dm365_queue_tc_mapping
[][2] = {
802 /* {event queue no, TC no} */
811 dm365_queue_priority_mapping
[][2] = {
812 /* {event queue no, Priority} */
820 static struct edma_soc_info dm365_edma_info
[] = {
827 .queue_tc_mapping
= dm365_queue_tc_mapping
,
828 .queue_priority_mapping
= dm365_queue_priority_mapping
,
829 .default_queue
= EVENTQ_3
,
833 static struct resource edma_resources
[] = {
837 .end
= 0x01c00000 + SZ_64K
- 1,
838 .flags
= IORESOURCE_MEM
,
843 .end
= 0x01c10000 + SZ_1K
- 1,
844 .flags
= IORESOURCE_MEM
,
849 .end
= 0x01c10400 + SZ_1K
- 1,
850 .flags
= IORESOURCE_MEM
,
855 .end
= 0x01c10800 + SZ_1K
- 1,
856 .flags
= IORESOURCE_MEM
,
861 .end
= 0x01c10c00 + SZ_1K
- 1,
862 .flags
= IORESOURCE_MEM
,
867 .flags
= IORESOURCE_IRQ
,
871 .start
= IRQ_CCERRINT
,
872 .flags
= IORESOURCE_IRQ
,
874 /* not using TC*_ERR */
877 static struct platform_device dm365_edma_device
= {
880 .dev
.platform_data
= dm365_edma_info
,
881 .num_resources
= ARRAY_SIZE(edma_resources
),
882 .resource
= edma_resources
,
885 static struct resource dm365_asp_resources
[] = {
887 .start
= DAVINCI_DM365_ASP0_BASE
,
888 .end
= DAVINCI_DM365_ASP0_BASE
+ SZ_8K
- 1,
889 .flags
= IORESOURCE_MEM
,
892 .start
= DAVINCI_DMA_ASP0_TX
,
893 .end
= DAVINCI_DMA_ASP0_TX
,
894 .flags
= IORESOURCE_DMA
,
897 .start
= DAVINCI_DMA_ASP0_RX
,
898 .end
= DAVINCI_DMA_ASP0_RX
,
899 .flags
= IORESOURCE_DMA
,
903 static struct platform_device dm365_asp_device
= {
904 .name
= "davinci-asp",
906 .num_resources
= ARRAY_SIZE(dm365_asp_resources
),
907 .resource
= dm365_asp_resources
,
910 static struct resource dm365_vc_resources
[] = {
912 .start
= DAVINCI_DM365_VC_BASE
,
913 .end
= DAVINCI_DM365_VC_BASE
+ SZ_1K
- 1,
914 .flags
= IORESOURCE_MEM
,
917 .start
= DAVINCI_DMA_VC_TX
,
918 .end
= DAVINCI_DMA_VC_TX
,
919 .flags
= IORESOURCE_DMA
,
922 .start
= DAVINCI_DMA_VC_RX
,
923 .end
= DAVINCI_DMA_VC_RX
,
924 .flags
= IORESOURCE_DMA
,
928 static struct platform_device dm365_vc_device
= {
929 .name
= "davinci_voicecodec",
931 .num_resources
= ARRAY_SIZE(dm365_vc_resources
),
932 .resource
= dm365_vc_resources
,
935 static struct resource dm365_rtc_resources
[] = {
937 .start
= DM365_RTC_BASE
,
938 .end
= DM365_RTC_BASE
+ SZ_1K
- 1,
939 .flags
= IORESOURCE_MEM
,
942 .start
= IRQ_DM365_RTCINT
,
943 .flags
= IORESOURCE_IRQ
,
947 static struct platform_device dm365_rtc_device
= {
948 .name
= "rtc_davinci",
950 .num_resources
= ARRAY_SIZE(dm365_rtc_resources
),
951 .resource
= dm365_rtc_resources
,
954 static struct map_desc dm365_io_desc
[] = {
957 .pfn
= __phys_to_pfn(IO_PHYS
),
962 .virtual = SRAM_VIRT
,
963 .pfn
= __phys_to_pfn(0x00010000),
965 /* MT_MEMORY_NONCACHED requires supersection alignment */
970 static struct resource dm365_ks_resources
[] = {
973 .start
= DM365_KEYSCAN_BASE
,
974 .end
= DM365_KEYSCAN_BASE
+ SZ_1K
- 1,
975 .flags
= IORESOURCE_MEM
,
979 .start
= IRQ_DM365_KEYINT
,
980 .end
= IRQ_DM365_KEYINT
,
981 .flags
= IORESOURCE_IRQ
,
985 static struct platform_device dm365_ks_device
= {
986 .name
= "davinci_keyscan",
988 .num_resources
= ARRAY_SIZE(dm365_ks_resources
),
989 .resource
= dm365_ks_resources
,
992 /* Contents of JTAG ID register used to identify exact cpu type */
993 static struct davinci_id dm365_ids
[] = {
997 .manufacturer
= 0x017,
998 .cpu_id
= DAVINCI_CPU_ID_DM365
,
999 .name
= "dm365_rev1.1",
1004 .manufacturer
= 0x017,
1005 .cpu_id
= DAVINCI_CPU_ID_DM365
,
1006 .name
= "dm365_rev1.2",
1010 static void __iomem
*dm365_psc_bases
[] = {
1011 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE
),
1014 struct davinci_timer_info dm365_timer_info
= {
1015 .timers
= davinci_timer_instance
,
1016 .clockevent_id
= T0_BOT
,
1017 .clocksource_id
= T0_TOP
,
1020 static struct plat_serial8250_port dm365_serial_platform_data
[] = {
1022 .mapbase
= DAVINCI_UART0_BASE
,
1023 .irq
= IRQ_UARTINT0
,
1024 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
1030 .mapbase
= DAVINCI_UART1_BASE
,
1031 .irq
= IRQ_UARTINT1
,
1032 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
1042 static struct platform_device dm365_serial_device
= {
1043 .name
= "serial8250",
1044 .id
= PLAT8250_DEV_PLATFORM
,
1046 .platform_data
= dm365_serial_platform_data
,
1050 static struct davinci_soc_info davinci_soc_info_dm365
= {
1051 .io_desc
= dm365_io_desc
,
1052 .io_desc_num
= ARRAY_SIZE(dm365_io_desc
),
1053 .jtag_id_base
= IO_ADDRESS(0x01c40028),
1055 .ids_num
= ARRAY_SIZE(dm365_ids
),
1056 .cpu_clks
= dm365_clks
,
1057 .psc_bases
= dm365_psc_bases
,
1058 .psc_bases_num
= ARRAY_SIZE(dm365_psc_bases
),
1059 .pinmux_base
= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE
),
1060 .pinmux_pins
= dm365_pins
,
1061 .pinmux_pins_num
= ARRAY_SIZE(dm365_pins
),
1062 .intc_base
= IO_ADDRESS(DAVINCI_ARM_INTC_BASE
),
1063 .intc_type
= DAVINCI_INTC_TYPE_AINTC
,
1064 .intc_irq_prios
= dm365_default_priorities
,
1065 .intc_irq_num
= DAVINCI_N_AINTC_IRQ
,
1066 .timer_info
= &dm365_timer_info
,
1067 .gpio_base
= IO_ADDRESS(DAVINCI_GPIO_BASE
),
1069 .gpio_irq
= IRQ_DM365_GPIO0
,
1070 .gpio_unbanked
= 8, /* really 16 ... skip muxed GPIOs */
1071 .serial_dev
= &dm365_serial_device
,
1072 .emac_pdata
= &dm365_emac_pdata
,
1073 .sram_dma
= 0x00010000,
1077 void __init
dm365_init_asp(struct snd_platform_data
*pdata
)
1079 davinci_cfg_reg(DM365_MCBSP0_BDX
);
1080 davinci_cfg_reg(DM365_MCBSP0_X
);
1081 davinci_cfg_reg(DM365_MCBSP0_BFSX
);
1082 davinci_cfg_reg(DM365_MCBSP0_BDR
);
1083 davinci_cfg_reg(DM365_MCBSP0_R
);
1084 davinci_cfg_reg(DM365_MCBSP0_BFSR
);
1085 davinci_cfg_reg(DM365_EVT2_ASP_TX
);
1086 davinci_cfg_reg(DM365_EVT3_ASP_RX
);
1087 dm365_asp_device
.dev
.platform_data
= pdata
;
1088 platform_device_register(&dm365_asp_device
);
1091 void __init
dm365_init_vc(struct snd_platform_data
*pdata
)
1093 davinci_cfg_reg(DM365_EVT2_VC_TX
);
1094 davinci_cfg_reg(DM365_EVT3_VC_RX
);
1095 dm365_vc_device
.dev
.platform_data
= pdata
;
1096 platform_device_register(&dm365_vc_device
);
1099 void __init
dm365_init_ks(struct davinci_ks_platform_data
*pdata
)
1101 dm365_ks_device
.dev
.platform_data
= pdata
;
1102 platform_device_register(&dm365_ks_device
);
1105 void __init
dm365_init_rtc(void)
1107 davinci_cfg_reg(DM365_INT_PRTCSS
);
1108 platform_device_register(&dm365_rtc_device
);
1111 void __init
dm365_init(void)
1113 davinci_common_init(&davinci_soc_info_dm365
);
1116 static struct resource dm365_vpss_resources
[] = {
1118 /* VPSS ISP5 Base address */
1120 .start
= 0x01c70000,
1121 .end
= 0x01c70000 + 0xff,
1122 .flags
= IORESOURCE_MEM
,
1125 /* VPSS CLK Base address */
1127 .start
= 0x01c70200,
1128 .end
= 0x01c70200 + 0xff,
1129 .flags
= IORESOURCE_MEM
,
1133 static struct platform_device dm365_vpss_device
= {
1136 .dev
.platform_data
= "dm365_vpss",
1137 .num_resources
= ARRAY_SIZE(dm365_vpss_resources
),
1138 .resource
= dm365_vpss_resources
,
1141 static struct resource vpfe_resources
[] = {
1143 .start
= IRQ_VDINT0
,
1145 .flags
= IORESOURCE_IRQ
,
1148 .start
= IRQ_VDINT1
,
1150 .flags
= IORESOURCE_IRQ
,
1154 static u64 vpfe_capture_dma_mask
= DMA_BIT_MASK(32);
1155 static struct platform_device vpfe_capture_dev
= {
1156 .name
= CAPTURE_DRV_NAME
,
1158 .num_resources
= ARRAY_SIZE(vpfe_resources
),
1159 .resource
= vpfe_resources
,
1161 .dma_mask
= &vpfe_capture_dma_mask
,
1162 .coherent_dma_mask
= DMA_BIT_MASK(32),
1166 static void dm365_isif_setup_pinmux(void)
1168 davinci_cfg_reg(DM365_VIN_CAM_WEN
);
1169 davinci_cfg_reg(DM365_VIN_CAM_VD
);
1170 davinci_cfg_reg(DM365_VIN_CAM_HD
);
1171 davinci_cfg_reg(DM365_VIN_YIN4_7_EN
);
1172 davinci_cfg_reg(DM365_VIN_YIN0_3_EN
);
1175 static struct resource isif_resource
[] = {
1176 /* ISIF Base address */
1178 .start
= 0x01c71000,
1179 .end
= 0x01c71000 + 0x1ff,
1180 .flags
= IORESOURCE_MEM
,
1182 /* ISIF Linearization table 0 */
1185 .end
= 0x1C7C000 + 0x2ff,
1186 .flags
= IORESOURCE_MEM
,
1188 /* ISIF Linearization table 1 */
1191 .end
= 0x1C7C400 + 0x2ff,
1192 .flags
= IORESOURCE_MEM
,
1195 static struct platform_device dm365_isif_dev
= {
1198 .num_resources
= ARRAY_SIZE(isif_resource
),
1199 .resource
= isif_resource
,
1201 .dma_mask
= &vpfe_capture_dma_mask
,
1202 .coherent_dma_mask
= DMA_BIT_MASK(32),
1203 .platform_data
= dm365_isif_setup_pinmux
,
1207 static int __init
dm365_init_devices(void)
1209 if (!cpu_is_davinci_dm365())
1212 davinci_cfg_reg(DM365_INT_EDMA_CC
);
1213 platform_device_register(&dm365_edma_device
);
1214 platform_device_register(&dm365_emac_device
);
1215 /* Add isif clock alias */
1216 clk_add_alias("master", dm365_isif_dev
.name
, "vpss_master", NULL
);
1217 platform_device_register(&dm365_vpss_device
);
1218 platform_device_register(&dm365_isif_dev
);
1219 platform_device_register(&vpfe_capture_dev
);
1222 postcore_initcall(dm365_init_devices
);
1224 void dm365_set_vpfe_config(struct vpfe_config
*cfg
)
1226 vpfe_capture_dev
.dev
.platform_data
= cfg
;