2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
34 #include "intel_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
40 #include "drm_crtc_helper.h"
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
);
45 static void intel_update_watermarks(struct drm_device
*dev
);
46 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
47 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t
;
73 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
75 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
76 int, int, intel_clock_t
*);
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
90 #define I8XX_M2_MAX 16
92 #define I8XX_P_MAX 128
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
253 /* We have parameter ranges for different type of outputs. */
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
332 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
333 int target
, int refclk
, intel_clock_t
*best_clock
);
335 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
336 int target
, int refclk
, intel_clock_t
*best_clock
);
339 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
340 int target
, int refclk
, intel_clock_t
*best_clock
);
342 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
343 int target
, int refclk
, intel_clock_t
*best_clock
);
345 static inline u32
/* units of 100MHz */
346 intel_fdi_link_freq(struct drm_device
*dev
)
349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
350 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
355 static const intel_limit_t intel_limits_i8xx_dvo
= {
356 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
357 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
358 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
359 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
360 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
361 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
362 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
363 .p1
= { .min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
364 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
365 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
366 .find_pll
= intel_find_best_PLL
,
369 static const intel_limit_t intel_limits_i8xx_lvds
= {
370 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
371 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
372 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
373 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
374 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
375 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
376 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
377 .p1
= { .min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
378 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
379 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
380 .find_pll
= intel_find_best_PLL
,
383 static const intel_limit_t intel_limits_i9xx_sdvo
= {
384 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
385 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
386 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
387 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
388 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
389 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
390 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
391 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
392 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
393 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
394 .find_pll
= intel_find_best_PLL
,
397 static const intel_limit_t intel_limits_i9xx_lvds
= {
398 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
399 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
400 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
401 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
402 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
403 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
404 .p
= { .min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
405 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
406 /* The single-channel range is 25-112Mhz, and dual-channel
407 * is 80-224Mhz. Prefer single channel as much as possible.
409 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
410 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
411 .find_pll
= intel_find_best_PLL
,
414 /* below parameter and function is for G4X Chipset Family*/
415 static const intel_limit_t intel_limits_g4x_sdvo
= {
416 .dot
= { .min
= G4X_DOT_SDVO_MIN
, .max
= G4X_DOT_SDVO_MAX
},
417 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
418 .n
= { .min
= G4X_N_SDVO_MIN
, .max
= G4X_N_SDVO_MAX
},
419 .m
= { .min
= G4X_M_SDVO_MIN
, .max
= G4X_M_SDVO_MAX
},
420 .m1
= { .min
= G4X_M1_SDVO_MIN
, .max
= G4X_M1_SDVO_MAX
},
421 .m2
= { .min
= G4X_M2_SDVO_MIN
, .max
= G4X_M2_SDVO_MAX
},
422 .p
= { .min
= G4X_P_SDVO_MIN
, .max
= G4X_P_SDVO_MAX
},
423 .p1
= { .min
= G4X_P1_SDVO_MIN
, .max
= G4X_P1_SDVO_MAX
},
424 .p2
= { .dot_limit
= G4X_P2_SDVO_LIMIT
,
425 .p2_slow
= G4X_P2_SDVO_SLOW
,
426 .p2_fast
= G4X_P2_SDVO_FAST
428 .find_pll
= intel_g4x_find_best_PLL
,
431 static const intel_limit_t intel_limits_g4x_hdmi
= {
432 .dot
= { .min
= G4X_DOT_HDMI_DAC_MIN
, .max
= G4X_DOT_HDMI_DAC_MAX
},
433 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
434 .n
= { .min
= G4X_N_HDMI_DAC_MIN
, .max
= G4X_N_HDMI_DAC_MAX
},
435 .m
= { .min
= G4X_M_HDMI_DAC_MIN
, .max
= G4X_M_HDMI_DAC_MAX
},
436 .m1
= { .min
= G4X_M1_HDMI_DAC_MIN
, .max
= G4X_M1_HDMI_DAC_MAX
},
437 .m2
= { .min
= G4X_M2_HDMI_DAC_MIN
, .max
= G4X_M2_HDMI_DAC_MAX
},
438 .p
= { .min
= G4X_P_HDMI_DAC_MIN
, .max
= G4X_P_HDMI_DAC_MAX
},
439 .p1
= { .min
= G4X_P1_HDMI_DAC_MIN
, .max
= G4X_P1_HDMI_DAC_MAX
},
440 .p2
= { .dot_limit
= G4X_P2_HDMI_DAC_LIMIT
,
441 .p2_slow
= G4X_P2_HDMI_DAC_SLOW
,
442 .p2_fast
= G4X_P2_HDMI_DAC_FAST
444 .find_pll
= intel_g4x_find_best_PLL
,
447 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
448 .dot
= { .min
= G4X_DOT_SINGLE_CHANNEL_LVDS_MIN
,
449 .max
= G4X_DOT_SINGLE_CHANNEL_LVDS_MAX
},
450 .vco
= { .min
= G4X_VCO_MIN
,
451 .max
= G4X_VCO_MAX
},
452 .n
= { .min
= G4X_N_SINGLE_CHANNEL_LVDS_MIN
,
453 .max
= G4X_N_SINGLE_CHANNEL_LVDS_MAX
},
454 .m
= { .min
= G4X_M_SINGLE_CHANNEL_LVDS_MIN
,
455 .max
= G4X_M_SINGLE_CHANNEL_LVDS_MAX
},
456 .m1
= { .min
= G4X_M1_SINGLE_CHANNEL_LVDS_MIN
,
457 .max
= G4X_M1_SINGLE_CHANNEL_LVDS_MAX
},
458 .m2
= { .min
= G4X_M2_SINGLE_CHANNEL_LVDS_MIN
,
459 .max
= G4X_M2_SINGLE_CHANNEL_LVDS_MAX
},
460 .p
= { .min
= G4X_P_SINGLE_CHANNEL_LVDS_MIN
,
461 .max
= G4X_P_SINGLE_CHANNEL_LVDS_MAX
},
462 .p1
= { .min
= G4X_P1_SINGLE_CHANNEL_LVDS_MIN
,
463 .max
= G4X_P1_SINGLE_CHANNEL_LVDS_MAX
},
464 .p2
= { .dot_limit
= G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT
,
465 .p2_slow
= G4X_P2_SINGLE_CHANNEL_LVDS_SLOW
,
466 .p2_fast
= G4X_P2_SINGLE_CHANNEL_LVDS_FAST
468 .find_pll
= intel_g4x_find_best_PLL
,
471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
472 .dot
= { .min
= G4X_DOT_DUAL_CHANNEL_LVDS_MIN
,
473 .max
= G4X_DOT_DUAL_CHANNEL_LVDS_MAX
},
474 .vco
= { .min
= G4X_VCO_MIN
,
475 .max
= G4X_VCO_MAX
},
476 .n
= { .min
= G4X_N_DUAL_CHANNEL_LVDS_MIN
,
477 .max
= G4X_N_DUAL_CHANNEL_LVDS_MAX
},
478 .m
= { .min
= G4X_M_DUAL_CHANNEL_LVDS_MIN
,
479 .max
= G4X_M_DUAL_CHANNEL_LVDS_MAX
},
480 .m1
= { .min
= G4X_M1_DUAL_CHANNEL_LVDS_MIN
,
481 .max
= G4X_M1_DUAL_CHANNEL_LVDS_MAX
},
482 .m2
= { .min
= G4X_M2_DUAL_CHANNEL_LVDS_MIN
,
483 .max
= G4X_M2_DUAL_CHANNEL_LVDS_MAX
},
484 .p
= { .min
= G4X_P_DUAL_CHANNEL_LVDS_MIN
,
485 .max
= G4X_P_DUAL_CHANNEL_LVDS_MAX
},
486 .p1
= { .min
= G4X_P1_DUAL_CHANNEL_LVDS_MIN
,
487 .max
= G4X_P1_DUAL_CHANNEL_LVDS_MAX
},
488 .p2
= { .dot_limit
= G4X_P2_DUAL_CHANNEL_LVDS_LIMIT
,
489 .p2_slow
= G4X_P2_DUAL_CHANNEL_LVDS_SLOW
,
490 .p2_fast
= G4X_P2_DUAL_CHANNEL_LVDS_FAST
492 .find_pll
= intel_g4x_find_best_PLL
,
495 static const intel_limit_t intel_limits_g4x_display_port
= {
496 .dot
= { .min
= G4X_DOT_DISPLAY_PORT_MIN
,
497 .max
= G4X_DOT_DISPLAY_PORT_MAX
},
498 .vco
= { .min
= G4X_VCO_MIN
,
500 .n
= { .min
= G4X_N_DISPLAY_PORT_MIN
,
501 .max
= G4X_N_DISPLAY_PORT_MAX
},
502 .m
= { .min
= G4X_M_DISPLAY_PORT_MIN
,
503 .max
= G4X_M_DISPLAY_PORT_MAX
},
504 .m1
= { .min
= G4X_M1_DISPLAY_PORT_MIN
,
505 .max
= G4X_M1_DISPLAY_PORT_MAX
},
506 .m2
= { .min
= G4X_M2_DISPLAY_PORT_MIN
,
507 .max
= G4X_M2_DISPLAY_PORT_MAX
},
508 .p
= { .min
= G4X_P_DISPLAY_PORT_MIN
,
509 .max
= G4X_P_DISPLAY_PORT_MAX
},
510 .p1
= { .min
= G4X_P1_DISPLAY_PORT_MIN
,
511 .max
= G4X_P1_DISPLAY_PORT_MAX
},
512 .p2
= { .dot_limit
= G4X_P2_DISPLAY_PORT_LIMIT
,
513 .p2_slow
= G4X_P2_DISPLAY_PORT_SLOW
,
514 .p2_fast
= G4X_P2_DISPLAY_PORT_FAST
},
515 .find_pll
= intel_find_pll_g4x_dp
,
518 static const intel_limit_t intel_limits_pineview_sdvo
= {
519 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
520 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
521 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
522 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
523 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
524 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
525 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
526 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
527 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
528 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
529 .find_pll
= intel_find_best_PLL
,
532 static const intel_limit_t intel_limits_pineview_lvds
= {
533 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
534 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
535 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
536 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
537 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
538 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
539 .p
= { .min
= PINEVIEW_P_LVDS_MIN
, .max
= PINEVIEW_P_LVDS_MAX
},
540 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
541 /* Pineview only supports single-channel mode. */
542 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
543 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_SLOW
},
544 .find_pll
= intel_find_best_PLL
,
547 static const intel_limit_t intel_limits_ironlake_dac
= {
548 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
549 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
550 .n
= { .min
= IRONLAKE_DAC_N_MIN
, .max
= IRONLAKE_DAC_N_MAX
},
551 .m
= { .min
= IRONLAKE_DAC_M_MIN
, .max
= IRONLAKE_DAC_M_MAX
},
552 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
553 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
554 .p
= { .min
= IRONLAKE_DAC_P_MIN
, .max
= IRONLAKE_DAC_P_MAX
},
555 .p1
= { .min
= IRONLAKE_DAC_P1_MIN
, .max
= IRONLAKE_DAC_P1_MAX
},
556 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
557 .p2_slow
= IRONLAKE_DAC_P2_SLOW
,
558 .p2_fast
= IRONLAKE_DAC_P2_FAST
},
559 .find_pll
= intel_g4x_find_best_PLL
,
562 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
563 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
564 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
565 .n
= { .min
= IRONLAKE_LVDS_S_N_MIN
, .max
= IRONLAKE_LVDS_S_N_MAX
},
566 .m
= { .min
= IRONLAKE_LVDS_S_M_MIN
, .max
= IRONLAKE_LVDS_S_M_MAX
},
567 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
568 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
569 .p
= { .min
= IRONLAKE_LVDS_S_P_MIN
, .max
= IRONLAKE_LVDS_S_P_MAX
},
570 .p1
= { .min
= IRONLAKE_LVDS_S_P1_MIN
, .max
= IRONLAKE_LVDS_S_P1_MAX
},
571 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
572 .p2_slow
= IRONLAKE_LVDS_S_P2_SLOW
,
573 .p2_fast
= IRONLAKE_LVDS_S_P2_FAST
},
574 .find_pll
= intel_g4x_find_best_PLL
,
577 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
578 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
579 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
580 .n
= { .min
= IRONLAKE_LVDS_D_N_MIN
, .max
= IRONLAKE_LVDS_D_N_MAX
},
581 .m
= { .min
= IRONLAKE_LVDS_D_M_MIN
, .max
= IRONLAKE_LVDS_D_M_MAX
},
582 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
583 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
584 .p
= { .min
= IRONLAKE_LVDS_D_P_MIN
, .max
= IRONLAKE_LVDS_D_P_MAX
},
585 .p1
= { .min
= IRONLAKE_LVDS_D_P1_MIN
, .max
= IRONLAKE_LVDS_D_P1_MAX
},
586 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
587 .p2_slow
= IRONLAKE_LVDS_D_P2_SLOW
,
588 .p2_fast
= IRONLAKE_LVDS_D_P2_FAST
},
589 .find_pll
= intel_g4x_find_best_PLL
,
592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
593 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
594 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
595 .n
= { .min
= IRONLAKE_LVDS_S_SSC_N_MIN
, .max
= IRONLAKE_LVDS_S_SSC_N_MAX
},
596 .m
= { .min
= IRONLAKE_LVDS_S_SSC_M_MIN
, .max
= IRONLAKE_LVDS_S_SSC_M_MAX
},
597 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
598 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
599 .p
= { .min
= IRONLAKE_LVDS_S_SSC_P_MIN
, .max
= IRONLAKE_LVDS_S_SSC_P_MAX
},
600 .p1
= { .min
= IRONLAKE_LVDS_S_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_S_SSC_P1_MAX
},
601 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
602 .p2_slow
= IRONLAKE_LVDS_S_SSC_P2_SLOW
,
603 .p2_fast
= IRONLAKE_LVDS_S_SSC_P2_FAST
},
604 .find_pll
= intel_g4x_find_best_PLL
,
607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
608 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
609 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
610 .n
= { .min
= IRONLAKE_LVDS_D_SSC_N_MIN
, .max
= IRONLAKE_LVDS_D_SSC_N_MAX
},
611 .m
= { .min
= IRONLAKE_LVDS_D_SSC_M_MIN
, .max
= IRONLAKE_LVDS_D_SSC_M_MAX
},
612 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
613 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
614 .p
= { .min
= IRONLAKE_LVDS_D_SSC_P_MIN
, .max
= IRONLAKE_LVDS_D_SSC_P_MAX
},
615 .p1
= { .min
= IRONLAKE_LVDS_D_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_D_SSC_P1_MAX
},
616 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
617 .p2_slow
= IRONLAKE_LVDS_D_SSC_P2_SLOW
,
618 .p2_fast
= IRONLAKE_LVDS_D_SSC_P2_FAST
},
619 .find_pll
= intel_g4x_find_best_PLL
,
622 static const intel_limit_t intel_limits_ironlake_display_port
= {
623 .dot
= { .min
= IRONLAKE_DOT_MIN
,
624 .max
= IRONLAKE_DOT_MAX
},
625 .vco
= { .min
= IRONLAKE_VCO_MIN
,
626 .max
= IRONLAKE_VCO_MAX
},
627 .n
= { .min
= IRONLAKE_DP_N_MIN
,
628 .max
= IRONLAKE_DP_N_MAX
},
629 .m
= { .min
= IRONLAKE_DP_M_MIN
,
630 .max
= IRONLAKE_DP_M_MAX
},
631 .m1
= { .min
= IRONLAKE_M1_MIN
,
632 .max
= IRONLAKE_M1_MAX
},
633 .m2
= { .min
= IRONLAKE_M2_MIN
,
634 .max
= IRONLAKE_M2_MAX
},
635 .p
= { .min
= IRONLAKE_DP_P_MIN
,
636 .max
= IRONLAKE_DP_P_MAX
},
637 .p1
= { .min
= IRONLAKE_DP_P1_MIN
,
638 .max
= IRONLAKE_DP_P1_MAX
},
639 .p2
= { .dot_limit
= IRONLAKE_DP_P2_LIMIT
,
640 .p2_slow
= IRONLAKE_DP_P2_SLOW
,
641 .p2_fast
= IRONLAKE_DP_P2_FAST
},
642 .find_pll
= intel_find_pll_ironlake_dp
,
645 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
)
647 struct drm_device
*dev
= crtc
->dev
;
648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
649 const intel_limit_t
*limit
;
652 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
653 if (dev_priv
->lvds_use_ssc
&& dev_priv
->lvds_ssc_freq
== 100)
656 if ((I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) ==
657 LVDS_CLKB_POWER_UP
) {
658 /* LVDS dual channel */
660 limit
= &intel_limits_ironlake_dual_lvds_100m
;
662 limit
= &intel_limits_ironlake_dual_lvds
;
665 limit
= &intel_limits_ironlake_single_lvds_100m
;
667 limit
= &intel_limits_ironlake_single_lvds
;
669 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
671 limit
= &intel_limits_ironlake_display_port
;
673 limit
= &intel_limits_ironlake_dac
;
678 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
680 struct drm_device
*dev
= crtc
->dev
;
681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
682 const intel_limit_t
*limit
;
684 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
685 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
687 /* LVDS with dual channel */
688 limit
= &intel_limits_g4x_dual_channel_lvds
;
690 /* LVDS with dual channel */
691 limit
= &intel_limits_g4x_single_channel_lvds
;
692 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
693 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
694 limit
= &intel_limits_g4x_hdmi
;
695 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
696 limit
= &intel_limits_g4x_sdvo
;
697 } else if (intel_pipe_has_type (crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
698 limit
= &intel_limits_g4x_display_port
;
699 } else /* The option is for other outputs */
700 limit
= &intel_limits_i9xx_sdvo
;
705 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
)
707 struct drm_device
*dev
= crtc
->dev
;
708 const intel_limit_t
*limit
;
710 if (HAS_PCH_SPLIT(dev
))
711 limit
= intel_ironlake_limit(crtc
);
712 else if (IS_G4X(dev
)) {
713 limit
= intel_g4x_limit(crtc
);
714 } else if (IS_PINEVIEW(dev
)) {
715 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
716 limit
= &intel_limits_pineview_lvds
;
718 limit
= &intel_limits_pineview_sdvo
;
719 } else if (!IS_GEN2(dev
)) {
720 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
721 limit
= &intel_limits_i9xx_lvds
;
723 limit
= &intel_limits_i9xx_sdvo
;
725 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
726 limit
= &intel_limits_i8xx_lvds
;
728 limit
= &intel_limits_i8xx_dvo
;
733 /* m1 is reserved as 0 in Pineview, n is a ring counter */
734 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
736 clock
->m
= clock
->m2
+ 2;
737 clock
->p
= clock
->p1
* clock
->p2
;
738 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
739 clock
->dot
= clock
->vco
/ clock
->p
;
742 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
744 if (IS_PINEVIEW(dev
)) {
745 pineview_clock(refclk
, clock
);
748 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
749 clock
->p
= clock
->p1
* clock
->p2
;
750 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
751 clock
->dot
= clock
->vco
/ clock
->p
;
755 * Returns whether any output on the specified pipe is of the specified type
757 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
759 struct drm_device
*dev
= crtc
->dev
;
760 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
761 struct intel_encoder
*encoder
;
763 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
764 if (encoder
->base
.crtc
== crtc
&& encoder
->type
== type
)
770 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
772 * Returns whether the given set of divisors are valid for a given refclk with
773 * the given connectors.
776 static bool intel_PLL_is_valid(struct drm_crtc
*crtc
, intel_clock_t
*clock
)
778 const intel_limit_t
*limit
= intel_limit (crtc
);
779 struct drm_device
*dev
= crtc
->dev
;
781 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
782 INTELPllInvalid ("p1 out of range\n");
783 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
784 INTELPllInvalid ("p out of range\n");
785 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
786 INTELPllInvalid ("m2 out of range\n");
787 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
788 INTELPllInvalid ("m1 out of range\n");
789 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
790 INTELPllInvalid ("m1 <= m2\n");
791 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
792 INTELPllInvalid ("m out of range\n");
793 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
794 INTELPllInvalid ("n out of range\n");
795 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
796 INTELPllInvalid ("vco out of range\n");
797 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
798 * connector, etc., rather than just a single range.
800 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
801 INTELPllInvalid ("dot out of range\n");
807 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
808 int target
, int refclk
, intel_clock_t
*best_clock
)
811 struct drm_device
*dev
= crtc
->dev
;
812 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
816 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
817 (I915_READ(LVDS
)) != 0) {
819 * For LVDS, if the panel is on, just rely on its current
820 * settings for dual-channel. We haven't figured out how to
821 * reliably set up different single/dual channel state, if we
824 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
826 clock
.p2
= limit
->p2
.p2_fast
;
828 clock
.p2
= limit
->p2
.p2_slow
;
830 if (target
< limit
->p2
.dot_limit
)
831 clock
.p2
= limit
->p2
.p2_slow
;
833 clock
.p2
= limit
->p2
.p2_fast
;
836 memset (best_clock
, 0, sizeof (*best_clock
));
838 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
840 for (clock
.m2
= limit
->m2
.min
;
841 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
842 /* m1 is always 0 in Pineview */
843 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
845 for (clock
.n
= limit
->n
.min
;
846 clock
.n
<= limit
->n
.max
; clock
.n
++) {
847 for (clock
.p1
= limit
->p1
.min
;
848 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
851 intel_clock(dev
, refclk
, &clock
);
853 if (!intel_PLL_is_valid(crtc
, &clock
))
856 this_err
= abs(clock
.dot
- target
);
857 if (this_err
< err
) {
866 return (err
!= target
);
870 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
871 int target
, int refclk
, intel_clock_t
*best_clock
)
873 struct drm_device
*dev
= crtc
->dev
;
874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
878 /* approximately equals target * 0.00585 */
879 int err_most
= (target
>> 8) + (target
>> 9);
882 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
885 if (HAS_PCH_SPLIT(dev
))
889 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
891 clock
.p2
= limit
->p2
.p2_fast
;
893 clock
.p2
= limit
->p2
.p2_slow
;
895 if (target
< limit
->p2
.dot_limit
)
896 clock
.p2
= limit
->p2
.p2_slow
;
898 clock
.p2
= limit
->p2
.p2_fast
;
901 memset(best_clock
, 0, sizeof(*best_clock
));
902 max_n
= limit
->n
.max
;
903 /* based on hardware requirement, prefer smaller n to precision */
904 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
905 /* based on hardware requirement, prefere larger m1,m2 */
906 for (clock
.m1
= limit
->m1
.max
;
907 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
908 for (clock
.m2
= limit
->m2
.max
;
909 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
910 for (clock
.p1
= limit
->p1
.max
;
911 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
914 intel_clock(dev
, refclk
, &clock
);
915 if (!intel_PLL_is_valid(crtc
, &clock
))
917 this_err
= abs(clock
.dot
- target
) ;
918 if (this_err
< err_most
) {
932 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
933 int target
, int refclk
, intel_clock_t
*best_clock
)
935 struct drm_device
*dev
= crtc
->dev
;
938 if (target
< 200000) {
951 intel_clock(dev
, refclk
, &clock
);
952 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
956 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
958 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
959 int target
, int refclk
, intel_clock_t
*best_clock
)
962 if (target
< 200000) {
975 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
976 clock
.p
= (clock
.p1
* clock
.p2
);
977 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
979 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
984 * intel_wait_for_vblank - wait for vblank on a given pipe
986 * @pipe: pipe to wait for
988 * Wait for vblank to occur on a given pipe. Needed for various bits of
991 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
994 int pipestat_reg
= (pipe
== 0 ? PIPEASTAT
: PIPEBSTAT
);
996 /* Clear existing vblank status. Note this will clear any other
997 * sticky status fields as well.
999 * This races with i915_driver_irq_handler() with the result
1000 * that either function could miss a vblank event. Here it is not
1001 * fatal, as we will either wait upon the next vblank interrupt or
1002 * timeout. Generally speaking intel_wait_for_vblank() is only
1003 * called during modeset at which time the GPU should be idle and
1004 * should *not* be performing page flips and thus not waiting on
1006 * Currently, the result of us stealing a vblank from the irq
1007 * handler is that a single frame will be skipped during swapbuffers.
1009 I915_WRITE(pipestat_reg
,
1010 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
1012 /* Wait for vblank interrupt bit to set */
1013 if (wait_for(I915_READ(pipestat_reg
) &
1014 PIPE_VBLANK_INTERRUPT_STATUS
,
1016 DRM_DEBUG_KMS("vblank wait timed out\n");
1020 * intel_wait_for_pipe_off - wait for pipe to turn off
1022 * @pipe: pipe to wait for
1024 * After disabling a pipe, we can't wait for vblank in the usual way,
1025 * spinning on the vblank interrupt status bit, since we won't actually
1026 * see an interrupt when the pipe is disabled.
1028 * On Gen4 and above:
1029 * wait for the pipe register state bit to turn off
1032 * wait for the display line value to settle (it usually
1033 * ends up stopping at the start of the next frame).
1036 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
1038 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1040 if (INTEL_INFO(dev
)->gen
>= 4) {
1041 int reg
= PIPECONF(pipe
);
1043 /* Wait for the Pipe State to go off */
1044 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1046 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1049 int reg
= PIPEDSL(pipe
);
1050 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
1052 /* Wait for the display line to settle */
1054 last_line
= I915_READ(reg
) & DSL_LINEMASK
;
1056 } while (((I915_READ(reg
) & DSL_LINEMASK
) != last_line
) &&
1057 time_after(timeout
, jiffies
));
1058 if (time_after(jiffies
, timeout
))
1059 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1063 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1065 struct drm_device
*dev
= crtc
->dev
;
1066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1067 struct drm_framebuffer
*fb
= crtc
->fb
;
1068 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1069 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
1070 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1072 u32 fbc_ctl
, fbc_ctl2
;
1074 if (fb
->pitch
== dev_priv
->cfb_pitch
&&
1075 obj_priv
->fence_reg
== dev_priv
->cfb_fence
&&
1076 intel_crtc
->plane
== dev_priv
->cfb_plane
&&
1077 I915_READ(FBC_CONTROL
) & FBC_CTL_EN
)
1080 i8xx_disable_fbc(dev
);
1082 dev_priv
->cfb_pitch
= dev_priv
->cfb_size
/ FBC_LL_SIZE
;
1084 if (fb
->pitch
< dev_priv
->cfb_pitch
)
1085 dev_priv
->cfb_pitch
= fb
->pitch
;
1087 /* FBC_CTL wants 64B units */
1088 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1089 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1090 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1091 plane
= dev_priv
->cfb_plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
1093 /* Clear old tags */
1094 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
1095 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
1098 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| plane
;
1099 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1100 fbc_ctl2
|= FBC_CTL_CPU_FENCE
;
1101 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
1102 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
1105 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
1107 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
1108 fbc_ctl
|= (dev_priv
->cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
1109 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
1110 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1111 fbc_ctl
|= dev_priv
->cfb_fence
;
1112 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1114 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1115 dev_priv
->cfb_pitch
, crtc
->y
, dev_priv
->cfb_plane
);
1118 void i8xx_disable_fbc(struct drm_device
*dev
)
1120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1123 /* Disable compression */
1124 fbc_ctl
= I915_READ(FBC_CONTROL
);
1125 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
1128 fbc_ctl
&= ~FBC_CTL_EN
;
1129 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1131 /* Wait for compressing bit to clear */
1132 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
1133 DRM_DEBUG_KMS("FBC idle timed out\n");
1137 DRM_DEBUG_KMS("disabled FBC\n");
1140 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
1142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1144 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
1147 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1149 struct drm_device
*dev
= crtc
->dev
;
1150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1151 struct drm_framebuffer
*fb
= crtc
->fb
;
1152 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1153 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
1154 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1155 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
1156 unsigned long stall_watermark
= 200;
1159 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1160 if (dpfc_ctl
& DPFC_CTL_EN
) {
1161 if (dev_priv
->cfb_pitch
== dev_priv
->cfb_pitch
/ 64 - 1 &&
1162 dev_priv
->cfb_fence
== obj_priv
->fence_reg
&&
1163 dev_priv
->cfb_plane
== intel_crtc
->plane
&&
1164 dev_priv
->cfb_y
== crtc
->y
)
1167 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
& ~DPFC_CTL_EN
);
1168 POSTING_READ(DPFC_CONTROL
);
1169 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1172 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1173 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1174 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1175 dev_priv
->cfb_y
= crtc
->y
;
1177 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
1178 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1179 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
;
1180 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1182 I915_WRITE(DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1185 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1186 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1187 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1188 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
1191 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
1193 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1196 void g4x_disable_fbc(struct drm_device
*dev
)
1198 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1201 /* Disable compression */
1202 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1203 if (dpfc_ctl
& DPFC_CTL_EN
) {
1204 dpfc_ctl
&= ~DPFC_CTL_EN
;
1205 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1207 DRM_DEBUG_KMS("disabled FBC\n");
1211 static bool g4x_fbc_enabled(struct drm_device
*dev
)
1213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1215 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
1218 static void ironlake_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1220 struct drm_device
*dev
= crtc
->dev
;
1221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1222 struct drm_framebuffer
*fb
= crtc
->fb
;
1223 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1224 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
1225 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1226 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
1227 unsigned long stall_watermark
= 200;
1230 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1231 if (dpfc_ctl
& DPFC_CTL_EN
) {
1232 if (dev_priv
->cfb_pitch
== dev_priv
->cfb_pitch
/ 64 - 1 &&
1233 dev_priv
->cfb_fence
== obj_priv
->fence_reg
&&
1234 dev_priv
->cfb_plane
== intel_crtc
->plane
&&
1235 dev_priv
->cfb_offset
== obj_priv
->gtt_offset
&&
1236 dev_priv
->cfb_y
== crtc
->y
)
1239 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
& ~DPFC_CTL_EN
);
1240 POSTING_READ(ILK_DPFC_CONTROL
);
1241 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1244 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1245 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1246 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1247 dev_priv
->cfb_offset
= obj_priv
->gtt_offset
;
1248 dev_priv
->cfb_y
= crtc
->y
;
1250 dpfc_ctl
&= DPFC_RESERVED
;
1251 dpfc_ctl
|= (plane
| DPFC_CTL_LIMIT_1X
);
1252 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1253 dpfc_ctl
|= (DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
);
1254 I915_WRITE(ILK_DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1256 I915_WRITE(ILK_DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1259 I915_WRITE(ILK_DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1260 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1261 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1262 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
1263 I915_WRITE(ILK_FBC_RT_BASE
, obj_priv
->gtt_offset
| ILK_FBC_RT_VALID
);
1265 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
1267 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1270 void ironlake_disable_fbc(struct drm_device
*dev
)
1272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1275 /* Disable compression */
1276 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1277 if (dpfc_ctl
& DPFC_CTL_EN
) {
1278 dpfc_ctl
&= ~DPFC_CTL_EN
;
1279 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
1281 DRM_DEBUG_KMS("disabled FBC\n");
1285 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
1287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1289 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
1292 bool intel_fbc_enabled(struct drm_device
*dev
)
1294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1296 if (!dev_priv
->display
.fbc_enabled
)
1299 return dev_priv
->display
.fbc_enabled(dev
);
1302 void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1304 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1306 if (!dev_priv
->display
.enable_fbc
)
1309 dev_priv
->display
.enable_fbc(crtc
, interval
);
1312 void intel_disable_fbc(struct drm_device
*dev
)
1314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1316 if (!dev_priv
->display
.disable_fbc
)
1319 dev_priv
->display
.disable_fbc(dev
);
1323 * intel_update_fbc - enable/disable FBC as needed
1324 * @dev: the drm_device
1326 * Set up the framebuffer compression hardware at mode set time. We
1327 * enable it if possible:
1328 * - plane A only (on pre-965)
1329 * - no pixel mulitply/line duplication
1330 * - no alpha buffer discard
1332 * - framebuffer <= 2048 in width, 1536 in height
1334 * We can't assume that any compression will take place (worst case),
1335 * so the compressed buffer has to be the same size as the uncompressed
1336 * one. It also must reside (along with the line length buffer) in
1339 * We need to enable/disable FBC on a global basis.
1341 static void intel_update_fbc(struct drm_device
*dev
)
1343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1344 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
1345 struct intel_crtc
*intel_crtc
;
1346 struct drm_framebuffer
*fb
;
1347 struct intel_framebuffer
*intel_fb
;
1348 struct drm_i915_gem_object
*obj_priv
;
1350 DRM_DEBUG_KMS("\n");
1352 if (!i915_powersave
)
1355 if (!I915_HAS_FBC(dev
))
1359 * If FBC is already on, we just have to verify that we can
1360 * keep it that way...
1361 * Need to disable if:
1362 * - more than one pipe is active
1363 * - changing FBC params (stride, fence, mode)
1364 * - new fb is too large to fit in compressed buffer
1365 * - going to an unsupported config (interlace, pixel multiply, etc.)
1367 list_for_each_entry(tmp_crtc
, &dev
->mode_config
.crtc_list
, head
) {
1368 if (tmp_crtc
->enabled
) {
1370 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1371 dev_priv
->no_fbc_reason
= FBC_MULTIPLE_PIPES
;
1378 if (!crtc
|| crtc
->fb
== NULL
) {
1379 DRM_DEBUG_KMS("no output, disabling\n");
1380 dev_priv
->no_fbc_reason
= FBC_NO_OUTPUT
;
1384 intel_crtc
= to_intel_crtc(crtc
);
1386 intel_fb
= to_intel_framebuffer(fb
);
1387 obj_priv
= to_intel_bo(intel_fb
->obj
);
1389 if (intel_fb
->obj
->size
> dev_priv
->cfb_size
) {
1390 DRM_DEBUG_KMS("framebuffer too large, disabling "
1392 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
1395 if ((crtc
->mode
.flags
& DRM_MODE_FLAG_INTERLACE
) ||
1396 (crtc
->mode
.flags
& DRM_MODE_FLAG_DBLSCAN
)) {
1397 DRM_DEBUG_KMS("mode incompatible with compression, "
1399 dev_priv
->no_fbc_reason
= FBC_UNSUPPORTED_MODE
;
1402 if ((crtc
->mode
.hdisplay
> 2048) ||
1403 (crtc
->mode
.vdisplay
> 1536)) {
1404 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1405 dev_priv
->no_fbc_reason
= FBC_MODE_TOO_LARGE
;
1408 if ((IS_I915GM(dev
) || IS_I945GM(dev
)) && intel_crtc
->plane
!= 0) {
1409 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1410 dev_priv
->no_fbc_reason
= FBC_BAD_PLANE
;
1413 if (obj_priv
->tiling_mode
!= I915_TILING_X
) {
1414 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1415 dev_priv
->no_fbc_reason
= FBC_NOT_TILED
;
1419 /* If the kernel debugger is active, always disable compression */
1420 if (in_dbg_master())
1423 intel_enable_fbc(crtc
, 500);
1427 /* Multiple disables should be harmless */
1428 if (intel_fbc_enabled(dev
)) {
1429 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1430 intel_disable_fbc(dev
);
1435 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1436 struct drm_gem_object
*obj
,
1439 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1443 switch (obj_priv
->tiling_mode
) {
1444 case I915_TILING_NONE
:
1445 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1446 alignment
= 128 * 1024;
1447 else if (INTEL_INFO(dev
)->gen
>= 4)
1448 alignment
= 4 * 1024;
1450 alignment
= 64 * 1024;
1453 /* pin() will align the object as required by fence */
1457 /* FIXME: Is this true? */
1458 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1464 ret
= i915_gem_object_pin(obj
, alignment
);
1468 ret
= i915_gem_object_set_to_display_plane(obj
, pipelined
);
1472 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1473 * fence, whereas 965+ only requires a fence if using
1474 * framebuffer compression. For simplicity, we always install
1475 * a fence as the cost is not that onerous.
1477 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
&&
1478 obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1479 ret
= i915_gem_object_get_fence_reg(obj
, false);
1487 i915_gem_object_unpin(obj
);
1491 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1493 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1494 int x
, int y
, enum mode_set_atomic state
)
1496 struct drm_device
*dev
= crtc
->dev
;
1497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1498 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1499 struct intel_framebuffer
*intel_fb
;
1500 struct drm_i915_gem_object
*obj_priv
;
1501 struct drm_gem_object
*obj
;
1502 int plane
= intel_crtc
->plane
;
1503 unsigned long Start
, Offset
;
1512 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1516 intel_fb
= to_intel_framebuffer(fb
);
1517 obj
= intel_fb
->obj
;
1518 obj_priv
= to_intel_bo(obj
);
1520 reg
= DSPCNTR(plane
);
1521 dspcntr
= I915_READ(reg
);
1522 /* Mask out pixel format bits in case we change it */
1523 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1524 switch (fb
->bits_per_pixel
) {
1526 dspcntr
|= DISPPLANE_8BPP
;
1529 if (fb
->depth
== 15)
1530 dspcntr
|= DISPPLANE_15_16BPP
;
1532 dspcntr
|= DISPPLANE_16BPP
;
1536 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
1539 DRM_ERROR("Unknown color depth\n");
1542 if (INTEL_INFO(dev
)->gen
>= 4) {
1543 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1544 dspcntr
|= DISPPLANE_TILED
;
1546 dspcntr
&= ~DISPPLANE_TILED
;
1549 if (HAS_PCH_SPLIT(dev
))
1551 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1553 I915_WRITE(reg
, dspcntr
);
1555 Start
= obj_priv
->gtt_offset
;
1556 Offset
= y
* fb
->pitch
+ x
* (fb
->bits_per_pixel
/ 8);
1558 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1559 Start
, Offset
, x
, y
, fb
->pitch
);
1560 I915_WRITE(DSPSTRIDE(plane
), fb
->pitch
);
1561 if (INTEL_INFO(dev
)->gen
>= 4) {
1562 I915_WRITE(DSPSURF(plane
), Start
);
1563 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
1564 I915_WRITE(DSPADDR(plane
), Offset
);
1566 I915_WRITE(DSPADDR(plane
), Start
+ Offset
);
1569 intel_update_fbc(dev
);
1570 intel_increase_pllclock(crtc
);
1576 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
1577 struct drm_framebuffer
*old_fb
)
1579 struct drm_device
*dev
= crtc
->dev
;
1580 struct drm_i915_master_private
*master_priv
;
1581 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1586 DRM_DEBUG_KMS("No FB bound\n");
1590 switch (intel_crtc
->plane
) {
1598 mutex_lock(&dev
->struct_mutex
);
1599 ret
= intel_pin_and_fence_fb_obj(dev
,
1600 to_intel_framebuffer(crtc
->fb
)->obj
,
1603 mutex_unlock(&dev
->struct_mutex
);
1608 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1609 struct drm_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
1610 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1612 wait_event(dev_priv
->pending_flip_queue
,
1613 atomic_read(&obj_priv
->pending_flip
) == 0);
1616 ret
= intel_pipe_set_base_atomic(crtc
, crtc
->fb
, x
, y
,
1617 LEAVE_ATOMIC_MODE_SET
);
1619 i915_gem_object_unpin(to_intel_framebuffer(crtc
->fb
)->obj
);
1620 mutex_unlock(&dev
->struct_mutex
);
1625 i915_gem_object_unpin(to_intel_framebuffer(old_fb
)->obj
);
1627 mutex_unlock(&dev
->struct_mutex
);
1629 if (!dev
->primary
->master
)
1632 master_priv
= dev
->primary
->master
->driver_priv
;
1633 if (!master_priv
->sarea_priv
)
1636 if (intel_crtc
->pipe
) {
1637 master_priv
->sarea_priv
->pipeB_x
= x
;
1638 master_priv
->sarea_priv
->pipeB_y
= y
;
1640 master_priv
->sarea_priv
->pipeA_x
= x
;
1641 master_priv
->sarea_priv
->pipeA_y
= y
;
1647 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
1649 struct drm_device
*dev
= crtc
->dev
;
1650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1653 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
1654 dpa_ctl
= I915_READ(DP_A
);
1655 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1657 if (clock
< 200000) {
1659 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1660 /* workaround for 160Mhz:
1661 1) program 0x4600c bits 15:0 = 0x8124
1662 2) program 0x46010 bit 0 = 1
1663 3) program 0x46034 bit 24 = 1
1664 4) program 0x64000 bit 14 = 1
1666 temp
= I915_READ(0x4600c);
1668 I915_WRITE(0x4600c, temp
| 0x8124);
1670 temp
= I915_READ(0x46010);
1671 I915_WRITE(0x46010, temp
| 1);
1673 temp
= I915_READ(0x46034);
1674 I915_WRITE(0x46034, temp
| (1 << 24));
1676 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1678 I915_WRITE(DP_A
, dpa_ctl
);
1684 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
1686 struct drm_device
*dev
= crtc
->dev
;
1687 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1688 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1689 int pipe
= intel_crtc
->pipe
;
1692 /* enable normal train */
1693 reg
= FDI_TX_CTL(pipe
);
1694 temp
= I915_READ(reg
);
1695 temp
&= ~FDI_LINK_TRAIN_NONE
;
1696 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
1697 I915_WRITE(reg
, temp
);
1699 reg
= FDI_RX_CTL(pipe
);
1700 temp
= I915_READ(reg
);
1701 if (HAS_PCH_CPT(dev
)) {
1702 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1703 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
1705 temp
&= ~FDI_LINK_TRAIN_NONE
;
1706 temp
|= FDI_LINK_TRAIN_NONE
;
1708 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
1710 /* wait one idle pattern time */
1715 /* The FDI link training functions for ILK/Ibexpeak. */
1716 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
1718 struct drm_device
*dev
= crtc
->dev
;
1719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1720 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1721 int pipe
= intel_crtc
->pipe
;
1722 u32 reg
, temp
, tries
;
1724 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1726 reg
= FDI_RX_IMR(pipe
);
1727 temp
= I915_READ(reg
);
1728 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1729 temp
&= ~FDI_RX_BIT_LOCK
;
1730 I915_WRITE(reg
, temp
);
1734 /* enable CPU FDI TX and PCH FDI RX */
1735 reg
= FDI_TX_CTL(pipe
);
1736 temp
= I915_READ(reg
);
1738 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1739 temp
&= ~FDI_LINK_TRAIN_NONE
;
1740 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1741 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
1743 reg
= FDI_RX_CTL(pipe
);
1744 temp
= I915_READ(reg
);
1745 temp
&= ~FDI_LINK_TRAIN_NONE
;
1746 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1747 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
1752 /* Ironlake workaround, enable clock pointer after FDI enable*/
1753 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_ENABLE
);
1755 reg
= FDI_RX_IIR(pipe
);
1756 for (tries
= 0; tries
< 5; tries
++) {
1757 temp
= I915_READ(reg
);
1758 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1760 if ((temp
& FDI_RX_BIT_LOCK
)) {
1761 DRM_DEBUG_KMS("FDI train 1 done.\n");
1762 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
1767 DRM_ERROR("FDI train 1 fail!\n");
1770 reg
= FDI_TX_CTL(pipe
);
1771 temp
= I915_READ(reg
);
1772 temp
&= ~FDI_LINK_TRAIN_NONE
;
1773 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1774 I915_WRITE(reg
, temp
);
1776 reg
= FDI_RX_CTL(pipe
);
1777 temp
= I915_READ(reg
);
1778 temp
&= ~FDI_LINK_TRAIN_NONE
;
1779 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1780 I915_WRITE(reg
, temp
);
1785 reg
= FDI_RX_IIR(pipe
);
1786 for (tries
= 0; tries
< 5; tries
++) {
1787 temp
= I915_READ(reg
);
1788 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1790 if (temp
& FDI_RX_SYMBOL_LOCK
) {
1791 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
1792 DRM_DEBUG_KMS("FDI train 2 done.\n");
1797 DRM_ERROR("FDI train 2 fail!\n");
1799 DRM_DEBUG_KMS("FDI train done\n");
1803 static const int const snb_b_fdi_train_param
[] = {
1804 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
1805 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
1806 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
1807 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
1810 /* The FDI link training functions for SNB/Cougarpoint. */
1811 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
1813 struct drm_device
*dev
= crtc
->dev
;
1814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1815 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1816 int pipe
= intel_crtc
->pipe
;
1819 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1821 reg
= FDI_RX_IMR(pipe
);
1822 temp
= I915_READ(reg
);
1823 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1824 temp
&= ~FDI_RX_BIT_LOCK
;
1825 I915_WRITE(reg
, temp
);
1830 /* enable CPU FDI TX and PCH FDI RX */
1831 reg
= FDI_TX_CTL(pipe
);
1832 temp
= I915_READ(reg
);
1834 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1835 temp
&= ~FDI_LINK_TRAIN_NONE
;
1836 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1837 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1839 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
1840 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
1842 reg
= FDI_RX_CTL(pipe
);
1843 temp
= I915_READ(reg
);
1844 if (HAS_PCH_CPT(dev
)) {
1845 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1846 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
1848 temp
&= ~FDI_LINK_TRAIN_NONE
;
1849 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1851 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
1856 for (i
= 0; i
< 4; i
++ ) {
1857 reg
= FDI_TX_CTL(pipe
);
1858 temp
= I915_READ(reg
);
1859 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1860 temp
|= snb_b_fdi_train_param
[i
];
1861 I915_WRITE(reg
, temp
);
1866 reg
= FDI_RX_IIR(pipe
);
1867 temp
= I915_READ(reg
);
1868 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1870 if (temp
& FDI_RX_BIT_LOCK
) {
1871 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
1872 DRM_DEBUG_KMS("FDI train 1 done.\n");
1877 DRM_ERROR("FDI train 1 fail!\n");
1880 reg
= FDI_TX_CTL(pipe
);
1881 temp
= I915_READ(reg
);
1882 temp
&= ~FDI_LINK_TRAIN_NONE
;
1883 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1885 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1887 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
1889 I915_WRITE(reg
, temp
);
1891 reg
= FDI_RX_CTL(pipe
);
1892 temp
= I915_READ(reg
);
1893 if (HAS_PCH_CPT(dev
)) {
1894 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1895 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
1897 temp
&= ~FDI_LINK_TRAIN_NONE
;
1898 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1900 I915_WRITE(reg
, temp
);
1905 for (i
= 0; i
< 4; i
++ ) {
1906 reg
= FDI_TX_CTL(pipe
);
1907 temp
= I915_READ(reg
);
1908 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1909 temp
|= snb_b_fdi_train_param
[i
];
1910 I915_WRITE(reg
, temp
);
1915 reg
= FDI_RX_IIR(pipe
);
1916 temp
= I915_READ(reg
);
1917 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1919 if (temp
& FDI_RX_SYMBOL_LOCK
) {
1920 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
1921 DRM_DEBUG_KMS("FDI train 2 done.\n");
1926 DRM_ERROR("FDI train 2 fail!\n");
1928 DRM_DEBUG_KMS("FDI train done.\n");
1931 static void ironlake_fdi_enable(struct drm_crtc
*crtc
)
1933 struct drm_device
*dev
= crtc
->dev
;
1934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1935 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1936 int pipe
= intel_crtc
->pipe
;
1939 /* Write the TU size bits so error detection works */
1940 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
1941 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
1943 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1944 reg
= FDI_RX_CTL(pipe
);
1945 temp
= I915_READ(reg
);
1946 temp
&= ~((0x7 << 19) | (0x7 << 16));
1947 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1948 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
1949 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
1954 /* Switch from Rawclk to PCDclk */
1955 temp
= I915_READ(reg
);
1956 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
1961 /* Enable CPU FDI TX PLL, always on for Ironlake */
1962 reg
= FDI_TX_CTL(pipe
);
1963 temp
= I915_READ(reg
);
1964 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
1965 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
1972 static void intel_flush_display_plane(struct drm_device
*dev
,
1975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1976 u32 reg
= DSPADDR(plane
);
1977 I915_WRITE(reg
, I915_READ(reg
));
1981 * When we disable a pipe, we need to clear any pending scanline wait events
1982 * to avoid hanging the ring, which we assume we are waiting on.
1984 static void intel_clear_scanline_wait(struct drm_device
*dev
)
1986 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1990 /* Can't break the hang on i8xx */
1993 tmp
= I915_READ(PRB0_CTL
);
1994 if (tmp
& RING_WAIT
) {
1995 I915_WRITE(PRB0_CTL
, tmp
);
1996 POSTING_READ(PRB0_CTL
);
2000 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2002 struct drm_i915_gem_object
*obj_priv
;
2003 struct drm_i915_private
*dev_priv
;
2005 if (crtc
->fb
== NULL
)
2008 obj_priv
= to_intel_bo(to_intel_framebuffer(crtc
->fb
)->obj
);
2009 dev_priv
= crtc
->dev
->dev_private
;
2010 wait_event(dev_priv
->pending_flip_queue
,
2011 atomic_read(&obj_priv
->pending_flip
) == 0);
2014 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
2016 struct drm_device
*dev
= crtc
->dev
;
2017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2018 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2019 int pipe
= intel_crtc
->pipe
;
2020 int plane
= intel_crtc
->plane
;
2023 if (intel_crtc
->active
)
2026 intel_crtc
->active
= true;
2027 intel_update_watermarks(dev
);
2029 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
2030 temp
= I915_READ(PCH_LVDS
);
2031 if ((temp
& LVDS_PORT_EN
) == 0)
2032 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
2035 ironlake_fdi_enable(crtc
);
2037 /* Enable panel fitting for LVDS */
2038 if (dev_priv
->pch_pf_size
&&
2039 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) || HAS_eDP
)) {
2040 /* Force use of hard-coded filter coefficients
2041 * as some pre-programmed values are broken,
2044 I915_WRITE(pipe
? PFB_CTL_1
: PFA_CTL_1
,
2045 PF_ENABLE
| PF_FILTER_MED_3x3
);
2046 I915_WRITE(pipe
? PFB_WIN_POS
: PFA_WIN_POS
,
2047 dev_priv
->pch_pf_pos
);
2048 I915_WRITE(pipe
? PFB_WIN_SZ
: PFA_WIN_SZ
,
2049 dev_priv
->pch_pf_size
);
2052 /* Enable CPU pipe */
2053 reg
= PIPECONF(pipe
);
2054 temp
= I915_READ(reg
);
2055 if ((temp
& PIPECONF_ENABLE
) == 0) {
2056 I915_WRITE(reg
, temp
| PIPECONF_ENABLE
);
2058 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2061 /* configure and enable CPU plane */
2062 reg
= DSPCNTR(plane
);
2063 temp
= I915_READ(reg
);
2064 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
2065 I915_WRITE(reg
, temp
| DISPLAY_PLANE_ENABLE
);
2066 intel_flush_display_plane(dev
, plane
);
2069 /* For PCH output, training FDI link */
2071 gen6_fdi_link_train(crtc
);
2073 ironlake_fdi_link_train(crtc
);
2075 /* enable PCH DPLL */
2076 reg
= PCH_DPLL(pipe
);
2077 temp
= I915_READ(reg
);
2078 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
2079 I915_WRITE(reg
, temp
| DPLL_VCO_ENABLE
);
2084 if (HAS_PCH_CPT(dev
)) {
2085 /* Be sure PCH DPLL SEL is set */
2086 temp
= I915_READ(PCH_DPLL_SEL
);
2087 if (pipe
== 0 && (temp
& TRANSA_DPLL_ENABLE
) == 0)
2088 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
2089 else if (pipe
== 1 && (temp
& TRANSB_DPLL_ENABLE
) == 0)
2090 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
2091 I915_WRITE(PCH_DPLL_SEL
, temp
);
2094 /* set transcoder timing */
2095 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
2096 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
2097 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
2099 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
2100 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
2101 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
2103 intel_fdi_normal_train(crtc
);
2105 /* For PCH DP, enable TRANS_DP_CTL */
2106 if (HAS_PCH_CPT(dev
) &&
2107 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
2108 reg
= TRANS_DP_CTL(pipe
);
2109 temp
= I915_READ(reg
);
2110 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
2111 TRANS_DP_SYNC_MASK
);
2112 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
2113 TRANS_DP_ENH_FRAMING
);
2115 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
2116 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
2117 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
2118 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
2120 switch (intel_trans_dp_port_sel(crtc
)) {
2122 temp
|= TRANS_DP_PORT_SEL_B
;
2125 temp
|= TRANS_DP_PORT_SEL_C
;
2128 temp
|= TRANS_DP_PORT_SEL_D
;
2131 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2132 temp
|= TRANS_DP_PORT_SEL_B
;
2136 I915_WRITE(reg
, temp
);
2139 /* enable PCH transcoder */
2140 reg
= TRANSCONF(pipe
);
2141 temp
= I915_READ(reg
);
2143 * make the BPC in transcoder be consistent with
2144 * that in pipeconf reg.
2146 temp
&= ~PIPE_BPC_MASK
;
2147 temp
|= I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
;
2148 I915_WRITE(reg
, temp
| TRANS_ENABLE
);
2149 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
2150 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
2152 intel_crtc_load_lut(crtc
);
2153 intel_update_fbc(dev
);
2154 intel_crtc_update_cursor(crtc
, true);
2157 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
2159 struct drm_device
*dev
= crtc
->dev
;
2160 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2161 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2162 int pipe
= intel_crtc
->pipe
;
2163 int plane
= intel_crtc
->plane
;
2166 if (!intel_crtc
->active
)
2169 intel_crtc_wait_for_pending_flips(crtc
);
2170 drm_vblank_off(dev
, pipe
);
2171 intel_crtc_update_cursor(crtc
, false);
2173 /* Disable display plane */
2174 reg
= DSPCNTR(plane
);
2175 temp
= I915_READ(reg
);
2176 if (temp
& DISPLAY_PLANE_ENABLE
) {
2177 I915_WRITE(reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
2178 intel_flush_display_plane(dev
, plane
);
2181 if (dev_priv
->cfb_plane
== plane
&&
2182 dev_priv
->display
.disable_fbc
)
2183 dev_priv
->display
.disable_fbc(dev
);
2185 /* disable cpu pipe, disable after all planes disabled */
2186 reg
= PIPECONF(pipe
);
2187 temp
= I915_READ(reg
);
2188 if (temp
& PIPECONF_ENABLE
) {
2189 I915_WRITE(reg
, temp
& ~PIPECONF_ENABLE
);
2191 /* wait for cpu pipe off, pipe state */
2192 intel_wait_for_pipe_off(dev
, intel_crtc
->pipe
);
2196 I915_WRITE(pipe
? PFB_CTL_1
: PFA_CTL_1
, 0);
2197 I915_WRITE(pipe
? PFB_WIN_SZ
: PFA_WIN_SZ
, 0);
2199 /* disable CPU FDI tx and PCH FDI rx */
2200 reg
= FDI_TX_CTL(pipe
);
2201 temp
= I915_READ(reg
);
2202 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2205 reg
= FDI_RX_CTL(pipe
);
2206 temp
= I915_READ(reg
);
2207 temp
&= ~(0x7 << 16);
2208 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2209 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2214 /* Ironlake workaround, disable clock pointer after downing FDI */
2215 I915_WRITE(FDI_RX_CHICKEN(pipe
),
2216 I915_READ(FDI_RX_CHICKEN(pipe
) &
2217 ~FDI_RX_PHASE_SYNC_POINTER_ENABLE
));
2219 /* still set train pattern 1 */
2220 reg
= FDI_TX_CTL(pipe
);
2221 temp
= I915_READ(reg
);
2222 temp
&= ~FDI_LINK_TRAIN_NONE
;
2223 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2224 I915_WRITE(reg
, temp
);
2226 reg
= FDI_RX_CTL(pipe
);
2227 temp
= I915_READ(reg
);
2228 if (HAS_PCH_CPT(dev
)) {
2229 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2230 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2232 temp
&= ~FDI_LINK_TRAIN_NONE
;
2233 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2235 /* BPC in FDI rx is consistent with that in PIPECONF */
2236 temp
&= ~(0x07 << 16);
2237 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2238 I915_WRITE(reg
, temp
);
2243 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
2244 temp
= I915_READ(PCH_LVDS
);
2245 if (temp
& LVDS_PORT_EN
) {
2246 I915_WRITE(PCH_LVDS
, temp
& ~LVDS_PORT_EN
);
2247 POSTING_READ(PCH_LVDS
);
2252 /* disable PCH transcoder */
2253 reg
= TRANSCONF(plane
);
2254 temp
= I915_READ(reg
);
2255 if (temp
& TRANS_ENABLE
) {
2256 I915_WRITE(reg
, temp
& ~TRANS_ENABLE
);
2257 /* wait for PCH transcoder off, transcoder state */
2258 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
2259 DRM_ERROR("failed to disable transcoder\n");
2262 if (HAS_PCH_CPT(dev
)) {
2263 /* disable TRANS_DP_CTL */
2264 reg
= TRANS_DP_CTL(pipe
);
2265 temp
= I915_READ(reg
);
2266 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
2267 I915_WRITE(reg
, temp
);
2269 /* disable DPLL_SEL */
2270 temp
= I915_READ(PCH_DPLL_SEL
);
2272 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
2274 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
2275 I915_WRITE(PCH_DPLL_SEL
, temp
);
2278 /* disable PCH DPLL */
2279 reg
= PCH_DPLL(pipe
);
2280 temp
= I915_READ(reg
);
2281 I915_WRITE(reg
, temp
& ~DPLL_VCO_ENABLE
);
2283 /* Switch from PCDclk to Rawclk */
2284 reg
= FDI_RX_CTL(pipe
);
2285 temp
= I915_READ(reg
);
2286 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2288 /* Disable CPU FDI TX PLL */
2289 reg
= FDI_TX_CTL(pipe
);
2290 temp
= I915_READ(reg
);
2291 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2296 reg
= FDI_RX_CTL(pipe
);
2297 temp
= I915_READ(reg
);
2298 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2300 /* Wait for the clocks to turn off. */
2304 intel_crtc
->active
= false;
2305 intel_update_watermarks(dev
);
2306 intel_update_fbc(dev
);
2307 intel_clear_scanline_wait(dev
);
2310 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2312 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2313 int pipe
= intel_crtc
->pipe
;
2314 int plane
= intel_crtc
->plane
;
2316 /* XXX: When our outputs are all unaware of DPMS modes other than off
2317 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2320 case DRM_MODE_DPMS_ON
:
2321 case DRM_MODE_DPMS_STANDBY
:
2322 case DRM_MODE_DPMS_SUSPEND
:
2323 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe
, plane
);
2324 ironlake_crtc_enable(crtc
);
2327 case DRM_MODE_DPMS_OFF
:
2328 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe
, plane
);
2329 ironlake_crtc_disable(crtc
);
2334 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
2336 if (!enable
&& intel_crtc
->overlay
) {
2337 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2339 mutex_lock(&dev
->struct_mutex
);
2340 (void) intel_overlay_switch_off(intel_crtc
->overlay
, false);
2341 mutex_unlock(&dev
->struct_mutex
);
2344 /* Let userspace switch the overlay on again. In most cases userspace
2345 * has to recompute where to put it anyway.
2349 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
2351 struct drm_device
*dev
= crtc
->dev
;
2352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2353 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2354 int pipe
= intel_crtc
->pipe
;
2355 int plane
= intel_crtc
->plane
;
2358 if (intel_crtc
->active
)
2361 intel_crtc
->active
= true;
2362 intel_update_watermarks(dev
);
2364 /* Enable the DPLL */
2366 temp
= I915_READ(reg
);
2367 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
2368 I915_WRITE(reg
, temp
);
2370 /* Wait for the clocks to stabilize. */
2374 I915_WRITE(reg
, temp
| DPLL_VCO_ENABLE
);
2376 /* Wait for the clocks to stabilize. */
2380 I915_WRITE(reg
, temp
| DPLL_VCO_ENABLE
);
2382 /* Wait for the clocks to stabilize. */
2387 /* Enable the pipe */
2388 reg
= PIPECONF(pipe
);
2389 temp
= I915_READ(reg
);
2390 if ((temp
& PIPECONF_ENABLE
) == 0)
2391 I915_WRITE(reg
, temp
| PIPECONF_ENABLE
);
2393 /* Enable the plane */
2394 reg
= DSPCNTR(plane
);
2395 temp
= I915_READ(reg
);
2396 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
2397 I915_WRITE(reg
, temp
| DISPLAY_PLANE_ENABLE
);
2398 intel_flush_display_plane(dev
, plane
);
2401 intel_crtc_load_lut(crtc
);
2402 intel_update_fbc(dev
);
2404 /* Give the overlay scaler a chance to enable if it's on this pipe */
2405 intel_crtc_dpms_overlay(intel_crtc
, true);
2406 intel_crtc_update_cursor(crtc
, true);
2409 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
2411 struct drm_device
*dev
= crtc
->dev
;
2412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2413 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2414 int pipe
= intel_crtc
->pipe
;
2415 int plane
= intel_crtc
->plane
;
2418 if (!intel_crtc
->active
)
2421 /* Give the overlay scaler a chance to disable if it's on this pipe */
2422 intel_crtc_wait_for_pending_flips(crtc
);
2423 drm_vblank_off(dev
, pipe
);
2424 intel_crtc_dpms_overlay(intel_crtc
, false);
2425 intel_crtc_update_cursor(crtc
, false);
2427 if (dev_priv
->cfb_plane
== plane
&&
2428 dev_priv
->display
.disable_fbc
)
2429 dev_priv
->display
.disable_fbc(dev
);
2431 /* Disable display plane */
2432 reg
= DSPCNTR(plane
);
2433 temp
= I915_READ(reg
);
2434 if (temp
& DISPLAY_PLANE_ENABLE
) {
2435 I915_WRITE(reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
2436 /* Flush the plane changes */
2437 intel_flush_display_plane(dev
, plane
);
2439 /* Wait for vblank for the disable to take effect */
2441 intel_wait_for_vblank(dev
, pipe
);
2444 /* Don't disable pipe A or pipe A PLLs if needed */
2445 if (pipe
== 0 && (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
2448 /* Next, disable display pipes */
2449 reg
= PIPECONF(pipe
);
2450 temp
= I915_READ(reg
);
2451 if (temp
& PIPECONF_ENABLE
) {
2452 I915_WRITE(reg
, temp
& ~PIPECONF_ENABLE
);
2454 /* Wait for the pipe to turn off */
2456 intel_wait_for_pipe_off(dev
, pipe
);
2460 temp
= I915_READ(reg
);
2461 if (temp
& DPLL_VCO_ENABLE
) {
2462 I915_WRITE(reg
, temp
& ~DPLL_VCO_ENABLE
);
2464 /* Wait for the clocks to turn off. */
2470 intel_crtc
->active
= false;
2471 intel_update_fbc(dev
);
2472 intel_update_watermarks(dev
);
2473 intel_clear_scanline_wait(dev
);
2476 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2478 /* XXX: When our outputs are all unaware of DPMS modes other than off
2479 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2482 case DRM_MODE_DPMS_ON
:
2483 case DRM_MODE_DPMS_STANDBY
:
2484 case DRM_MODE_DPMS_SUSPEND
:
2485 i9xx_crtc_enable(crtc
);
2487 case DRM_MODE_DPMS_OFF
:
2488 i9xx_crtc_disable(crtc
);
2494 * Sets the power management mode of the pipe and plane.
2496 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2498 struct drm_device
*dev
= crtc
->dev
;
2499 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2500 struct drm_i915_master_private
*master_priv
;
2501 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2502 int pipe
= intel_crtc
->pipe
;
2505 if (intel_crtc
->dpms_mode
== mode
)
2508 intel_crtc
->dpms_mode
= mode
;
2510 dev_priv
->display
.dpms(crtc
, mode
);
2512 if (!dev
->primary
->master
)
2515 master_priv
= dev
->primary
->master
->driver_priv
;
2516 if (!master_priv
->sarea_priv
)
2519 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
2523 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2524 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2527 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2528 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2531 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
2536 static void intel_crtc_disable(struct drm_crtc
*crtc
)
2538 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
2539 struct drm_device
*dev
= crtc
->dev
;
2541 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
2544 mutex_lock(&dev
->struct_mutex
);
2545 i915_gem_object_unpin(to_intel_framebuffer(crtc
->fb
)->obj
);
2546 mutex_unlock(&dev
->struct_mutex
);
2550 /* Prepare for a mode set.
2552 * Note we could be a lot smarter here. We need to figure out which outputs
2553 * will be enabled, which disabled (in short, how the config will changes)
2554 * and perform the minimum necessary steps to accomplish that, e.g. updating
2555 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2556 * panel fitting is in the proper state, etc.
2558 static void i9xx_crtc_prepare(struct drm_crtc
*crtc
)
2560 i9xx_crtc_disable(crtc
);
2563 static void i9xx_crtc_commit(struct drm_crtc
*crtc
)
2565 i9xx_crtc_enable(crtc
);
2568 static void ironlake_crtc_prepare(struct drm_crtc
*crtc
)
2570 ironlake_crtc_disable(crtc
);
2573 static void ironlake_crtc_commit(struct drm_crtc
*crtc
)
2575 ironlake_crtc_enable(crtc
);
2578 void intel_encoder_prepare (struct drm_encoder
*encoder
)
2580 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2581 /* lvds has its own version of prepare see intel_lvds_prepare */
2582 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
2585 void intel_encoder_commit (struct drm_encoder
*encoder
)
2587 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2588 /* lvds has its own version of commit see intel_lvds_commit */
2589 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
2592 void intel_encoder_destroy(struct drm_encoder
*encoder
)
2594 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
2596 drm_encoder_cleanup(encoder
);
2597 kfree(intel_encoder
);
2600 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
2601 struct drm_display_mode
*mode
,
2602 struct drm_display_mode
*adjusted_mode
)
2604 struct drm_device
*dev
= crtc
->dev
;
2606 if (HAS_PCH_SPLIT(dev
)) {
2607 /* FDI link clock is fixed at 2.7G */
2608 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
2612 /* XXX some encoders set the crtcinfo, others don't.
2613 * Obviously we need some form of conflict resolution here...
2615 if (adjusted_mode
->crtc_htotal
== 0)
2616 drm_mode_set_crtcinfo(adjusted_mode
, 0);
2621 static int i945_get_display_clock_speed(struct drm_device
*dev
)
2626 static int i915_get_display_clock_speed(struct drm_device
*dev
)
2631 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
2636 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
2640 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
2642 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
2645 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
2646 case GC_DISPLAY_CLOCK_333_MHZ
:
2649 case GC_DISPLAY_CLOCK_190_200_MHZ
:
2655 static int i865_get_display_clock_speed(struct drm_device
*dev
)
2660 static int i855_get_display_clock_speed(struct drm_device
*dev
)
2663 /* Assume that the hardware is in the high speed state. This
2664 * should be the default.
2666 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
2667 case GC_CLOCK_133_200
:
2668 case GC_CLOCK_100_200
:
2670 case GC_CLOCK_166_250
:
2672 case GC_CLOCK_100_133
:
2676 /* Shouldn't happen */
2680 static int i830_get_display_clock_speed(struct drm_device
*dev
)
2694 fdi_reduce_ratio(u32
*num
, u32
*den
)
2696 while (*num
> 0xffffff || *den
> 0xffffff) {
2702 #define DATA_N 0x800000
2703 #define LINK_N 0x80000
2706 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
2707 int link_clock
, struct fdi_m_n
*m_n
)
2711 m_n
->tu
= 64; /* default size */
2713 temp
= (u64
) DATA_N
* pixel_clock
;
2714 temp
= div_u64(temp
, link_clock
);
2715 m_n
->gmch_m
= div_u64(temp
* bits_per_pixel
, nlanes
);
2716 m_n
->gmch_m
>>= 3; /* convert to bytes_per_pixel */
2717 m_n
->gmch_n
= DATA_N
;
2718 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
2720 temp
= (u64
) LINK_N
* pixel_clock
;
2721 m_n
->link_m
= div_u64(temp
, link_clock
);
2722 m_n
->link_n
= LINK_N
;
2723 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
2727 struct intel_watermark_params
{
2728 unsigned long fifo_size
;
2729 unsigned long max_wm
;
2730 unsigned long default_wm
;
2731 unsigned long guard_size
;
2732 unsigned long cacheline_size
;
2735 /* Pineview has different values for various configs */
2736 static struct intel_watermark_params pineview_display_wm
= {
2737 PINEVIEW_DISPLAY_FIFO
,
2741 PINEVIEW_FIFO_LINE_SIZE
2743 static struct intel_watermark_params pineview_display_hplloff_wm
= {
2744 PINEVIEW_DISPLAY_FIFO
,
2746 PINEVIEW_DFT_HPLLOFF_WM
,
2748 PINEVIEW_FIFO_LINE_SIZE
2750 static struct intel_watermark_params pineview_cursor_wm
= {
2751 PINEVIEW_CURSOR_FIFO
,
2752 PINEVIEW_CURSOR_MAX_WM
,
2753 PINEVIEW_CURSOR_DFT_WM
,
2754 PINEVIEW_CURSOR_GUARD_WM
,
2755 PINEVIEW_FIFO_LINE_SIZE
,
2757 static struct intel_watermark_params pineview_cursor_hplloff_wm
= {
2758 PINEVIEW_CURSOR_FIFO
,
2759 PINEVIEW_CURSOR_MAX_WM
,
2760 PINEVIEW_CURSOR_DFT_WM
,
2761 PINEVIEW_CURSOR_GUARD_WM
,
2762 PINEVIEW_FIFO_LINE_SIZE
2764 static struct intel_watermark_params g4x_wm_info
= {
2771 static struct intel_watermark_params g4x_cursor_wm_info
= {
2778 static struct intel_watermark_params i965_cursor_wm_info
= {
2783 I915_FIFO_LINE_SIZE
,
2785 static struct intel_watermark_params i945_wm_info
= {
2792 static struct intel_watermark_params i915_wm_info
= {
2799 static struct intel_watermark_params i855_wm_info
= {
2806 static struct intel_watermark_params i830_wm_info
= {
2814 static struct intel_watermark_params ironlake_display_wm_info
= {
2822 static struct intel_watermark_params ironlake_cursor_wm_info
= {
2830 static struct intel_watermark_params ironlake_display_srwm_info
= {
2831 ILK_DISPLAY_SR_FIFO
,
2832 ILK_DISPLAY_MAX_SRWM
,
2833 ILK_DISPLAY_DFT_SRWM
,
2838 static struct intel_watermark_params ironlake_cursor_srwm_info
= {
2840 ILK_CURSOR_MAX_SRWM
,
2841 ILK_CURSOR_DFT_SRWM
,
2847 * intel_calculate_wm - calculate watermark level
2848 * @clock_in_khz: pixel clock
2849 * @wm: chip FIFO params
2850 * @pixel_size: display pixel size
2851 * @latency_ns: memory latency for the platform
2853 * Calculate the watermark level (the level at which the display plane will
2854 * start fetching from memory again). Each chip has a different display
2855 * FIFO size and allocation, so the caller needs to figure that out and pass
2856 * in the correct intel_watermark_params structure.
2858 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2859 * on the pixel size. When it reaches the watermark level, it'll start
2860 * fetching FIFO line sized based chunks from memory until the FIFO fills
2861 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2862 * will occur, and a display engine hang could result.
2864 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
2865 struct intel_watermark_params
*wm
,
2867 unsigned long latency_ns
)
2869 long entries_required
, wm_size
;
2872 * Note: we need to make sure we don't overflow for various clock &
2874 * clocks go from a few thousand to several hundred thousand.
2875 * latency is usually a few thousand
2877 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
2879 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
2881 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required
);
2883 wm_size
= wm
->fifo_size
- (entries_required
+ wm
->guard_size
);
2885 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size
);
2887 /* Don't promote wm_size to unsigned... */
2888 if (wm_size
> (long)wm
->max_wm
)
2889 wm_size
= wm
->max_wm
;
2891 wm_size
= wm
->default_wm
;
2895 struct cxsr_latency
{
2898 unsigned long fsb_freq
;
2899 unsigned long mem_freq
;
2900 unsigned long display_sr
;
2901 unsigned long display_hpll_disable
;
2902 unsigned long cursor_sr
;
2903 unsigned long cursor_hpll_disable
;
2906 static const struct cxsr_latency cxsr_latency_table
[] = {
2907 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2908 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2909 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2910 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2911 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2913 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2914 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2915 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2916 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2917 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2919 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2920 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2921 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2922 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2923 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2925 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2926 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2927 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2928 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2929 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2931 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2932 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2933 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2934 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2935 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2937 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2938 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2939 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2940 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2941 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2944 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
2949 const struct cxsr_latency
*latency
;
2952 if (fsb
== 0 || mem
== 0)
2955 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
2956 latency
= &cxsr_latency_table
[i
];
2957 if (is_desktop
== latency
->is_desktop
&&
2958 is_ddr3
== latency
->is_ddr3
&&
2959 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
2963 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2968 static void pineview_disable_cxsr(struct drm_device
*dev
)
2970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2972 /* deactivate cxsr */
2973 I915_WRITE(DSPFW3
, I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
);
2977 * Latency for FIFO fetches is dependent on several factors:
2978 * - memory configuration (speed, channels)
2980 * - current MCH state
2981 * It can be fairly high in some situations, so here we assume a fairly
2982 * pessimal value. It's a tradeoff between extra memory fetches (if we
2983 * set this value too high, the FIFO will fetch frequently to stay full)
2984 * and power consumption (set it too low to save power and we might see
2985 * FIFO underruns and display "flicker").
2987 * A value of 5us seems to be a good balance; safe for very low end
2988 * platforms but not overly aggressive on lower latency configs.
2990 static const int latency_ns
= 5000;
2992 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
2994 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2995 uint32_t dsparb
= I915_READ(DSPARB
);
2998 size
= dsparb
& 0x7f;
3000 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
3002 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3003 plane
? "B" : "A", size
);
3008 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
3010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3011 uint32_t dsparb
= I915_READ(DSPARB
);
3014 size
= dsparb
& 0x1ff;
3016 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
3017 size
>>= 1; /* Convert to cachelines */
3019 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3020 plane
? "B" : "A", size
);
3025 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
3027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3028 uint32_t dsparb
= I915_READ(DSPARB
);
3031 size
= dsparb
& 0x7f;
3032 size
>>= 2; /* Convert to cachelines */
3034 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3041 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
3043 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3044 uint32_t dsparb
= I915_READ(DSPARB
);
3047 size
= dsparb
& 0x7f;
3048 size
>>= 1; /* Convert to cachelines */
3050 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3051 plane
? "B" : "A", size
);
3056 static void pineview_update_wm(struct drm_device
*dev
, int planea_clock
,
3057 int planeb_clock
, int sr_hdisplay
, int unused
,
3060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3061 const struct cxsr_latency
*latency
;
3066 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
3067 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
3069 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3070 pineview_disable_cxsr(dev
);
3074 if (!planea_clock
|| !planeb_clock
) {
3075 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3078 wm
= intel_calculate_wm(sr_clock
, &pineview_display_wm
,
3079 pixel_size
, latency
->display_sr
);
3080 reg
= I915_READ(DSPFW1
);
3081 reg
&= ~DSPFW_SR_MASK
;
3082 reg
|= wm
<< DSPFW_SR_SHIFT
;
3083 I915_WRITE(DSPFW1
, reg
);
3084 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
3087 wm
= intel_calculate_wm(sr_clock
, &pineview_cursor_wm
,
3088 pixel_size
, latency
->cursor_sr
);
3089 reg
= I915_READ(DSPFW3
);
3090 reg
&= ~DSPFW_CURSOR_SR_MASK
;
3091 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
3092 I915_WRITE(DSPFW3
, reg
);
3094 /* Display HPLL off SR */
3095 wm
= intel_calculate_wm(sr_clock
, &pineview_display_hplloff_wm
,
3096 pixel_size
, latency
->display_hpll_disable
);
3097 reg
= I915_READ(DSPFW3
);
3098 reg
&= ~DSPFW_HPLL_SR_MASK
;
3099 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
3100 I915_WRITE(DSPFW3
, reg
);
3102 /* cursor HPLL off SR */
3103 wm
= intel_calculate_wm(sr_clock
, &pineview_cursor_hplloff_wm
,
3104 pixel_size
, latency
->cursor_hpll_disable
);
3105 reg
= I915_READ(DSPFW3
);
3106 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
3107 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
3108 I915_WRITE(DSPFW3
, reg
);
3109 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
3113 I915_READ(DSPFW3
) | PINEVIEW_SELF_REFRESH_EN
);
3114 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3116 pineview_disable_cxsr(dev
);
3117 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3121 static void g4x_update_wm(struct drm_device
*dev
, int planea_clock
,
3122 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3126 int total_size
, cacheline_size
;
3127 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
, cursor_sr
;
3128 struct intel_watermark_params planea_params
, planeb_params
;
3129 unsigned long line_time_us
;
3130 int sr_clock
, sr_entries
= 0, entries_required
;
3132 /* Create copies of the base settings for each pipe */
3133 planea_params
= planeb_params
= g4x_wm_info
;
3135 /* Grab a couple of global values before we overwrite them */
3136 total_size
= planea_params
.fifo_size
;
3137 cacheline_size
= planea_params
.cacheline_size
;
3140 * Note: we need to make sure we don't overflow for various clock &
3142 * clocks go from a few thousand to several hundred thousand.
3143 * latency is usually a few thousand
3145 entries_required
= ((planea_clock
/ 1000) * pixel_size
* latency_ns
) /
3147 entries_required
= DIV_ROUND_UP(entries_required
, G4X_FIFO_LINE_SIZE
);
3148 planea_wm
= entries_required
+ planea_params
.guard_size
;
3150 entries_required
= ((planeb_clock
/ 1000) * pixel_size
* latency_ns
) /
3152 entries_required
= DIV_ROUND_UP(entries_required
, G4X_FIFO_LINE_SIZE
);
3153 planeb_wm
= entries_required
+ planeb_params
.guard_size
;
3155 cursora_wm
= cursorb_wm
= 16;
3158 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
3160 /* Calc sr entries for one plane configs */
3161 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
3162 /* self-refresh has much higher latency */
3163 static const int sr_latency_ns
= 12000;
3165 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3166 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3168 /* Use ns/us then divide to preserve precision */
3169 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3170 pixel_size
* sr_hdisplay
;
3171 sr_entries
= DIV_ROUND_UP(sr_entries
, cacheline_size
);
3173 entries_required
= (((sr_latency_ns
/ line_time_us
) +
3174 1000) / 1000) * pixel_size
* 64;
3175 entries_required
= DIV_ROUND_UP(entries_required
,
3176 g4x_cursor_wm_info
.cacheline_size
);
3177 cursor_sr
= entries_required
+ g4x_cursor_wm_info
.guard_size
;
3179 if (cursor_sr
> g4x_cursor_wm_info
.max_wm
)
3180 cursor_sr
= g4x_cursor_wm_info
.max_wm
;
3181 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3182 "cursor %d\n", sr_entries
, cursor_sr
);
3184 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
3186 /* Turn off self refresh if both pipes are enabled */
3187 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3191 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3192 planea_wm
, planeb_wm
, sr_entries
);
3197 I915_WRITE(DSPFW1
, (sr_entries
<< DSPFW_SR_SHIFT
) |
3198 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
3199 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) | planea_wm
);
3200 I915_WRITE(DSPFW2
, (I915_READ(DSPFW2
) & DSPFW_CURSORA_MASK
) |
3201 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
3202 /* HPLL off in SR has some issues on G4x... disable it */
3203 I915_WRITE(DSPFW3
, (I915_READ(DSPFW3
) & ~DSPFW_HPLL_SR_EN
) |
3204 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
3207 static void i965_update_wm(struct drm_device
*dev
, int planea_clock
,
3208 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3211 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3212 unsigned long line_time_us
;
3213 int sr_clock
, sr_entries
, srwm
= 1;
3216 /* Calc sr entries for one plane configs */
3217 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
3218 /* self-refresh has much higher latency */
3219 static const int sr_latency_ns
= 12000;
3221 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3222 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3224 /* Use ns/us then divide to preserve precision */
3225 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3226 pixel_size
* sr_hdisplay
;
3227 sr_entries
= DIV_ROUND_UP(sr_entries
, I915_FIFO_LINE_SIZE
);
3228 DRM_DEBUG("self-refresh entries: %d\n", sr_entries
);
3229 srwm
= I965_FIFO_SIZE
- sr_entries
;
3234 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3236 sr_entries
= DIV_ROUND_UP(sr_entries
,
3237 i965_cursor_wm_info
.cacheline_size
);
3238 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
3239 (sr_entries
+ i965_cursor_wm_info
.guard_size
);
3241 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
3242 cursor_sr
= i965_cursor_wm_info
.max_wm
;
3244 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3245 "cursor %d\n", srwm
, cursor_sr
);
3247 if (IS_CRESTLINE(dev
))
3248 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
3250 /* Turn off self refresh if both pipes are enabled */
3251 if (IS_CRESTLINE(dev
))
3252 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3256 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3259 /* 965 has limitations... */
3260 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) | (8 << 16) | (8 << 8) |
3262 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
3263 /* update cursor SR watermark */
3264 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
3267 static void i9xx_update_wm(struct drm_device
*dev
, int planea_clock
,
3268 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3274 int total_size
, cacheline_size
, cwm
, srwm
= 1;
3275 int planea_wm
, planeb_wm
;
3276 struct intel_watermark_params planea_params
, planeb_params
;
3277 unsigned long line_time_us
;
3278 int sr_clock
, sr_entries
= 0;
3280 /* Create copies of the base settings for each pipe */
3281 if (IS_CRESTLINE(dev
) || IS_I945GM(dev
))
3282 planea_params
= planeb_params
= i945_wm_info
;
3283 else if (!IS_GEN2(dev
))
3284 planea_params
= planeb_params
= i915_wm_info
;
3286 planea_params
= planeb_params
= i855_wm_info
;
3288 /* Grab a couple of global values before we overwrite them */
3289 total_size
= planea_params
.fifo_size
;
3290 cacheline_size
= planea_params
.cacheline_size
;
3292 /* Update per-plane FIFO sizes */
3293 planea_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
3294 planeb_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
3296 planea_wm
= intel_calculate_wm(planea_clock
, &planea_params
,
3297 pixel_size
, latency_ns
);
3298 planeb_wm
= intel_calculate_wm(planeb_clock
, &planeb_params
,
3299 pixel_size
, latency_ns
);
3300 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
3303 * Overlay gets an aggressive default since video jitter is bad.
3307 /* Calc sr entries for one plane configs */
3308 if (HAS_FW_BLC(dev
) && sr_hdisplay
&&
3309 (!planea_clock
|| !planeb_clock
)) {
3310 /* self-refresh has much higher latency */
3311 static const int sr_latency_ns
= 6000;
3313 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3314 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3316 /* Use ns/us then divide to preserve precision */
3317 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3318 pixel_size
* sr_hdisplay
;
3319 sr_entries
= DIV_ROUND_UP(sr_entries
, cacheline_size
);
3320 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries
);
3321 srwm
= total_size
- sr_entries
;
3325 if (IS_I945G(dev
) || IS_I945GM(dev
))
3326 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
3327 else if (IS_I915GM(dev
)) {
3328 /* 915M has a smaller SRWM field */
3329 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
3330 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
3333 /* Turn off self refresh if both pipes are enabled */
3334 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
3335 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3337 } else if (IS_I915GM(dev
)) {
3338 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
3342 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3343 planea_wm
, planeb_wm
, cwm
, srwm
);
3345 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
3346 fwater_hi
= (cwm
& 0x1f);
3348 /* Set request length to 8 cachelines per fetch */
3349 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
3350 fwater_hi
= fwater_hi
| (1 << 8);
3352 I915_WRITE(FW_BLC
, fwater_lo
);
3353 I915_WRITE(FW_BLC2
, fwater_hi
);
3356 static void i830_update_wm(struct drm_device
*dev
, int planea_clock
, int unused
,
3357 int unused2
, int unused3
, int pixel_size
)
3359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3360 uint32_t fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
3363 i830_wm_info
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
3365 planea_wm
= intel_calculate_wm(planea_clock
, &i830_wm_info
,
3366 pixel_size
, latency_ns
);
3367 fwater_lo
|= (3<<8) | planea_wm
;
3369 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
3371 I915_WRITE(FW_BLC
, fwater_lo
);
3374 #define ILK_LP0_PLANE_LATENCY 700
3375 #define ILK_LP0_CURSOR_LATENCY 1300
3377 static bool ironlake_compute_wm0(struct drm_device
*dev
,
3382 struct drm_crtc
*crtc
;
3383 int htotal
, hdisplay
, clock
, pixel_size
= 0;
3384 int line_time_us
, line_count
, entries
;
3386 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
3387 if (crtc
->fb
== NULL
|| !crtc
->enabled
)
3390 htotal
= crtc
->mode
.htotal
;
3391 hdisplay
= crtc
->mode
.hdisplay
;
3392 clock
= crtc
->mode
.clock
;
3393 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3395 /* Use the small buffer method to calculate plane watermark */
3396 entries
= ((clock
* pixel_size
/ 1000) * ILK_LP0_PLANE_LATENCY
) / 1000;
3397 entries
= DIV_ROUND_UP(entries
,
3398 ironlake_display_wm_info
.cacheline_size
);
3399 *plane_wm
= entries
+ ironlake_display_wm_info
.guard_size
;
3400 if (*plane_wm
> (int)ironlake_display_wm_info
.max_wm
)
3401 *plane_wm
= ironlake_display_wm_info
.max_wm
;
3403 /* Use the large buffer method to calculate cursor watermark */
3404 line_time_us
= ((htotal
* 1000) / clock
);
3405 line_count
= (ILK_LP0_CURSOR_LATENCY
/ line_time_us
+ 1000) / 1000;
3406 entries
= line_count
* 64 * pixel_size
;
3407 entries
= DIV_ROUND_UP(entries
,
3408 ironlake_cursor_wm_info
.cacheline_size
);
3409 *cursor_wm
= entries
+ ironlake_cursor_wm_info
.guard_size
;
3410 if (*cursor_wm
> ironlake_cursor_wm_info
.max_wm
)
3411 *cursor_wm
= ironlake_cursor_wm_info
.max_wm
;
3416 static void ironlake_update_wm(struct drm_device
*dev
,
3417 int planea_clock
, int planeb_clock
,
3418 int sr_hdisplay
, int sr_htotal
,
3421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3422 int plane_wm
, cursor_wm
, enabled
;
3426 if (ironlake_compute_wm0(dev
, 0, &plane_wm
, &cursor_wm
)) {
3427 I915_WRITE(WM0_PIPEA_ILK
,
3428 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
3429 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3430 " plane %d, " "cursor: %d\n",
3431 plane_wm
, cursor_wm
);
3435 if (ironlake_compute_wm0(dev
, 1, &plane_wm
, &cursor_wm
)) {
3436 I915_WRITE(WM0_PIPEB_ILK
,
3437 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
3438 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3439 " plane %d, cursor: %d\n",
3440 plane_wm
, cursor_wm
);
3445 * Calculate and update the self-refresh watermark only when one
3446 * display plane is used.
3449 if (enabled
== 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3450 unsigned long line_time_us
;
3451 int small
, large
, plane_fbc
;
3452 int sr_clock
, entries
;
3453 int line_count
, line_size
;
3454 /* Read the self-refresh latency. The unit is 0.5us */
3455 int ilk_sr_latency
= I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
;
3457 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3458 line_time_us
= (sr_htotal
* 1000) / sr_clock
;
3460 /* Use ns/us then divide to preserve precision */
3461 line_count
= ((ilk_sr_latency
* 500) / line_time_us
+ 1000)
3463 line_size
= sr_hdisplay
* pixel_size
;
3465 /* Use the minimum of the small and large buffer method for primary */
3466 small
= ((sr_clock
* pixel_size
/ 1000) * (ilk_sr_latency
* 500)) / 1000;
3467 large
= line_count
* line_size
;
3469 entries
= DIV_ROUND_UP(min(small
, large
),
3470 ironlake_display_srwm_info
.cacheline_size
);
3472 plane_fbc
= entries
* 64;
3473 plane_fbc
= DIV_ROUND_UP(plane_fbc
, line_size
);
3475 plane_wm
= entries
+ ironlake_display_srwm_info
.guard_size
;
3476 if (plane_wm
> (int)ironlake_display_srwm_info
.max_wm
)
3477 plane_wm
= ironlake_display_srwm_info
.max_wm
;
3479 /* calculate the self-refresh watermark for display cursor */
3480 entries
= line_count
* pixel_size
* 64;
3481 entries
= DIV_ROUND_UP(entries
,
3482 ironlake_cursor_srwm_info
.cacheline_size
);
3484 cursor_wm
= entries
+ ironlake_cursor_srwm_info
.guard_size
;
3485 if (cursor_wm
> (int)ironlake_cursor_srwm_info
.max_wm
)
3486 cursor_wm
= ironlake_cursor_srwm_info
.max_wm
;
3488 /* configure watermark and enable self-refresh */
3489 tmp
= (WM1_LP_SR_EN
|
3490 (ilk_sr_latency
<< WM1_LP_LATENCY_SHIFT
) |
3491 (plane_fbc
<< WM1_LP_FBC_SHIFT
) |
3492 (plane_wm
<< WM1_LP_SR_SHIFT
) |
3494 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3495 " cursor %d\n", plane_wm
, plane_fbc
, cursor_wm
);
3497 I915_WRITE(WM1_LP_ILK
, tmp
);
3498 /* XXX setup WM2 and WM3 */
3502 * intel_update_watermarks - update FIFO watermark values based on current modes
3504 * Calculate watermark values for the various WM regs based on current mode
3505 * and plane configuration.
3507 * There are several cases to deal with here:
3508 * - normal (i.e. non-self-refresh)
3509 * - self-refresh (SR) mode
3510 * - lines are large relative to FIFO size (buffer can hold up to 2)
3511 * - lines are small relative to FIFO size (buffer can hold more than 2
3512 * lines), so need to account for TLB latency
3514 * The normal calculation is:
3515 * watermark = dotclock * bytes per pixel * latency
3516 * where latency is platform & configuration dependent (we assume pessimal
3519 * The SR calculation is:
3520 * watermark = (trunc(latency/line time)+1) * surface width *
3523 * line time = htotal / dotclock
3524 * surface width = hdisplay for normal plane and 64 for cursor
3525 * and latency is assumed to be high, as above.
3527 * The final value programmed to the register should always be rounded up,
3528 * and include an extra 2 entries to account for clock crossings.
3530 * We don't use the sprite, so we can ignore that. And on Crestline we have
3531 * to set the non-SR watermarks to 8.
3533 static void intel_update_watermarks(struct drm_device
*dev
)
3535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3536 struct drm_crtc
*crtc
;
3537 int sr_hdisplay
= 0;
3538 unsigned long planea_clock
= 0, planeb_clock
= 0, sr_clock
= 0;
3539 int enabled
= 0, pixel_size
= 0;
3542 if (!dev_priv
->display
.update_wm
)
3545 /* Get the clock config from both planes */
3546 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3547 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3548 if (intel_crtc
->active
) {
3550 if (intel_crtc
->plane
== 0) {
3551 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3552 intel_crtc
->pipe
, crtc
->mode
.clock
);
3553 planea_clock
= crtc
->mode
.clock
;
3555 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3556 intel_crtc
->pipe
, crtc
->mode
.clock
);
3557 planeb_clock
= crtc
->mode
.clock
;
3559 sr_hdisplay
= crtc
->mode
.hdisplay
;
3560 sr_clock
= crtc
->mode
.clock
;
3561 sr_htotal
= crtc
->mode
.htotal
;
3563 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3565 pixel_size
= 4; /* by default */
3572 dev_priv
->display
.update_wm(dev
, planea_clock
, planeb_clock
,
3573 sr_hdisplay
, sr_htotal
, pixel_size
);
3576 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
3577 struct drm_display_mode
*mode
,
3578 struct drm_display_mode
*adjusted_mode
,
3580 struct drm_framebuffer
*old_fb
)
3582 struct drm_device
*dev
= crtc
->dev
;
3583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3584 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3585 int pipe
= intel_crtc
->pipe
;
3586 int plane
= intel_crtc
->plane
;
3587 u32 fp_reg
, dpll_reg
;
3588 int refclk
, num_connectors
= 0;
3589 intel_clock_t clock
, reduced_clock
;
3590 u32 dpll
, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
3591 bool ok
, has_reduced_clock
= false, is_sdvo
= false, is_dvo
= false;
3592 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
3593 struct intel_encoder
*has_edp_encoder
= NULL
;
3594 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3595 struct intel_encoder
*encoder
;
3596 const intel_limit_t
*limit
;
3598 struct fdi_m_n m_n
= {0};
3602 drm_vblank_pre_modeset(dev
, pipe
);
3604 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
3605 if (encoder
->base
.crtc
!= crtc
)
3608 switch (encoder
->type
) {
3609 case INTEL_OUTPUT_LVDS
:
3612 case INTEL_OUTPUT_SDVO
:
3613 case INTEL_OUTPUT_HDMI
:
3615 if (encoder
->needs_tv_clock
)
3618 case INTEL_OUTPUT_DVO
:
3621 case INTEL_OUTPUT_TVOUT
:
3624 case INTEL_OUTPUT_ANALOG
:
3627 case INTEL_OUTPUT_DISPLAYPORT
:
3630 case INTEL_OUTPUT_EDP
:
3631 has_edp_encoder
= encoder
;
3638 if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_connectors
< 2) {
3639 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
3640 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3642 } else if (!IS_GEN2(dev
)) {
3644 if (HAS_PCH_SPLIT(dev
) &&
3645 (!has_edp_encoder
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
)))
3646 refclk
= 120000; /* 120Mhz refclk */
3652 * Returns a set of divisors for the desired target clock with the given
3653 * refclk, or FALSE. The returned values represent the clock equation:
3654 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3656 limit
= intel_limit(crtc
);
3657 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, &clock
);
3659 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3660 drm_vblank_post_modeset(dev
, pipe
);
3664 /* Ensure that the cursor is valid for the new mode before changing... */
3665 intel_crtc_update_cursor(crtc
, true);
3667 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
3668 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
3669 dev_priv
->lvds_downclock
,
3672 if (has_reduced_clock
&& (clock
.p
!= reduced_clock
.p
)) {
3674 * If the different P is found, it means that we can't
3675 * switch the display clock by using the FP0/FP1.
3676 * In such case we will disable the LVDS downclock
3679 DRM_DEBUG_KMS("Different P is found for "
3680 "LVDS clock/downclock\n");
3681 has_reduced_clock
= 0;
3684 /* SDVO TV has fixed PLL values depend on its clock range,
3685 this mirrors vbios setting. */
3686 if (is_sdvo
&& is_tv
) {
3687 if (adjusted_mode
->clock
>= 100000
3688 && adjusted_mode
->clock
< 140500) {
3694 } else if (adjusted_mode
->clock
>= 140500
3695 && adjusted_mode
->clock
<= 200000) {
3705 if (HAS_PCH_SPLIT(dev
)) {
3706 int lane
= 0, link_bw
, bpp
;
3707 /* CPU eDP doesn't require FDI link, so just set DP M/N
3708 according to current link config */
3709 if (has_edp_encoder
&& !intel_encoder_is_pch_edp(&encoder
->base
)) {
3710 target_clock
= mode
->clock
;
3711 intel_edp_link_config(has_edp_encoder
,
3714 /* [e]DP over FDI requires target mode clock
3715 instead of link clock */
3716 if (is_dp
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
))
3717 target_clock
= mode
->clock
;
3719 target_clock
= adjusted_mode
->clock
;
3721 /* FDI is a binary signal running at ~2.7GHz, encoding
3722 * each output octet as 10 bits. The actual frequency
3723 * is stored as a divider into a 100MHz clock, and the
3724 * mode pixel clock is stored in units of 1KHz.
3725 * Hence the bw of each lane in terms of the mode signal
3728 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
3731 /* determine panel color depth */
3732 temp
= I915_READ(PIPECONF(pipe
));
3733 temp
&= ~PIPE_BPC_MASK
;
3735 /* the BPC will be 6 if it is 18-bit LVDS panel */
3736 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) == LVDS_A3_POWER_UP
)
3740 } else if (has_edp_encoder
) {
3741 switch (dev_priv
->edp
.bpp
/3) {
3757 I915_WRITE(PIPECONF(pipe
), temp
);
3759 switch (temp
& PIPE_BPC_MASK
) {
3773 DRM_ERROR("unknown pipe bpc value\n");
3779 * Account for spread spectrum to avoid
3780 * oversubscribing the link. Max center spread
3781 * is 2.5%; use 5% for safety's sake.
3783 u32 bps
= target_clock
* bpp
* 21 / 20;
3784 lane
= bps
/ (link_bw
* 8) + 1;
3787 intel_crtc
->fdi_lanes
= lane
;
3789 ironlake_compute_m_n(bpp
, lane
, target_clock
, link_bw
, &m_n
);
3792 /* Ironlake: try to setup display ref clock before DPLL
3793 * enabling. This is only under driver's control after
3794 * PCH B stepping, previous chipset stepping should be
3795 * ignoring this setting.
3797 if (HAS_PCH_SPLIT(dev
)) {
3798 temp
= I915_READ(PCH_DREF_CONTROL
);
3799 /* Always enable nonspread source */
3800 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
3801 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
3802 temp
&= ~DREF_SSC_SOURCE_MASK
;
3803 temp
|= DREF_SSC_SOURCE_ENABLE
;
3804 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3806 POSTING_READ(PCH_DREF_CONTROL
);
3809 if (has_edp_encoder
) {
3810 if (dev_priv
->lvds_use_ssc
) {
3811 temp
|= DREF_SSC1_ENABLE
;
3812 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3814 POSTING_READ(PCH_DREF_CONTROL
);
3817 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
3819 /* Enable CPU source on CPU attached eDP */
3820 if (!intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
3821 if (dev_priv
->lvds_use_ssc
)
3822 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
3824 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
3826 /* Enable SSC on PCH eDP if needed */
3827 if (dev_priv
->lvds_use_ssc
) {
3828 DRM_ERROR("enabling SSC on PCH\n");
3829 temp
|= DREF_SUPERSPREAD_SOURCE_ENABLE
;
3832 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3833 POSTING_READ(PCH_DREF_CONTROL
);
3838 if (IS_PINEVIEW(dev
)) {
3839 fp
= (1 << clock
.n
) << 16 | clock
.m1
<< 8 | clock
.m2
;
3840 if (has_reduced_clock
)
3841 fp2
= (1 << reduced_clock
.n
) << 16 |
3842 reduced_clock
.m1
<< 8 | reduced_clock
.m2
;
3844 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
3845 if (has_reduced_clock
)
3846 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
3851 if (!HAS_PCH_SPLIT(dev
))
3852 dpll
= DPLL_VGA_MODE_DIS
;
3854 if (!IS_GEN2(dev
)) {
3856 dpll
|= DPLLB_MODE_LVDS
;
3858 dpll
|= DPLLB_MODE_DAC_SERIAL
;
3860 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
3861 if (pixel_multiplier
> 1) {
3862 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3863 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
3864 else if (HAS_PCH_SPLIT(dev
))
3865 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
3867 dpll
|= DPLL_DVO_HIGH_SPEED
;
3869 if (is_dp
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
))
3870 dpll
|= DPLL_DVO_HIGH_SPEED
;
3872 /* compute bitmask from p1 value */
3873 if (IS_PINEVIEW(dev
))
3874 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
3876 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3878 if (HAS_PCH_SPLIT(dev
))
3879 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3880 if (IS_G4X(dev
) && has_reduced_clock
)
3881 dpll
|= (1 << (reduced_clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3885 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
3888 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
3891 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
3894 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
3897 if (INTEL_INFO(dev
)->gen
>= 4 && !HAS_PCH_SPLIT(dev
))
3898 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
3901 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3904 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
3906 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3908 dpll
|= PLL_P2_DIVIDE_BY_4
;
3912 if (is_sdvo
&& is_tv
)
3913 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
3915 /* XXX: just matching BIOS for now */
3916 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3918 else if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_connectors
< 2)
3919 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
3921 dpll
|= PLL_REF_INPUT_DREFCLK
;
3923 /* setup pipeconf */
3924 pipeconf
= I915_READ(PIPECONF(pipe
));
3926 /* Set up the display plane register */
3927 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
3929 /* Ironlake's plane is forced to pipe, bit 24 is to
3930 enable color space conversion */
3931 if (!HAS_PCH_SPLIT(dev
)) {
3933 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
3935 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
3938 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
3939 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3942 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3946 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
3947 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
3949 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
3952 dspcntr
|= DISPLAY_PLANE_ENABLE
;
3953 pipeconf
|= PIPECONF_ENABLE
;
3954 dpll
|= DPLL_VCO_ENABLE
;
3956 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
3957 drm_mode_debug_printmodeline(mode
);
3959 /* assign to Ironlake registers */
3960 if (HAS_PCH_SPLIT(dev
)) {
3961 fp_reg
= PCH_FP0(pipe
);
3962 dpll_reg
= PCH_DPLL(pipe
);
3965 dpll_reg
= DPLL(pipe
);
3968 /* PCH eDP needs FDI, but CPU eDP does not */
3969 if (!has_edp_encoder
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
3970 I915_WRITE(fp_reg
, fp
);
3971 I915_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3973 POSTING_READ(dpll_reg
);
3977 /* enable transcoder DPLL */
3978 if (HAS_PCH_CPT(dev
)) {
3979 temp
= I915_READ(PCH_DPLL_SEL
);
3981 temp
|= TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
;
3983 temp
|= TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
;
3984 I915_WRITE(PCH_DPLL_SEL
, temp
);
3986 POSTING_READ(PCH_DPLL_SEL
);
3990 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3991 * This is an exception to the general rule that mode_set doesn't turn
3996 if (HAS_PCH_SPLIT(dev
))
3999 temp
= I915_READ(reg
);
4000 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
4002 if (HAS_PCH_CPT(dev
))
4003 temp
|= PORT_TRANS_B_SEL_CPT
;
4005 temp
|= LVDS_PIPEB_SELECT
;
4007 if (HAS_PCH_CPT(dev
))
4008 temp
&= ~PORT_TRANS_SEL_MASK
;
4010 temp
&= ~LVDS_PIPEB_SELECT
;
4012 /* set the corresponsding LVDS_BORDER bit */
4013 temp
|= dev_priv
->lvds_border_bits
;
4014 /* Set the B0-B3 data pairs corresponding to whether we're going to
4015 * set the DPLLs for dual-channel mode or not.
4018 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
4020 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
4022 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4023 * appropriately here, but we need to look more thoroughly into how
4024 * panels behave in the two modes.
4026 /* set the dithering flag on non-PCH LVDS as needed */
4027 if (INTEL_INFO(dev
)->gen
>= 4 && !HAS_PCH_SPLIT(dev
)) {
4028 if (dev_priv
->lvds_dither
)
4029 temp
|= LVDS_ENABLE_DITHER
;
4031 temp
&= ~LVDS_ENABLE_DITHER
;
4033 I915_WRITE(reg
, temp
);
4036 /* set the dithering flag and clear for anything other than a panel. */
4037 if (HAS_PCH_SPLIT(dev
)) {
4038 pipeconf
&= ~PIPECONF_DITHER_EN
;
4039 pipeconf
&= ~PIPECONF_DITHER_TYPE_MASK
;
4040 if (dev_priv
->lvds_dither
&& (is_lvds
|| has_edp_encoder
)) {
4041 pipeconf
|= PIPECONF_DITHER_EN
;
4042 pipeconf
|= PIPECONF_DITHER_TYPE_ST1
;
4046 if (is_dp
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
4047 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4048 } else if (HAS_PCH_SPLIT(dev
)) {
4049 /* For non-DP output, clear any trans DP clock recovery setting.*/
4051 I915_WRITE(TRANSA_DATA_M1
, 0);
4052 I915_WRITE(TRANSA_DATA_N1
, 0);
4053 I915_WRITE(TRANSA_DP_LINK_M1
, 0);
4054 I915_WRITE(TRANSA_DP_LINK_N1
, 0);
4056 I915_WRITE(TRANSB_DATA_M1
, 0);
4057 I915_WRITE(TRANSB_DATA_N1
, 0);
4058 I915_WRITE(TRANSB_DP_LINK_M1
, 0);
4059 I915_WRITE(TRANSB_DP_LINK_N1
, 0);
4063 if (!has_edp_encoder
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
4064 I915_WRITE(fp_reg
, fp
);
4065 I915_WRITE(dpll_reg
, dpll
);
4067 /* Wait for the clocks to stabilize. */
4068 POSTING_READ(dpll_reg
);
4071 if (INTEL_INFO(dev
)->gen
>= 4 && !HAS_PCH_SPLIT(dev
)) {
4074 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4076 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4080 I915_WRITE(DPLL_MD(pipe
), temp
);
4082 /* write it again -- the BIOS does, after all */
4083 I915_WRITE(dpll_reg
, dpll
);
4086 /* Wait for the clocks to stabilize. */
4087 POSTING_READ(dpll_reg
);
4091 intel_crtc
->lowfreq_avail
= false;
4092 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
4093 I915_WRITE(fp_reg
+ 4, fp2
);
4094 intel_crtc
->lowfreq_avail
= true;
4095 if (HAS_PIPE_CXSR(dev
)) {
4096 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4097 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4100 I915_WRITE(fp_reg
+ 4, fp
);
4101 if (HAS_PIPE_CXSR(dev
)) {
4102 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4103 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4107 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4108 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4109 /* the chip adds 2 halflines automatically */
4110 adjusted_mode
->crtc_vdisplay
-= 1;
4111 adjusted_mode
->crtc_vtotal
-= 1;
4112 adjusted_mode
->crtc_vblank_start
-= 1;
4113 adjusted_mode
->crtc_vblank_end
-= 1;
4114 adjusted_mode
->crtc_vsync_end
-= 1;
4115 adjusted_mode
->crtc_vsync_start
-= 1;
4117 pipeconf
&= ~PIPECONF_INTERLACE_W_FIELD_INDICATION
; /* progressive */
4119 I915_WRITE(HTOTAL(pipe
),
4120 (adjusted_mode
->crtc_hdisplay
- 1) |
4121 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4122 I915_WRITE(HBLANK(pipe
),
4123 (adjusted_mode
->crtc_hblank_start
- 1) |
4124 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4125 I915_WRITE(HSYNC(pipe
),
4126 (adjusted_mode
->crtc_hsync_start
- 1) |
4127 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4129 I915_WRITE(VTOTAL(pipe
),
4130 (adjusted_mode
->crtc_vdisplay
- 1) |
4131 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4132 I915_WRITE(VBLANK(pipe
),
4133 (adjusted_mode
->crtc_vblank_start
- 1) |
4134 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4135 I915_WRITE(VSYNC(pipe
),
4136 (adjusted_mode
->crtc_vsync_start
- 1) |
4137 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4139 /* pipesrc and dspsize control the size that is scaled from,
4140 * which should always be the user's requested size.
4142 if (!HAS_PCH_SPLIT(dev
)) {
4143 I915_WRITE(DSPSIZE(plane
),
4144 ((mode
->vdisplay
- 1) << 16) |
4145 (mode
->hdisplay
- 1));
4146 I915_WRITE(DSPPOS(plane
), 0);
4148 I915_WRITE(PIPESRC(pipe
),
4149 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4151 if (HAS_PCH_SPLIT(dev
)) {
4152 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
4153 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
4154 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
4155 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
4157 if (has_edp_encoder
&& !intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
4158 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
4162 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4163 POSTING_READ(PIPECONF(pipe
));
4165 intel_wait_for_vblank(dev
, pipe
);
4168 /* enable address swizzle for tiling buffer */
4169 temp
= I915_READ(DISP_ARB_CTL
);
4170 I915_WRITE(DISP_ARB_CTL
, temp
| DISP_TILE_SURFACE_SWIZZLING
);
4173 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4175 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
4177 intel_update_watermarks(dev
);
4179 drm_vblank_post_modeset(dev
, pipe
);
4184 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4185 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4187 struct drm_device
*dev
= crtc
->dev
;
4188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4189 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4190 int palreg
= (intel_crtc
->pipe
== 0) ? PALETTE_A
: PALETTE_B
;
4193 /* The clocks have to be on to load the palette. */
4197 /* use legacy palette for Ironlake */
4198 if (HAS_PCH_SPLIT(dev
))
4199 palreg
= (intel_crtc
->pipe
== 0) ? LGC_PALETTE_A
:
4202 for (i
= 0; i
< 256; i
++) {
4203 I915_WRITE(palreg
+ 4 * i
,
4204 (intel_crtc
->lut_r
[i
] << 16) |
4205 (intel_crtc
->lut_g
[i
] << 8) |
4206 intel_crtc
->lut_b
[i
]);
4210 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
4212 struct drm_device
*dev
= crtc
->dev
;
4213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4214 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4215 bool visible
= base
!= 0;
4218 if (intel_crtc
->cursor_visible
== visible
)
4221 cntl
= I915_READ(CURACNTR
);
4223 /* On these chipsets we can only modify the base whilst
4224 * the cursor is disabled.
4226 I915_WRITE(CURABASE
, base
);
4228 cntl
&= ~(CURSOR_FORMAT_MASK
);
4229 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4230 cntl
|= CURSOR_ENABLE
|
4231 CURSOR_GAMMA_ENABLE
|
4234 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
4235 I915_WRITE(CURACNTR
, cntl
);
4237 intel_crtc
->cursor_visible
= visible
;
4240 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
4242 struct drm_device
*dev
= crtc
->dev
;
4243 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4244 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4245 int pipe
= intel_crtc
->pipe
;
4246 bool visible
= base
!= 0;
4248 if (intel_crtc
->cursor_visible
!= visible
) {
4249 uint32_t cntl
= I915_READ(pipe
== 0 ? CURACNTR
: CURBCNTR
);
4251 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
4252 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
4253 cntl
|= pipe
<< 28; /* Connect to correct pipe */
4255 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
4256 cntl
|= CURSOR_MODE_DISABLE
;
4258 I915_WRITE(pipe
== 0 ? CURACNTR
: CURBCNTR
, cntl
);
4260 intel_crtc
->cursor_visible
= visible
;
4262 /* and commit changes on next vblank */
4263 I915_WRITE(pipe
== 0 ? CURABASE
: CURBBASE
, base
);
4266 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4267 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
4270 struct drm_device
*dev
= crtc
->dev
;
4271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4272 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4273 int pipe
= intel_crtc
->pipe
;
4274 int x
= intel_crtc
->cursor_x
;
4275 int y
= intel_crtc
->cursor_y
;
4281 if (on
&& crtc
->enabled
&& crtc
->fb
) {
4282 base
= intel_crtc
->cursor_addr
;
4283 if (x
> (int) crtc
->fb
->width
)
4286 if (y
> (int) crtc
->fb
->height
)
4292 if (x
+ intel_crtc
->cursor_width
< 0)
4295 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
4298 pos
|= x
<< CURSOR_X_SHIFT
;
4301 if (y
+ intel_crtc
->cursor_height
< 0)
4304 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
4307 pos
|= y
<< CURSOR_Y_SHIFT
;
4309 visible
= base
!= 0;
4310 if (!visible
&& !intel_crtc
->cursor_visible
)
4313 I915_WRITE(pipe
== 0 ? CURAPOS
: CURBPOS
, pos
);
4314 if (IS_845G(dev
) || IS_I865G(dev
))
4315 i845_update_cursor(crtc
, base
);
4317 i9xx_update_cursor(crtc
, base
);
4320 intel_mark_busy(dev
, to_intel_framebuffer(crtc
->fb
)->obj
);
4323 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
4324 struct drm_file
*file_priv
,
4326 uint32_t width
, uint32_t height
)
4328 struct drm_device
*dev
= crtc
->dev
;
4329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4330 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4331 struct drm_gem_object
*bo
;
4332 struct drm_i915_gem_object
*obj_priv
;
4336 DRM_DEBUG_KMS("\n");
4338 /* if we want to turn off the cursor ignore width and height */
4340 DRM_DEBUG_KMS("cursor off\n");
4343 mutex_lock(&dev
->struct_mutex
);
4347 /* Currently we only support 64x64 cursors */
4348 if (width
!= 64 || height
!= 64) {
4349 DRM_ERROR("we currently only support 64x64 cursors\n");
4353 bo
= drm_gem_object_lookup(dev
, file_priv
, handle
);
4357 obj_priv
= to_intel_bo(bo
);
4359 if (bo
->size
< width
* height
* 4) {
4360 DRM_ERROR("buffer is to small\n");
4365 /* we only need to pin inside GTT if cursor is non-phy */
4366 mutex_lock(&dev
->struct_mutex
);
4367 if (!dev_priv
->info
->cursor_needs_physical
) {
4368 ret
= i915_gem_object_pin(bo
, PAGE_SIZE
);
4370 DRM_ERROR("failed to pin cursor bo\n");
4374 ret
= i915_gem_object_set_to_gtt_domain(bo
, 0);
4376 DRM_ERROR("failed to move cursor bo into the GTT\n");
4380 addr
= obj_priv
->gtt_offset
;
4382 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
4383 ret
= i915_gem_attach_phys_object(dev
, bo
,
4384 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
4387 DRM_ERROR("failed to attach phys object\n");
4390 addr
= obj_priv
->phys_obj
->handle
->busaddr
;
4394 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
4397 if (intel_crtc
->cursor_bo
) {
4398 if (dev_priv
->info
->cursor_needs_physical
) {
4399 if (intel_crtc
->cursor_bo
!= bo
)
4400 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
4402 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
4403 drm_gem_object_unreference(intel_crtc
->cursor_bo
);
4406 mutex_unlock(&dev
->struct_mutex
);
4408 intel_crtc
->cursor_addr
= addr
;
4409 intel_crtc
->cursor_bo
= bo
;
4410 intel_crtc
->cursor_width
= width
;
4411 intel_crtc
->cursor_height
= height
;
4413 intel_crtc_update_cursor(crtc
, true);
4417 i915_gem_object_unpin(bo
);
4419 mutex_unlock(&dev
->struct_mutex
);
4421 drm_gem_object_unreference_unlocked(bo
);
4425 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
4427 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4429 intel_crtc
->cursor_x
= x
;
4430 intel_crtc
->cursor_y
= y
;
4432 intel_crtc_update_cursor(crtc
, true);
4437 /** Sets the color ramps on behalf of RandR */
4438 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
4439 u16 blue
, int regno
)
4441 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4443 intel_crtc
->lut_r
[regno
] = red
>> 8;
4444 intel_crtc
->lut_g
[regno
] = green
>> 8;
4445 intel_crtc
->lut_b
[regno
] = blue
>> 8;
4448 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
4449 u16
*blue
, int regno
)
4451 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4453 *red
= intel_crtc
->lut_r
[regno
] << 8;
4454 *green
= intel_crtc
->lut_g
[regno
] << 8;
4455 *blue
= intel_crtc
->lut_b
[regno
] << 8;
4458 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
4459 u16
*blue
, uint32_t start
, uint32_t size
)
4461 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
4462 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4464 for (i
= start
; i
< end
; i
++) {
4465 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
4466 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
4467 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
4470 intel_crtc_load_lut(crtc
);
4474 * Get a pipe with a simple mode set on it for doing load-based monitor
4477 * It will be up to the load-detect code to adjust the pipe as appropriate for
4478 * its requirements. The pipe will be connected to no other encoders.
4480 * Currently this code will only succeed if there is a pipe with no encoders
4481 * configured for it. In the future, it could choose to temporarily disable
4482 * some outputs to free up a pipe for its use.
4484 * \return crtc, or NULL if no pipes are available.
4487 /* VESA 640x480x72Hz mode to set on the pipe */
4488 static struct drm_display_mode load_detect_mode
= {
4489 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
4490 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
4493 struct drm_crtc
*intel_get_load_detect_pipe(struct intel_encoder
*intel_encoder
,
4494 struct drm_connector
*connector
,
4495 struct drm_display_mode
*mode
,
4498 struct intel_crtc
*intel_crtc
;
4499 struct drm_crtc
*possible_crtc
;
4500 struct drm_crtc
*supported_crtc
=NULL
;
4501 struct drm_encoder
*encoder
= &intel_encoder
->base
;
4502 struct drm_crtc
*crtc
= NULL
;
4503 struct drm_device
*dev
= encoder
->dev
;
4504 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
4505 struct drm_crtc_helper_funcs
*crtc_funcs
;
4509 * Algorithm gets a little messy:
4510 * - if the connector already has an assigned crtc, use it (but make
4511 * sure it's on first)
4512 * - try to find the first unused crtc that can drive this connector,
4513 * and use that if we find one
4514 * - if there are no unused crtcs available, try to use the first
4515 * one we found that supports the connector
4518 /* See if we already have a CRTC for this connector */
4519 if (encoder
->crtc
) {
4520 crtc
= encoder
->crtc
;
4521 /* Make sure the crtc and connector are running */
4522 intel_crtc
= to_intel_crtc(crtc
);
4523 *dpms_mode
= intel_crtc
->dpms_mode
;
4524 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
4525 crtc_funcs
= crtc
->helper_private
;
4526 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
4527 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
4532 /* Find an unused one (if possible) */
4533 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
4535 if (!(encoder
->possible_crtcs
& (1 << i
)))
4537 if (!possible_crtc
->enabled
) {
4538 crtc
= possible_crtc
;
4541 if (!supported_crtc
)
4542 supported_crtc
= possible_crtc
;
4546 * If we didn't find an unused CRTC, don't use any.
4552 encoder
->crtc
= crtc
;
4553 connector
->encoder
= encoder
;
4554 intel_encoder
->load_detect_temp
= true;
4556 intel_crtc
= to_intel_crtc(crtc
);
4557 *dpms_mode
= intel_crtc
->dpms_mode
;
4559 if (!crtc
->enabled
) {
4561 mode
= &load_detect_mode
;
4562 drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, crtc
->fb
);
4564 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
4565 crtc_funcs
= crtc
->helper_private
;
4566 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
4569 /* Add this connector to the crtc */
4570 encoder_funcs
->mode_set(encoder
, &crtc
->mode
, &crtc
->mode
);
4571 encoder_funcs
->commit(encoder
);
4573 /* let the connector get through one full cycle before testing */
4574 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
4579 void intel_release_load_detect_pipe(struct intel_encoder
*intel_encoder
,
4580 struct drm_connector
*connector
, int dpms_mode
)
4582 struct drm_encoder
*encoder
= &intel_encoder
->base
;
4583 struct drm_device
*dev
= encoder
->dev
;
4584 struct drm_crtc
*crtc
= encoder
->crtc
;
4585 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
4586 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
4588 if (intel_encoder
->load_detect_temp
) {
4589 encoder
->crtc
= NULL
;
4590 connector
->encoder
= NULL
;
4591 intel_encoder
->load_detect_temp
= false;
4592 crtc
->enabled
= drm_helper_crtc_in_use(crtc
);
4593 drm_helper_disable_unused_functions(dev
);
4596 /* Switch crtc and encoder back off if necessary */
4597 if (crtc
->enabled
&& dpms_mode
!= DRM_MODE_DPMS_ON
) {
4598 if (encoder
->crtc
== crtc
)
4599 encoder_funcs
->dpms(encoder
, dpms_mode
);
4600 crtc_funcs
->dpms(crtc
, dpms_mode
);
4604 /* Returns the clock of the currently programmed mode of the given pipe. */
4605 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
4607 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4608 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4609 int pipe
= intel_crtc
->pipe
;
4610 u32 dpll
= I915_READ((pipe
== 0) ? DPLL_A
: DPLL_B
);
4612 intel_clock_t clock
;
4614 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
4615 fp
= I915_READ((pipe
== 0) ? FPA0
: FPB0
);
4617 fp
= I915_READ((pipe
== 0) ? FPA1
: FPB1
);
4619 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
4620 if (IS_PINEVIEW(dev
)) {
4621 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
4622 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
4624 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
4625 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
4628 if (!IS_GEN2(dev
)) {
4629 if (IS_PINEVIEW(dev
))
4630 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
4631 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
4633 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
4634 DPLL_FPA01_P1_POST_DIV_SHIFT
);
4636 switch (dpll
& DPLL_MODE_MASK
) {
4637 case DPLLB_MODE_DAC_SERIAL
:
4638 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
4641 case DPLLB_MODE_LVDS
:
4642 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
4646 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4647 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
4651 /* XXX: Handle the 100Mhz refclk */
4652 intel_clock(dev
, 96000, &clock
);
4654 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
4657 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
4658 DPLL_FPA01_P1_POST_DIV_SHIFT
);
4661 if ((dpll
& PLL_REF_INPUT_MASK
) ==
4662 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
4663 /* XXX: might not be 66MHz */
4664 intel_clock(dev
, 66000, &clock
);
4666 intel_clock(dev
, 48000, &clock
);
4668 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
4671 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
4672 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
4674 if (dpll
& PLL_P2_DIVIDE_BY_4
)
4679 intel_clock(dev
, 48000, &clock
);
4683 /* XXX: It would be nice to validate the clocks, but we can't reuse
4684 * i830PllIsValid() because it relies on the xf86_config connector
4685 * configuration being accurate, which it isn't necessarily.
4691 /** Returns the currently programmed mode of the given pipe. */
4692 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
4693 struct drm_crtc
*crtc
)
4695 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4696 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4697 int pipe
= intel_crtc
->pipe
;
4698 struct drm_display_mode
*mode
;
4699 int htot
= I915_READ((pipe
== 0) ? HTOTAL_A
: HTOTAL_B
);
4700 int hsync
= I915_READ((pipe
== 0) ? HSYNC_A
: HSYNC_B
);
4701 int vtot
= I915_READ((pipe
== 0) ? VTOTAL_A
: VTOTAL_B
);
4702 int vsync
= I915_READ((pipe
== 0) ? VSYNC_A
: VSYNC_B
);
4704 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
4708 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
4709 mode
->hdisplay
= (htot
& 0xffff) + 1;
4710 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
4711 mode
->hsync_start
= (hsync
& 0xffff) + 1;
4712 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
4713 mode
->vdisplay
= (vtot
& 0xffff) + 1;
4714 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
4715 mode
->vsync_start
= (vsync
& 0xffff) + 1;
4716 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
4718 drm_mode_set_name(mode
);
4719 drm_mode_set_crtcinfo(mode
, 0);
4724 #define GPU_IDLE_TIMEOUT 500 /* ms */
4726 /* When this timer fires, we've been idle for awhile */
4727 static void intel_gpu_idle_timer(unsigned long arg
)
4729 struct drm_device
*dev
= (struct drm_device
*)arg
;
4730 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4732 dev_priv
->busy
= false;
4734 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
4737 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4739 static void intel_crtc_idle_timer(unsigned long arg
)
4741 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
4742 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4743 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
4745 intel_crtc
->busy
= false;
4747 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
4750 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
4752 struct drm_device
*dev
= crtc
->dev
;
4753 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4754 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4755 int pipe
= intel_crtc
->pipe
;
4756 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
4757 int dpll
= I915_READ(dpll_reg
);
4759 if (HAS_PCH_SPLIT(dev
))
4762 if (!dev_priv
->lvds_downclock_avail
)
4765 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
4766 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4768 /* Unlock panel regs */
4769 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) |
4772 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
4773 I915_WRITE(dpll_reg
, dpll
);
4774 dpll
= I915_READ(dpll_reg
);
4775 intel_wait_for_vblank(dev
, pipe
);
4776 dpll
= I915_READ(dpll_reg
);
4777 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
4778 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4780 /* ...and lock them again */
4781 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
4784 /* Schedule downclock */
4785 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
4786 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
4789 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
4791 struct drm_device
*dev
= crtc
->dev
;
4792 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4793 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4794 int pipe
= intel_crtc
->pipe
;
4795 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
4796 int dpll
= I915_READ(dpll_reg
);
4798 if (HAS_PCH_SPLIT(dev
))
4801 if (!dev_priv
->lvds_downclock_avail
)
4805 * Since this is called by a timer, we should never get here in
4808 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
4809 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4811 /* Unlock panel regs */
4812 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) |
4815 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
4816 I915_WRITE(dpll_reg
, dpll
);
4817 dpll
= I915_READ(dpll_reg
);
4818 intel_wait_for_vblank(dev
, pipe
);
4819 dpll
= I915_READ(dpll_reg
);
4820 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
4821 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4823 /* ...and lock them again */
4824 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
4830 * intel_idle_update - adjust clocks for idleness
4831 * @work: work struct
4833 * Either the GPU or display (or both) went idle. Check the busy status
4834 * here and adjust the CRTC and GPU clocks as necessary.
4836 static void intel_idle_update(struct work_struct
*work
)
4838 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
4840 struct drm_device
*dev
= dev_priv
->dev
;
4841 struct drm_crtc
*crtc
;
4842 struct intel_crtc
*intel_crtc
;
4845 if (!i915_powersave
)
4848 mutex_lock(&dev
->struct_mutex
);
4850 i915_update_gfx_val(dev_priv
);
4852 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4853 /* Skip inactive CRTCs */
4858 intel_crtc
= to_intel_crtc(crtc
);
4859 if (!intel_crtc
->busy
)
4860 intel_decrease_pllclock(crtc
);
4863 if ((enabled
== 1) && (IS_I945G(dev
) || IS_I945GM(dev
))) {
4864 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4865 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
4868 mutex_unlock(&dev
->struct_mutex
);
4872 * intel_mark_busy - mark the GPU and possibly the display busy
4874 * @obj: object we're operating on
4876 * Callers can use this function to indicate that the GPU is busy processing
4877 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4878 * buffer), we'll also mark the display as busy, so we know to increase its
4881 void intel_mark_busy(struct drm_device
*dev
, struct drm_gem_object
*obj
)
4883 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4884 struct drm_crtc
*crtc
= NULL
;
4885 struct intel_framebuffer
*intel_fb
;
4886 struct intel_crtc
*intel_crtc
;
4888 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4891 if (!dev_priv
->busy
) {
4892 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4895 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4896 fw_blc_self
= I915_READ(FW_BLC_SELF
);
4897 fw_blc_self
&= ~FW_BLC_SELF_EN
;
4898 I915_WRITE(FW_BLC_SELF
, fw_blc_self
| FW_BLC_SELF_EN_MASK
);
4900 dev_priv
->busy
= true;
4902 mod_timer(&dev_priv
->idle_timer
, jiffies
+
4903 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
4905 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4909 intel_crtc
= to_intel_crtc(crtc
);
4910 intel_fb
= to_intel_framebuffer(crtc
->fb
);
4911 if (intel_fb
->obj
== obj
) {
4912 if (!intel_crtc
->busy
) {
4913 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4916 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4917 fw_blc_self
= I915_READ(FW_BLC_SELF
);
4918 fw_blc_self
&= ~FW_BLC_SELF_EN
;
4919 I915_WRITE(FW_BLC_SELF
, fw_blc_self
| FW_BLC_SELF_EN_MASK
);
4921 /* Non-busy -> busy, upclock */
4922 intel_increase_pllclock(crtc
);
4923 intel_crtc
->busy
= true;
4925 /* Busy -> busy, put off timer */
4926 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
4927 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
4933 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
4935 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4936 struct drm_device
*dev
= crtc
->dev
;
4937 struct intel_unpin_work
*work
;
4938 unsigned long flags
;
4940 spin_lock_irqsave(&dev
->event_lock
, flags
);
4941 work
= intel_crtc
->unpin_work
;
4942 intel_crtc
->unpin_work
= NULL
;
4943 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4946 cancel_work_sync(&work
->work
);
4950 drm_crtc_cleanup(crtc
);
4955 static void intel_unpin_work_fn(struct work_struct
*__work
)
4957 struct intel_unpin_work
*work
=
4958 container_of(__work
, struct intel_unpin_work
, work
);
4960 mutex_lock(&work
->dev
->struct_mutex
);
4961 i915_gem_object_unpin(work
->old_fb_obj
);
4962 drm_gem_object_unreference(work
->pending_flip_obj
);
4963 drm_gem_object_unreference(work
->old_fb_obj
);
4964 mutex_unlock(&work
->dev
->struct_mutex
);
4968 static void do_intel_finish_page_flip(struct drm_device
*dev
,
4969 struct drm_crtc
*crtc
)
4971 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4972 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4973 struct intel_unpin_work
*work
;
4974 struct drm_i915_gem_object
*obj_priv
;
4975 struct drm_pending_vblank_event
*e
;
4977 unsigned long flags
;
4979 /* Ignore early vblank irqs */
4980 if (intel_crtc
== NULL
)
4983 spin_lock_irqsave(&dev
->event_lock
, flags
);
4984 work
= intel_crtc
->unpin_work
;
4985 if (work
== NULL
|| !work
->pending
) {
4986 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4990 intel_crtc
->unpin_work
= NULL
;
4991 drm_vblank_put(dev
, intel_crtc
->pipe
);
4995 do_gettimeofday(&now
);
4996 e
->event
.sequence
= drm_vblank_count(dev
, intel_crtc
->pipe
);
4997 e
->event
.tv_sec
= now
.tv_sec
;
4998 e
->event
.tv_usec
= now
.tv_usec
;
4999 list_add_tail(&e
->base
.link
,
5000 &e
->base
.file_priv
->event_list
);
5001 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
5004 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5006 obj_priv
= to_intel_bo(work
->old_fb_obj
);
5007 atomic_clear_mask(1 << intel_crtc
->plane
,
5008 &obj_priv
->pending_flip
.counter
);
5009 if (atomic_read(&obj_priv
->pending_flip
) == 0)
5010 wake_up(&dev_priv
->pending_flip_queue
);
5011 schedule_work(&work
->work
);
5013 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
5016 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
5018 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5019 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
5021 do_intel_finish_page_flip(dev
, crtc
);
5024 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
5026 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5027 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
5029 do_intel_finish_page_flip(dev
, crtc
);
5032 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
5034 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5035 struct intel_crtc
*intel_crtc
=
5036 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
5037 unsigned long flags
;
5039 spin_lock_irqsave(&dev
->event_lock
, flags
);
5040 if (intel_crtc
->unpin_work
) {
5041 if ((++intel_crtc
->unpin_work
->pending
) > 1)
5042 DRM_ERROR("Prepared flip multiple times\n");
5044 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5046 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5049 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
5050 struct drm_framebuffer
*fb
,
5051 struct drm_pending_vblank_event
*event
)
5053 struct drm_device
*dev
= crtc
->dev
;
5054 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5055 struct intel_framebuffer
*intel_fb
;
5056 struct drm_i915_gem_object
*obj_priv
;
5057 struct drm_gem_object
*obj
;
5058 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5059 struct intel_unpin_work
*work
;
5060 unsigned long flags
, offset
;
5061 int pipe
= intel_crtc
->pipe
;
5065 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
5069 work
->event
= event
;
5070 work
->dev
= crtc
->dev
;
5071 intel_fb
= to_intel_framebuffer(crtc
->fb
);
5072 work
->old_fb_obj
= intel_fb
->obj
;
5073 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
5075 /* We borrow the event spin lock for protecting unpin_work */
5076 spin_lock_irqsave(&dev
->event_lock
, flags
);
5077 if (intel_crtc
->unpin_work
) {
5078 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5081 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5084 intel_crtc
->unpin_work
= work
;
5085 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5087 intel_fb
= to_intel_framebuffer(fb
);
5088 obj
= intel_fb
->obj
;
5090 mutex_lock(&dev
->struct_mutex
);
5091 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, true);
5095 /* Reference the objects for the scheduled work. */
5096 drm_gem_object_reference(work
->old_fb_obj
);
5097 drm_gem_object_reference(obj
);
5101 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
5105 /* Block clients from rendering to the new back buffer until
5106 * the flip occurs and the object is no longer visible.
5108 atomic_add(1 << intel_crtc
->plane
,
5109 &to_intel_bo(work
->old_fb_obj
)->pending_flip
);
5111 work
->pending_flip_obj
= obj
;
5112 obj_priv
= to_intel_bo(obj
);
5114 if (IS_GEN3(dev
) || IS_GEN2(dev
)) {
5117 /* Can't queue multiple flips, so wait for the previous
5118 * one to finish before executing the next.
5121 if (intel_crtc
->plane
)
5122 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
5124 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
5125 OUT_RING(MI_WAIT_FOR_EVENT
| flip_mask
);
5130 work
->enable_stall_check
= true;
5132 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5133 offset
= crtc
->y
* fb
->pitch
+ crtc
->x
* fb
->bits_per_pixel
/8;
5136 switch(INTEL_INFO(dev
)->gen
) {
5138 OUT_RING(MI_DISPLAY_FLIP
|
5139 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5140 OUT_RING(fb
->pitch
);
5141 OUT_RING(obj_priv
->gtt_offset
+ offset
);
5146 OUT_RING(MI_DISPLAY_FLIP_I915
|
5147 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5148 OUT_RING(fb
->pitch
);
5149 OUT_RING(obj_priv
->gtt_offset
+ offset
);
5155 /* i965+ uses the linear or tiled offsets from the
5156 * Display Registers (which do not change across a page-flip)
5157 * so we need only reprogram the base address.
5159 OUT_RING(MI_DISPLAY_FLIP
|
5160 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5161 OUT_RING(fb
->pitch
);
5162 OUT_RING(obj_priv
->gtt_offset
| obj_priv
->tiling_mode
);
5164 /* XXX Enabling the panel-fitter across page-flip is so far
5165 * untested on non-native modes, so ignore it for now.
5166 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5169 pipesrc
= I915_READ(pipe
== 0 ? PIPEASRC
: PIPEBSRC
) & 0x0fff0fff;
5170 OUT_RING(pf
| pipesrc
);
5174 OUT_RING(MI_DISPLAY_FLIP
|
5175 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5176 OUT_RING(fb
->pitch
| obj_priv
->tiling_mode
);
5177 OUT_RING(obj_priv
->gtt_offset
);
5179 pf
= I915_READ(pipe
== 0 ? PFA_CTL_1
: PFB_CTL_1
) & PF_ENABLE
;
5180 pipesrc
= I915_READ(pipe
== 0 ? PIPEASRC
: PIPEBSRC
) & 0x0fff0fff;
5181 OUT_RING(pf
| pipesrc
);
5186 mutex_unlock(&dev
->struct_mutex
);
5188 trace_i915_flip_request(intel_crtc
->plane
, obj
);
5193 drm_gem_object_unreference(work
->old_fb_obj
);
5194 drm_gem_object_unreference(obj
);
5196 mutex_unlock(&dev
->struct_mutex
);
5198 spin_lock_irqsave(&dev
->event_lock
, flags
);
5199 intel_crtc
->unpin_work
= NULL
;
5200 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5207 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
5208 .dpms
= intel_crtc_dpms
,
5209 .mode_fixup
= intel_crtc_mode_fixup
,
5210 .mode_set
= intel_crtc_mode_set
,
5211 .mode_set_base
= intel_pipe_set_base
,
5212 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
5213 .load_lut
= intel_crtc_load_lut
,
5214 .disable
= intel_crtc_disable
,
5217 static const struct drm_crtc_funcs intel_crtc_funcs
= {
5218 .cursor_set
= intel_crtc_cursor_set
,
5219 .cursor_move
= intel_crtc_cursor_move
,
5220 .gamma_set
= intel_crtc_gamma_set
,
5221 .set_config
= drm_crtc_helper_set_config
,
5222 .destroy
= intel_crtc_destroy
,
5223 .page_flip
= intel_crtc_page_flip
,
5227 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
5229 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5230 struct intel_crtc
*intel_crtc
;
5233 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
5234 if (intel_crtc
== NULL
)
5237 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
5239 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
5240 for (i
= 0; i
< 256; i
++) {
5241 intel_crtc
->lut_r
[i
] = i
;
5242 intel_crtc
->lut_g
[i
] = i
;
5243 intel_crtc
->lut_b
[i
] = i
;
5246 /* Swap pipes & planes for FBC on pre-965 */
5247 intel_crtc
->pipe
= pipe
;
5248 intel_crtc
->plane
= pipe
;
5249 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
5250 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5251 intel_crtc
->plane
= !pipe
;
5254 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
5255 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
5256 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
5257 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
5259 intel_crtc
->cursor_addr
= 0;
5260 intel_crtc
->dpms_mode
= -1;
5261 intel_crtc
->active
= true; /* force the pipe off on setup_init_config */
5263 if (HAS_PCH_SPLIT(dev
)) {
5264 intel_helper_funcs
.prepare
= ironlake_crtc_prepare
;
5265 intel_helper_funcs
.commit
= ironlake_crtc_commit
;
5267 intel_helper_funcs
.prepare
= i9xx_crtc_prepare
;
5268 intel_helper_funcs
.commit
= i9xx_crtc_commit
;
5271 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
5273 intel_crtc
->busy
= false;
5275 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
5276 (unsigned long)intel_crtc
);
5279 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
5280 struct drm_file
*file_priv
)
5282 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5283 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
5284 struct drm_mode_object
*drmmode_obj
;
5285 struct intel_crtc
*crtc
;
5288 DRM_ERROR("called with no initialization\n");
5292 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
5293 DRM_MODE_OBJECT_CRTC
);
5296 DRM_ERROR("no such CRTC id\n");
5300 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
5301 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
5306 static int intel_encoder_clones(struct drm_device
*dev
, int type_mask
)
5308 struct intel_encoder
*encoder
;
5312 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
5313 if (type_mask
& encoder
->clone_mask
)
5314 index_mask
|= (1 << entry
);
5321 static void intel_setup_outputs(struct drm_device
*dev
)
5323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5324 struct intel_encoder
*encoder
;
5325 bool dpd_is_edp
= false;
5327 if (IS_MOBILE(dev
) && !IS_I830(dev
))
5328 intel_lvds_init(dev
);
5330 if (HAS_PCH_SPLIT(dev
)) {
5331 dpd_is_edp
= intel_dpd_is_edp(dev
);
5333 if (IS_MOBILE(dev
) && (I915_READ(DP_A
) & DP_DETECTED
))
5334 intel_dp_init(dev
, DP_A
);
5336 if (dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
5337 intel_dp_init(dev
, PCH_DP_D
);
5340 intel_crt_init(dev
);
5342 if (HAS_PCH_SPLIT(dev
)) {
5345 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
5346 /* PCH SDVOB multiplex with HDMIB */
5347 found
= intel_sdvo_init(dev
, PCH_SDVOB
);
5349 intel_hdmi_init(dev
, HDMIB
);
5350 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
5351 intel_dp_init(dev
, PCH_DP_B
);
5354 if (I915_READ(HDMIC
) & PORT_DETECTED
)
5355 intel_hdmi_init(dev
, HDMIC
);
5357 if (I915_READ(HDMID
) & PORT_DETECTED
)
5358 intel_hdmi_init(dev
, HDMID
);
5360 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
5361 intel_dp_init(dev
, PCH_DP_C
);
5363 if (!dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
5364 intel_dp_init(dev
, PCH_DP_D
);
5366 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
5369 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
5370 DRM_DEBUG_KMS("probing SDVOB\n");
5371 found
= intel_sdvo_init(dev
, SDVOB
);
5372 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
5373 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5374 intel_hdmi_init(dev
, SDVOB
);
5377 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
5378 DRM_DEBUG_KMS("probing DP_B\n");
5379 intel_dp_init(dev
, DP_B
);
5383 /* Before G4X SDVOC doesn't have its own detect register */
5385 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
5386 DRM_DEBUG_KMS("probing SDVOC\n");
5387 found
= intel_sdvo_init(dev
, SDVOC
);
5390 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
5392 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
5393 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5394 intel_hdmi_init(dev
, SDVOC
);
5396 if (SUPPORTS_INTEGRATED_DP(dev
)) {
5397 DRM_DEBUG_KMS("probing DP_C\n");
5398 intel_dp_init(dev
, DP_C
);
5402 if (SUPPORTS_INTEGRATED_DP(dev
) &&
5403 (I915_READ(DP_D
) & DP_DETECTED
)) {
5404 DRM_DEBUG_KMS("probing DP_D\n");
5405 intel_dp_init(dev
, DP_D
);
5407 } else if (IS_GEN2(dev
))
5408 intel_dvo_init(dev
);
5410 if (SUPPORTS_TV(dev
))
5413 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
5414 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
5415 encoder
->base
.possible_clones
=
5416 intel_encoder_clones(dev
, encoder
->clone_mask
);
5420 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
5422 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
5424 drm_framebuffer_cleanup(fb
);
5425 drm_gem_object_unreference_unlocked(intel_fb
->obj
);
5430 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
5431 struct drm_file
*file_priv
,
5432 unsigned int *handle
)
5434 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
5435 struct drm_gem_object
*object
= intel_fb
->obj
;
5437 return drm_gem_handle_create(file_priv
, object
, handle
);
5440 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
5441 .destroy
= intel_user_framebuffer_destroy
,
5442 .create_handle
= intel_user_framebuffer_create_handle
,
5445 int intel_framebuffer_init(struct drm_device
*dev
,
5446 struct intel_framebuffer
*intel_fb
,
5447 struct drm_mode_fb_cmd
*mode_cmd
,
5448 struct drm_gem_object
*obj
)
5450 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
5453 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
5456 if (mode_cmd
->pitch
& 63)
5459 switch (mode_cmd
->bpp
) {
5469 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
5471 DRM_ERROR("framebuffer init failed %d\n", ret
);
5475 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
5476 intel_fb
->obj
= obj
;
5480 static struct drm_framebuffer
*
5481 intel_user_framebuffer_create(struct drm_device
*dev
,
5482 struct drm_file
*filp
,
5483 struct drm_mode_fb_cmd
*mode_cmd
)
5485 struct drm_gem_object
*obj
;
5486 struct intel_framebuffer
*intel_fb
;
5489 obj
= drm_gem_object_lookup(dev
, filp
, mode_cmd
->handle
);
5491 return ERR_PTR(-ENOENT
);
5493 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
5495 return ERR_PTR(-ENOMEM
);
5497 ret
= intel_framebuffer_init(dev
, intel_fb
,
5500 drm_gem_object_unreference_unlocked(obj
);
5502 return ERR_PTR(ret
);
5505 return &intel_fb
->base
;
5508 static const struct drm_mode_config_funcs intel_mode_funcs
= {
5509 .fb_create
= intel_user_framebuffer_create
,
5510 .output_poll_changed
= intel_fb_output_poll_changed
,
5513 static struct drm_gem_object
*
5514 intel_alloc_context_page(struct drm_device
*dev
)
5516 struct drm_gem_object
*ctx
;
5519 ctx
= i915_gem_alloc_object(dev
, 4096);
5521 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5525 mutex_lock(&dev
->struct_mutex
);
5526 ret
= i915_gem_object_pin(ctx
, 4096);
5528 DRM_ERROR("failed to pin power context: %d\n", ret
);
5532 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
5534 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
5537 mutex_unlock(&dev
->struct_mutex
);
5542 i915_gem_object_unpin(ctx
);
5544 drm_gem_object_unreference(ctx
);
5545 mutex_unlock(&dev
->struct_mutex
);
5549 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
5551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5554 rgvswctl
= I915_READ16(MEMSWCTL
);
5555 if (rgvswctl
& MEMCTL_CMD_STS
) {
5556 DRM_DEBUG("gpu busy, RCS change rejected\n");
5557 return false; /* still busy with another command */
5560 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
5561 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
5562 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5563 POSTING_READ16(MEMSWCTL
);
5565 rgvswctl
|= MEMCTL_CMD_STS
;
5566 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5571 void ironlake_enable_drps(struct drm_device
*dev
)
5573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5574 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
5575 u8 fmax
, fmin
, fstart
, vstart
;
5577 /* Enable temp reporting */
5578 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
5579 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
5581 /* 100ms RC evaluation intervals */
5582 I915_WRITE(RCUPEI
, 100000);
5583 I915_WRITE(RCDNEI
, 100000);
5585 /* Set max/min thresholds to 90ms and 80ms respectively */
5586 I915_WRITE(RCBMAXAVG
, 90000);
5587 I915_WRITE(RCBMINAVG
, 80000);
5589 I915_WRITE(MEMIHYST
, 1);
5591 /* Set up min, max, and cur for interrupt handling */
5592 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
5593 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
5594 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
5595 MEMMODE_FSTART_SHIFT
;
5597 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
5600 dev_priv
->fmax
= fmax
; /* IPS callback will increase this */
5601 dev_priv
->fstart
= fstart
;
5603 dev_priv
->max_delay
= fstart
;
5604 dev_priv
->min_delay
= fmin
;
5605 dev_priv
->cur_delay
= fstart
;
5607 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5608 fmax
, fmin
, fstart
);
5610 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
5613 * Interrupts will be enabled in ironlake_irq_postinstall
5616 I915_WRITE(VIDSTART
, vstart
);
5617 POSTING_READ(VIDSTART
);
5619 rgvmodectl
|= MEMMODE_SWMODE_EN
;
5620 I915_WRITE(MEMMODECTL
, rgvmodectl
);
5622 if (wait_for((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
5623 DRM_ERROR("stuck trying to change perf mode\n");
5626 ironlake_set_drps(dev
, fstart
);
5628 dev_priv
->last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
5630 dev_priv
->last_time1
= jiffies_to_msecs(jiffies
);
5631 dev_priv
->last_count2
= I915_READ(0x112f4);
5632 getrawmonotonic(&dev_priv
->last_time2
);
5635 void ironlake_disable_drps(struct drm_device
*dev
)
5637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5638 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
5640 /* Ack interrupts, disable EFC interrupt */
5641 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
5642 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
5643 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
5644 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
5645 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
5647 /* Go back to the starting frequency */
5648 ironlake_set_drps(dev
, dev_priv
->fstart
);
5650 rgvswctl
|= MEMCTL_CMD_STS
;
5651 I915_WRITE(MEMSWCTL
, rgvswctl
);
5656 static unsigned long intel_pxfreq(u32 vidfreq
)
5659 int div
= (vidfreq
& 0x3f0000) >> 16;
5660 int post
= (vidfreq
& 0x3000) >> 12;
5661 int pre
= (vidfreq
& 0x7);
5666 freq
= ((div
* 133333) / ((1<<post
) * pre
));
5671 void intel_init_emon(struct drm_device
*dev
)
5673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5678 /* Disable to program */
5682 /* Program energy weights for various events */
5683 I915_WRITE(SDEW
, 0x15040d00);
5684 I915_WRITE(CSIEW0
, 0x007f0000);
5685 I915_WRITE(CSIEW1
, 0x1e220004);
5686 I915_WRITE(CSIEW2
, 0x04000004);
5688 for (i
= 0; i
< 5; i
++)
5689 I915_WRITE(PEW
+ (i
* 4), 0);
5690 for (i
= 0; i
< 3; i
++)
5691 I915_WRITE(DEW
+ (i
* 4), 0);
5693 /* Program P-state weights to account for frequency power adjustment */
5694 for (i
= 0; i
< 16; i
++) {
5695 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
5696 unsigned long freq
= intel_pxfreq(pxvidfreq
);
5697 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
5702 val
*= (freq
/ 1000);
5704 val
/= (127*127*900);
5706 DRM_ERROR("bad pxval: %ld\n", val
);
5709 /* Render standby states get 0 weight */
5713 for (i
= 0; i
< 4; i
++) {
5714 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
5715 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
5716 I915_WRITE(PXW
+ (i
* 4), val
);
5719 /* Adjust magic regs to magic values (more experimental results) */
5720 I915_WRITE(OGW0
, 0);
5721 I915_WRITE(OGW1
, 0);
5722 I915_WRITE(EG0
, 0x00007f00);
5723 I915_WRITE(EG1
, 0x0000000e);
5724 I915_WRITE(EG2
, 0x000e0000);
5725 I915_WRITE(EG3
, 0x68000300);
5726 I915_WRITE(EG4
, 0x42000000);
5727 I915_WRITE(EG5
, 0x00140031);
5731 for (i
= 0; i
< 8; i
++)
5732 I915_WRITE(PXWL
+ (i
* 4), 0);
5734 /* Enable PMON + select events */
5735 I915_WRITE(ECR
, 0x80000019);
5737 lcfuse
= I915_READ(LCFUSE02
);
5739 dev_priv
->corr
= (lcfuse
& LCFUSE_HIV_MASK
);
5742 void intel_init_clock_gating(struct drm_device
*dev
)
5744 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5747 * Disable clock gating reported to work incorrectly according to the
5748 * specs, but enable as much else as we can.
5750 if (HAS_PCH_SPLIT(dev
)) {
5751 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
5754 /* Required for FBC */
5755 dspclk_gate
|= DPFDUNIT_CLOCK_GATE_DISABLE
;
5756 /* Required for CxSR */
5757 dspclk_gate
|= DPARBUNIT_CLOCK_GATE_DISABLE
;
5759 I915_WRITE(PCH_3DCGDIS0
,
5760 MARIUNIT_CLOCK_GATE_DISABLE
|
5761 SVSMUNIT_CLOCK_GATE_DISABLE
);
5764 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
5767 * On Ibex Peak and Cougar Point, we need to disable clock
5768 * gating for the panel power sequencer or it will fail to
5769 * start up when no ports are active.
5771 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
5774 * According to the spec the following bits should be set in
5775 * order to enable memory self-refresh
5776 * The bit 22/21 of 0x42004
5777 * The bit 5 of 0x42020
5778 * The bit 15 of 0x45000
5781 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5782 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
5783 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
5784 I915_WRITE(ILK_DSPCLK_GATE
,
5785 (I915_READ(ILK_DSPCLK_GATE
) |
5786 ILK_DPARB_CLK_GATE
));
5787 I915_WRITE(DISP_ARB_CTL
,
5788 (I915_READ(DISP_ARB_CTL
) |
5790 I915_WRITE(WM3_LP_ILK
, 0);
5791 I915_WRITE(WM2_LP_ILK
, 0);
5792 I915_WRITE(WM1_LP_ILK
, 0);
5795 * Based on the document from hardware guys the following bits
5796 * should be set unconditionally in order to enable FBC.
5797 * The bit 22 of 0x42000
5798 * The bit 22 of 0x42004
5799 * The bit 7,8,9 of 0x42020.
5801 if (IS_IRONLAKE_M(dev
)) {
5802 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5803 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5805 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5806 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5808 I915_WRITE(ILK_DSPCLK_GATE
,
5809 I915_READ(ILK_DSPCLK_GATE
) |
5815 } else if (IS_G4X(dev
)) {
5816 uint32_t dspclk_gate
;
5817 I915_WRITE(RENCLK_GATE_D1
, 0);
5818 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
5819 GS_UNIT_CLOCK_GATE_DISABLE
|
5820 CL_UNIT_CLOCK_GATE_DISABLE
);
5821 I915_WRITE(RAMCLK_GATE_D
, 0);
5822 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
5823 OVRUNIT_CLOCK_GATE_DISABLE
|
5824 OVCUNIT_CLOCK_GATE_DISABLE
;
5826 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
5827 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
5828 } else if (IS_CRESTLINE(dev
)) {
5829 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
5830 I915_WRITE(RENCLK_GATE_D2
, 0);
5831 I915_WRITE(DSPCLK_GATE_D
, 0);
5832 I915_WRITE(RAMCLK_GATE_D
, 0);
5833 I915_WRITE16(DEUC
, 0);
5834 } else if (IS_BROADWATER(dev
)) {
5835 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
5836 I965_RCC_CLOCK_GATE_DISABLE
|
5837 I965_RCPB_CLOCK_GATE_DISABLE
|
5838 I965_ISC_CLOCK_GATE_DISABLE
|
5839 I965_FBC_CLOCK_GATE_DISABLE
);
5840 I915_WRITE(RENCLK_GATE_D2
, 0);
5841 } else if (IS_GEN3(dev
)) {
5842 u32 dstate
= I915_READ(D_STATE
);
5844 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
5845 DSTATE_DOT_CLOCK_GATING
;
5846 I915_WRITE(D_STATE
, dstate
);
5847 } else if (IS_I85X(dev
) || IS_I865G(dev
)) {
5848 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
5849 } else if (IS_I830(dev
)) {
5850 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
5854 * GPU can automatically power down the render unit if given a page
5857 if (IS_IRONLAKE_M(dev
)) {
5858 if (dev_priv
->renderctx
== NULL
)
5859 dev_priv
->renderctx
= intel_alloc_context_page(dev
);
5860 if (dev_priv
->renderctx
) {
5861 struct drm_i915_gem_object
*obj_priv
;
5862 obj_priv
= to_intel_bo(dev_priv
->renderctx
);
5865 OUT_RING(MI_SET_CONTEXT
);
5866 OUT_RING(obj_priv
->gtt_offset
|
5868 MI_SAVE_EXT_STATE_EN
|
5869 MI_RESTORE_EXT_STATE_EN
|
5870 MI_RESTORE_INHIBIT
);
5876 DRM_DEBUG_KMS("Failed to allocate render context."
5880 if (I915_HAS_RC6(dev
) && drm_core_check_feature(dev
, DRIVER_MODESET
)) {
5881 struct drm_i915_gem_object
*obj_priv
= NULL
;
5883 if (dev_priv
->pwrctx
) {
5884 obj_priv
= to_intel_bo(dev_priv
->pwrctx
);
5886 struct drm_gem_object
*pwrctx
;
5888 pwrctx
= intel_alloc_context_page(dev
);
5890 dev_priv
->pwrctx
= pwrctx
;
5891 obj_priv
= to_intel_bo(pwrctx
);
5896 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
| PWRCTX_EN
);
5897 I915_WRITE(MCHBAR_RENDER_STANDBY
,
5898 I915_READ(MCHBAR_RENDER_STANDBY
) & ~RCX_SW_EXIT
);
5903 /* Set up chip specific display functions */
5904 static void intel_init_display(struct drm_device
*dev
)
5906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5908 /* We always want a DPMS function */
5909 if (HAS_PCH_SPLIT(dev
))
5910 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
5912 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
5914 if (I915_HAS_FBC(dev
)) {
5915 if (IS_IRONLAKE_M(dev
)) {
5916 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
5917 dev_priv
->display
.enable_fbc
= ironlake_enable_fbc
;
5918 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
5919 } else if (IS_GM45(dev
)) {
5920 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
5921 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
5922 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
5923 } else if (IS_CRESTLINE(dev
)) {
5924 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
5925 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
5926 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
5928 /* 855GM needs testing */
5931 /* Returns the core display clock speed */
5932 if (IS_I945G(dev
) || (IS_G33(dev
) && ! IS_PINEVIEW_M(dev
)))
5933 dev_priv
->display
.get_display_clock_speed
=
5934 i945_get_display_clock_speed
;
5935 else if (IS_I915G(dev
))
5936 dev_priv
->display
.get_display_clock_speed
=
5937 i915_get_display_clock_speed
;
5938 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
5939 dev_priv
->display
.get_display_clock_speed
=
5940 i9xx_misc_get_display_clock_speed
;
5941 else if (IS_I915GM(dev
))
5942 dev_priv
->display
.get_display_clock_speed
=
5943 i915gm_get_display_clock_speed
;
5944 else if (IS_I865G(dev
))
5945 dev_priv
->display
.get_display_clock_speed
=
5946 i865_get_display_clock_speed
;
5947 else if (IS_I85X(dev
))
5948 dev_priv
->display
.get_display_clock_speed
=
5949 i855_get_display_clock_speed
;
5951 dev_priv
->display
.get_display_clock_speed
=
5952 i830_get_display_clock_speed
;
5954 /* For FIFO watermark updates */
5955 if (HAS_PCH_SPLIT(dev
)) {
5957 if (I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
)
5958 dev_priv
->display
.update_wm
= ironlake_update_wm
;
5960 DRM_DEBUG_KMS("Failed to get proper latency. "
5962 dev_priv
->display
.update_wm
= NULL
;
5965 dev_priv
->display
.update_wm
= NULL
;
5966 } else if (IS_PINEVIEW(dev
)) {
5967 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
5970 dev_priv
->mem_freq
)) {
5971 DRM_INFO("failed to find known CxSR latency "
5972 "(found ddr%s fsb freq %d, mem freq %d), "
5974 (dev_priv
->is_ddr3
== 1) ? "3": "2",
5975 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
5976 /* Disable CxSR and never update its watermark again */
5977 pineview_disable_cxsr(dev
);
5978 dev_priv
->display
.update_wm
= NULL
;
5980 dev_priv
->display
.update_wm
= pineview_update_wm
;
5981 } else if (IS_G4X(dev
))
5982 dev_priv
->display
.update_wm
= g4x_update_wm
;
5983 else if (IS_GEN4(dev
))
5984 dev_priv
->display
.update_wm
= i965_update_wm
;
5985 else if (IS_GEN3(dev
)) {
5986 dev_priv
->display
.update_wm
= i9xx_update_wm
;
5987 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
5988 } else if (IS_I85X(dev
)) {
5989 dev_priv
->display
.update_wm
= i9xx_update_wm
;
5990 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
5992 dev_priv
->display
.update_wm
= i830_update_wm
;
5994 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
5996 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
6001 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6002 * resume, or other times. This quirk makes sure that's the case for
6005 static void quirk_pipea_force (struct drm_device
*dev
)
6007 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6009 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
6010 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6013 struct intel_quirk
{
6015 int subsystem_vendor
;
6016 int subsystem_device
;
6017 void (*hook
)(struct drm_device
*dev
);
6020 struct intel_quirk intel_quirks
[] = {
6021 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6022 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force
},
6023 /* HP Mini needs pipe A force quirk (LP: #322104) */
6024 { 0x27ae,0x103c, 0x361a, quirk_pipea_force
},
6026 /* Thinkpad R31 needs pipe A force quirk */
6027 { 0x3577, 0x1014, 0x0505, quirk_pipea_force
},
6028 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6029 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
6031 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6032 { 0x3577, 0x1014, 0x0513, quirk_pipea_force
},
6033 /* ThinkPad X40 needs pipe A force quirk */
6035 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6036 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
6038 /* 855 & before need to leave pipe A & dpll A up */
6039 { 0x3582, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
6040 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
6043 static void intel_init_quirks(struct drm_device
*dev
)
6045 struct pci_dev
*d
= dev
->pdev
;
6048 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
6049 struct intel_quirk
*q
= &intel_quirks
[i
];
6051 if (d
->device
== q
->device
&&
6052 (d
->subsystem_vendor
== q
->subsystem_vendor
||
6053 q
->subsystem_vendor
== PCI_ANY_ID
) &&
6054 (d
->subsystem_device
== q
->subsystem_device
||
6055 q
->subsystem_device
== PCI_ANY_ID
))
6060 /* Disable the VGA plane that we never use */
6061 static void i915_disable_vga(struct drm_device
*dev
)
6063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6067 if (HAS_PCH_SPLIT(dev
))
6068 vga_reg
= CPU_VGACNTRL
;
6072 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
6073 outb(1, VGA_SR_INDEX
);
6074 sr1
= inb(VGA_SR_DATA
);
6075 outb(sr1
| 1<<5, VGA_SR_DATA
);
6076 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
6079 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
6080 POSTING_READ(vga_reg
);
6083 void intel_modeset_init(struct drm_device
*dev
)
6085 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6088 drm_mode_config_init(dev
);
6090 dev
->mode_config
.min_width
= 0;
6091 dev
->mode_config
.min_height
= 0;
6093 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
6095 intel_init_quirks(dev
);
6097 intel_init_display(dev
);
6100 dev
->mode_config
.max_width
= 2048;
6101 dev
->mode_config
.max_height
= 2048;
6102 } else if (IS_GEN3(dev
)) {
6103 dev
->mode_config
.max_width
= 4096;
6104 dev
->mode_config
.max_height
= 4096;
6106 dev
->mode_config
.max_width
= 8192;
6107 dev
->mode_config
.max_height
= 8192;
6110 /* set memory base */
6112 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 0);
6114 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 2);
6116 if (IS_MOBILE(dev
) || !IS_GEN2(dev
))
6117 dev_priv
->num_pipe
= 2;
6119 dev_priv
->num_pipe
= 1;
6120 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6121 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
6123 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
6124 intel_crtc_init(dev
, i
);
6127 intel_setup_outputs(dev
);
6129 intel_init_clock_gating(dev
);
6131 /* Just disable it once at startup */
6132 i915_disable_vga(dev
);
6134 if (IS_IRONLAKE_M(dev
)) {
6135 ironlake_enable_drps(dev
);
6136 intel_init_emon(dev
);
6139 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
6140 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
6141 (unsigned long)dev
);
6143 intel_setup_overlay(dev
);
6146 void intel_modeset_cleanup(struct drm_device
*dev
)
6148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6149 struct drm_crtc
*crtc
;
6150 struct intel_crtc
*intel_crtc
;
6152 drm_kms_helper_poll_fini(dev
);
6153 mutex_lock(&dev
->struct_mutex
);
6155 intel_unregister_dsm_handler();
6158 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6159 /* Skip inactive CRTCs */
6163 intel_crtc
= to_intel_crtc(crtc
);
6164 intel_increase_pllclock(crtc
);
6167 if (dev_priv
->display
.disable_fbc
)
6168 dev_priv
->display
.disable_fbc(dev
);
6170 if (dev_priv
->renderctx
) {
6171 struct drm_i915_gem_object
*obj_priv
;
6173 obj_priv
= to_intel_bo(dev_priv
->renderctx
);
6174 I915_WRITE(CCID
, obj_priv
->gtt_offset
&~ CCID_EN
);
6176 i915_gem_object_unpin(dev_priv
->renderctx
);
6177 drm_gem_object_unreference(dev_priv
->renderctx
);
6180 if (dev_priv
->pwrctx
) {
6181 struct drm_i915_gem_object
*obj_priv
;
6183 obj_priv
= to_intel_bo(dev_priv
->pwrctx
);
6184 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
&~ PWRCTX_EN
);
6186 i915_gem_object_unpin(dev_priv
->pwrctx
);
6187 drm_gem_object_unreference(dev_priv
->pwrctx
);
6190 if (IS_IRONLAKE_M(dev
))
6191 ironlake_disable_drps(dev
);
6193 mutex_unlock(&dev
->struct_mutex
);
6195 /* Disable the irq before mode object teardown, for the irq might
6196 * enqueue unpin/hotplug work. */
6197 drm_irq_uninstall(dev
);
6198 cancel_work_sync(&dev_priv
->hotplug_work
);
6200 /* Shut off idle work before the crtcs get freed. */
6201 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6202 intel_crtc
= to_intel_crtc(crtc
);
6203 del_timer_sync(&intel_crtc
->idle_timer
);
6205 del_timer_sync(&dev_priv
->idle_timer
);
6206 cancel_work_sync(&dev_priv
->idle_work
);
6208 drm_mode_config_cleanup(dev
);
6212 * Return which encoder is currently attached for connector.
6214 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
6216 return &intel_attached_encoder(connector
)->base
;
6219 void intel_connector_attach_encoder(struct intel_connector
*connector
,
6220 struct intel_encoder
*encoder
)
6222 connector
->encoder
= encoder
;
6223 drm_mode_connector_attach_encoder(&connector
->base
,
6228 * set vga decode state - true == enable VGA decode
6230 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
6232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6235 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
6237 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
6239 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
6240 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);