include/drm/i915_drm.h

   1 /*
   2  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  20  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #ifndef _I915_DRM_H_
  28 #define _I915_DRM_H_
  29
  30 /* Please note that modifications to all structs defined here are
  31  * subject to backwards-compatibility constraints.
  32  */
  33
  34 #include "drm.h"
  35
  36 /* Each region is a minimum of 16k, and there are at most 255 of them.
  37  */
  38 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
  39                                  * of chars for next/prev indices */
  40 #define I915_LOG_MIN_TEX_REGION_SIZE 14
  41
  42 typedef struct _drm_i915_init {
  43         enum {
  44                 I915_INIT_DMA = 0x01,
  45                 I915_CLEANUP_DMA = 0x02,
  46                 I915_RESUME_DMA = 0x03
  47         } func;
  48         unsigned int mmio_offset;
  49         int sarea_priv_offset;
  50         unsigned int ring_start;
  51         unsigned int ring_end;
  52         unsigned int ring_size;
  53         unsigned int front_offset;
  54         unsigned int back_offset;
  55         unsigned int depth_offset;
  56         unsigned int w;
  57         unsigned int h;
  58         unsigned int pitch;
  59         unsigned int pitch_bits;
  60         unsigned int back_pitch;
  61         unsigned int depth_pitch;
  62         unsigned int cpp;
  63         unsigned int chipset;
  64 } drm_i915_init_t;
  65
  66 typedef struct _drm_i915_sarea {
  67         struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
  68         int last_upload;        /* last time texture was uploaded */
  69         int last_enqueue;       /* last time a buffer was enqueued */
  70         int last_dispatch;      /* age of the most recently dispatched buffer */
  71         int ctxOwner;           /* last context to upload state */
  72         int texAge;
  73         int pf_enabled;         /* is pageflipping allowed? */
  74         int pf_active;
  75         int pf_current_page;    /* which buffer is being displayed? */
  76         int perf_boxes;         /* performance boxes to be displayed */
  77         int width, height;      /* screen size in pixels */
  78
  79         drm_handle_t front_handle;
  80         int front_offset;
  81         int front_size;
  82
  83         drm_handle_t back_handle;
  84         int back_offset;
  85         int back_size;
  86
  87         drm_handle_t depth_handle;
  88         int depth_offset;
  89         int depth_size;
  90
  91         drm_handle_t tex_handle;
  92         int tex_offset;
  93         int tex_size;
  94         int log_tex_granularity;
  95         int pitch;
  96         int rotation;           /* 0, 90, 180 or 270 */
  97         int rotated_offset;
  98         int rotated_size;
  99         int rotated_pitch;
 100         int virtualX, virtualY;
 101
 102         unsigned int front_tiled;
 103         unsigned int back_tiled;
 104         unsigned int depth_tiled;
 105         unsigned int rotated_tiled;
 106         unsigned int rotated2_tiled;
 107
 108         int pipeA_x;
 109         int pipeA_y;
 110         int pipeA_w;
 111         int pipeA_h;
 112         int pipeB_x;
 113         int pipeB_y;
 114         int pipeB_w;
 115         int pipeB_h;
 116 } drm_i915_sarea_t;
 117
 118 /* Flags for perf_boxes
 119  */
 120 #define I915_BOX_RING_EMPTY    0x1
 121 #define I915_BOX_FLIP          0x2
 122 #define I915_BOX_WAIT          0x4
 123 #define I915_BOX_TEXTURE_LOAD  0x8
 124 #define I915_BOX_LOST_CONTEXT  0x10
 125
 126 /* I915 specific ioctls
 127  * The device specific ioctl range is 0x40 to 0x79.
 128  */
 129 #define DRM_I915_INIT           0x00
 130 #define DRM_I915_FLUSH          0x01
 131 #define DRM_I915_FLIP           0x02
 132 #define DRM_I915_BATCHBUFFER    0x03
 133 #define DRM_I915_IRQ_EMIT       0x04
 134 #define DRM_I915_IRQ_WAIT       0x05
 135 #define DRM_I915_GETPARAM       0x06
 136 #define DRM_I915_SETPARAM       0x07
 137 #define DRM_I915_ALLOC          0x08
 138 #define DRM_I915_FREE           0x09
 139 #define DRM_I915_INIT_HEAP      0x0a
 140 #define DRM_I915_CMDBUFFER      0x0b
 141 #define DRM_I915_DESTROY_HEAP   0x0c
 142 #define DRM_I915_SET_VBLANK_PIPE        0x0d
 143 #define DRM_I915_GET_VBLANK_PIPE        0x0e
 144 #define DRM_I915_VBLANK_SWAP    0x0f
 145 #define DRM_I915_HWS_ADDR       0x11
 146
 147 #define DRM_IOCTL_I915_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 148 #define DRM_IOCTL_I915_FLUSH            DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
 149 #define DRM_IOCTL_I915_FLIP             DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
 150 #define DRM_IOCTL_I915_BATCHBUFFER      DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
 151 #define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
 152 #define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
 153 #define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
 154 #define DRM_IOCTL_I915_SETPARAM         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
 155 #define DRM_IOCTL_I915_ALLOC            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
 156 #define DRM_IOCTL_I915_FREE             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
 157 #define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
 158 #define DRM_IOCTL_I915_CMDBUFFER        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
 159 #define DRM_IOCTL_I915_DESTROY_HEAP     DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
 160 #define DRM_IOCTL_I915_SET_VBLANK_PIPE  DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 161 #define DRM_IOCTL_I915_GET_VBLANK_PIPE  DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 162 #define DRM_IOCTL_I915_VBLANK_SWAP      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
 163
 164 /* Allow drivers to submit batchbuffers directly to hardware, relying
 165  * on the security mechanisms provided by hardware.
 166  */
 167 typedef struct _drm_i915_batchbuffer {
 168         int start;              /* agp offset */
 169         int used;               /* nr bytes in use */
 170         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 171         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
 172         int num_cliprects;      /* mulitpass with multiple cliprects? */
 173         struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
 174 } drm_i915_batchbuffer_t;
 175
 176 /* As above, but pass a pointer to userspace buffer which can be
 177  * validated by the kernel prior to sending to hardware.
 178  */
 179 typedef struct _drm_i915_cmdbuffer {
 180         char __user *buf;       /* pointer to userspace command buffer */
 181         int sz;                 /* nr bytes in buf */
 182         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 183         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
 184         int num_cliprects;      /* mulitpass with multiple cliprects? */
 185         struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
 186 } drm_i915_cmdbuffer_t;
 187
 188 /* Userspace can request & wait on irq's:
 189  */
 190 typedef struct drm_i915_irq_emit {
 191         int __user *irq_seq;
 192 } drm_i915_irq_emit_t;
 193
 194 typedef struct drm_i915_irq_wait {
 195         int irq_seq;
 196 } drm_i915_irq_wait_t;
 197
 198 /* Ioctl to query kernel params:
 199  */
 200 #define I915_PARAM_IRQ_ACTIVE            1
 201 #define I915_PARAM_ALLOW_BATCHBUFFER     2
 202 #define I915_PARAM_LAST_DISPATCH         3
 203
 204 typedef struct drm_i915_getparam {
 205         int param;
 206         int __user *value;
 207 } drm_i915_getparam_t;
 208
 209 /* Ioctl to set kernel params:
 210  */
 211 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
 212 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
 213 #define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
 214
 215 typedef struct drm_i915_setparam {
 216         int param;
 217         int value;
 218 } drm_i915_setparam_t;
 219
 220 /* A memory manager for regions of shared memory:
 221  */
 222 #define I915_MEM_REGION_AGP 1
 223
 224 typedef struct drm_i915_mem_alloc {
 225         int region;
 226         int alignment;
 227         int size;
 228         int __user *region_offset;      /* offset from start of fb or agp */
 229 } drm_i915_mem_alloc_t;
 230
 231 typedef struct drm_i915_mem_free {
 232         int region;
 233         int region_offset;
 234 } drm_i915_mem_free_t;
 235
 236 typedef struct drm_i915_mem_init_heap {
 237         int region;
 238         int size;
 239         int start;
 240 } drm_i915_mem_init_heap_t;
 241
 242 /* Allow memory manager to be torn down and re-initialized (eg on
 243  * rotate):
 244  */
 245 typedef struct drm_i915_mem_destroy_heap {
 246         int region;
 247 } drm_i915_mem_destroy_heap_t;
 248
 249 /* Allow X server to configure which pipes to monitor for vblank signals
 250  */
 251 #define DRM_I915_VBLANK_PIPE_A  1
 252 #define DRM_I915_VBLANK_PIPE_B  2
 253
 254 typedef struct drm_i915_vblank_pipe {
 255         int pipe;
 256 } drm_i915_vblank_pipe_t;
 257
 258 /* Schedule buffer swap at given vertical blank:
 259  */
 260 typedef struct drm_i915_vblank_swap {
 261         drm_drawable_t drawable;
 262         enum drm_vblank_seq_type seqtype;
 263         unsigned int sequence;
 264 } drm_i915_vblank_swap_t;
 265
 266 typedef struct drm_i915_hws_addr {
 267         uint64_t addr;
 268 } drm_i915_hws_addr_t;
 269
 270 #endif                          /* _I915_DRM_H_ */