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stmmac: fix a bug while checking the HW cap reg (v2)
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_main.c
blobfcdd5a2cbb5519a535c1b8b2d141efcf72ef3412
1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
30
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/kernel.h>
34 #include <linux/interrupt.h>
35 #include <linux/etherdevice.h>
36 #include <linux/platform_device.h>
37 #include <linux/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/skbuff.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_ether.h>
42 #include <linux/crc32.h>
43 #include <linux/mii.h>
44 #include <linux/if.h>
45 #include <linux/if_vlan.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/slab.h>
48 #include <linux/prefetch.h>
49 #ifdef CONFIG_STMMAC_DEBUG_FS
50 #include <linux/debugfs.h>
51 #include <linux/seq_file.h>
52 #endif
53 #include "stmmac.h"
54
55 #define STMMAC_RESOURCE_NAME "stmmaceth"
56
57 #undef STMMAC_DEBUG
58 /*#define STMMAC_DEBUG*/
59 #ifdef STMMAC_DEBUG
60 #define DBG(nlevel, klevel, fmt, args...) \
61 ((void)(netif_msg_##nlevel(priv) && \
62 printk(KERN_##klevel fmt, ## args)))
63 #else
64 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
65 #endif
66
67 #undef STMMAC_RX_DEBUG
68 /*#define STMMAC_RX_DEBUG*/
69 #ifdef STMMAC_RX_DEBUG
70 #define RX_DBG(fmt, args...) printk(fmt, ## args)
71 #else
72 #define RX_DBG(fmt, args...) do { } while (0)
73 #endif
74
75 #undef STMMAC_XMIT_DEBUG
76 /*#define STMMAC_XMIT_DEBUG*/
77 #ifdef STMMAC_TX_DEBUG
78 #define TX_DBG(fmt, args...) printk(fmt, ## args)
79 #else
80 #define TX_DBG(fmt, args...) do { } while (0)
81 #endif
82
83 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
84 #define JUMBO_LEN 9000
85
86 /* Module parameters */
87 #define TX_TIMEO 5000 /* default 5 seconds */
88 static int watchdog = TX_TIMEO;
89 module_param(watchdog, int, S_IRUGO | S_IWUSR);
90 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
91
92 static int debug = -1; /* -1: default, 0: no output, 16: all */
93 module_param(debug, int, S_IRUGO | S_IWUSR);
94 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
95
96 static int phyaddr = -1;
97 module_param(phyaddr, int, S_IRUGO);
98 MODULE_PARM_DESC(phyaddr, "Physical device address");
99
100 #define DMA_TX_SIZE 256
101 static int dma_txsize = DMA_TX_SIZE;
102 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
103 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
104
105 #define DMA_RX_SIZE 256
106 static int dma_rxsize = DMA_RX_SIZE;
107 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
108 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
109
110 static int flow_ctrl = FLOW_OFF;
111 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
112 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
113
114 static int pause = PAUSE_TIME;
115 module_param(pause, int, S_IRUGO | S_IWUSR);
116 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
117
118 #define TC_DEFAULT 64
119 static int tc = TC_DEFAULT;
120 module_param(tc, int, S_IRUGO | S_IWUSR);
121 MODULE_PARM_DESC(tc, "DMA threshold control value");
122
123 /* Pay attention to tune this parameter; take care of both
124 * hardware capability and network stabitily/performance impact.
125 * Many tests showed that ~4ms latency seems to be good enough. */
126 #ifdef CONFIG_STMMAC_TIMER
127 #define DEFAULT_PERIODIC_RATE 256
128 static int tmrate = DEFAULT_PERIODIC_RATE;
129 module_param(tmrate, int, S_IRUGO | S_IWUSR);
130 MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
131 #endif
132
133 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
134 static int buf_sz = DMA_BUFFER_SIZE;
135 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
136 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
137
138 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
139 NETIF_MSG_LINK | NETIF_MSG_IFUP |
140 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
141
142 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
143
144 /**
145 * stmmac_verify_args - verify the driver parameters.
146 * Description: it verifies if some wrong parameter is passed to the driver.
147 * Note that wrong parameters are replaced with the default values.
148 */
149 static void stmmac_verify_args(void)
150 {
151 if (unlikely(watchdog < 0))
152 watchdog = TX_TIMEO;
153 if (unlikely(dma_rxsize < 0))
154 dma_rxsize = DMA_RX_SIZE;
155 if (unlikely(dma_txsize < 0))
156 dma_txsize = DMA_TX_SIZE;
157 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
158 buf_sz = DMA_BUFFER_SIZE;
159 if (unlikely(flow_ctrl > 1))
160 flow_ctrl = FLOW_AUTO;
161 else if (likely(flow_ctrl < 0))
162 flow_ctrl = FLOW_OFF;
163 if (unlikely((pause < 0) || (pause > 0xffff)))
164 pause = PAUSE_TIME;
165 }
166
167 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
168 static void print_pkt(unsigned char *buf, int len)
169 {
170 int j;
171 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
172 for (j = 0; j < len; j++) {
173 if ((j % 16) == 0)
174 pr_info("\n %03x:", j);
175 pr_info(" %02x", buf[j]);
176 }
177 pr_info("\n");
178 }
179 #endif
180
181 /* minimum number of free TX descriptors required to wake up TX process */
182 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
183
184 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
185 {
186 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
187 }
188
189 /* On some ST platforms, some HW system configuraton registers have to be
190 * set according to the link speed negotiated.
191 */
192 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
193 {
194 struct phy_device *phydev = priv->phydev;
195
196 if (likely(priv->plat->fix_mac_speed))
197 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
198 phydev->speed);
199 }
200
201 /**
202 * stmmac_adjust_link
203 * @dev: net device structure
204 * Description: it adjusts the link parameters.
205 */
206 static void stmmac_adjust_link(struct net_device *dev)
207 {
208 struct stmmac_priv *priv = netdev_priv(dev);
209 struct phy_device *phydev = priv->phydev;
210 unsigned long flags;
211 int new_state = 0;
212 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
213
214 if (phydev == NULL)
215 return;
216
217 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
218 phydev->addr, phydev->link);
219
220 spin_lock_irqsave(&priv->lock, flags);
221 if (phydev->link) {
222 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
223
224 /* Now we make sure that we can be in full duplex mode.
225 * If not, we operate in half-duplex mode. */
226 if (phydev->duplex != priv->oldduplex) {
227 new_state = 1;
228 if (!(phydev->duplex))
229 ctrl &= ~priv->hw->link.duplex;
230 else
231 ctrl |= priv->hw->link.duplex;
232 priv->oldduplex = phydev->duplex;
233 }
234 /* Flow Control operation */
235 if (phydev->pause)
236 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
237 fc, pause_time);
238
239 if (phydev->speed != priv->speed) {
240 new_state = 1;
241 switch (phydev->speed) {
242 case 1000:
243 if (likely(priv->plat->has_gmac))
244 ctrl &= ~priv->hw->link.port;
245 stmmac_hw_fix_mac_speed(priv);
246 break;
247 case 100:
248 case 10:
249 if (priv->plat->has_gmac) {
250 ctrl |= priv->hw->link.port;
251 if (phydev->speed == SPEED_100) {
252 ctrl |= priv->hw->link.speed;
253 } else {
254 ctrl &= ~(priv->hw->link.speed);
255 }
256 } else {
257 ctrl &= ~priv->hw->link.port;
258 }
259 stmmac_hw_fix_mac_speed(priv);
260 break;
261 default:
262 if (netif_msg_link(priv))
263 pr_warning("%s: Speed (%d) is not 10"
264 " or 100!\n", dev->name, phydev->speed);
265 break;
266 }
267
268 priv->speed = phydev->speed;
269 }
270
271 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
272
273 if (!priv->oldlink) {
274 new_state = 1;
275 priv->oldlink = 1;
276 }
277 } else if (priv->oldlink) {
278 new_state = 1;
279 priv->oldlink = 0;
280 priv->speed = 0;
281 priv->oldduplex = -1;
282 }
283
284 if (new_state && netif_msg_link(priv))
285 phy_print_status(phydev);
286
287 spin_unlock_irqrestore(&priv->lock, flags);
288
289 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
290 }
291
292 /**
293 * stmmac_init_phy - PHY initialization
294 * @dev: net device structure
295 * Description: it initializes the driver's PHY state, and attaches the PHY
296 * to the mac driver.
297 * Return value:
298 * 0 on success
299 */
300 static int stmmac_init_phy(struct net_device *dev)
301 {
302 struct stmmac_priv *priv = netdev_priv(dev);
303 struct phy_device *phydev;
304 char phy_id[MII_BUS_ID_SIZE + 3];
305 char bus_id[MII_BUS_ID_SIZE];
306 int interface = priv->plat->interface;
307 priv->oldlink = 0;
308 priv->speed = 0;
309 priv->oldduplex = -1;
310
311 snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id);
312 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
313 priv->plat->phy_addr);
314 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
315
316 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface);
317
318 if (IS_ERR(phydev)) {
319 pr_err("%s: Could not attach to PHY\n", dev->name);
320 return PTR_ERR(phydev);
321 }
322
323 /* Stop Advertising 1000BASE Capability if interface is not GMII */
324 if ((interface) && ((interface == PHY_INTERFACE_MODE_MII) ||
325 (interface == PHY_INTERFACE_MODE_RMII))) {
326 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
327 SUPPORTED_Asym_Pause);
328 priv->phydev->advertising = priv->phydev->supported;
329 }
330
331 /*
332 * Broken HW is sometimes missing the pull-up resistor on the
333 * MDIO line, which results in reads to non-existent devices returning
334 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
335 * device as well.
336 * Note: phydev->phy_id is the result of reading the UID PHY registers.
337 */
338 if (phydev->phy_id == 0) {
339 phy_disconnect(phydev);
340 return -ENODEV;
341 }
342 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
343 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
344
345 priv->phydev = phydev;
346
347 return 0;
348 }
349
350 static inline void stmmac_enable_mac(void __iomem *ioaddr)
351 {
352 u32 value = readl(ioaddr + MAC_CTRL_REG);
353
354 value |= MAC_RNABLE_RX | MAC_ENABLE_TX;
355 writel(value, ioaddr + MAC_CTRL_REG);
356 }
357
358 static inline void stmmac_disable_mac(void __iomem *ioaddr)
359 {
360 u32 value = readl(ioaddr + MAC_CTRL_REG);
361
362 value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX);
363 writel(value, ioaddr + MAC_CTRL_REG);
364 }
365
366 /**
367 * display_ring
368 * @p: pointer to the ring.
369 * @size: size of the ring.
370 * Description: display all the descriptors within the ring.
371 */
372 static void display_ring(struct dma_desc *p, int size)
373 {
374 struct tmp_s {
375 u64 a;
376 unsigned int b;
377 unsigned int c;
378 };
379 int i;
380 for (i = 0; i < size; i++) {
381 struct tmp_s *x = (struct tmp_s *)(p + i);
382 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
383 i, (unsigned int)virt_to_phys(&p[i]),
384 (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
385 x->b, x->c);
386 pr_info("\n");
387 }
388 }
389
390 static int stmmac_set_bfsize(int mtu, int bufsize)
391 {
392 int ret = bufsize;
393
394 if (mtu >= BUF_SIZE_4KiB)
395 ret = BUF_SIZE_8KiB;
396 else if (mtu >= BUF_SIZE_2KiB)
397 ret = BUF_SIZE_4KiB;
398 else if (mtu >= DMA_BUFFER_SIZE)
399 ret = BUF_SIZE_2KiB;
400 else
401 ret = DMA_BUFFER_SIZE;
402
403 return ret;
404 }
405
406 /**
407 * init_dma_desc_rings - init the RX/TX descriptor rings
408 * @dev: net device structure
409 * Description: this function initializes the DMA RX/TX descriptors
410 * and allocates the socket buffers. It suppors the chained and ring
411 * modes.
412 */
413 static void init_dma_desc_rings(struct net_device *dev)
414 {
415 int i;
416 struct stmmac_priv *priv = netdev_priv(dev);
417 struct sk_buff *skb;
418 unsigned int txsize = priv->dma_tx_size;
419 unsigned int rxsize = priv->dma_rx_size;
420 unsigned int bfsize;
421 int dis_ic = 0;
422 int des3_as_data_buf = 0;
423
424 /* Set the max buffer size according to the DESC mode
425 * and the MTU. Note that RING mode allows 16KiB bsize. */
426 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
427
428 if (bfsize == BUF_SIZE_16KiB)
429 des3_as_data_buf = 1;
430 else
431 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
432
433 #ifdef CONFIG_STMMAC_TIMER
434 /* Disable interrupts on completion for the reception if timer is on */
435 if (likely(priv->tm->enable))
436 dis_ic = 1;
437 #endif
438
439 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
440 txsize, rxsize, bfsize);
441
442 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
443 priv->rx_skbuff =
444 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
445 priv->dma_rx =
446 (struct dma_desc *)dma_alloc_coherent(priv->device,
447 rxsize *
448 sizeof(struct dma_desc),
449 &priv->dma_rx_phy,
450 GFP_KERNEL);
451 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
452 GFP_KERNEL);
453 priv->dma_tx =
454 (struct dma_desc *)dma_alloc_coherent(priv->device,
455 txsize *
456 sizeof(struct dma_desc),
457 &priv->dma_tx_phy,
458 GFP_KERNEL);
459
460 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
461 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
462 return;
463 }
464
465 DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, "
466 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
467 dev->name, priv->dma_rx, priv->dma_tx,
468 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
469
470 /* RX INITIALIZATION */
471 DBG(probe, INFO, "stmmac: SKB addresses:\n"
472 "skb\t\tskb data\tdma data\n");
473
474 for (i = 0; i < rxsize; i++) {
475 struct dma_desc *p = priv->dma_rx + i;
476
477 skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN,
478 GFP_KERNEL);
479 if (unlikely(skb == NULL)) {
480 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
481 break;
482 }
483 skb_reserve(skb, NET_IP_ALIGN);
484 priv->rx_skbuff[i] = skb;
485 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
486 bfsize, DMA_FROM_DEVICE);
487
488 p->des2 = priv->rx_skbuff_dma[i];
489
490 priv->hw->ring->init_desc3(des3_as_data_buf, p);
491
492 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
493 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
494 }
495 priv->cur_rx = 0;
496 priv->dirty_rx = (unsigned int)(i - rxsize);
497 priv->dma_buf_sz = bfsize;
498 buf_sz = bfsize;
499
500 /* TX INITIALIZATION */
501 for (i = 0; i < txsize; i++) {
502 priv->tx_skbuff[i] = NULL;
503 priv->dma_tx[i].des2 = 0;
504 }
505
506 /* In case of Chained mode this sets the des3 to the next
507 * element in the chain */
508 priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize);
509 priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize);
510
511 priv->dirty_tx = 0;
512 priv->cur_tx = 0;
513
514 /* Clear the Rx/Tx descriptors */
515 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
516 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
517
518 if (netif_msg_hw(priv)) {
519 pr_info("RX descriptor ring:\n");
520 display_ring(priv->dma_rx, rxsize);
521 pr_info("TX descriptor ring:\n");
522 display_ring(priv->dma_tx, txsize);
523 }
524 }
525
526 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
527 {
528 int i;
529
530 for (i = 0; i < priv->dma_rx_size; i++) {
531 if (priv->rx_skbuff[i]) {
532 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
533 priv->dma_buf_sz, DMA_FROM_DEVICE);
534 dev_kfree_skb_any(priv->rx_skbuff[i]);
535 }
536 priv->rx_skbuff[i] = NULL;
537 }
538 }
539
540 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
541 {
542 int i;
543
544 for (i = 0; i < priv->dma_tx_size; i++) {
545 if (priv->tx_skbuff[i] != NULL) {
546 struct dma_desc *p = priv->dma_tx + i;
547 if (p->des2)
548 dma_unmap_single(priv->device, p->des2,
549 priv->hw->desc->get_tx_len(p),
550 DMA_TO_DEVICE);
551 dev_kfree_skb_any(priv->tx_skbuff[i]);
552 priv->tx_skbuff[i] = NULL;
553 }
554 }
555 }
556
557 static void free_dma_desc_resources(struct stmmac_priv *priv)
558 {
559 /* Release the DMA TX/RX socket buffers */
560 dma_free_rx_skbufs(priv);
561 dma_free_tx_skbufs(priv);
562
563 /* Free the region of consistent memory previously allocated for
564 * the DMA */
565 dma_free_coherent(priv->device,
566 priv->dma_tx_size * sizeof(struct dma_desc),
567 priv->dma_tx, priv->dma_tx_phy);
568 dma_free_coherent(priv->device,
569 priv->dma_rx_size * sizeof(struct dma_desc),
570 priv->dma_rx, priv->dma_rx_phy);
571 kfree(priv->rx_skbuff_dma);
572 kfree(priv->rx_skbuff);
573 kfree(priv->tx_skbuff);
574 }
575
576 /**
577 * stmmac_dma_operation_mode - HW DMA operation mode
578 * @priv : pointer to the private device structure.
579 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
580 * or Store-And-Forward capability.
581 */
582 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
583 {
584 if (likely(priv->plat->force_sf_dma_mode ||
585 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
586 /*
587 * In case of GMAC, SF mode can be enabled
588 * to perform the TX COE in HW. This depends on:
589 * 1) TX COE if actually supported
590 * 2) There is no bugged Jumbo frame support
591 * that needs to not insert csum in the TDES.
592 */
593 priv->hw->dma->dma_mode(priv->ioaddr,
594 SF_DMA_MODE, SF_DMA_MODE);
595 tc = SF_DMA_MODE;
596 } else
597 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
598 }
599
600 /**
601 * stmmac_tx:
602 * @priv: private driver structure
603 * Description: it reclaims resources after transmission completes.
604 */
605 static void stmmac_tx(struct stmmac_priv *priv)
606 {
607 unsigned int txsize = priv->dma_tx_size;
608
609 spin_lock(&priv->tx_lock);
610
611 while (priv->dirty_tx != priv->cur_tx) {
612 int last;
613 unsigned int entry = priv->dirty_tx % txsize;
614 struct sk_buff *skb = priv->tx_skbuff[entry];
615 struct dma_desc *p = priv->dma_tx + entry;
616
617 /* Check if the descriptor is owned by the DMA. */
618 if (priv->hw->desc->get_tx_owner(p))
619 break;
620
621 /* Verify tx error by looking at the last segment */
622 last = priv->hw->desc->get_tx_ls(p);
623 if (likely(last)) {
624 int tx_error =
625 priv->hw->desc->tx_status(&priv->dev->stats,
626 &priv->xstats, p,
627 priv->ioaddr);
628 if (likely(tx_error == 0)) {
629 priv->dev->stats.tx_packets++;
630 priv->xstats.tx_pkt_n++;
631 } else
632 priv->dev->stats.tx_errors++;
633 }
634 TX_DBG("%s: curr %d, dirty %d\n", __func__,
635 priv->cur_tx, priv->dirty_tx);
636
637 if (likely(p->des2))
638 dma_unmap_single(priv->device, p->des2,
639 priv->hw->desc->get_tx_len(p),
640 DMA_TO_DEVICE);
641 priv->hw->ring->clean_desc3(p);
642
643 if (likely(skb != NULL)) {
644 /*
645 * If there's room in the queue (limit it to size)
646 * we add this skb back into the pool,
647 * if it's the right size.
648 */
649 if ((skb_queue_len(&priv->rx_recycle) <
650 priv->dma_rx_size) &&
651 skb_recycle_check(skb, priv->dma_buf_sz))
652 __skb_queue_head(&priv->rx_recycle, skb);
653 else
654 dev_kfree_skb(skb);
655
656 priv->tx_skbuff[entry] = NULL;
657 }
658
659 priv->hw->desc->release_tx_desc(p);
660
661 entry = (++priv->dirty_tx) % txsize;
662 }
663 if (unlikely(netif_queue_stopped(priv->dev) &&
664 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
665 netif_tx_lock(priv->dev);
666 if (netif_queue_stopped(priv->dev) &&
667 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
668 TX_DBG("%s: restart transmit\n", __func__);
669 netif_wake_queue(priv->dev);
670 }
671 netif_tx_unlock(priv->dev);
672 }
673 spin_unlock(&priv->tx_lock);
674 }
675
676 static inline void stmmac_enable_irq(struct stmmac_priv *priv)
677 {
678 #ifdef CONFIG_STMMAC_TIMER
679 if (likely(priv->tm->enable))
680 priv->tm->timer_start(tmrate);
681 else
682 #endif
683 priv->hw->dma->enable_dma_irq(priv->ioaddr);
684 }
685
686 static inline void stmmac_disable_irq(struct stmmac_priv *priv)
687 {
688 #ifdef CONFIG_STMMAC_TIMER
689 if (likely(priv->tm->enable))
690 priv->tm->timer_stop();
691 else
692 #endif
693 priv->hw->dma->disable_dma_irq(priv->ioaddr);
694 }
695
696 static int stmmac_has_work(struct stmmac_priv *priv)
697 {
698 unsigned int has_work = 0;
699 int rxret, tx_work = 0;
700
701 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
702 (priv->cur_rx % priv->dma_rx_size));
703
704 if (priv->dirty_tx != priv->cur_tx)
705 tx_work = 1;
706
707 if (likely(!rxret || tx_work))
708 has_work = 1;
709
710 return has_work;
711 }
712
713 static inline void _stmmac_schedule(struct stmmac_priv *priv)
714 {
715 if (likely(stmmac_has_work(priv))) {
716 stmmac_disable_irq(priv);
717 napi_schedule(&priv->napi);
718 }
719 }
720
721 #ifdef CONFIG_STMMAC_TIMER
722 void stmmac_schedule(struct net_device *dev)
723 {
724 struct stmmac_priv *priv = netdev_priv(dev);
725
726 priv->xstats.sched_timer_n++;
727
728 _stmmac_schedule(priv);
729 }
730
731 static void stmmac_no_timer_started(unsigned int x)
732 {;
733 };
734
735 static void stmmac_no_timer_stopped(void)
736 {;
737 };
738 #endif
739
740 /**
741 * stmmac_tx_err:
742 * @priv: pointer to the private device structure
743 * Description: it cleans the descriptors and restarts the transmission
744 * in case of errors.
745 */
746 static void stmmac_tx_err(struct stmmac_priv *priv)
747 {
748 netif_stop_queue(priv->dev);
749
750 priv->hw->dma->stop_tx(priv->ioaddr);
751 dma_free_tx_skbufs(priv);
752 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
753 priv->dirty_tx = 0;
754 priv->cur_tx = 0;
755 priv->hw->dma->start_tx(priv->ioaddr);
756
757 priv->dev->stats.tx_errors++;
758 netif_wake_queue(priv->dev);
759 }
760
761
762 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
763 {
764 int status;
765
766 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
767 if (likely(status == handle_tx_rx))
768 _stmmac_schedule(priv);
769
770 else if (unlikely(status == tx_hard_error_bump_tc)) {
771 /* Try to bump up the dma threshold on this failure */
772 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
773 tc += 64;
774 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
775 priv->xstats.threshold = tc;
776 }
777 } else if (unlikely(status == tx_hard_error))
778 stmmac_tx_err(priv);
779 }
780
781 static void stmmac_mmc_setup(struct stmmac_priv *priv)
782 {
783 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
784 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
785
786 /* Do not manage MMC IRQ (FIXME) */
787 dwmac_mmc_intr_all_mask(priv->ioaddr);
788 dwmac_mmc_ctrl(priv->ioaddr, mode);
789 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
790 }
791
792 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
793 {
794 u32 hwid = priv->hw->synopsys_uid;
795
796 /* Only check valid Synopsys Id because old MAC chips
797 * have no HW registers where get the ID */
798 if (likely(hwid)) {
799 u32 uid = ((hwid & 0x0000ff00) >> 8);
800 u32 synid = (hwid & 0x000000ff);
801
802 pr_info("STMMAC - user ID: 0x%x, Synopsys ID: 0x%x\n",
803 uid, synid);
804
805 return synid;
806 }
807 return 0;
808 }
809
810 /* New GMAC chips support a new register to indicate the
811 * presence of the optional feature/functions.
812 */
813 static int stmmac_get_hw_features(struct stmmac_priv *priv)
814 {
815 u32 hw_cap = 0;
816 if (priv->hw->dma->get_hw_feature) {
817 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
818
819 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
820 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
821 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
822 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
823 priv->dma_cap.multi_addr =
824 (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
825 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
826 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
827 priv->dma_cap.pmt_remote_wake_up =
828 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
829 priv->dma_cap.pmt_magic_frame =
830 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
831 /*MMC*/
832 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
833 /* IEEE 1588-2002*/
834 priv->dma_cap.time_stamp =
835 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
836 /* IEEE 1588-2008*/
837 priv->dma_cap.atime_stamp =
838 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
839 /* 802.3az - Energy-Efficient Ethernet (EEE) */
840 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
841 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
842 /* TX and RX csum */
843 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
844 priv->dma_cap.rx_coe_type1 =
845 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
846 priv->dma_cap.rx_coe_type2 =
847 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
848 priv->dma_cap.rxfifo_over_2048 =
849 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
850 /* TX and RX number of channels */
851 priv->dma_cap.number_rx_channel =
852 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
853 priv->dma_cap.number_tx_channel =
854 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
855 /* Alternate (enhanced) DESC mode*/
856 priv->dma_cap.enh_desc =
857 (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
858
859 } else
860 pr_debug("\tNo HW DMA feature register supported");
861
862 return hw_cap;
863 }
864
865 /**
866 * stmmac_open - open entry point of the driver
867 * @dev : pointer to the device structure.
868 * Description:
869 * This function is the open entry point of the driver.
870 * Return value:
871 * 0 on success and an appropriate (-)ve integer as defined in errno.h
872 * file on failure.
873 */
874 static int stmmac_open(struct net_device *dev)
875 {
876 struct stmmac_priv *priv = netdev_priv(dev);
877 int ret;
878
879 /* Check that the MAC address is valid. If its not, refuse
880 * to bring the device up. The user must specify an
881 * address using the following linux command:
882 * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */
883 if (!is_valid_ether_addr(dev->dev_addr)) {
884 random_ether_addr(dev->dev_addr);
885 pr_warning("%s: generated random MAC address %pM\n", dev->name,
886 dev->dev_addr);
887 }
888
889 stmmac_verify_args();
890
891 #ifdef CONFIG_STMMAC_TIMER
892 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
893 if (unlikely(priv->tm == NULL)) {
894 pr_err("%s: ERROR: timer memory alloc failed\n", __func__);
895 return -ENOMEM;
896 }
897 priv->tm->freq = tmrate;
898
899 /* Test if the external timer can be actually used.
900 * In case of failure continue without timer. */
901 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
902 pr_warning("stmmaceth: cannot attach the external timer.\n");
903 priv->tm->freq = 0;
904 priv->tm->timer_start = stmmac_no_timer_started;
905 priv->tm->timer_stop = stmmac_no_timer_stopped;
906 } else
907 priv->tm->enable = 1;
908 #endif
909 ret = stmmac_init_phy(dev);
910 if (unlikely(ret)) {
911 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
912 goto open_error;
913 }
914
915 /* Create and initialize the TX/RX descriptors chains. */
916 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
917 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
918 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
919 init_dma_desc_rings(dev);
920
921 /* DMA initialization and SW reset */
922 ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl,
923 priv->dma_tx_phy, priv->dma_rx_phy);
924 if (ret < 0) {
925 pr_err("%s: DMA initialization failed\n", __func__);
926 goto open_error;
927 }
928
929 /* Copy the MAC addr into the HW */
930 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
931 /* If required, perform hw setup of the bus. */
932 if (priv->plat->bus_setup)
933 priv->plat->bus_setup(priv->ioaddr);
934 /* Initialize the MAC Core */
935 priv->hw->mac->core_init(priv->ioaddr);
936
937 stmmac_get_synopsys_id(priv);
938
939 stmmac_get_hw_features(priv);
940
941 if (priv->rx_coe)
942 pr_info("stmmac: Rx Checksum Offload Engine supported\n");
943 if (priv->plat->tx_coe)
944 pr_info("\tTX Checksum insertion supported\n");
945 netdev_update_features(dev);
946
947 /* Request the IRQ lines */
948 ret = request_irq(dev->irq, stmmac_interrupt,
949 IRQF_SHARED, dev->name, dev);
950 if (unlikely(ret < 0)) {
951 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
952 __func__, dev->irq, ret);
953 goto open_error;
954 }
955
956 /* Enable the MAC Rx/Tx */
957 stmmac_enable_mac(priv->ioaddr);
958
959 /* Set the HW DMA mode and the COE */
960 stmmac_dma_operation_mode(priv);
961
962 /* Extra statistics */
963 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
964 priv->xstats.threshold = tc;
965
966 if (priv->dma_cap.rmon)
967 stmmac_mmc_setup(priv);
968
969 /* Start the ball rolling... */
970 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
971 priv->hw->dma->start_tx(priv->ioaddr);
972 priv->hw->dma->start_rx(priv->ioaddr);
973
974 #ifdef CONFIG_STMMAC_TIMER
975 priv->tm->timer_start(tmrate);
976 #endif
977 /* Dump DMA/MAC registers */
978 if (netif_msg_hw(priv)) {
979 priv->hw->mac->dump_regs(priv->ioaddr);
980 priv->hw->dma->dump_regs(priv->ioaddr);
981 }
982
983 if (priv->phydev)
984 phy_start(priv->phydev);
985
986 napi_enable(&priv->napi);
987 skb_queue_head_init(&priv->rx_recycle);
988 netif_start_queue(dev);
989
990 return 0;
991
992 open_error:
993 #ifdef CONFIG_STMMAC_TIMER
994 kfree(priv->tm);
995 #endif
996 if (priv->phydev)
997 phy_disconnect(priv->phydev);
998
999 return ret;
1000 }
1001
1002 /**
1003 * stmmac_release - close entry point of the driver
1004 * @dev : device pointer.
1005 * Description:
1006 * This is the stop entry point of the driver.
1007 */
1008 static int stmmac_release(struct net_device *dev)
1009 {
1010 struct stmmac_priv *priv = netdev_priv(dev);
1011
1012 /* Stop and disconnect the PHY */
1013 if (priv->phydev) {
1014 phy_stop(priv->phydev);
1015 phy_disconnect(priv->phydev);
1016 priv->phydev = NULL;
1017 }
1018
1019 netif_stop_queue(dev);
1020
1021 #ifdef CONFIG_STMMAC_TIMER
1022 /* Stop and release the timer */
1023 stmmac_close_ext_timer();
1024 if (priv->tm != NULL)
1025 kfree(priv->tm);
1026 #endif
1027 napi_disable(&priv->napi);
1028 skb_queue_purge(&priv->rx_recycle);
1029
1030 /* Free the IRQ lines */
1031 free_irq(dev->irq, dev);
1032
1033 /* Stop TX/RX DMA and clear the descriptors */
1034 priv->hw->dma->stop_tx(priv->ioaddr);
1035 priv->hw->dma->stop_rx(priv->ioaddr);
1036
1037 /* Release and free the Rx/Tx resources */
1038 free_dma_desc_resources(priv);
1039
1040 /* Disable the MAC Rx/Tx */
1041 stmmac_disable_mac(priv->ioaddr);
1042
1043 netif_carrier_off(dev);
1044
1045 return 0;
1046 }
1047
1048 /**
1049 * stmmac_xmit:
1050 * @skb : the socket buffer
1051 * @dev : device pointer
1052 * Description : Tx entry point of the driver.
1053 */
1054 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1055 {
1056 struct stmmac_priv *priv = netdev_priv(dev);
1057 unsigned int txsize = priv->dma_tx_size;
1058 unsigned int entry;
1059 int i, csum_insertion = 0;
1060 int nfrags = skb_shinfo(skb)->nr_frags;
1061 struct dma_desc *desc, *first;
1062 unsigned int nopaged_len = skb_headlen(skb);
1063
1064 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1065 if (!netif_queue_stopped(dev)) {
1066 netif_stop_queue(dev);
1067 /* This is a hard error, log it. */
1068 pr_err("%s: BUG! Tx Ring full when queue awake\n",
1069 __func__);
1070 }
1071 return NETDEV_TX_BUSY;
1072 }
1073
1074 spin_lock(&priv->tx_lock);
1075
1076 entry = priv->cur_tx % txsize;
1077
1078 #ifdef STMMAC_XMIT_DEBUG
1079 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1080 pr_info("stmmac xmit:\n"
1081 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1082 "\tn_frags: %d - ip_summed: %d - %s gso\n",
1083 skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1084 !skb_is_gso(skb) ? "isn't" : "is");
1085 #endif
1086
1087 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1088
1089 desc = priv->dma_tx + entry;
1090 first = desc;
1091
1092 #ifdef STMMAC_XMIT_DEBUG
1093 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1094 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1095 "\t\tn_frags: %d, ip_summed: %d\n",
1096 skb->len, nopaged_len, nfrags, skb->ip_summed);
1097 #endif
1098 priv->tx_skbuff[entry] = skb;
1099
1100 if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) {
1101 entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion);
1102 desc = priv->dma_tx + entry;
1103 } else {
1104 desc->des2 = dma_map_single(priv->device, skb->data,
1105 nopaged_len, DMA_TO_DEVICE);
1106 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1107 csum_insertion);
1108 }
1109
1110 for (i = 0; i < nfrags; i++) {
1111 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1112 int len = skb_frag_size(frag);
1113
1114 entry = (++priv->cur_tx) % txsize;
1115 desc = priv->dma_tx + entry;
1116
1117 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1118 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1119 DMA_TO_DEVICE);
1120 priv->tx_skbuff[entry] = NULL;
1121 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
1122 wmb();
1123 priv->hw->desc->set_tx_owner(desc);
1124 }
1125
1126 /* Interrupt on completition only for the latest segment */
1127 priv->hw->desc->close_tx_desc(desc);
1128
1129 #ifdef CONFIG_STMMAC_TIMER
1130 /* Clean IC while using timer */
1131 if (likely(priv->tm->enable))
1132 priv->hw->desc->clear_tx_ic(desc);
1133 #endif
1134
1135 wmb();
1136
1137 /* To avoid raise condition */
1138 priv->hw->desc->set_tx_owner(first);
1139
1140 priv->cur_tx++;
1141
1142 #ifdef STMMAC_XMIT_DEBUG
1143 if (netif_msg_pktdata(priv)) {
1144 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1145 "first=%p, nfrags=%d\n",
1146 (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1147 entry, first, nfrags);
1148 display_ring(priv->dma_tx, txsize);
1149 pr_info(">>> frame to be transmitted: ");
1150 print_pkt(skb->data, skb->len);
1151 }
1152 #endif
1153 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1154 TX_DBG("%s: stop transmitted packets\n", __func__);
1155 netif_stop_queue(dev);
1156 }
1157
1158 dev->stats.tx_bytes += skb->len;
1159
1160 skb_tx_timestamp(skb);
1161
1162 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1163
1164 spin_unlock(&priv->tx_lock);
1165
1166 return NETDEV_TX_OK;
1167 }
1168
1169 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1170 {
1171 unsigned int rxsize = priv->dma_rx_size;
1172 int bfsize = priv->dma_buf_sz;
1173 struct dma_desc *p = priv->dma_rx;
1174
1175 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1176 unsigned int entry = priv->dirty_rx % rxsize;
1177 if (likely(priv->rx_skbuff[entry] == NULL)) {
1178 struct sk_buff *skb;
1179
1180 skb = __skb_dequeue(&priv->rx_recycle);
1181 if (skb == NULL)
1182 skb = netdev_alloc_skb_ip_align(priv->dev,
1183 bfsize);
1184
1185 if (unlikely(skb == NULL))
1186 break;
1187
1188 priv->rx_skbuff[entry] = skb;
1189 priv->rx_skbuff_dma[entry] =
1190 dma_map_single(priv->device, skb->data, bfsize,
1191 DMA_FROM_DEVICE);
1192
1193 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1194
1195 if (unlikely(priv->plat->has_gmac))
1196 priv->hw->ring->refill_desc3(bfsize, p + entry);
1197
1198 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1199 }
1200 wmb();
1201 priv->hw->desc->set_rx_owner(p + entry);
1202 }
1203 }
1204
1205 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1206 {
1207 unsigned int rxsize = priv->dma_rx_size;
1208 unsigned int entry = priv->cur_rx % rxsize;
1209 unsigned int next_entry;
1210 unsigned int count = 0;
1211 struct dma_desc *p = priv->dma_rx + entry;
1212 struct dma_desc *p_next;
1213
1214 #ifdef STMMAC_RX_DEBUG
1215 if (netif_msg_hw(priv)) {
1216 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1217 display_ring(priv->dma_rx, rxsize);
1218 }
1219 #endif
1220 count = 0;
1221 while (!priv->hw->desc->get_rx_owner(p)) {
1222 int status;
1223
1224 if (count >= limit)
1225 break;
1226
1227 count++;
1228
1229 next_entry = (++priv->cur_rx) % rxsize;
1230 p_next = priv->dma_rx + next_entry;
1231 prefetch(p_next);
1232
1233 /* read the status of the incoming frame */
1234 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1235 &priv->xstats, p));
1236 if (unlikely(status == discard_frame))
1237 priv->dev->stats.rx_errors++;
1238 else {
1239 struct sk_buff *skb;
1240 int frame_len;
1241
1242 frame_len = priv->hw->desc->get_rx_frame_len(p);
1243 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1244 * Type frames (LLC/LLC-SNAP) */
1245 if (unlikely(status != llc_snap))
1246 frame_len -= ETH_FCS_LEN;
1247 #ifdef STMMAC_RX_DEBUG
1248 if (frame_len > ETH_FRAME_LEN)
1249 pr_debug("\tRX frame size %d, COE status: %d\n",
1250 frame_len, status);
1251
1252 if (netif_msg_hw(priv))
1253 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1254 p, entry, p->des2);
1255 #endif
1256 skb = priv->rx_skbuff[entry];
1257 if (unlikely(!skb)) {
1258 pr_err("%s: Inconsistent Rx descriptor chain\n",
1259 priv->dev->name);
1260 priv->dev->stats.rx_dropped++;
1261 break;
1262 }
1263 prefetch(skb->data - NET_IP_ALIGN);
1264 priv->rx_skbuff[entry] = NULL;
1265
1266 skb_put(skb, frame_len);
1267 dma_unmap_single(priv->device,
1268 priv->rx_skbuff_dma[entry],
1269 priv->dma_buf_sz, DMA_FROM_DEVICE);
1270 #ifdef STMMAC_RX_DEBUG
1271 if (netif_msg_pktdata(priv)) {
1272 pr_info(" frame received (%dbytes)", frame_len);
1273 print_pkt(skb->data, frame_len);
1274 }
1275 #endif
1276 skb->protocol = eth_type_trans(skb, priv->dev);
1277
1278 if (unlikely(status == csum_none)) {
1279 /* always for the old mac 10/100 */
1280 skb_checksum_none_assert(skb);
1281 netif_receive_skb(skb);
1282 } else {
1283 skb->ip_summed = CHECKSUM_UNNECESSARY;
1284 napi_gro_receive(&priv->napi, skb);
1285 }
1286
1287 priv->dev->stats.rx_packets++;
1288 priv->dev->stats.rx_bytes += frame_len;
1289 }
1290 entry = next_entry;
1291 p = p_next; /* use prefetched values */
1292 }
1293
1294 stmmac_rx_refill(priv);
1295
1296 priv->xstats.rx_pkt_n += count;
1297
1298 return count;
1299 }
1300
1301 /**
1302 * stmmac_poll - stmmac poll method (NAPI)
1303 * @napi : pointer to the napi structure.
1304 * @budget : maximum number of packets that the current CPU can receive from
1305 * all interfaces.
1306 * Description :
1307 * This function implements the the reception process.
1308 * Also it runs the TX completion thread
1309 */
1310 static int stmmac_poll(struct napi_struct *napi, int budget)
1311 {
1312 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1313 int work_done = 0;
1314
1315 priv->xstats.poll_n++;
1316 stmmac_tx(priv);
1317 work_done = stmmac_rx(priv, budget);
1318
1319 if (work_done < budget) {
1320 napi_complete(napi);
1321 stmmac_enable_irq(priv);
1322 }
1323 return work_done;
1324 }
1325
1326 /**
1327 * stmmac_tx_timeout
1328 * @dev : Pointer to net device structure
1329 * Description: this function is called when a packet transmission fails to
1330 * complete within a reasonable tmrate. The driver will mark the error in the
1331 * netdev structure and arrange for the device to be reset to a sane state
1332 * in order to transmit a new packet.
1333 */
1334 static void stmmac_tx_timeout(struct net_device *dev)
1335 {
1336 struct stmmac_priv *priv = netdev_priv(dev);
1337
1338 /* Clear Tx resources and restart transmitting again */
1339 stmmac_tx_err(priv);
1340 }
1341
1342 /* Configuration changes (passed on by ifconfig) */
1343 static int stmmac_config(struct net_device *dev, struct ifmap *map)
1344 {
1345 if (dev->flags & IFF_UP) /* can't act on a running interface */
1346 return -EBUSY;
1347
1348 /* Don't allow changing the I/O address */
1349 if (map->base_addr != dev->base_addr) {
1350 pr_warning("%s: can't change I/O address\n", dev->name);
1351 return -EOPNOTSUPP;
1352 }
1353
1354 /* Don't allow changing the IRQ */
1355 if (map->irq != dev->irq) {
1356 pr_warning("%s: can't change IRQ number %d\n",
1357 dev->name, dev->irq);
1358 return -EOPNOTSUPP;
1359 }
1360
1361 /* ignore other fields */
1362 return 0;
1363 }
1364
1365 /**
1366 * stmmac_set_rx_mode - entry point for multicast addressing
1367 * @dev : pointer to the device structure
1368 * Description:
1369 * This function is a driver entry point which gets called by the kernel
1370 * whenever multicast addresses must be enabled/disabled.
1371 * Return value:
1372 * void.
1373 */
1374 static void stmmac_set_rx_mode(struct net_device *dev)
1375 {
1376 struct stmmac_priv *priv = netdev_priv(dev);
1377
1378 spin_lock(&priv->lock);
1379 priv->hw->mac->set_filter(dev);
1380 spin_unlock(&priv->lock);
1381 }
1382
1383 /**
1384 * stmmac_change_mtu - entry point to change MTU size for the device.
1385 * @dev : device pointer.
1386 * @new_mtu : the new MTU size for the device.
1387 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1388 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1389 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1390 * Return value:
1391 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1392 * file on failure.
1393 */
1394 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1395 {
1396 struct stmmac_priv *priv = netdev_priv(dev);
1397 int max_mtu;
1398
1399 if (netif_running(dev)) {
1400 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1401 return -EBUSY;
1402 }
1403
1404 if (priv->plat->enh_desc)
1405 max_mtu = JUMBO_LEN;
1406 else
1407 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
1408
1409 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1410 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1411 return -EINVAL;
1412 }
1413
1414 dev->mtu = new_mtu;
1415 netdev_update_features(dev);
1416
1417 return 0;
1418 }
1419
1420 static u32 stmmac_fix_features(struct net_device *dev, u32 features)
1421 {
1422 struct stmmac_priv *priv = netdev_priv(dev);
1423
1424 if (!priv->rx_coe)
1425 features &= ~NETIF_F_RXCSUM;
1426 if (!priv->plat->tx_coe)
1427 features &= ~NETIF_F_ALL_CSUM;
1428
1429 /* Some GMAC devices have a bugged Jumbo frame support that
1430 * needs to have the Tx COE disabled for oversized frames
1431 * (due to limited buffer sizes). In this case we disable
1432 * the TX csum insertionin the TDES and not use SF. */
1433 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1434 features &= ~NETIF_F_ALL_CSUM;
1435
1436 return features;
1437 }
1438
1439 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1440 {
1441 struct net_device *dev = (struct net_device *)dev_id;
1442 struct stmmac_priv *priv = netdev_priv(dev);
1443
1444 if (unlikely(!dev)) {
1445 pr_err("%s: invalid dev pointer\n", __func__);
1446 return IRQ_NONE;
1447 }
1448
1449 if (priv->plat->has_gmac)
1450 /* To handle GMAC own interrupts */
1451 priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr);
1452
1453 stmmac_dma_interrupt(priv);
1454
1455 return IRQ_HANDLED;
1456 }
1457
1458 #ifdef CONFIG_NET_POLL_CONTROLLER
1459 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1460 * to allow network I/O with interrupts disabled. */
1461 static void stmmac_poll_controller(struct net_device *dev)
1462 {
1463 disable_irq(dev->irq);
1464 stmmac_interrupt(dev->irq, dev);
1465 enable_irq(dev->irq);
1466 }
1467 #endif
1468
1469 /**
1470 * stmmac_ioctl - Entry point for the Ioctl
1471 * @dev: Device pointer.
1472 * @rq: An IOCTL specefic structure, that can contain a pointer to
1473 * a proprietary structure used to pass information to the driver.
1474 * @cmd: IOCTL command
1475 * Description:
1476 * Currently there are no special functionality supported in IOCTL, just the
1477 * phy_mii_ioctl(...) can be invoked.
1478 */
1479 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1480 {
1481 struct stmmac_priv *priv = netdev_priv(dev);
1482 int ret;
1483
1484 if (!netif_running(dev))
1485 return -EINVAL;
1486
1487 if (!priv->phydev)
1488 return -EINVAL;
1489
1490 spin_lock(&priv->lock);
1491 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1492 spin_unlock(&priv->lock);
1493
1494 return ret;
1495 }
1496
1497 #ifdef CONFIG_STMMAC_DEBUG_FS
1498 static struct dentry *stmmac_fs_dir;
1499 static struct dentry *stmmac_rings_status;
1500 static struct dentry *stmmac_dma_cap;
1501
1502 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
1503 {
1504 struct tmp_s {
1505 u64 a;
1506 unsigned int b;
1507 unsigned int c;
1508 };
1509 int i;
1510 struct net_device *dev = seq->private;
1511 struct stmmac_priv *priv = netdev_priv(dev);
1512
1513 seq_printf(seq, "=======================\n");
1514 seq_printf(seq, " RX descriptor ring\n");
1515 seq_printf(seq, "=======================\n");
1516
1517 for (i = 0; i < priv->dma_rx_size; i++) {
1518 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i);
1519 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1520 i, (unsigned int)(x->a),
1521 (unsigned int)((x->a) >> 32), x->b, x->c);
1522 seq_printf(seq, "\n");
1523 }
1524
1525 seq_printf(seq, "\n");
1526 seq_printf(seq, "=======================\n");
1527 seq_printf(seq, " TX descriptor ring\n");
1528 seq_printf(seq, "=======================\n");
1529
1530 for (i = 0; i < priv->dma_tx_size; i++) {
1531 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i);
1532 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1533 i, (unsigned int)(x->a),
1534 (unsigned int)((x->a) >> 32), x->b, x->c);
1535 seq_printf(seq, "\n");
1536 }
1537
1538 return 0;
1539 }
1540
1541 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
1542 {
1543 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
1544 }
1545
1546 static const struct file_operations stmmac_rings_status_fops = {
1547 .owner = THIS_MODULE,
1548 .open = stmmac_sysfs_ring_open,
1549 .read = seq_read,
1550 .llseek = seq_lseek,
1551 .release = seq_release,
1552 };
1553
1554 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
1555 {
1556 struct net_device *dev = seq->private;
1557 struct stmmac_priv *priv = netdev_priv(dev);
1558
1559 if (!stmmac_get_hw_features(priv)) {
1560 seq_printf(seq, "DMA HW features not supported\n");
1561 return 0;
1562 }
1563
1564 seq_printf(seq, "==============================\n");
1565 seq_printf(seq, "\tDMA HW features\n");
1566 seq_printf(seq, "==============================\n");
1567
1568 seq_printf(seq, "\t10/100 Mbps %s\n",
1569 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
1570 seq_printf(seq, "\t1000 Mbps %s\n",
1571 (priv->dma_cap.mbps_1000) ? "Y" : "N");
1572 seq_printf(seq, "\tHalf duple %s\n",
1573 (priv->dma_cap.half_duplex) ? "Y" : "N");
1574 seq_printf(seq, "\tHash Filter: %s\n",
1575 (priv->dma_cap.hash_filter) ? "Y" : "N");
1576 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1577 (priv->dma_cap.multi_addr) ? "Y" : "N");
1578 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1579 (priv->dma_cap.pcs) ? "Y" : "N");
1580 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1581 (priv->dma_cap.sma_mdio) ? "Y" : "N");
1582 seq_printf(seq, "\tPMT Remote wake up: %s\n",
1583 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
1584 seq_printf(seq, "\tPMT Magic Frame: %s\n",
1585 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
1586 seq_printf(seq, "\tRMON module: %s\n",
1587 (priv->dma_cap.rmon) ? "Y" : "N");
1588 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
1589 (priv->dma_cap.time_stamp) ? "Y" : "N");
1590 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1591 (priv->dma_cap.atime_stamp) ? "Y" : "N");
1592 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1593 (priv->dma_cap.eee) ? "Y" : "N");
1594 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
1595 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
1596 (priv->dma_cap.tx_coe) ? "Y" : "N");
1597 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
1598 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
1599 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
1600 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
1601 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
1602 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
1603 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
1604 priv->dma_cap.number_rx_channel);
1605 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
1606 priv->dma_cap.number_tx_channel);
1607 seq_printf(seq, "\tEnhanced descriptors: %s\n",
1608 (priv->dma_cap.enh_desc) ? "Y" : "N");
1609
1610 return 0;
1611 }
1612
1613 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
1614 {
1615 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
1616 }
1617
1618 static const struct file_operations stmmac_dma_cap_fops = {
1619 .owner = THIS_MODULE,
1620 .open = stmmac_sysfs_dma_cap_open,
1621 .read = seq_read,
1622 .llseek = seq_lseek,
1623 .release = seq_release,
1624 };
1625
1626 static int stmmac_init_fs(struct net_device *dev)
1627 {
1628 /* Create debugfs entries */
1629 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
1630
1631 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
1632 pr_err("ERROR %s, debugfs create directory failed\n",
1633 STMMAC_RESOURCE_NAME);
1634
1635 return -ENOMEM;
1636 }
1637
1638 /* Entry to report DMA RX/TX rings */
1639 stmmac_rings_status = debugfs_create_file("descriptors_status",
1640 S_IRUGO, stmmac_fs_dir, dev,
1641 &stmmac_rings_status_fops);
1642
1643 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
1644 pr_info("ERROR creating stmmac ring debugfs file\n");
1645 debugfs_remove(stmmac_fs_dir);
1646
1647 return -ENOMEM;
1648 }
1649
1650 /* Entry to report the DMA HW features */
1651 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
1652 dev, &stmmac_dma_cap_fops);
1653
1654 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
1655 pr_info("ERROR creating stmmac MMC debugfs file\n");
1656 debugfs_remove(stmmac_rings_status);
1657 debugfs_remove(stmmac_fs_dir);
1658
1659 return -ENOMEM;
1660 }
1661
1662 return 0;
1663 }
1664
1665 static void stmmac_exit_fs(void)
1666 {
1667 debugfs_remove(stmmac_rings_status);
1668 debugfs_remove(stmmac_dma_cap);
1669 debugfs_remove(stmmac_fs_dir);
1670 }
1671 #endif /* CONFIG_STMMAC_DEBUG_FS */
1672
1673 static const struct net_device_ops stmmac_netdev_ops = {
1674 .ndo_open = stmmac_open,
1675 .ndo_start_xmit = stmmac_xmit,
1676 .ndo_stop = stmmac_release,
1677 .ndo_change_mtu = stmmac_change_mtu,
1678 .ndo_fix_features = stmmac_fix_features,
1679 .ndo_set_rx_mode = stmmac_set_rx_mode,
1680 .ndo_tx_timeout = stmmac_tx_timeout,
1681 .ndo_do_ioctl = stmmac_ioctl,
1682 .ndo_set_config = stmmac_config,
1683 #ifdef CONFIG_NET_POLL_CONTROLLER
1684 .ndo_poll_controller = stmmac_poll_controller,
1685 #endif
1686 .ndo_set_mac_address = eth_mac_addr,
1687 };
1688
1689 /**
1690 * stmmac_probe - Initialization of the adapter .
1691 * @dev : device pointer
1692 * Description: The function initializes the network device structure for
1693 * the STMMAC driver. It also calls the low level routines
1694 * in order to init the HW (i.e. the DMA engine)
1695 */
1696 static int stmmac_probe(struct net_device *dev)
1697 {
1698 int ret = 0;
1699 struct stmmac_priv *priv = netdev_priv(dev);
1700
1701 ether_setup(dev);
1702
1703 dev->netdev_ops = &stmmac_netdev_ops;
1704 stmmac_set_ethtool_ops(dev);
1705
1706 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1707 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
1708 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1709 #ifdef STMMAC_VLAN_TAG_USED
1710 /* Both mac100 and gmac support receive VLAN tag detection */
1711 dev->features |= NETIF_F_HW_VLAN_RX;
1712 #endif
1713 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1714
1715 if (flow_ctrl)
1716 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
1717
1718 priv->pause = pause;
1719 netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1720
1721 /* Get the MAC address */
1722 priv->hw->mac->get_umac_addr((void __iomem *) dev->base_addr,
1723 dev->dev_addr, 0);
1724
1725 if (!is_valid_ether_addr(dev->dev_addr))
1726 pr_warning("\tno valid MAC address;"
1727 "please, use ifconfig or nwhwconfig!\n");
1728
1729 spin_lock_init(&priv->lock);
1730 spin_lock_init(&priv->tx_lock);
1731
1732 ret = register_netdev(dev);
1733 if (ret) {
1734 pr_err("%s: ERROR %i registering the device\n",
1735 __func__, ret);
1736 return -ENODEV;
1737 }
1738
1739 DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1740 dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
1741 (dev->features & NETIF_F_IP_CSUM) ? "on" : "off");
1742
1743 return ret;
1744 }
1745
1746 /**
1747 * stmmac_mac_device_setup
1748 * @dev : device pointer
1749 * Description: select and initialise the mac device (mac100 or Gmac).
1750 */
1751 static int stmmac_mac_device_setup(struct net_device *dev)
1752 {
1753 struct stmmac_priv *priv = netdev_priv(dev);
1754
1755 struct mac_device_info *device;
1756
1757 if (priv->plat->has_gmac) {
1758 dev->priv_flags |= IFF_UNICAST_FLT;
1759 device = dwmac1000_setup(priv->ioaddr);
1760 } else {
1761 device = dwmac100_setup(priv->ioaddr);
1762 }
1763
1764 if (!device)
1765 return -ENOMEM;
1766
1767 if (priv->plat->enh_desc) {
1768 device->desc = &enh_desc_ops;
1769 pr_info("\tEnhanced descriptor structure\n");
1770 } else
1771 device->desc = &ndesc_ops;
1772
1773 priv->hw = device;
1774 priv->hw->ring = &ring_mode_ops;
1775
1776 if (device_can_wakeup(priv->device)) {
1777 priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */
1778 enable_irq_wake(priv->wol_irq);
1779 }
1780
1781 return 0;
1782 }
1783
1784 /**
1785 * stmmac_dvr_probe
1786 * @pdev: platform device pointer
1787 * Description: the driver is initialized through platform_device.
1788 */
1789 static int stmmac_dvr_probe(struct platform_device *pdev)
1790 {
1791 int ret = 0;
1792 struct resource *res;
1793 void __iomem *addr = NULL;
1794 struct net_device *ndev = NULL;
1795 struct stmmac_priv *priv = NULL;
1796 struct plat_stmmacenet_data *plat_dat;
1797
1798 pr_info("STMMAC driver:\n\tplatform registration... ");
1799 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1800 if (!res)
1801 return -ENODEV;
1802 pr_info("\tdone!\n");
1803
1804 if (!request_mem_region(res->start, resource_size(res),
1805 pdev->name)) {
1806 pr_err("%s: ERROR: memory allocation failed"
1807 "cannot get the I/O addr 0x%x\n",
1808 __func__, (unsigned int)res->start);
1809 return -EBUSY;
1810 }
1811
1812 addr = ioremap(res->start, resource_size(res));
1813 if (!addr) {
1814 pr_err("%s: ERROR: memory mapping failed\n", __func__);
1815 ret = -ENOMEM;
1816 goto out_release_region;
1817 }
1818
1819 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1820 if (!ndev) {
1821 pr_err("%s: ERROR: allocating the device\n", __func__);
1822 ret = -ENOMEM;
1823 goto out_unmap;
1824 }
1825
1826 SET_NETDEV_DEV(ndev, &pdev->dev);
1827
1828 /* Get the MAC information */
1829 ndev->irq = platform_get_irq_byname(pdev, "macirq");
1830 if (ndev->irq == -ENXIO) {
1831 pr_err("%s: ERROR: MAC IRQ configuration "
1832 "information not found\n", __func__);
1833 ret = -ENXIO;
1834 goto out_free_ndev;
1835 }
1836
1837 priv = netdev_priv(ndev);
1838 priv->device = &(pdev->dev);
1839 priv->dev = ndev;
1840 plat_dat = pdev->dev.platform_data;
1841
1842 priv->plat = plat_dat;
1843
1844 priv->ioaddr = addr;
1845
1846 /* PMT module is not integrated in all the MAC devices. */
1847 if (plat_dat->pmt) {
1848 pr_info("\tPMT module supported\n");
1849 device_set_wakeup_capable(&pdev->dev, 1);
1850 }
1851 /*
1852 * On some platforms e.g. SPEAr the wake up irq differs from the mac irq
1853 * The external wake up irq can be passed through the platform code
1854 * named as "eth_wake_irq"
1855 *
1856 * In case the wake up interrupt is not passed from the platform
1857 * so the driver will continue to use the mac irq (ndev->irq)
1858 */
1859 priv->wol_irq = platform_get_irq_byname(pdev, "eth_wake_irq");
1860 if (priv->wol_irq == -ENXIO)
1861 priv->wol_irq = ndev->irq;
1862
1863
1864 platform_set_drvdata(pdev, ndev);
1865
1866 /* Set the I/O base addr */
1867 ndev->base_addr = (unsigned long)addr;
1868
1869 /* Custom initialisation */
1870 if (priv->plat->init) {
1871 ret = priv->plat->init(pdev);
1872 if (unlikely(ret))
1873 goto out_free_ndev;
1874 }
1875
1876 /* MAC HW revice detection */
1877 ret = stmmac_mac_device_setup(ndev);
1878 if (ret < 0)
1879 goto out_plat_exit;
1880
1881 /* Network Device Registration */
1882 ret = stmmac_probe(ndev);
1883 if (ret < 0)
1884 goto out_plat_exit;
1885
1886 /* Override with kernel parameters if supplied XXX CRS XXX
1887 * this needs to have multiple instances */
1888 if ((phyaddr >= 0) && (phyaddr <= 31))
1889 priv->plat->phy_addr = phyaddr;
1890
1891 pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
1892 "\tIO base addr: 0x%p)\n", ndev->name, pdev->name,
1893 pdev->id, ndev->irq, addr);
1894
1895 /* MDIO bus Registration */
1896 pr_debug("\tMDIO bus (id: %d)...", priv->plat->bus_id);
1897 ret = stmmac_mdio_register(ndev);
1898 if (ret < 0)
1899 goto out_unregister;
1900 pr_debug("registered!\n");
1901
1902 #ifdef CONFIG_STMMAC_DEBUG_FS
1903 ret = stmmac_init_fs(ndev);
1904 if (ret < 0)
1905 pr_warning("\tFailed debugFS registration");
1906 #endif
1907
1908 return 0;
1909
1910 out_unregister:
1911 unregister_netdev(ndev);
1912 out_plat_exit:
1913 if (priv->plat->exit)
1914 priv->plat->exit(pdev);
1915 out_free_ndev:
1916 free_netdev(ndev);
1917 platform_set_drvdata(pdev, NULL);
1918 out_unmap:
1919 iounmap(addr);
1920 out_release_region:
1921 release_mem_region(res->start, resource_size(res));
1922
1923 return ret;
1924 }
1925
1926 /**
1927 * stmmac_dvr_remove
1928 * @pdev: platform device pointer
1929 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1930 * changes the link status, releases the DMA descriptor rings,
1931 * unregisters the MDIO bus and unmaps the allocated memory.
1932 */
1933 static int stmmac_dvr_remove(struct platform_device *pdev)
1934 {
1935 struct net_device *ndev = platform_get_drvdata(pdev);
1936 struct stmmac_priv *priv = netdev_priv(ndev);
1937 struct resource *res;
1938
1939 pr_info("%s:\n\tremoving driver", __func__);
1940
1941 priv->hw->dma->stop_rx(priv->ioaddr);
1942 priv->hw->dma->stop_tx(priv->ioaddr);
1943
1944 stmmac_disable_mac(priv->ioaddr);
1945
1946 netif_carrier_off(ndev);
1947
1948 stmmac_mdio_unregister(ndev);
1949
1950 if (priv->plat->exit)
1951 priv->plat->exit(pdev);
1952
1953 platform_set_drvdata(pdev, NULL);
1954 unregister_netdev(ndev);
1955
1956 iounmap((void *)priv->ioaddr);
1957 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1958 release_mem_region(res->start, resource_size(res));
1959
1960 #ifdef CONFIG_STMMAC_DEBUG_FS
1961 stmmac_exit_fs();
1962 #endif
1963
1964 free_netdev(ndev);
1965
1966 return 0;
1967 }
1968
1969 #ifdef CONFIG_PM
1970 static int stmmac_suspend(struct device *dev)
1971 {
1972 struct net_device *ndev = dev_get_drvdata(dev);
1973 struct stmmac_priv *priv = netdev_priv(ndev);
1974 int dis_ic = 0;
1975
1976 if (!ndev || !netif_running(ndev))
1977 return 0;
1978
1979 spin_lock(&priv->lock);
1980
1981 netif_device_detach(ndev);
1982 netif_stop_queue(ndev);
1983 if (priv->phydev)
1984 phy_stop(priv->phydev);
1985
1986 #ifdef CONFIG_STMMAC_TIMER
1987 priv->tm->timer_stop();
1988 if (likely(priv->tm->enable))
1989 dis_ic = 1;
1990 #endif
1991 napi_disable(&priv->napi);
1992
1993 /* Stop TX/RX DMA */
1994 priv->hw->dma->stop_tx(priv->ioaddr);
1995 priv->hw->dma->stop_rx(priv->ioaddr);
1996 /* Clear the Rx/Tx descriptors */
1997 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
1998 dis_ic);
1999 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
2000
2001 /* Enable Power down mode by programming the PMT regs */
2002 if (device_may_wakeup(priv->device))
2003 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2004 else
2005 stmmac_disable_mac(priv->ioaddr);
2006
2007 spin_unlock(&priv->lock);
2008 return 0;
2009 }
2010
2011 static int stmmac_resume(struct device *dev)
2012 {
2013 struct net_device *ndev = dev_get_drvdata(dev);
2014 struct stmmac_priv *priv = netdev_priv(ndev);
2015
2016 if (!netif_running(ndev))
2017 return 0;
2018
2019 spin_lock(&priv->lock);
2020
2021 /* Power Down bit, into the PM register, is cleared
2022 * automatically as soon as a magic packet or a Wake-up frame
2023 * is received. Anyway, it's better to manually clear
2024 * this bit because it can generate problems while resuming
2025 * from another devices (e.g. serial console). */
2026 if (device_may_wakeup(priv->device))
2027 priv->hw->mac->pmt(priv->ioaddr, 0);
2028
2029 netif_device_attach(ndev);
2030
2031 /* Enable the MAC and DMA */
2032 stmmac_enable_mac(priv->ioaddr);
2033 priv->hw->dma->start_tx(priv->ioaddr);
2034 priv->hw->dma->start_rx(priv->ioaddr);
2035
2036 #ifdef CONFIG_STMMAC_TIMER
2037 if (likely(priv->tm->enable))
2038 priv->tm->timer_start(tmrate);
2039 #endif
2040 napi_enable(&priv->napi);
2041
2042 if (priv->phydev)
2043 phy_start(priv->phydev);
2044
2045 netif_start_queue(ndev);
2046
2047 spin_unlock(&priv->lock);
2048 return 0;
2049 }
2050
2051 static int stmmac_freeze(struct device *dev)
2052 {
2053 struct net_device *ndev = dev_get_drvdata(dev);
2054
2055 if (!ndev || !netif_running(ndev))
2056 return 0;
2057
2058 return stmmac_release(ndev);
2059 }
2060
2061 static int stmmac_restore(struct device *dev)
2062 {
2063 struct net_device *ndev = dev_get_drvdata(dev);
2064
2065 if (!ndev || !netif_running(ndev))
2066 return 0;
2067
2068 return stmmac_open(ndev);
2069 }
2070
2071 static const struct dev_pm_ops stmmac_pm_ops = {
2072 .suspend = stmmac_suspend,
2073 .resume = stmmac_resume,
2074 .freeze = stmmac_freeze,
2075 .thaw = stmmac_restore,
2076 .restore = stmmac_restore,
2077 };
2078 #else
2079 static const struct dev_pm_ops stmmac_pm_ops;
2080 #endif /* CONFIG_PM */
2081
2082 static struct platform_driver stmmac_driver = {
2083 .probe = stmmac_dvr_probe,
2084 .remove = stmmac_dvr_remove,
2085 .driver = {
2086 .name = STMMAC_RESOURCE_NAME,
2087 .owner = THIS_MODULE,
2088 .pm = &stmmac_pm_ops,
2089 },
2090 };
2091
2092 /**
2093 * stmmac_init_module - Entry point for the driver
2094 * Description: This function is the entry point for the driver.
2095 */
2096 static int __init stmmac_init_module(void)
2097 {
2098 int ret;
2099
2100 ret = platform_driver_register(&stmmac_driver);
2101 return ret;
2102 }
2103
2104 /**
2105 * stmmac_cleanup_module - Cleanup routine for the driver
2106 * Description: This function is the cleanup routine for the driver.
2107 */
2108 static void __exit stmmac_cleanup_module(void)
2109 {
2110 platform_driver_unregister(&stmmac_driver);
2111 }
2112
2113 #ifndef MODULE
2114 static int __init stmmac_cmdline_opt(char *str)
2115 {
2116 char *opt;
2117
2118 if (!str || !*str)
2119 return -EINVAL;
2120 while ((opt = strsep(&str, ",")) != NULL) {
2121 if (!strncmp(opt, "debug:", 6)) {
2122 if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug))
2123 goto err;
2124 } else if (!strncmp(opt, "phyaddr:", 8)) {
2125 if (strict_strtoul(opt + 8, 0,
2126 (unsigned long *)&phyaddr))
2127 goto err;
2128 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2129 if (strict_strtoul(opt + 11, 0,
2130 (unsigned long *)&dma_txsize))
2131 goto err;
2132 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2133 if (strict_strtoul(opt + 11, 0,
2134 (unsigned long *)&dma_rxsize))
2135 goto err;
2136 } else if (!strncmp(opt, "buf_sz:", 7)) {
2137 if (strict_strtoul(opt + 7, 0,
2138 (unsigned long *)&buf_sz))
2139 goto err;
2140 } else if (!strncmp(opt, "tc:", 3)) {
2141 if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc))
2142 goto err;
2143 } else if (!strncmp(opt, "watchdog:", 9)) {
2144 if (strict_strtoul(opt + 9, 0,
2145 (unsigned long *)&watchdog))
2146 goto err;
2147 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2148 if (strict_strtoul(opt + 10, 0,
2149 (unsigned long *)&flow_ctrl))
2150 goto err;
2151 } else if (!strncmp(opt, "pause:", 6)) {
2152 if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause))
2153 goto err;
2154 #ifdef CONFIG_STMMAC_TIMER
2155 } else if (!strncmp(opt, "tmrate:", 7)) {
2156 if (strict_strtoul(opt + 7, 0,
2157 (unsigned long *)&tmrate))
2158 goto err;
2159 #endif
2160 }
2161 }
2162 return 0;
2163
2164 err:
2165 pr_err("%s: ERROR broken module parameter conversion", __func__);
2166 return -EINVAL;
2167 }
2168
2169 __setup("stmmaceth=", stmmac_cmdline_opt);
2170 #endif
2171
2172 module_init(stmmac_init_module);
2173 module_exit(stmmac_cleanup_module);
2174
2175 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver");
2176 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2177 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree