arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2005 Texas Instruments, Inc.
   9  * Richard Woodruff <r-woodruff2@ti.com>
  10  *
  11  * Based on pm.c for omap1
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17
  18 #include <linux/pm.h>
  19 #include <linux/suspend.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/module.h>
  22 #include <linux/list.h>
  23 #include <linux/err.h>
  24 #include <linux/gpio.h>
  25
  26 #include <mach/sram.h>
  27 #include <mach/clockdomain.h>
  28 #include <mach/powerdomain.h>
  29 #include <mach/control.h>
  30 #include <mach/serial.h>
  31
  32 #include "cm.h"
  33 #include "cm-regbits-34xx.h"
  34 #include "prm-regbits-34xx.h"
  35
  36 #include "prm.h"
  37 #include "pm.h"
  38
  39 struct power_state {
  40         struct powerdomain *pwrdm;
  41         u32 next_state;
  42 #ifdef CONFIG_SUSPEND
  43         u32 saved_state;
  44 #endif
  45         struct list_head node;
  46 };
  47
  48 static LIST_HEAD(pwrst_list);
  49
  50 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  51
  52 static struct powerdomain *mpu_pwrdm;
  53
  54 /*
  55  * PRCM Interrupt Handler Helper Function
  56  *
  57  * The purpose of this function is to clear any wake-up events latched
  58  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
  59  * may occur whilst attempting to clear a PM_WKST_x register and thus
  60  * set another bit in this register. A while loop is used to ensure
  61  * that any peripheral wake-up events occurring while attempting to
  62  * clear the PM_WKST_x are detected and cleared.
  63  */
  64 static void prcm_clear_mod_irqs(s16 module, u8 regs)
  65 {
  66         u32 wkst, fclk, iclk;
  67         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
  68         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
  69         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
  70         u16 grpsel_off = (regs == 3) ?
  71                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
  72
  73         wkst = prm_read_mod_reg(module, wkst_off);
  74         wkst &= prm_read_mod_reg(module, grpsel_off);
  75         if (wkst) {
  76                 iclk = cm_read_mod_reg(module, iclk_off);
  77                 fclk = cm_read_mod_reg(module, fclk_off);
  78                 while (wkst) {
  79                         cm_set_mod_reg_bits(wkst, module, iclk_off);
  80                         cm_set_mod_reg_bits(wkst, module, fclk_off);
  81                         prm_write_mod_reg(wkst, module, wkst_off);
  82                         wkst = prm_read_mod_reg(module, wkst_off);
  83                 }
  84                 cm_write_mod_reg(iclk, module, iclk_off);
  85                 cm_write_mod_reg(fclk, module, fclk_off);
  86         }
  87 }
  88
  89 /*
  90  * PRCM Interrupt Handler
  91  *
  92  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
  93  * interrupts from the PRCM for the MPU. These bits must be cleared in
  94  * order to clear the PRCM interrupt. The PRCM interrupt handler is
  95  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
  96  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
  97  * register indicates that a wake-up event is pending for the MPU and
  98  * this bit can only be cleared if the all the wake-up events latched
  99  * in the various PM_WKST_x registers have been cleared. The interrupt
 100  * handler is implemented using a do-while loop so that if a wake-up
 101  * event occurred during the processing of the prcm interrupt handler
 102  * (setting a bit in the corresponding PM_WKST_x register and thus
 103  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 104  * this would be handled.
 105  */
 106 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 107 {
 108         u32 irqstatus_mpu;
 109
 110         do {
 111                 prcm_clear_mod_irqs(WKUP_MOD, 1);
 112                 prcm_clear_mod_irqs(CORE_MOD, 1);
 113                 prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 114                 if (omap_rev() > OMAP3430_REV_ES1_0) {
 115                         prcm_clear_mod_irqs(CORE_MOD, 3);
 116                         prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 117                 }
 118
 119                 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 120                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 121                 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 122                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 123
 124         } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
 125
 126         return IRQ_HANDLED;
 127 }
 128
 129 static void omap_sram_idle(void)
 130 {
 131         /* Variable to tell what needs to be saved and restored
 132          * in omap_sram_idle*/
 133         /* save_state = 0 => Nothing to save and restored */
 134         /* save_state = 1 => Only L1 and logic lost */
 135         /* save_state = 2 => Only L2 lost */
 136         /* save_state = 3 => L1, L2 and logic lost */
 137         int save_state = 0, mpu_next_state;
 138
 139         if (!_omap_sram_idle)
 140                 return;
 141
 142         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 143         switch (mpu_next_state) {
 144         case PWRDM_POWER_RET:
 145                 /* No need to save context */
 146                 save_state = 0;
 147                 break;
 148         default:
 149                 /* Invalid state */
 150                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 151                 return;
 152         }
 153         pwrdm_pre_transition();
 154
 155         omap2_gpio_prepare_for_retention();
 156         omap_uart_prepare_idle(0);
 157         omap_uart_prepare_idle(1);
 158         omap_uart_prepare_idle(2);
 159
 160         _omap_sram_idle(NULL, save_state);
 161         cpu_init();
 162
 163         omap_uart_resume_idle(2);
 164         omap_uart_resume_idle(1);
 165         omap_uart_resume_idle(0);
 166         omap2_gpio_resume_after_retention();
 167
 168         pwrdm_post_transition();
 169
 170 }
 171
 172 /*
 173  * Check if functional clocks are enabled before entering
 174  * sleep. This function could be behind CONFIG_PM_DEBUG
 175  * when all drivers are configuring their sysconfig registers
 176  * properly and using their clocks properly.
 177  */
 178 static int omap3_fclks_active(void)
 179 {
 180         u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
 181                 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
 182
 183         fck_core1 = cm_read_mod_reg(CORE_MOD,
 184                                     CM_FCLKEN1);
 185         if (omap_rev() > OMAP3430_REV_ES1_0) {
 186                 fck_core3 = cm_read_mod_reg(CORE_MOD,
 187                                             OMAP3430ES2_CM_FCLKEN3);
 188                 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
 189                                           CM_FCLKEN);
 190                 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 191                                               CM_FCLKEN);
 192         } else
 193                 fck_sgx = cm_read_mod_reg(GFX_MOD,
 194                                           OMAP3430ES2_CM_FCLKEN3);
 195         fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
 196                                   CM_FCLKEN);
 197         fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
 198                                   CM_FCLKEN);
 199         fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
 200                                   CM_FCLKEN);
 201
 202         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
 203         fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
 204         fck_per &= ~OMAP3430_EN_UART3;
 205
 206         if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
 207             fck_cam | fck_per | fck_usbhost)
 208                 return 1;
 209         return 0;
 210 }
 211
 212 static int omap3_can_sleep(void)
 213 {
 214         if (!omap_uart_can_sleep())
 215                 return 0;
 216         if (omap3_fclks_active())
 217                 return 0;
 218         return 1;
 219 }
 220
 221 /* This sets pwrdm state (other than mpu & core. Currently only ON &
 222  * RET are supported. Function is assuming that clkdm doesn't have
 223  * hw_sup mode enabled. */
 224 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 225 {
 226         u32 cur_state;
 227         int sleep_switch = 0;
 228         int ret = 0;
 229
 230         if (pwrdm == NULL || IS_ERR(pwrdm))
 231                 return -EINVAL;
 232
 233         while (!(pwrdm->pwrsts & (1 << state))) {
 234                 if (state == PWRDM_POWER_OFF)
 235                         return ret;
 236                 state--;
 237         }
 238
 239         cur_state = pwrdm_read_next_pwrst(pwrdm);
 240         if (cur_state == state)
 241                 return ret;
 242
 243         if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
 244                 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
 245                 sleep_switch = 1;
 246                 pwrdm_wait_transition(pwrdm);
 247         }
 248
 249         ret = pwrdm_set_next_pwrst(pwrdm, state);
 250         if (ret) {
 251                 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
 252                        pwrdm->name);
 253                 goto err;
 254         }
 255
 256         if (sleep_switch) {
 257                 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
 258                 pwrdm_wait_transition(pwrdm);
 259                 pwrdm_state_switch(pwrdm);
 260         }
 261
 262 err:
 263         return ret;
 264 }
 265
 266 static void omap3_pm_idle(void)
 267 {
 268         local_irq_disable();
 269         local_fiq_disable();
 270
 271         if (!omap3_can_sleep())
 272                 goto out;
 273
 274         if (omap_irq_pending())
 275                 goto out;
 276
 277         omap_sram_idle();
 278
 279 out:
 280         local_fiq_enable();
 281         local_irq_enable();
 282 }
 283
 284 #ifdef CONFIG_SUSPEND
 285 static suspend_state_t suspend_state;
 286
 287 static int omap3_pm_prepare(void)
 288 {
 289         disable_hlt();
 290         return 0;
 291 }
 292
 293 static int omap3_pm_suspend(void)
 294 {
 295         struct power_state *pwrst;
 296         int state, ret = 0;
 297
 298         /* Read current next_pwrsts */
 299         list_for_each_entry(pwrst, &pwrst_list, node)
 300                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 301         /* Set ones wanted by suspend */
 302         list_for_each_entry(pwrst, &pwrst_list, node) {
 303                 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 304                         goto restore;
 305                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 306                         goto restore;
 307         }
 308
 309         omap_uart_prepare_suspend();
 310         omap_sram_idle();
 311
 312 restore:
 313         /* Restore next_pwrsts */
 314         list_for_each_entry(pwrst, &pwrst_list, node) {
 315                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 316                 if (state > pwrst->next_state) {
 317                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 318                                "target state %d\n",
 319                                pwrst->pwrdm->name, pwrst->next_state);
 320                         ret = -1;
 321                 }
 322                 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 323         }
 324         if (ret)
 325                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 326         else
 327                 printk(KERN_INFO "Successfully put all powerdomains "
 328                        "to target state\n");
 329
 330         return ret;
 331 }
 332
 333 static int omap3_pm_enter(suspend_state_t unused)
 334 {
 335         int ret = 0;
 336
 337         switch (suspend_state) {
 338         case PM_SUSPEND_STANDBY:
 339         case PM_SUSPEND_MEM:
 340                 ret = omap3_pm_suspend();
 341                 break;
 342         default:
 343                 ret = -EINVAL;
 344         }
 345
 346         return ret;
 347 }
 348
 349 static void omap3_pm_finish(void)
 350 {
 351         enable_hlt();
 352 }
 353
 354 /* Hooks to enable / disable UART interrupts during suspend */
 355 static int omap3_pm_begin(suspend_state_t state)
 356 {
 357         suspend_state = state;
 358         omap_uart_enable_irqs(0);
 359         return 0;
 360 }
 361
 362 static void omap3_pm_end(void)
 363 {
 364         suspend_state = PM_SUSPEND_ON;
 365         omap_uart_enable_irqs(1);
 366         return;
 367 }
 368
 369 static struct platform_suspend_ops omap_pm_ops = {
 370         .begin          = omap3_pm_begin,
 371         .end            = omap3_pm_end,
 372         .prepare        = omap3_pm_prepare,
 373         .enter          = omap3_pm_enter,
 374         .finish         = omap3_pm_finish,
 375         .valid          = suspend_valid_only_mem,
 376 };
 377 #endif /* CONFIG_SUSPEND */
 378
 379
 380 /**
 381  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 382  *                   retention
 383  *
 384  * In cases where IVA2 is activated by bootcode, it may prevent
 385  * full-chip retention or off-mode because it is not idle.  This
 386  * function forces the IVA2 into idle state so it can go
 387  * into retention/off and thus allow full-chip retention/off.
 388  *
 389  **/
 390 static void __init omap3_iva_idle(void)
 391 {
 392         /* ensure IVA2 clock is disabled */
 393         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 394
 395         /* if no clock activity, nothing else to do */
 396         if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 397               OMAP3430_CLKACTIVITY_IVA2_MASK))
 398                 return;
 399
 400         /* Reset IVA2 */
 401         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 402                           OMAP3430_RST2_IVA2 |
 403                           OMAP3430_RST3_IVA2,
 404                           OMAP3430_IVA2_MOD, RM_RSTCTRL);
 405
 406         /* Enable IVA2 clock */
 407         cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
 408                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 409
 410         /* Set IVA2 boot mode to 'idle' */
 411         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 412                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 413
 414         /* Un-reset IVA2 */
 415         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
 416
 417         /* Disable IVA2 clock */
 418         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 419
 420         /* Reset IVA2 */
 421         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 422                           OMAP3430_RST2_IVA2 |
 423                           OMAP3430_RST3_IVA2,
 424                           OMAP3430_IVA2_MOD, RM_RSTCTRL);
 425 }
 426
 427 static void __init omap3_d2d_idle(void)
 428 {
 429         u16 mask, padconf;
 430
 431         /* In a stand alone OMAP3430 where there is not a stacked
 432          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 433          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 434          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 435         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 436         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 437         padconf |= mask;
 438         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 439
 440         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 441         padconf |= mask;
 442         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 443
 444         /* reset modem */
 445         prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
 446                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
 447                           CORE_MOD, RM_RSTCTRL);
 448         prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
 449 }
 450
 451 static void __init prcm_setup_regs(void)
 452 {
 453         /* XXX Reset all wkdeps. This should be done when initializing
 454          * powerdomains */
 455         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
 456         prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
 457         prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
 458         prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
 459         prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
 460         prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
 461         if (omap_rev() > OMAP3430_REV_ES1_0) {
 462                 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
 463                 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 464         } else
 465                 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 466
 467         /*
 468          * Enable interface clock autoidle for all modules.
 469          * Note that in the long run this should be done by clockfw
 470          */
 471         cm_write_mod_reg(
 472                 OMAP3430_AUTO_MODEM |
 473                 OMAP3430ES2_AUTO_MMC3 |
 474                 OMAP3430ES2_AUTO_ICR |
 475                 OMAP3430_AUTO_AES2 |
 476                 OMAP3430_AUTO_SHA12 |
 477                 OMAP3430_AUTO_DES2 |
 478                 OMAP3430_AUTO_MMC2 |
 479                 OMAP3430_AUTO_MMC1 |
 480                 OMAP3430_AUTO_MSPRO |
 481                 OMAP3430_AUTO_HDQ |
 482                 OMAP3430_AUTO_MCSPI4 |
 483                 OMAP3430_AUTO_MCSPI3 |
 484                 OMAP3430_AUTO_MCSPI2 |
 485                 OMAP3430_AUTO_MCSPI1 |
 486                 OMAP3430_AUTO_I2C3 |
 487                 OMAP3430_AUTO_I2C2 |
 488                 OMAP3430_AUTO_I2C1 |
 489                 OMAP3430_AUTO_UART2 |
 490                 OMAP3430_AUTO_UART1 |
 491                 OMAP3430_AUTO_GPT11 |
 492                 OMAP3430_AUTO_GPT10 |
 493                 OMAP3430_AUTO_MCBSP5 |
 494                 OMAP3430_AUTO_MCBSP1 |
 495                 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
 496                 OMAP3430_AUTO_MAILBOXES |
 497                 OMAP3430_AUTO_OMAPCTRL |
 498                 OMAP3430ES1_AUTO_FSHOSTUSB |
 499                 OMAP3430_AUTO_HSOTGUSB |
 500                 OMAP3430_AUTO_SAD2D |
 501                 OMAP3430_AUTO_SSI,
 502                 CORE_MOD, CM_AUTOIDLE1);
 503
 504         cm_write_mod_reg(
 505                 OMAP3430_AUTO_PKA |
 506                 OMAP3430_AUTO_AES1 |
 507                 OMAP3430_AUTO_RNG |
 508                 OMAP3430_AUTO_SHA11 |
 509                 OMAP3430_AUTO_DES1,
 510                 CORE_MOD, CM_AUTOIDLE2);
 511
 512         if (omap_rev() > OMAP3430_REV_ES1_0) {
 513                 cm_write_mod_reg(
 514                         OMAP3430_AUTO_MAD2D |
 515                         OMAP3430ES2_AUTO_USBTLL,
 516                         CORE_MOD, CM_AUTOIDLE3);
 517         }
 518
 519         cm_write_mod_reg(
 520                 OMAP3430_AUTO_WDT2 |
 521                 OMAP3430_AUTO_WDT1 |
 522                 OMAP3430_AUTO_GPIO1 |
 523                 OMAP3430_AUTO_32KSYNC |
 524                 OMAP3430_AUTO_GPT12 |
 525                 OMAP3430_AUTO_GPT1 ,
 526                 WKUP_MOD, CM_AUTOIDLE);
 527
 528         cm_write_mod_reg(
 529                 OMAP3430_AUTO_DSS,
 530                 OMAP3430_DSS_MOD,
 531                 CM_AUTOIDLE);
 532
 533         cm_write_mod_reg(
 534                 OMAP3430_AUTO_CAM,
 535                 OMAP3430_CAM_MOD,
 536                 CM_AUTOIDLE);
 537
 538         cm_write_mod_reg(
 539                 OMAP3430_AUTO_GPIO6 |
 540                 OMAP3430_AUTO_GPIO5 |
 541                 OMAP3430_AUTO_GPIO4 |
 542                 OMAP3430_AUTO_GPIO3 |
 543                 OMAP3430_AUTO_GPIO2 |
 544                 OMAP3430_AUTO_WDT3 |
 545                 OMAP3430_AUTO_UART3 |
 546                 OMAP3430_AUTO_GPT9 |
 547                 OMAP3430_AUTO_GPT8 |
 548                 OMAP3430_AUTO_GPT7 |
 549                 OMAP3430_AUTO_GPT6 |
 550                 OMAP3430_AUTO_GPT5 |
 551                 OMAP3430_AUTO_GPT4 |
 552                 OMAP3430_AUTO_GPT3 |
 553                 OMAP3430_AUTO_GPT2 |
 554                 OMAP3430_AUTO_MCBSP4 |
 555                 OMAP3430_AUTO_MCBSP3 |
 556                 OMAP3430_AUTO_MCBSP2,
 557                 OMAP3430_PER_MOD,
 558                 CM_AUTOIDLE);
 559
 560         if (omap_rev() > OMAP3430_REV_ES1_0) {
 561                 cm_write_mod_reg(
 562                         OMAP3430ES2_AUTO_USBHOST,
 563                         OMAP3430ES2_USBHOST_MOD,
 564                         CM_AUTOIDLE);
 565         }
 566
 567         /*
 568          * Set all plls to autoidle. This is needed until autoidle is
 569          * enabled by clockfw
 570          */
 571         cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
 572                          OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 573         cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
 574                          MPU_MOD,
 575                          CM_AUTOIDLE2);
 576         cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
 577                          (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 578                          PLL_MOD,
 579                          CM_AUTOIDLE);
 580         cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
 581                          PLL_MOD,
 582                          CM_AUTOIDLE2);
 583
 584         /*
 585          * Enable control of expternal oscillator through
 586          * sys_clkreq. In the long run clock framework should
 587          * take care of this.
 588          */
 589         prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 590                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 591                              OMAP3430_GR_MOD,
 592                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 593
 594         /* setup wakup source */
 595         prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
 596                           OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
 597                           WKUP_MOD, PM_WKEN);
 598         /* No need to write EN_IO, that is always enabled */
 599         prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
 600                           OMAP3430_EN_GPT12,
 601                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 602         /* For some reason IO doesn't generate wakeup event even if
 603          * it is selected to mpu wakeup goup */
 604         prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
 605                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 606
 607         /* Don't attach IVA interrupts */
 608         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 609         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 610         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 611         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 612
 613         /* Clear any pending 'reset' flags */
 614         prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
 615         prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
 616         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
 617         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
 618         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
 619         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
 620         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
 621
 622         /* Clear any pending PRCM interrupts */
 623         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 624
 625         /* Don't attach IVA interrupts */
 626         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 627         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 628         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 629         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 630
 631         /* Clear any pending 'reset' flags */
 632         prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
 633         prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
 634         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
 635         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
 636         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
 637         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
 638         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
 639
 640         /* Clear any pending PRCM interrupts */
 641         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 642
 643         omap3_iva_idle();
 644         omap3_d2d_idle();
 645 }
 646
 647 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 648 {
 649         struct power_state *pwrst;
 650
 651         list_for_each_entry(pwrst, &pwrst_list, node) {
 652                 if (pwrst->pwrdm == pwrdm)
 653                         return pwrst->next_state;
 654         }
 655         return -EINVAL;
 656 }
 657
 658 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 659 {
 660         struct power_state *pwrst;
 661
 662         list_for_each_entry(pwrst, &pwrst_list, node) {
 663                 if (pwrst->pwrdm == pwrdm) {
 664                         pwrst->next_state = state;
 665                         return 0;
 666                 }
 667         }
 668         return -EINVAL;
 669 }
 670
 671 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 672 {
 673         struct power_state *pwrst;
 674
 675         if (!pwrdm->pwrsts)
 676                 return 0;
 677
 678         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 679         if (!pwrst)
 680                 return -ENOMEM;
 681         pwrst->pwrdm = pwrdm;
 682         pwrst->next_state = PWRDM_POWER_RET;
 683         list_add(&pwrst->node, &pwrst_list);
 684
 685         if (pwrdm_has_hdwr_sar(pwrdm))
 686                 pwrdm_enable_hdwr_sar(pwrdm);
 687
 688         return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 689 }
 690
 691 /*
 692  * Enable hw supervised mode for all clockdomains if it's
 693  * supported. Initiate sleep transition for other clockdomains, if
 694  * they are not used
 695  */
 696 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 697 {
 698         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 699                 omap2_clkdm_allow_idle(clkdm);
 700         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 701                  atomic_read(&clkdm->usecount) == 0)
 702                 omap2_clkdm_sleep(clkdm);
 703         return 0;
 704 }
 705
 706 static int __init omap3_pm_init(void)
 707 {
 708         struct power_state *pwrst, *tmp;
 709         int ret;
 710
 711         if (!cpu_is_omap34xx())
 712                 return -ENODEV;
 713
 714         printk(KERN_ERR "Power Management for TI OMAP3.\n");
 715
 716         /* XXX prcm_setup_regs needs to be before enabling hw
 717          * supervised mode for powerdomains */
 718         prcm_setup_regs();
 719
 720         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 721                           (irq_handler_t)prcm_interrupt_handler,
 722                           IRQF_DISABLED, "prcm", NULL);
 723         if (ret) {
 724                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 725                        INT_34XX_PRCM_MPU_IRQ);
 726                 goto err1;
 727         }
 728
 729         ret = pwrdm_for_each(pwrdms_setup, NULL);
 730         if (ret) {
 731                 printk(KERN_ERR "Failed to setup powerdomains\n");
 732                 goto err2;
 733         }
 734
 735         (void) clkdm_for_each(clkdms_setup, NULL);
 736
 737         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 738         if (mpu_pwrdm == NULL) {
 739                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
 740                 goto err2;
 741         }
 742
 743         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
 744                                          omap34xx_cpu_suspend_sz);
 745
 746 #ifdef CONFIG_SUSPEND
 747         suspend_set_ops(&omap_pm_ops);
 748 #endif /* CONFIG_SUSPEND */
 749
 750         pm_idle = omap3_pm_idle;
 751
 752 err1:
 753         return ret;
 754 err2:
 755         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
 756         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 757                 list_del(&pwrst->node);
 758                 kfree(pwrst);
 759         }
 760         return ret;
 761 }
 762
 763 late_initcall(omap3_pm_init);