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net: use DMA_x_DEVICE and dma_mapping_error with skb_frag_dma_map
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ethernet / marvell / skge.c
blob32db4c877ff1c313cb97e6e87f91b26d391281dc
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
28 #include <linux/in.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
36 #include <linux/if_vlan.h>
37 #include <linux/ip.h>
38 #include <linux/delay.h>
39 #include <linux/crc32.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/debugfs.h>
42 #include <linux/sched.h>
43 #include <linux/seq_file.h>
44 #include <linux/mii.h>
45 #include <linux/slab.h>
46 #include <linux/dmi.h>
47 #include <linux/prefetch.h>
48 #include <asm/irq.h>
49
50 #include "skge.h"
51
52 #define DRV_NAME "skge"
53 #define DRV_VERSION "1.14"
54
55 #define DEFAULT_TX_RING_SIZE 128
56 #define DEFAULT_RX_RING_SIZE 512
57 #define MAX_TX_RING_SIZE 1024
58 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
59 #define MAX_RX_RING_SIZE 4096
60 #define RX_COPY_THRESHOLD 128
61 #define RX_BUF_SIZE 1536
62 #define PHY_RETRIES 1000
63 #define ETH_JUMBO_MTU 9000
64 #define TX_WATCHDOG (5 * HZ)
65 #define NAPI_WEIGHT 64
66 #define BLINK_MS 250
67 #define LINK_HZ HZ
68
69 #define SKGE_EEPROM_MAGIC 0x9933aabb
70
71
72 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
73 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
74 MODULE_LICENSE("GPL");
75 MODULE_VERSION(DRV_VERSION);
76
77 static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
78 NETIF_MSG_LINK | NETIF_MSG_IFUP |
79 NETIF_MSG_IFDOWN);
80
81 static int debug = -1; /* defaults above */
82 module_param(debug, int, 0);
83 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
84
85 static DEFINE_PCI_DEVICE_TABLE(skge_id_table) = {
86 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */
87 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */
88 #ifdef CONFIG_SKGE_GENESIS
89 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */
90 #endif
91 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */
92 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */
93 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */
94 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) }, /* D-Link DGE-530T Rev C1 */
95 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, /* Marvell Yukon 88E8001/8003/8010 */
96 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
97 { PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, /* CNet PowerG-2000 */
98 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) }, /* Linksys EG1064 v2 */
99 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */
100 { 0 }
101 };
102 MODULE_DEVICE_TABLE(pci, skge_id_table);
103
104 static int skge_up(struct net_device *dev);
105 static int skge_down(struct net_device *dev);
106 static void skge_phy_reset(struct skge_port *skge);
107 static void skge_tx_clean(struct net_device *dev);
108 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
109 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
110 static void genesis_get_stats(struct skge_port *skge, u64 *data);
111 static void yukon_get_stats(struct skge_port *skge, u64 *data);
112 static void yukon_init(struct skge_hw *hw, int port);
113 static void genesis_mac_init(struct skge_hw *hw, int port);
114 static void genesis_link_up(struct skge_port *skge);
115 static void skge_set_multicast(struct net_device *dev);
116 static irqreturn_t skge_intr(int irq, void *dev_id);
117
118 /* Avoid conditionals by using array */
119 static const int txqaddr[] = { Q_XA1, Q_XA2 };
120 static const int rxqaddr[] = { Q_R1, Q_R2 };
121 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
122 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
123 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
124 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
125
126 static inline bool is_genesis(const struct skge_hw *hw)
127 {
128 #ifdef CONFIG_SKGE_GENESIS
129 return hw->chip_id == CHIP_ID_GENESIS;
130 #else
131 return false;
132 #endif
133 }
134
135 static int skge_get_regs_len(struct net_device *dev)
136 {
137 return 0x4000;
138 }
139
140 /*
141 * Returns copy of whole control register region
142 * Note: skip RAM address register because accessing it will
143 * cause bus hangs!
144 */
145 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
146 void *p)
147 {
148 const struct skge_port *skge = netdev_priv(dev);
149 const void __iomem *io = skge->hw->regs;
150
151 regs->version = 1;
152 memset(p, 0, regs->len);
153 memcpy_fromio(p, io, B3_RAM_ADDR);
154
155 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
156 regs->len - B3_RI_WTO_R1);
157 }
158
159 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
160 static u32 wol_supported(const struct skge_hw *hw)
161 {
162 if (is_genesis(hw))
163 return 0;
164
165 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
166 return 0;
167
168 return WAKE_MAGIC | WAKE_PHY;
169 }
170
171 static void skge_wol_init(struct skge_port *skge)
172 {
173 struct skge_hw *hw = skge->hw;
174 int port = skge->port;
175 u16 ctrl;
176
177 skge_write16(hw, B0_CTST, CS_RST_CLR);
178 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
179
180 /* Turn on Vaux */
181 skge_write8(hw, B0_POWER_CTRL,
182 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
183
184 /* WA code for COMA mode -- clear PHY reset */
185 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
186 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
187 u32 reg = skge_read32(hw, B2_GP_IO);
188 reg |= GP_DIR_9;
189 reg &= ~GP_IO_9;
190 skge_write32(hw, B2_GP_IO, reg);
191 }
192
193 skge_write32(hw, SK_REG(port, GPHY_CTRL),
194 GPC_DIS_SLEEP |
195 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
196 GPC_ANEG_1 | GPC_RST_SET);
197
198 skge_write32(hw, SK_REG(port, GPHY_CTRL),
199 GPC_DIS_SLEEP |
200 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
201 GPC_ANEG_1 | GPC_RST_CLR);
202
203 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
204
205 /* Force to 10/100 skge_reset will re-enable on resume */
206 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
207 (PHY_AN_100FULL | PHY_AN_100HALF |
208 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
209 /* no 1000 HD/FD */
210 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
211 gm_phy_write(hw, port, PHY_MARV_CTRL,
212 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
213 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
214
215
216 /* Set GMAC to no flow control and auto update for speed/duplex */
217 gma_write16(hw, port, GM_GP_CTRL,
218 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
219 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
220
221 /* Set WOL address */
222 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
223 skge->netdev->dev_addr, ETH_ALEN);
224
225 /* Turn on appropriate WOL control bits */
226 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
227 ctrl = 0;
228 if (skge->wol & WAKE_PHY)
229 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
230 else
231 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
232
233 if (skge->wol & WAKE_MAGIC)
234 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
235 else
236 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
237
238 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
239 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
240
241 /* block receiver */
242 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
243 }
244
245 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
246 {
247 struct skge_port *skge = netdev_priv(dev);
248
249 wol->supported = wol_supported(skge->hw);
250 wol->wolopts = skge->wol;
251 }
252
253 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
254 {
255 struct skge_port *skge = netdev_priv(dev);
256 struct skge_hw *hw = skge->hw;
257
258 if ((wol->wolopts & ~wol_supported(hw)) ||
259 !device_can_wakeup(&hw->pdev->dev))
260 return -EOPNOTSUPP;
261
262 skge->wol = wol->wolopts;
263
264 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
265
266 return 0;
267 }
268
269 /* Determine supported/advertised modes based on hardware.
270 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
271 */
272 static u32 skge_supported_modes(const struct skge_hw *hw)
273 {
274 u32 supported;
275
276 if (hw->copper) {
277 supported = (SUPPORTED_10baseT_Half |
278 SUPPORTED_10baseT_Full |
279 SUPPORTED_100baseT_Half |
280 SUPPORTED_100baseT_Full |
281 SUPPORTED_1000baseT_Half |
282 SUPPORTED_1000baseT_Full |
283 SUPPORTED_Autoneg |
284 SUPPORTED_TP);
285
286 if (is_genesis(hw))
287 supported &= ~(SUPPORTED_10baseT_Half |
288 SUPPORTED_10baseT_Full |
289 SUPPORTED_100baseT_Half |
290 SUPPORTED_100baseT_Full);
291
292 else if (hw->chip_id == CHIP_ID_YUKON)
293 supported &= ~SUPPORTED_1000baseT_Half;
294 } else
295 supported = (SUPPORTED_1000baseT_Full |
296 SUPPORTED_1000baseT_Half |
297 SUPPORTED_FIBRE |
298 SUPPORTED_Autoneg);
299
300 return supported;
301 }
302
303 static int skge_get_settings(struct net_device *dev,
304 struct ethtool_cmd *ecmd)
305 {
306 struct skge_port *skge = netdev_priv(dev);
307 struct skge_hw *hw = skge->hw;
308
309 ecmd->transceiver = XCVR_INTERNAL;
310 ecmd->supported = skge_supported_modes(hw);
311
312 if (hw->copper) {
313 ecmd->port = PORT_TP;
314 ecmd->phy_address = hw->phy_addr;
315 } else
316 ecmd->port = PORT_FIBRE;
317
318 ecmd->advertising = skge->advertising;
319 ecmd->autoneg = skge->autoneg;
320 ethtool_cmd_speed_set(ecmd, skge->speed);
321 ecmd->duplex = skge->duplex;
322 return 0;
323 }
324
325 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
326 {
327 struct skge_port *skge = netdev_priv(dev);
328 const struct skge_hw *hw = skge->hw;
329 u32 supported = skge_supported_modes(hw);
330 int err = 0;
331
332 if (ecmd->autoneg == AUTONEG_ENABLE) {
333 ecmd->advertising = supported;
334 skge->duplex = -1;
335 skge->speed = -1;
336 } else {
337 u32 setting;
338 u32 speed = ethtool_cmd_speed(ecmd);
339
340 switch (speed) {
341 case SPEED_1000:
342 if (ecmd->duplex == DUPLEX_FULL)
343 setting = SUPPORTED_1000baseT_Full;
344 else if (ecmd->duplex == DUPLEX_HALF)
345 setting = SUPPORTED_1000baseT_Half;
346 else
347 return -EINVAL;
348 break;
349 case SPEED_100:
350 if (ecmd->duplex == DUPLEX_FULL)
351 setting = SUPPORTED_100baseT_Full;
352 else if (ecmd->duplex == DUPLEX_HALF)
353 setting = SUPPORTED_100baseT_Half;
354 else
355 return -EINVAL;
356 break;
357
358 case SPEED_10:
359 if (ecmd->duplex == DUPLEX_FULL)
360 setting = SUPPORTED_10baseT_Full;
361 else if (ecmd->duplex == DUPLEX_HALF)
362 setting = SUPPORTED_10baseT_Half;
363 else
364 return -EINVAL;
365 break;
366 default:
367 return -EINVAL;
368 }
369
370 if ((setting & supported) == 0)
371 return -EINVAL;
372
373 skge->speed = speed;
374 skge->duplex = ecmd->duplex;
375 }
376
377 skge->autoneg = ecmd->autoneg;
378 skge->advertising = ecmd->advertising;
379
380 if (netif_running(dev)) {
381 skge_down(dev);
382 err = skge_up(dev);
383 if (err) {
384 dev_close(dev);
385 return err;
386 }
387 }
388
389 return 0;
390 }
391
392 static void skge_get_drvinfo(struct net_device *dev,
393 struct ethtool_drvinfo *info)
394 {
395 struct skge_port *skge = netdev_priv(dev);
396
397 strcpy(info->driver, DRV_NAME);
398 strcpy(info->version, DRV_VERSION);
399 strcpy(info->fw_version, "N/A");
400 strcpy(info->bus_info, pci_name(skge->hw->pdev));
401 }
402
403 static const struct skge_stat {
404 char name[ETH_GSTRING_LEN];
405 u16 xmac_offset;
406 u16 gma_offset;
407 } skge_stats[] = {
408 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
409 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
410
411 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
412 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
413 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
414 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
415 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
416 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
417 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
418 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
419
420 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
421 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
422 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
423 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
424 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
425 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
426
427 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
428 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
429 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
430 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
431 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
432 };
433
434 static int skge_get_sset_count(struct net_device *dev, int sset)
435 {
436 switch (sset) {
437 case ETH_SS_STATS:
438 return ARRAY_SIZE(skge_stats);
439 default:
440 return -EOPNOTSUPP;
441 }
442 }
443
444 static void skge_get_ethtool_stats(struct net_device *dev,
445 struct ethtool_stats *stats, u64 *data)
446 {
447 struct skge_port *skge = netdev_priv(dev);
448
449 if (is_genesis(skge->hw))
450 genesis_get_stats(skge, data);
451 else
452 yukon_get_stats(skge, data);
453 }
454
455 /* Use hardware MIB variables for critical path statistics and
456 * transmit feedback not reported at interrupt.
457 * Other errors are accounted for in interrupt handler.
458 */
459 static struct net_device_stats *skge_get_stats(struct net_device *dev)
460 {
461 struct skge_port *skge = netdev_priv(dev);
462 u64 data[ARRAY_SIZE(skge_stats)];
463
464 if (is_genesis(skge->hw))
465 genesis_get_stats(skge, data);
466 else
467 yukon_get_stats(skge, data);
468
469 dev->stats.tx_bytes = data[0];
470 dev->stats.rx_bytes = data[1];
471 dev->stats.tx_packets = data[2] + data[4] + data[6];
472 dev->stats.rx_packets = data[3] + data[5] + data[7];
473 dev->stats.multicast = data[3] + data[5];
474 dev->stats.collisions = data[10];
475 dev->stats.tx_aborted_errors = data[12];
476
477 return &dev->stats;
478 }
479
480 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
481 {
482 int i;
483
484 switch (stringset) {
485 case ETH_SS_STATS:
486 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
487 memcpy(data + i * ETH_GSTRING_LEN,
488 skge_stats[i].name, ETH_GSTRING_LEN);
489 break;
490 }
491 }
492
493 static void skge_get_ring_param(struct net_device *dev,
494 struct ethtool_ringparam *p)
495 {
496 struct skge_port *skge = netdev_priv(dev);
497
498 p->rx_max_pending = MAX_RX_RING_SIZE;
499 p->tx_max_pending = MAX_TX_RING_SIZE;
500 p->rx_mini_max_pending = 0;
501 p->rx_jumbo_max_pending = 0;
502
503 p->rx_pending = skge->rx_ring.count;
504 p->tx_pending = skge->tx_ring.count;
505 p->rx_mini_pending = 0;
506 p->rx_jumbo_pending = 0;
507 }
508
509 static int skge_set_ring_param(struct net_device *dev,
510 struct ethtool_ringparam *p)
511 {
512 struct skge_port *skge = netdev_priv(dev);
513 int err = 0;
514
515 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
516 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
517 return -EINVAL;
518
519 skge->rx_ring.count = p->rx_pending;
520 skge->tx_ring.count = p->tx_pending;
521
522 if (netif_running(dev)) {
523 skge_down(dev);
524 err = skge_up(dev);
525 if (err)
526 dev_close(dev);
527 }
528
529 return err;
530 }
531
532 static u32 skge_get_msglevel(struct net_device *netdev)
533 {
534 struct skge_port *skge = netdev_priv(netdev);
535 return skge->msg_enable;
536 }
537
538 static void skge_set_msglevel(struct net_device *netdev, u32 value)
539 {
540 struct skge_port *skge = netdev_priv(netdev);
541 skge->msg_enable = value;
542 }
543
544 static int skge_nway_reset(struct net_device *dev)
545 {
546 struct skge_port *skge = netdev_priv(dev);
547
548 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
549 return -EINVAL;
550
551 skge_phy_reset(skge);
552 return 0;
553 }
554
555 static void skge_get_pauseparam(struct net_device *dev,
556 struct ethtool_pauseparam *ecmd)
557 {
558 struct skge_port *skge = netdev_priv(dev);
559
560 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
561 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
562 ecmd->tx_pause = (ecmd->rx_pause ||
563 (skge->flow_control == FLOW_MODE_LOC_SEND));
564
565 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
566 }
567
568 static int skge_set_pauseparam(struct net_device *dev,
569 struct ethtool_pauseparam *ecmd)
570 {
571 struct skge_port *skge = netdev_priv(dev);
572 struct ethtool_pauseparam old;
573 int err = 0;
574
575 skge_get_pauseparam(dev, &old);
576
577 if (ecmd->autoneg != old.autoneg)
578 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
579 else {
580 if (ecmd->rx_pause && ecmd->tx_pause)
581 skge->flow_control = FLOW_MODE_SYMMETRIC;
582 else if (ecmd->rx_pause && !ecmd->tx_pause)
583 skge->flow_control = FLOW_MODE_SYM_OR_REM;
584 else if (!ecmd->rx_pause && ecmd->tx_pause)
585 skge->flow_control = FLOW_MODE_LOC_SEND;
586 else
587 skge->flow_control = FLOW_MODE_NONE;
588 }
589
590 if (netif_running(dev)) {
591 skge_down(dev);
592 err = skge_up(dev);
593 if (err) {
594 dev_close(dev);
595 return err;
596 }
597 }
598
599 return 0;
600 }
601
602 /* Chip internal frequency for clock calculations */
603 static inline u32 hwkhz(const struct skge_hw *hw)
604 {
605 return is_genesis(hw) ? 53125 : 78125;
606 }
607
608 /* Chip HZ to microseconds */
609 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
610 {
611 return (ticks * 1000) / hwkhz(hw);
612 }
613
614 /* Microseconds to chip HZ */
615 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
616 {
617 return hwkhz(hw) * usec / 1000;
618 }
619
620 static int skge_get_coalesce(struct net_device *dev,
621 struct ethtool_coalesce *ecmd)
622 {
623 struct skge_port *skge = netdev_priv(dev);
624 struct skge_hw *hw = skge->hw;
625 int port = skge->port;
626
627 ecmd->rx_coalesce_usecs = 0;
628 ecmd->tx_coalesce_usecs = 0;
629
630 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
631 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
632 u32 msk = skge_read32(hw, B2_IRQM_MSK);
633
634 if (msk & rxirqmask[port])
635 ecmd->rx_coalesce_usecs = delay;
636 if (msk & txirqmask[port])
637 ecmd->tx_coalesce_usecs = delay;
638 }
639
640 return 0;
641 }
642
643 /* Note: interrupt timer is per board, but can turn on/off per port */
644 static int skge_set_coalesce(struct net_device *dev,
645 struct ethtool_coalesce *ecmd)
646 {
647 struct skge_port *skge = netdev_priv(dev);
648 struct skge_hw *hw = skge->hw;
649 int port = skge->port;
650 u32 msk = skge_read32(hw, B2_IRQM_MSK);
651 u32 delay = 25;
652
653 if (ecmd->rx_coalesce_usecs == 0)
654 msk &= ~rxirqmask[port];
655 else if (ecmd->rx_coalesce_usecs < 25 ||
656 ecmd->rx_coalesce_usecs > 33333)
657 return -EINVAL;
658 else {
659 msk |= rxirqmask[port];
660 delay = ecmd->rx_coalesce_usecs;
661 }
662
663 if (ecmd->tx_coalesce_usecs == 0)
664 msk &= ~txirqmask[port];
665 else if (ecmd->tx_coalesce_usecs < 25 ||
666 ecmd->tx_coalesce_usecs > 33333)
667 return -EINVAL;
668 else {
669 msk |= txirqmask[port];
670 delay = min(delay, ecmd->rx_coalesce_usecs);
671 }
672
673 skge_write32(hw, B2_IRQM_MSK, msk);
674 if (msk == 0)
675 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
676 else {
677 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
678 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
679 }
680 return 0;
681 }
682
683 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
684 static void skge_led(struct skge_port *skge, enum led_mode mode)
685 {
686 struct skge_hw *hw = skge->hw;
687 int port = skge->port;
688
689 spin_lock_bh(&hw->phy_lock);
690 if (is_genesis(hw)) {
691 switch (mode) {
692 case LED_MODE_OFF:
693 if (hw->phy_type == SK_PHY_BCOM)
694 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
695 else {
696 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
697 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
698 }
699 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
700 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
701 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
702 break;
703
704 case LED_MODE_ON:
705 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
706 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
707
708 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
709 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
710
711 break;
712
713 case LED_MODE_TST:
714 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
715 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
716 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
717
718 if (hw->phy_type == SK_PHY_BCOM)
719 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
720 else {
721 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
722 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
723 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
724 }
725
726 }
727 } else {
728 switch (mode) {
729 case LED_MODE_OFF:
730 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
731 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
732 PHY_M_LED_MO_DUP(MO_LED_OFF) |
733 PHY_M_LED_MO_10(MO_LED_OFF) |
734 PHY_M_LED_MO_100(MO_LED_OFF) |
735 PHY_M_LED_MO_1000(MO_LED_OFF) |
736 PHY_M_LED_MO_RX(MO_LED_OFF));
737 break;
738 case LED_MODE_ON:
739 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
740 PHY_M_LED_PULS_DUR(PULS_170MS) |
741 PHY_M_LED_BLINK_RT(BLINK_84MS) |
742 PHY_M_LEDC_TX_CTRL |
743 PHY_M_LEDC_DP_CTRL);
744
745 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
746 PHY_M_LED_MO_RX(MO_LED_OFF) |
747 (skge->speed == SPEED_100 ?
748 PHY_M_LED_MO_100(MO_LED_ON) : 0));
749 break;
750 case LED_MODE_TST:
751 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
752 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
753 PHY_M_LED_MO_DUP(MO_LED_ON) |
754 PHY_M_LED_MO_10(MO_LED_ON) |
755 PHY_M_LED_MO_100(MO_LED_ON) |
756 PHY_M_LED_MO_1000(MO_LED_ON) |
757 PHY_M_LED_MO_RX(MO_LED_ON));
758 }
759 }
760 spin_unlock_bh(&hw->phy_lock);
761 }
762
763 /* blink LED's for finding board */
764 static int skge_set_phys_id(struct net_device *dev,
765 enum ethtool_phys_id_state state)
766 {
767 struct skge_port *skge = netdev_priv(dev);
768
769 switch (state) {
770 case ETHTOOL_ID_ACTIVE:
771 return 2; /* cycle on/off twice per second */
772
773 case ETHTOOL_ID_ON:
774 skge_led(skge, LED_MODE_TST);
775 break;
776
777 case ETHTOOL_ID_OFF:
778 skge_led(skge, LED_MODE_OFF);
779 break;
780
781 case ETHTOOL_ID_INACTIVE:
782 /* back to regular LED state */
783 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
784 }
785
786 return 0;
787 }
788
789 static int skge_get_eeprom_len(struct net_device *dev)
790 {
791 struct skge_port *skge = netdev_priv(dev);
792 u32 reg2;
793
794 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
795 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
796 }
797
798 static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
799 {
800 u32 val;
801
802 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
803
804 do {
805 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
806 } while (!(offset & PCI_VPD_ADDR_F));
807
808 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
809 return val;
810 }
811
812 static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
813 {
814 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
815 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
816 offset | PCI_VPD_ADDR_F);
817
818 do {
819 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
820 } while (offset & PCI_VPD_ADDR_F);
821 }
822
823 static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
824 u8 *data)
825 {
826 struct skge_port *skge = netdev_priv(dev);
827 struct pci_dev *pdev = skge->hw->pdev;
828 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
829 int length = eeprom->len;
830 u16 offset = eeprom->offset;
831
832 if (!cap)
833 return -EINVAL;
834
835 eeprom->magic = SKGE_EEPROM_MAGIC;
836
837 while (length > 0) {
838 u32 val = skge_vpd_read(pdev, cap, offset);
839 int n = min_t(int, length, sizeof(val));
840
841 memcpy(data, &val, n);
842 length -= n;
843 data += n;
844 offset += n;
845 }
846 return 0;
847 }
848
849 static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
850 u8 *data)
851 {
852 struct skge_port *skge = netdev_priv(dev);
853 struct pci_dev *pdev = skge->hw->pdev;
854 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
855 int length = eeprom->len;
856 u16 offset = eeprom->offset;
857
858 if (!cap)
859 return -EINVAL;
860
861 if (eeprom->magic != SKGE_EEPROM_MAGIC)
862 return -EINVAL;
863
864 while (length > 0) {
865 u32 val;
866 int n = min_t(int, length, sizeof(val));
867
868 if (n < sizeof(val))
869 val = skge_vpd_read(pdev, cap, offset);
870 memcpy(&val, data, n);
871
872 skge_vpd_write(pdev, cap, offset, val);
873
874 length -= n;
875 data += n;
876 offset += n;
877 }
878 return 0;
879 }
880
881 static const struct ethtool_ops skge_ethtool_ops = {
882 .get_settings = skge_get_settings,
883 .set_settings = skge_set_settings,
884 .get_drvinfo = skge_get_drvinfo,
885 .get_regs_len = skge_get_regs_len,
886 .get_regs = skge_get_regs,
887 .get_wol = skge_get_wol,
888 .set_wol = skge_set_wol,
889 .get_msglevel = skge_get_msglevel,
890 .set_msglevel = skge_set_msglevel,
891 .nway_reset = skge_nway_reset,
892 .get_link = ethtool_op_get_link,
893 .get_eeprom_len = skge_get_eeprom_len,
894 .get_eeprom = skge_get_eeprom,
895 .set_eeprom = skge_set_eeprom,
896 .get_ringparam = skge_get_ring_param,
897 .set_ringparam = skge_set_ring_param,
898 .get_pauseparam = skge_get_pauseparam,
899 .set_pauseparam = skge_set_pauseparam,
900 .get_coalesce = skge_get_coalesce,
901 .set_coalesce = skge_set_coalesce,
902 .get_strings = skge_get_strings,
903 .set_phys_id = skge_set_phys_id,
904 .get_sset_count = skge_get_sset_count,
905 .get_ethtool_stats = skge_get_ethtool_stats,
906 };
907
908 /*
909 * Allocate ring elements and chain them together
910 * One-to-one association of board descriptors with ring elements
911 */
912 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
913 {
914 struct skge_tx_desc *d;
915 struct skge_element *e;
916 int i;
917
918 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
919 if (!ring->start)
920 return -ENOMEM;
921
922 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
923 e->desc = d;
924 if (i == ring->count - 1) {
925 e->next = ring->start;
926 d->next_offset = base;
927 } else {
928 e->next = e + 1;
929 d->next_offset = base + (i+1) * sizeof(*d);
930 }
931 }
932 ring->to_use = ring->to_clean = ring->start;
933
934 return 0;
935 }
936
937 /* Allocate and setup a new buffer for receiving */
938 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
939 struct sk_buff *skb, unsigned int bufsize)
940 {
941 struct skge_rx_desc *rd = e->desc;
942 u64 map;
943
944 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
945 PCI_DMA_FROMDEVICE);
946
947 rd->dma_lo = map;
948 rd->dma_hi = map >> 32;
949 e->skb = skb;
950 rd->csum1_start = ETH_HLEN;
951 rd->csum2_start = ETH_HLEN;
952 rd->csum1 = 0;
953 rd->csum2 = 0;
954
955 wmb();
956
957 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
958 dma_unmap_addr_set(e, mapaddr, map);
959 dma_unmap_len_set(e, maplen, bufsize);
960 }
961
962 /* Resume receiving using existing skb,
963 * Note: DMA address is not changed by chip.
964 * MTU not changed while receiver active.
965 */
966 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
967 {
968 struct skge_rx_desc *rd = e->desc;
969
970 rd->csum2 = 0;
971 rd->csum2_start = ETH_HLEN;
972
973 wmb();
974
975 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
976 }
977
978
979 /* Free all buffers in receive ring, assumes receiver stopped */
980 static void skge_rx_clean(struct skge_port *skge)
981 {
982 struct skge_hw *hw = skge->hw;
983 struct skge_ring *ring = &skge->rx_ring;
984 struct skge_element *e;
985
986 e = ring->start;
987 do {
988 struct skge_rx_desc *rd = e->desc;
989 rd->control = 0;
990 if (e->skb) {
991 pci_unmap_single(hw->pdev,
992 dma_unmap_addr(e, mapaddr),
993 dma_unmap_len(e, maplen),
994 PCI_DMA_FROMDEVICE);
995 dev_kfree_skb(e->skb);
996 e->skb = NULL;
997 }
998 } while ((e = e->next) != ring->start);
999 }
1000
1001
1002 /* Allocate buffers for receive ring
1003 * For receive: to_clean is next received frame.
1004 */
1005 static int skge_rx_fill(struct net_device *dev)
1006 {
1007 struct skge_port *skge = netdev_priv(dev);
1008 struct skge_ring *ring = &skge->rx_ring;
1009 struct skge_element *e;
1010
1011 e = ring->start;
1012 do {
1013 struct sk_buff *skb;
1014
1015 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1016 GFP_KERNEL);
1017 if (!skb)
1018 return -ENOMEM;
1019
1020 skb_reserve(skb, NET_IP_ALIGN);
1021 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
1022 } while ((e = e->next) != ring->start);
1023
1024 ring->to_clean = ring->start;
1025 return 0;
1026 }
1027
1028 static const char *skge_pause(enum pause_status status)
1029 {
1030 switch (status) {
1031 case FLOW_STAT_NONE:
1032 return "none";
1033 case FLOW_STAT_REM_SEND:
1034 return "rx only";
1035 case FLOW_STAT_LOC_SEND:
1036 return "tx_only";
1037 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1038 return "both";
1039 default:
1040 return "indeterminated";
1041 }
1042 }
1043
1044
1045 static void skge_link_up(struct skge_port *skge)
1046 {
1047 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1048 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1049
1050 netif_carrier_on(skge->netdev);
1051 netif_wake_queue(skge->netdev);
1052
1053 netif_info(skge, link, skge->netdev,
1054 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1055 skge->speed,
1056 skge->duplex == DUPLEX_FULL ? "full" : "half",
1057 skge_pause(skge->flow_status));
1058 }
1059
1060 static void skge_link_down(struct skge_port *skge)
1061 {
1062 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
1063 netif_carrier_off(skge->netdev);
1064 netif_stop_queue(skge->netdev);
1065
1066 netif_info(skge, link, skge->netdev, "Link is down\n");
1067 }
1068
1069 static void xm_link_down(struct skge_hw *hw, int port)
1070 {
1071 struct net_device *dev = hw->dev[port];
1072 struct skge_port *skge = netdev_priv(dev);
1073
1074 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1075
1076 if (netif_carrier_ok(dev))
1077 skge_link_down(skge);
1078 }
1079
1080 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1081 {
1082 int i;
1083
1084 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1085 *val = xm_read16(hw, port, XM_PHY_DATA);
1086
1087 if (hw->phy_type == SK_PHY_XMAC)
1088 goto ready;
1089
1090 for (i = 0; i < PHY_RETRIES; i++) {
1091 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1092 goto ready;
1093 udelay(1);
1094 }
1095
1096 return -ETIMEDOUT;
1097 ready:
1098 *val = xm_read16(hw, port, XM_PHY_DATA);
1099
1100 return 0;
1101 }
1102
1103 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1104 {
1105 u16 v = 0;
1106 if (__xm_phy_read(hw, port, reg, &v))
1107 pr_warning("%s: phy read timed out\n", hw->dev[port]->name);
1108 return v;
1109 }
1110
1111 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1112 {
1113 int i;
1114
1115 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1116 for (i = 0; i < PHY_RETRIES; i++) {
1117 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1118 goto ready;
1119 udelay(1);
1120 }
1121 return -EIO;
1122
1123 ready:
1124 xm_write16(hw, port, XM_PHY_DATA, val);
1125 for (i = 0; i < PHY_RETRIES; i++) {
1126 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1127 return 0;
1128 udelay(1);
1129 }
1130 return -ETIMEDOUT;
1131 }
1132
1133 static void genesis_init(struct skge_hw *hw)
1134 {
1135 /* set blink source counter */
1136 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1137 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1138
1139 /* configure mac arbiter */
1140 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1141
1142 /* configure mac arbiter timeout values */
1143 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1144 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1145 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1146 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1147
1148 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1149 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1150 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1151 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1152
1153 /* configure packet arbiter timeout */
1154 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1155 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1156 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1157 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1158 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1159 }
1160
1161 static void genesis_reset(struct skge_hw *hw, int port)
1162 {
1163 static const u8 zero[8] = { 0 };
1164 u32 reg;
1165
1166 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1167
1168 /* reset the statistics module */
1169 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1170 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1171 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1172 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1173 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1174
1175 /* disable Broadcom PHY IRQ */
1176 if (hw->phy_type == SK_PHY_BCOM)
1177 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1178
1179 xm_outhash(hw, port, XM_HSM, zero);
1180
1181 /* Flush TX and RX fifo */
1182 reg = xm_read32(hw, port, XM_MODE);
1183 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1184 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1185 }
1186
1187 /* Convert mode to MII values */
1188 static const u16 phy_pause_map[] = {
1189 [FLOW_MODE_NONE] = 0,
1190 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1191 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1192 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1193 };
1194
1195 /* special defines for FIBER (88E1011S only) */
1196 static const u16 fiber_pause_map[] = {
1197 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1198 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1199 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1200 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1201 };
1202
1203
1204 /* Check status of Broadcom phy link */
1205 static void bcom_check_link(struct skge_hw *hw, int port)
1206 {
1207 struct net_device *dev = hw->dev[port];
1208 struct skge_port *skge = netdev_priv(dev);
1209 u16 status;
1210
1211 /* read twice because of latch */
1212 xm_phy_read(hw, port, PHY_BCOM_STAT);
1213 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1214
1215 if ((status & PHY_ST_LSYNC) == 0) {
1216 xm_link_down(hw, port);
1217 return;
1218 }
1219
1220 if (skge->autoneg == AUTONEG_ENABLE) {
1221 u16 lpa, aux;
1222
1223 if (!(status & PHY_ST_AN_OVER))
1224 return;
1225
1226 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1227 if (lpa & PHY_B_AN_RF) {
1228 netdev_notice(dev, "remote fault\n");
1229 return;
1230 }
1231
1232 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1233
1234 /* Check Duplex mismatch */
1235 switch (aux & PHY_B_AS_AN_RES_MSK) {
1236 case PHY_B_RES_1000FD:
1237 skge->duplex = DUPLEX_FULL;
1238 break;
1239 case PHY_B_RES_1000HD:
1240 skge->duplex = DUPLEX_HALF;
1241 break;
1242 default:
1243 netdev_notice(dev, "duplex mismatch\n");
1244 return;
1245 }
1246
1247 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1248 switch (aux & PHY_B_AS_PAUSE_MSK) {
1249 case PHY_B_AS_PAUSE_MSK:
1250 skge->flow_status = FLOW_STAT_SYMMETRIC;
1251 break;
1252 case PHY_B_AS_PRR:
1253 skge->flow_status = FLOW_STAT_REM_SEND;
1254 break;
1255 case PHY_B_AS_PRT:
1256 skge->flow_status = FLOW_STAT_LOC_SEND;
1257 break;
1258 default:
1259 skge->flow_status = FLOW_STAT_NONE;
1260 }
1261 skge->speed = SPEED_1000;
1262 }
1263
1264 if (!netif_carrier_ok(dev))
1265 genesis_link_up(skge);
1266 }
1267
1268 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1269 * Phy on for 100 or 10Mbit operation
1270 */
1271 static void bcom_phy_init(struct skge_port *skge)
1272 {
1273 struct skge_hw *hw = skge->hw;
1274 int port = skge->port;
1275 int i;
1276 u16 id1, r, ext, ctl;
1277
1278 /* magic workaround patterns for Broadcom */
1279 static const struct {
1280 u16 reg;
1281 u16 val;
1282 } A1hack[] = {
1283 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1284 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1285 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1286 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1287 }, C0hack[] = {
1288 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1289 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1290 };
1291
1292 /* read Id from external PHY (all have the same address) */
1293 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1294
1295 /* Optimize MDIO transfer by suppressing preamble. */
1296 r = xm_read16(hw, port, XM_MMU_CMD);
1297 r |= XM_MMU_NO_PRE;
1298 xm_write16(hw, port, XM_MMU_CMD, r);
1299
1300 switch (id1) {
1301 case PHY_BCOM_ID1_C0:
1302 /*
1303 * Workaround BCOM Errata for the C0 type.
1304 * Write magic patterns to reserved registers.
1305 */
1306 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1307 xm_phy_write(hw, port,
1308 C0hack[i].reg, C0hack[i].val);
1309
1310 break;
1311 case PHY_BCOM_ID1_A1:
1312 /*
1313 * Workaround BCOM Errata for the A1 type.
1314 * Write magic patterns to reserved registers.
1315 */
1316 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1317 xm_phy_write(hw, port,
1318 A1hack[i].reg, A1hack[i].val);
1319 break;
1320 }
1321
1322 /*
1323 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1324 * Disable Power Management after reset.
1325 */
1326 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1327 r |= PHY_B_AC_DIS_PM;
1328 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1329
1330 /* Dummy read */
1331 xm_read16(hw, port, XM_ISRC);
1332
1333 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1334 ctl = PHY_CT_SP1000; /* always 1000mbit */
1335
1336 if (skge->autoneg == AUTONEG_ENABLE) {
1337 /*
1338 * Workaround BCOM Errata #1 for the C5 type.
1339 * 1000Base-T Link Acquisition Failure in Slave Mode
1340 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1341 */
1342 u16 adv = PHY_B_1000C_RD;
1343 if (skge->advertising & ADVERTISED_1000baseT_Half)
1344 adv |= PHY_B_1000C_AHD;
1345 if (skge->advertising & ADVERTISED_1000baseT_Full)
1346 adv |= PHY_B_1000C_AFD;
1347 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1348
1349 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1350 } else {
1351 if (skge->duplex == DUPLEX_FULL)
1352 ctl |= PHY_CT_DUP_MD;
1353 /* Force to slave */
1354 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1355 }
1356
1357 /* Set autonegotiation pause parameters */
1358 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1359 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1360
1361 /* Handle Jumbo frames */
1362 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1363 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1364 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1365
1366 ext |= PHY_B_PEC_HIGH_LA;
1367
1368 }
1369
1370 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1371 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1372
1373 /* Use link status change interrupt */
1374 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1375 }
1376
1377 static void xm_phy_init(struct skge_port *skge)
1378 {
1379 struct skge_hw *hw = skge->hw;
1380 int port = skge->port;
1381 u16 ctrl = 0;
1382
1383 if (skge->autoneg == AUTONEG_ENABLE) {
1384 if (skge->advertising & ADVERTISED_1000baseT_Half)
1385 ctrl |= PHY_X_AN_HD;
1386 if (skge->advertising & ADVERTISED_1000baseT_Full)
1387 ctrl |= PHY_X_AN_FD;
1388
1389 ctrl |= fiber_pause_map[skge->flow_control];
1390
1391 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1392
1393 /* Restart Auto-negotiation */
1394 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1395 } else {
1396 /* Set DuplexMode in Config register */
1397 if (skge->duplex == DUPLEX_FULL)
1398 ctrl |= PHY_CT_DUP_MD;
1399 /*
1400 * Do NOT enable Auto-negotiation here. This would hold
1401 * the link down because no IDLEs are transmitted
1402 */
1403 }
1404
1405 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1406
1407 /* Poll PHY for status changes */
1408 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1409 }
1410
1411 static int xm_check_link(struct net_device *dev)
1412 {
1413 struct skge_port *skge = netdev_priv(dev);
1414 struct skge_hw *hw = skge->hw;
1415 int port = skge->port;
1416 u16 status;
1417
1418 /* read twice because of latch */
1419 xm_phy_read(hw, port, PHY_XMAC_STAT);
1420 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1421
1422 if ((status & PHY_ST_LSYNC) == 0) {
1423 xm_link_down(hw, port);
1424 return 0;
1425 }
1426
1427 if (skge->autoneg == AUTONEG_ENABLE) {
1428 u16 lpa, res;
1429
1430 if (!(status & PHY_ST_AN_OVER))
1431 return 0;
1432
1433 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1434 if (lpa & PHY_B_AN_RF) {
1435 netdev_notice(dev, "remote fault\n");
1436 return 0;
1437 }
1438
1439 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1440
1441 /* Check Duplex mismatch */
1442 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1443 case PHY_X_RS_FD:
1444 skge->duplex = DUPLEX_FULL;
1445 break;
1446 case PHY_X_RS_HD:
1447 skge->duplex = DUPLEX_HALF;
1448 break;
1449 default:
1450 netdev_notice(dev, "duplex mismatch\n");
1451 return 0;
1452 }
1453
1454 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1455 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1456 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1457 (lpa & PHY_X_P_SYM_MD))
1458 skge->flow_status = FLOW_STAT_SYMMETRIC;
1459 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1460 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1461 /* Enable PAUSE receive, disable PAUSE transmit */
1462 skge->flow_status = FLOW_STAT_REM_SEND;
1463 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1464 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1465 /* Disable PAUSE receive, enable PAUSE transmit */
1466 skge->flow_status = FLOW_STAT_LOC_SEND;
1467 else
1468 skge->flow_status = FLOW_STAT_NONE;
1469
1470 skge->speed = SPEED_1000;
1471 }
1472
1473 if (!netif_carrier_ok(dev))
1474 genesis_link_up(skge);
1475 return 1;
1476 }
1477
1478 /* Poll to check for link coming up.
1479 *
1480 * Since internal PHY is wired to a level triggered pin, can't
1481 * get an interrupt when carrier is detected, need to poll for
1482 * link coming up.
1483 */
1484 static void xm_link_timer(unsigned long arg)
1485 {
1486 struct skge_port *skge = (struct skge_port *) arg;
1487 struct net_device *dev = skge->netdev;
1488 struct skge_hw *hw = skge->hw;
1489 int port = skge->port;
1490 int i;
1491 unsigned long flags;
1492
1493 if (!netif_running(dev))
1494 return;
1495
1496 spin_lock_irqsave(&hw->phy_lock, flags);
1497
1498 /*
1499 * Verify that the link by checking GPIO register three times.
1500 * This pin has the signal from the link_sync pin connected to it.
1501 */
1502 for (i = 0; i < 3; i++) {
1503 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1504 goto link_down;
1505 }
1506
1507 /* Re-enable interrupt to detect link down */
1508 if (xm_check_link(dev)) {
1509 u16 msk = xm_read16(hw, port, XM_IMSK);
1510 msk &= ~XM_IS_INP_ASS;
1511 xm_write16(hw, port, XM_IMSK, msk);
1512 xm_read16(hw, port, XM_ISRC);
1513 } else {
1514 link_down:
1515 mod_timer(&skge->link_timer,
1516 round_jiffies(jiffies + LINK_HZ));
1517 }
1518 spin_unlock_irqrestore(&hw->phy_lock, flags);
1519 }
1520
1521 static void genesis_mac_init(struct skge_hw *hw, int port)
1522 {
1523 struct net_device *dev = hw->dev[port];
1524 struct skge_port *skge = netdev_priv(dev);
1525 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1526 int i;
1527 u32 r;
1528 static const u8 zero[6] = { 0 };
1529
1530 for (i = 0; i < 10; i++) {
1531 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1532 MFF_SET_MAC_RST);
1533 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1534 goto reset_ok;
1535 udelay(1);
1536 }
1537
1538 netdev_warn(dev, "genesis reset failed\n");
1539
1540 reset_ok:
1541 /* Unreset the XMAC. */
1542 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1543
1544 /*
1545 * Perform additional initialization for external PHYs,
1546 * namely for the 1000baseTX cards that use the XMAC's
1547 * GMII mode.
1548 */
1549 if (hw->phy_type != SK_PHY_XMAC) {
1550 /* Take external Phy out of reset */
1551 r = skge_read32(hw, B2_GP_IO);
1552 if (port == 0)
1553 r |= GP_DIR_0|GP_IO_0;
1554 else
1555 r |= GP_DIR_2|GP_IO_2;
1556
1557 skge_write32(hw, B2_GP_IO, r);
1558
1559 /* Enable GMII interface */
1560 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1561 }
1562
1563
1564 switch (hw->phy_type) {
1565 case SK_PHY_XMAC:
1566 xm_phy_init(skge);
1567 break;
1568 case SK_PHY_BCOM:
1569 bcom_phy_init(skge);
1570 bcom_check_link(hw, port);
1571 }
1572
1573 /* Set Station Address */
1574 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1575
1576 /* We don't use match addresses so clear */
1577 for (i = 1; i < 16; i++)
1578 xm_outaddr(hw, port, XM_EXM(i), zero);
1579
1580 /* Clear MIB counters */
1581 xm_write16(hw, port, XM_STAT_CMD,
1582 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1583 /* Clear two times according to Errata #3 */
1584 xm_write16(hw, port, XM_STAT_CMD,
1585 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1586
1587 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1588 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1589
1590 /* We don't need the FCS appended to the packet. */
1591 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1592 if (jumbo)
1593 r |= XM_RX_BIG_PK_OK;
1594
1595 if (skge->duplex == DUPLEX_HALF) {
1596 /*
1597 * If in manual half duplex mode the other side might be in
1598 * full duplex mode, so ignore if a carrier extension is not seen
1599 * on frames received
1600 */
1601 r |= XM_RX_DIS_CEXT;
1602 }
1603 xm_write16(hw, port, XM_RX_CMD, r);
1604
1605 /* We want short frames padded to 60 bytes. */
1606 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1607
1608 /* Increase threshold for jumbo frames on dual port */
1609 if (hw->ports > 1 && jumbo)
1610 xm_write16(hw, port, XM_TX_THR, 1020);
1611 else
1612 xm_write16(hw, port, XM_TX_THR, 512);
1613
1614 /*
1615 * Enable the reception of all error frames. This is is
1616 * a necessary evil due to the design of the XMAC. The
1617 * XMAC's receive FIFO is only 8K in size, however jumbo
1618 * frames can be up to 9000 bytes in length. When bad
1619 * frame filtering is enabled, the XMAC's RX FIFO operates
1620 * in 'store and forward' mode. For this to work, the
1621 * entire frame has to fit into the FIFO, but that means
1622 * that jumbo frames larger than 8192 bytes will be
1623 * truncated. Disabling all bad frame filtering causes
1624 * the RX FIFO to operate in streaming mode, in which
1625 * case the XMAC will start transferring frames out of the
1626 * RX FIFO as soon as the FIFO threshold is reached.
1627 */
1628 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1629
1630
1631 /*
1632 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1633 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1634 * and 'Octets Rx OK Hi Cnt Ov'.
1635 */
1636 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1637
1638 /*
1639 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1640 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1641 * and 'Octets Tx OK Hi Cnt Ov'.
1642 */
1643 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1644
1645 /* Configure MAC arbiter */
1646 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1647
1648 /* configure timeout values */
1649 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1650 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1651 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1652 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1653
1654 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1655 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1656 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1657 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1658
1659 /* Configure Rx MAC FIFO */
1660 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1661 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1662 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1663
1664 /* Configure Tx MAC FIFO */
1665 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1666 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1667 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1668
1669 if (jumbo) {
1670 /* Enable frame flushing if jumbo frames used */
1671 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
1672 } else {
1673 /* enable timeout timers if normal frames */
1674 skge_write16(hw, B3_PA_CTRL,
1675 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1676 }
1677 }
1678
1679 static void genesis_stop(struct skge_port *skge)
1680 {
1681 struct skge_hw *hw = skge->hw;
1682 int port = skge->port;
1683 unsigned retries = 1000;
1684 u16 cmd;
1685
1686 /* Disable Tx and Rx */
1687 cmd = xm_read16(hw, port, XM_MMU_CMD);
1688 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1689 xm_write16(hw, port, XM_MMU_CMD, cmd);
1690
1691 genesis_reset(hw, port);
1692
1693 /* Clear Tx packet arbiter timeout IRQ */
1694 skge_write16(hw, B3_PA_CTRL,
1695 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1696
1697 /* Reset the MAC */
1698 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1699 do {
1700 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1701 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1702 break;
1703 } while (--retries > 0);
1704
1705 /* For external PHYs there must be special handling */
1706 if (hw->phy_type != SK_PHY_XMAC) {
1707 u32 reg = skge_read32(hw, B2_GP_IO);
1708 if (port == 0) {
1709 reg |= GP_DIR_0;
1710 reg &= ~GP_IO_0;
1711 } else {
1712 reg |= GP_DIR_2;
1713 reg &= ~GP_IO_2;
1714 }
1715 skge_write32(hw, B2_GP_IO, reg);
1716 skge_read32(hw, B2_GP_IO);
1717 }
1718
1719 xm_write16(hw, port, XM_MMU_CMD,
1720 xm_read16(hw, port, XM_MMU_CMD)
1721 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1722
1723 xm_read16(hw, port, XM_MMU_CMD);
1724 }
1725
1726
1727 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1728 {
1729 struct skge_hw *hw = skge->hw;
1730 int port = skge->port;
1731 int i;
1732 unsigned long timeout = jiffies + HZ;
1733
1734 xm_write16(hw, port,
1735 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1736
1737 /* wait for update to complete */
1738 while (xm_read16(hw, port, XM_STAT_CMD)
1739 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1740 if (time_after(jiffies, timeout))
1741 break;
1742 udelay(10);
1743 }
1744
1745 /* special case for 64 bit octet counter */
1746 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1747 | xm_read32(hw, port, XM_TXO_OK_LO);
1748 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1749 | xm_read32(hw, port, XM_RXO_OK_LO);
1750
1751 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1752 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1753 }
1754
1755 static void genesis_mac_intr(struct skge_hw *hw, int port)
1756 {
1757 struct net_device *dev = hw->dev[port];
1758 struct skge_port *skge = netdev_priv(dev);
1759 u16 status = xm_read16(hw, port, XM_ISRC);
1760
1761 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1762 "mac interrupt status 0x%x\n", status);
1763
1764 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1765 xm_link_down(hw, port);
1766 mod_timer(&skge->link_timer, jiffies + 1);
1767 }
1768
1769 if (status & XM_IS_TXF_UR) {
1770 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1771 ++dev->stats.tx_fifo_errors;
1772 }
1773 }
1774
1775 static void genesis_link_up(struct skge_port *skge)
1776 {
1777 struct skge_hw *hw = skge->hw;
1778 int port = skge->port;
1779 u16 cmd, msk;
1780 u32 mode;
1781
1782 cmd = xm_read16(hw, port, XM_MMU_CMD);
1783
1784 /*
1785 * enabling pause frame reception is required for 1000BT
1786 * because the XMAC is not reset if the link is going down
1787 */
1788 if (skge->flow_status == FLOW_STAT_NONE ||
1789 skge->flow_status == FLOW_STAT_LOC_SEND)
1790 /* Disable Pause Frame Reception */
1791 cmd |= XM_MMU_IGN_PF;
1792 else
1793 /* Enable Pause Frame Reception */
1794 cmd &= ~XM_MMU_IGN_PF;
1795
1796 xm_write16(hw, port, XM_MMU_CMD, cmd);
1797
1798 mode = xm_read32(hw, port, XM_MODE);
1799 if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
1800 skge->flow_status == FLOW_STAT_LOC_SEND) {
1801 /*
1802 * Configure Pause Frame Generation
1803 * Use internal and external Pause Frame Generation.
1804 * Sending pause frames is edge triggered.
1805 * Send a Pause frame with the maximum pause time if
1806 * internal oder external FIFO full condition occurs.
1807 * Send a zero pause time frame to re-start transmission.
1808 */
1809 /* XM_PAUSE_DA = '010000C28001' (default) */
1810 /* XM_MAC_PTIME = 0xffff (maximum) */
1811 /* remember this value is defined in big endian (!) */
1812 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1813
1814 mode |= XM_PAUSE_MODE;
1815 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1816 } else {
1817 /*
1818 * disable pause frame generation is required for 1000BT
1819 * because the XMAC is not reset if the link is going down
1820 */
1821 /* Disable Pause Mode in Mode Register */
1822 mode &= ~XM_PAUSE_MODE;
1823
1824 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1825 }
1826
1827 xm_write32(hw, port, XM_MODE, mode);
1828
1829 /* Turn on detection of Tx underrun */
1830 msk = xm_read16(hw, port, XM_IMSK);
1831 msk &= ~XM_IS_TXF_UR;
1832 xm_write16(hw, port, XM_IMSK, msk);
1833
1834 xm_read16(hw, port, XM_ISRC);
1835
1836 /* get MMU Command Reg. */
1837 cmd = xm_read16(hw, port, XM_MMU_CMD);
1838 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1839 cmd |= XM_MMU_GMII_FD;
1840
1841 /*
1842 * Workaround BCOM Errata (#10523) for all BCom Phys
1843 * Enable Power Management after link up
1844 */
1845 if (hw->phy_type == SK_PHY_BCOM) {
1846 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1847 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1848 & ~PHY_B_AC_DIS_PM);
1849 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1850 }
1851
1852 /* enable Rx/Tx */
1853 xm_write16(hw, port, XM_MMU_CMD,
1854 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1855 skge_link_up(skge);
1856 }
1857
1858
1859 static inline void bcom_phy_intr(struct skge_port *skge)
1860 {
1861 struct skge_hw *hw = skge->hw;
1862 int port = skge->port;
1863 u16 isrc;
1864
1865 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1866 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1867 "phy interrupt status 0x%x\n", isrc);
1868
1869 if (isrc & PHY_B_IS_PSE)
1870 pr_err("%s: uncorrectable pair swap error\n",
1871 hw->dev[port]->name);
1872
1873 /* Workaround BCom Errata:
1874 * enable and disable loopback mode if "NO HCD" occurs.
1875 */
1876 if (isrc & PHY_B_IS_NO_HDCL) {
1877 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1878 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1879 ctrl | PHY_CT_LOOP);
1880 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1881 ctrl & ~PHY_CT_LOOP);
1882 }
1883
1884 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1885 bcom_check_link(hw, port);
1886
1887 }
1888
1889 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1890 {
1891 int i;
1892
1893 gma_write16(hw, port, GM_SMI_DATA, val);
1894 gma_write16(hw, port, GM_SMI_CTRL,
1895 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1896 for (i = 0; i < PHY_RETRIES; i++) {
1897 udelay(1);
1898
1899 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1900 return 0;
1901 }
1902
1903 pr_warning("%s: phy write timeout\n", hw->dev[port]->name);
1904 return -EIO;
1905 }
1906
1907 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1908 {
1909 int i;
1910
1911 gma_write16(hw, port, GM_SMI_CTRL,
1912 GM_SMI_CT_PHY_AD(hw->phy_addr)
1913 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1914
1915 for (i = 0; i < PHY_RETRIES; i++) {
1916 udelay(1);
1917 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1918 goto ready;
1919 }
1920
1921 return -ETIMEDOUT;
1922 ready:
1923 *val = gma_read16(hw, port, GM_SMI_DATA);
1924 return 0;
1925 }
1926
1927 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1928 {
1929 u16 v = 0;
1930 if (__gm_phy_read(hw, port, reg, &v))
1931 pr_warning("%s: phy read timeout\n", hw->dev[port]->name);
1932 return v;
1933 }
1934
1935 /* Marvell Phy Initialization */
1936 static void yukon_init(struct skge_hw *hw, int port)
1937 {
1938 struct skge_port *skge = netdev_priv(hw->dev[port]);
1939 u16 ctrl, ct1000, adv;
1940
1941 if (skge->autoneg == AUTONEG_ENABLE) {
1942 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1943
1944 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1945 PHY_M_EC_MAC_S_MSK);
1946 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1947
1948 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1949
1950 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1951 }
1952
1953 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1954 if (skge->autoneg == AUTONEG_DISABLE)
1955 ctrl &= ~PHY_CT_ANE;
1956
1957 ctrl |= PHY_CT_RESET;
1958 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1959
1960 ctrl = 0;
1961 ct1000 = 0;
1962 adv = PHY_AN_CSMA;
1963
1964 if (skge->autoneg == AUTONEG_ENABLE) {
1965 if (hw->copper) {
1966 if (skge->advertising & ADVERTISED_1000baseT_Full)
1967 ct1000 |= PHY_M_1000C_AFD;
1968 if (skge->advertising & ADVERTISED_1000baseT_Half)
1969 ct1000 |= PHY_M_1000C_AHD;
1970 if (skge->advertising & ADVERTISED_100baseT_Full)
1971 adv |= PHY_M_AN_100_FD;
1972 if (skge->advertising & ADVERTISED_100baseT_Half)
1973 adv |= PHY_M_AN_100_HD;
1974 if (skge->advertising & ADVERTISED_10baseT_Full)
1975 adv |= PHY_M_AN_10_FD;
1976 if (skge->advertising & ADVERTISED_10baseT_Half)
1977 adv |= PHY_M_AN_10_HD;
1978
1979 /* Set Flow-control capabilities */
1980 adv |= phy_pause_map[skge->flow_control];
1981 } else {
1982 if (skge->advertising & ADVERTISED_1000baseT_Full)
1983 adv |= PHY_M_AN_1000X_AFD;
1984 if (skge->advertising & ADVERTISED_1000baseT_Half)
1985 adv |= PHY_M_AN_1000X_AHD;
1986
1987 adv |= fiber_pause_map[skge->flow_control];
1988 }
1989
1990 /* Restart Auto-negotiation */
1991 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1992 } else {
1993 /* forced speed/duplex settings */
1994 ct1000 = PHY_M_1000C_MSE;
1995
1996 if (skge->duplex == DUPLEX_FULL)
1997 ctrl |= PHY_CT_DUP_MD;
1998
1999 switch (skge->speed) {
2000 case SPEED_1000:
2001 ctrl |= PHY_CT_SP1000;
2002 break;
2003 case SPEED_100:
2004 ctrl |= PHY_CT_SP100;
2005 break;
2006 }
2007
2008 ctrl |= PHY_CT_RESET;
2009 }
2010
2011 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2012
2013 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2014 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2015
2016 /* Enable phy interrupt on autonegotiation complete (or link up) */
2017 if (skge->autoneg == AUTONEG_ENABLE)
2018 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2019 else
2020 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2021 }
2022
2023 static void yukon_reset(struct skge_hw *hw, int port)
2024 {
2025 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2026 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2027 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2028 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2029 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2030
2031 gma_write16(hw, port, GM_RX_CTRL,
2032 gma_read16(hw, port, GM_RX_CTRL)
2033 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2034 }
2035
2036 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2037 static int is_yukon_lite_a0(struct skge_hw *hw)
2038 {
2039 u32 reg;
2040 int ret;
2041
2042 if (hw->chip_id != CHIP_ID_YUKON)
2043 return 0;
2044
2045 reg = skge_read32(hw, B2_FAR);
2046 skge_write8(hw, B2_FAR + 3, 0xff);
2047 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2048 skge_write32(hw, B2_FAR, reg);
2049 return ret;
2050 }
2051
2052 static void yukon_mac_init(struct skge_hw *hw, int port)
2053 {
2054 struct skge_port *skge = netdev_priv(hw->dev[port]);
2055 int i;
2056 u32 reg;
2057 const u8 *addr = hw->dev[port]->dev_addr;
2058
2059 /* WA code for COMA mode -- set PHY reset */
2060 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2061 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2062 reg = skge_read32(hw, B2_GP_IO);
2063 reg |= GP_DIR_9 | GP_IO_9;
2064 skge_write32(hw, B2_GP_IO, reg);
2065 }
2066
2067 /* hard reset */
2068 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2069 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2070
2071 /* WA code for COMA mode -- clear PHY reset */
2072 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2073 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2074 reg = skge_read32(hw, B2_GP_IO);
2075 reg |= GP_DIR_9;
2076 reg &= ~GP_IO_9;
2077 skge_write32(hw, B2_GP_IO, reg);
2078 }
2079
2080 /* Set hardware config mode */
2081 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2082 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2083 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2084
2085 /* Clear GMC reset */
2086 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2087 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2088 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2089
2090 if (skge->autoneg == AUTONEG_DISABLE) {
2091 reg = GM_GPCR_AU_ALL_DIS;
2092 gma_write16(hw, port, GM_GP_CTRL,
2093 gma_read16(hw, port, GM_GP_CTRL) | reg);
2094
2095 switch (skge->speed) {
2096 case SPEED_1000:
2097 reg &= ~GM_GPCR_SPEED_100;
2098 reg |= GM_GPCR_SPEED_1000;
2099 break;
2100 case SPEED_100:
2101 reg &= ~GM_GPCR_SPEED_1000;
2102 reg |= GM_GPCR_SPEED_100;
2103 break;
2104 case SPEED_10:
2105 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2106 break;
2107 }
2108
2109 if (skge->duplex == DUPLEX_FULL)
2110 reg |= GM_GPCR_DUP_FULL;
2111 } else
2112 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2113
2114 switch (skge->flow_control) {
2115 case FLOW_MODE_NONE:
2116 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2117 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2118 break;
2119 case FLOW_MODE_LOC_SEND:
2120 /* disable Rx flow-control */
2121 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2122 break;
2123 case FLOW_MODE_SYMMETRIC:
2124 case FLOW_MODE_SYM_OR_REM:
2125 /* enable Tx & Rx flow-control */
2126 break;
2127 }
2128
2129 gma_write16(hw, port, GM_GP_CTRL, reg);
2130 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2131
2132 yukon_init(hw, port);
2133
2134 /* MIB clear */
2135 reg = gma_read16(hw, port, GM_PHY_ADDR);
2136 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2137
2138 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2139 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2140 gma_write16(hw, port, GM_PHY_ADDR, reg);
2141
2142 /* transmit control */
2143 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2144
2145 /* receive control reg: unicast + multicast + no FCS */
2146 gma_write16(hw, port, GM_RX_CTRL,
2147 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2148
2149 /* transmit flow control */
2150 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2151
2152 /* transmit parameter */
2153 gma_write16(hw, port, GM_TX_PARAM,
2154 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2155 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2156 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2157
2158 /* configure the Serial Mode Register */
2159 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2160 | GM_SMOD_VLAN_ENA
2161 | IPG_DATA_VAL(IPG_DATA_DEF);
2162
2163 if (hw->dev[port]->mtu > ETH_DATA_LEN)
2164 reg |= GM_SMOD_JUMBO_ENA;
2165
2166 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2167
2168 /* physical address: used for pause frames */
2169 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2170 /* virtual address for data */
2171 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2172
2173 /* enable interrupt mask for counter overflows */
2174 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2175 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2176 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2177
2178 /* Initialize Mac Fifo */
2179
2180 /* Configure Rx MAC FIFO */
2181 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2182 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2183
2184 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2185 if (is_yukon_lite_a0(hw))
2186 reg &= ~GMF_RX_F_FL_ON;
2187
2188 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2189 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2190 /*
2191 * because Pause Packet Truncation in GMAC is not working
2192 * we have to increase the Flush Threshold to 64 bytes
2193 * in order to flush pause packets in Rx FIFO on Yukon-1
2194 */
2195 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2196
2197 /* Configure Tx MAC FIFO */
2198 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2199 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2200 }
2201
2202 /* Go into power down mode */
2203 static void yukon_suspend(struct skge_hw *hw, int port)
2204 {
2205 u16 ctrl;
2206
2207 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2208 ctrl |= PHY_M_PC_POL_R_DIS;
2209 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2210
2211 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2212 ctrl |= PHY_CT_RESET;
2213 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2214
2215 /* switch IEEE compatible power down mode on */
2216 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2217 ctrl |= PHY_CT_PDOWN;
2218 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2219 }
2220
2221 static void yukon_stop(struct skge_port *skge)
2222 {
2223 struct skge_hw *hw = skge->hw;
2224 int port = skge->port;
2225
2226 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2227 yukon_reset(hw, port);
2228
2229 gma_write16(hw, port, GM_GP_CTRL,
2230 gma_read16(hw, port, GM_GP_CTRL)
2231 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2232 gma_read16(hw, port, GM_GP_CTRL);
2233
2234 yukon_suspend(hw, port);
2235
2236 /* set GPHY Control reset */
2237 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2238 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2239 }
2240
2241 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2242 {
2243 struct skge_hw *hw = skge->hw;
2244 int port = skge->port;
2245 int i;
2246
2247 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2248 | gma_read32(hw, port, GM_TXO_OK_LO);
2249 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2250 | gma_read32(hw, port, GM_RXO_OK_LO);
2251
2252 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2253 data[i] = gma_read32(hw, port,
2254 skge_stats[i].gma_offset);
2255 }
2256
2257 static void yukon_mac_intr(struct skge_hw *hw, int port)
2258 {
2259 struct net_device *dev = hw->dev[port];
2260 struct skge_port *skge = netdev_priv(dev);
2261 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2262
2263 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2264 "mac interrupt status 0x%x\n", status);
2265
2266 if (status & GM_IS_RX_FF_OR) {
2267 ++dev->stats.rx_fifo_errors;
2268 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2269 }
2270
2271 if (status & GM_IS_TX_FF_UR) {
2272 ++dev->stats.tx_fifo_errors;
2273 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2274 }
2275
2276 }
2277
2278 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2279 {
2280 switch (aux & PHY_M_PS_SPEED_MSK) {
2281 case PHY_M_PS_SPEED_1000:
2282 return SPEED_1000;
2283 case PHY_M_PS_SPEED_100:
2284 return SPEED_100;
2285 default:
2286 return SPEED_10;
2287 }
2288 }
2289
2290 static void yukon_link_up(struct skge_port *skge)
2291 {
2292 struct skge_hw *hw = skge->hw;
2293 int port = skge->port;
2294 u16 reg;
2295
2296 /* Enable Transmit FIFO Underrun */
2297 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2298
2299 reg = gma_read16(hw, port, GM_GP_CTRL);
2300 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2301 reg |= GM_GPCR_DUP_FULL;
2302
2303 /* enable Rx/Tx */
2304 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2305 gma_write16(hw, port, GM_GP_CTRL, reg);
2306
2307 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2308 skge_link_up(skge);
2309 }
2310
2311 static void yukon_link_down(struct skge_port *skge)
2312 {
2313 struct skge_hw *hw = skge->hw;
2314 int port = skge->port;
2315 u16 ctrl;
2316
2317 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2318 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2319 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2320
2321 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2322 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2323 ctrl |= PHY_M_AN_ASP;
2324 /* restore Asymmetric Pause bit */
2325 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2326 }
2327
2328 skge_link_down(skge);
2329
2330 yukon_init(hw, port);
2331 }
2332
2333 static void yukon_phy_intr(struct skge_port *skge)
2334 {
2335 struct skge_hw *hw = skge->hw;
2336 int port = skge->port;
2337 const char *reason = NULL;
2338 u16 istatus, phystat;
2339
2340 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2341 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2342
2343 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2344 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
2345
2346 if (istatus & PHY_M_IS_AN_COMPL) {
2347 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2348 & PHY_M_AN_RF) {
2349 reason = "remote fault";
2350 goto failed;
2351 }
2352
2353 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2354 reason = "master/slave fault";
2355 goto failed;
2356 }
2357
2358 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2359 reason = "speed/duplex";
2360 goto failed;
2361 }
2362
2363 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2364 ? DUPLEX_FULL : DUPLEX_HALF;
2365 skge->speed = yukon_speed(hw, phystat);
2366
2367 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2368 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2369 case PHY_M_PS_PAUSE_MSK:
2370 skge->flow_status = FLOW_STAT_SYMMETRIC;
2371 break;
2372 case PHY_M_PS_RX_P_EN:
2373 skge->flow_status = FLOW_STAT_REM_SEND;
2374 break;
2375 case PHY_M_PS_TX_P_EN:
2376 skge->flow_status = FLOW_STAT_LOC_SEND;
2377 break;
2378 default:
2379 skge->flow_status = FLOW_STAT_NONE;
2380 }
2381
2382 if (skge->flow_status == FLOW_STAT_NONE ||
2383 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2384 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2385 else
2386 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2387 yukon_link_up(skge);
2388 return;
2389 }
2390
2391 if (istatus & PHY_M_IS_LSP_CHANGE)
2392 skge->speed = yukon_speed(hw, phystat);
2393
2394 if (istatus & PHY_M_IS_DUP_CHANGE)
2395 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2396 if (istatus & PHY_M_IS_LST_CHANGE) {
2397 if (phystat & PHY_M_PS_LINK_UP)
2398 yukon_link_up(skge);
2399 else
2400 yukon_link_down(skge);
2401 }
2402 return;
2403 failed:
2404 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
2405
2406 /* XXX restart autonegotiation? */
2407 }
2408
2409 static void skge_phy_reset(struct skge_port *skge)
2410 {
2411 struct skge_hw *hw = skge->hw;
2412 int port = skge->port;
2413 struct net_device *dev = hw->dev[port];
2414
2415 netif_stop_queue(skge->netdev);
2416 netif_carrier_off(skge->netdev);
2417
2418 spin_lock_bh(&hw->phy_lock);
2419 if (is_genesis(hw)) {
2420 genesis_reset(hw, port);
2421 genesis_mac_init(hw, port);
2422 } else {
2423 yukon_reset(hw, port);
2424 yukon_init(hw, port);
2425 }
2426 spin_unlock_bh(&hw->phy_lock);
2427
2428 skge_set_multicast(dev);
2429 }
2430
2431 /* Basic MII support */
2432 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2433 {
2434 struct mii_ioctl_data *data = if_mii(ifr);
2435 struct skge_port *skge = netdev_priv(dev);
2436 struct skge_hw *hw = skge->hw;
2437 int err = -EOPNOTSUPP;
2438
2439 if (!netif_running(dev))
2440 return -ENODEV; /* Phy still in reset */
2441
2442 switch (cmd) {
2443 case SIOCGMIIPHY:
2444 data->phy_id = hw->phy_addr;
2445
2446 /* fallthru */
2447 case SIOCGMIIREG: {
2448 u16 val = 0;
2449 spin_lock_bh(&hw->phy_lock);
2450
2451 if (is_genesis(hw))
2452 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2453 else
2454 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2455 spin_unlock_bh(&hw->phy_lock);
2456 data->val_out = val;
2457 break;
2458 }
2459
2460 case SIOCSMIIREG:
2461 spin_lock_bh(&hw->phy_lock);
2462 if (is_genesis(hw))
2463 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2464 data->val_in);
2465 else
2466 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2467 data->val_in);
2468 spin_unlock_bh(&hw->phy_lock);
2469 break;
2470 }
2471 return err;
2472 }
2473
2474 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2475 {
2476 u32 end;
2477
2478 start /= 8;
2479 len /= 8;
2480 end = start + len - 1;
2481
2482 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2483 skge_write32(hw, RB_ADDR(q, RB_START), start);
2484 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2485 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2486 skge_write32(hw, RB_ADDR(q, RB_END), end);
2487
2488 if (q == Q_R1 || q == Q_R2) {
2489 /* Set thresholds on receive queue's */
2490 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2491 start + (2*len)/3);
2492 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2493 start + (len/3));
2494 } else {
2495 /* Enable store & forward on Tx queue's because
2496 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2497 */
2498 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2499 }
2500
2501 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2502 }
2503
2504 /* Setup Bus Memory Interface */
2505 static void skge_qset(struct skge_port *skge, u16 q,
2506 const struct skge_element *e)
2507 {
2508 struct skge_hw *hw = skge->hw;
2509 u32 watermark = 0x600;
2510 u64 base = skge->dma + (e->desc - skge->mem);
2511
2512 /* optimization to reduce window on 32bit/33mhz */
2513 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2514 watermark /= 2;
2515
2516 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2517 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2518 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2519 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2520 }
2521
2522 static int skge_up(struct net_device *dev)
2523 {
2524 struct skge_port *skge = netdev_priv(dev);
2525 struct skge_hw *hw = skge->hw;
2526 int port = skge->port;
2527 u32 chunk, ram_addr;
2528 size_t rx_size, tx_size;
2529 int err;
2530
2531 if (!is_valid_ether_addr(dev->dev_addr))
2532 return -EINVAL;
2533
2534 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
2535
2536 if (dev->mtu > RX_BUF_SIZE)
2537 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2538 else
2539 skge->rx_buf_size = RX_BUF_SIZE;
2540
2541
2542 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2543 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2544 skge->mem_size = tx_size + rx_size;
2545 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2546 if (!skge->mem)
2547 return -ENOMEM;
2548
2549 BUG_ON(skge->dma & 7);
2550
2551 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2552 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2553 err = -EINVAL;
2554 goto free_pci_mem;
2555 }
2556
2557 memset(skge->mem, 0, skge->mem_size);
2558
2559 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2560 if (err)
2561 goto free_pci_mem;
2562
2563 err = skge_rx_fill(dev);
2564 if (err)
2565 goto free_rx_ring;
2566
2567 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2568 skge->dma + rx_size);
2569 if (err)
2570 goto free_rx_ring;
2571
2572 if (hw->ports == 1) {
2573 err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED,
2574 dev->name, hw);
2575 if (err) {
2576 netdev_err(dev, "Unable to allocate interrupt %d error: %d\n",
2577 hw->pdev->irq, err);
2578 goto free_tx_ring;
2579 }
2580 }
2581
2582 /* Initialize MAC */
2583 spin_lock_bh(&hw->phy_lock);
2584 if (is_genesis(hw))
2585 genesis_mac_init(hw, port);
2586 else
2587 yukon_mac_init(hw, port);
2588 spin_unlock_bh(&hw->phy_lock);
2589
2590 /* Configure RAMbuffers - equally between ports and tx/rx */
2591 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2592 ram_addr = hw->ram_offset + 2 * chunk * port;
2593
2594 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2595 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2596
2597 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2598 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2599 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2600
2601 /* Start receiver BMU */
2602 wmb();
2603 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2604 skge_led(skge, LED_MODE_ON);
2605
2606 spin_lock_irq(&hw->hw_lock);
2607 hw->intr_mask |= portmask[port];
2608 skge_write32(hw, B0_IMSK, hw->intr_mask);
2609 skge_read32(hw, B0_IMSK);
2610 spin_unlock_irq(&hw->hw_lock);
2611
2612 napi_enable(&skge->napi);
2613 return 0;
2614
2615 free_tx_ring:
2616 kfree(skge->tx_ring.start);
2617 free_rx_ring:
2618 skge_rx_clean(skge);
2619 kfree(skge->rx_ring.start);
2620 free_pci_mem:
2621 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2622 skge->mem = NULL;
2623
2624 return err;
2625 }
2626
2627 /* stop receiver */
2628 static void skge_rx_stop(struct skge_hw *hw, int port)
2629 {
2630 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2631 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2632 RB_RST_SET|RB_DIS_OP_MD);
2633 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2634 }
2635
2636 static int skge_down(struct net_device *dev)
2637 {
2638 struct skge_port *skge = netdev_priv(dev);
2639 struct skge_hw *hw = skge->hw;
2640 int port = skge->port;
2641
2642 if (skge->mem == NULL)
2643 return 0;
2644
2645 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
2646
2647 netif_tx_disable(dev);
2648
2649 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)
2650 del_timer_sync(&skge->link_timer);
2651
2652 napi_disable(&skge->napi);
2653 netif_carrier_off(dev);
2654
2655 spin_lock_irq(&hw->hw_lock);
2656 hw->intr_mask &= ~portmask[port];
2657 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask);
2658 skge_read32(hw, B0_IMSK);
2659 spin_unlock_irq(&hw->hw_lock);
2660
2661 if (hw->ports == 1)
2662 free_irq(hw->pdev->irq, hw);
2663
2664 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2665 if (is_genesis(hw))
2666 genesis_stop(skge);
2667 else
2668 yukon_stop(skge);
2669
2670 /* Stop transmitter */
2671 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2672 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2673 RB_RST_SET|RB_DIS_OP_MD);
2674
2675
2676 /* Disable Force Sync bit and Enable Alloc bit */
2677 skge_write8(hw, SK_REG(port, TXA_CTRL),
2678 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2679
2680 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2681 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2682 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2683
2684 /* Reset PCI FIFO */
2685 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2686 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2687
2688 /* Reset the RAM Buffer async Tx queue */
2689 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2690
2691 skge_rx_stop(hw, port);
2692
2693 if (is_genesis(hw)) {
2694 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2695 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2696 } else {
2697 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2698 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2699 }
2700
2701 skge_led(skge, LED_MODE_OFF);
2702
2703 netif_tx_lock_bh(dev);
2704 skge_tx_clean(dev);
2705 netif_tx_unlock_bh(dev);
2706
2707 skge_rx_clean(skge);
2708
2709 kfree(skge->rx_ring.start);
2710 kfree(skge->tx_ring.start);
2711 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2712 skge->mem = NULL;
2713 return 0;
2714 }
2715
2716 static inline int skge_avail(const struct skge_ring *ring)
2717 {
2718 smp_mb();
2719 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2720 + (ring->to_clean - ring->to_use) - 1;
2721 }
2722
2723 static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2724 struct net_device *dev)
2725 {
2726 struct skge_port *skge = netdev_priv(dev);
2727 struct skge_hw *hw = skge->hw;
2728 struct skge_element *e;
2729 struct skge_tx_desc *td;
2730 int i;
2731 u32 control, len;
2732 u64 map;
2733
2734 if (skb_padto(skb, ETH_ZLEN))
2735 return NETDEV_TX_OK;
2736
2737 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2738 return NETDEV_TX_BUSY;
2739
2740 e = skge->tx_ring.to_use;
2741 td = e->desc;
2742 BUG_ON(td->control & BMU_OWN);
2743 e->skb = skb;
2744 len = skb_headlen(skb);
2745 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2746 dma_unmap_addr_set(e, mapaddr, map);
2747 dma_unmap_len_set(e, maplen, len);
2748
2749 td->dma_lo = map;
2750 td->dma_hi = map >> 32;
2751
2752 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2753 const int offset = skb_checksum_start_offset(skb);
2754
2755 /* This seems backwards, but it is what the sk98lin
2756 * does. Looks like hardware is wrong?
2757 */
2758 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
2759 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2760 control = BMU_TCP_CHECK;
2761 else
2762 control = BMU_UDP_CHECK;
2763
2764 td->csum_offs = 0;
2765 td->csum_start = offset;
2766 td->csum_write = offset + skb->csum_offset;
2767 } else
2768 control = BMU_CHECK;
2769
2770 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2771 control |= BMU_EOF | BMU_IRQ_EOF;
2772 else {
2773 struct skge_tx_desc *tf = td;
2774
2775 control |= BMU_STFWD;
2776 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2777 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2778
2779 map = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
2780 frag->size, DMA_TO_DEVICE);
2781
2782 e = e->next;
2783 e->skb = skb;
2784 tf = e->desc;
2785 BUG_ON(tf->control & BMU_OWN);
2786
2787 tf->dma_lo = map;
2788 tf->dma_hi = (u64) map >> 32;
2789 dma_unmap_addr_set(e, mapaddr, map);
2790 dma_unmap_len_set(e, maplen, frag->size);
2791
2792 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2793 }
2794 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2795 }
2796 /* Make sure all the descriptors written */
2797 wmb();
2798 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2799 wmb();
2800
2801 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2802
2803 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2804 "tx queued, slot %td, len %d\n",
2805 e - skge->tx_ring.start, skb->len);
2806
2807 skge->tx_ring.to_use = e->next;
2808 smp_wmb();
2809
2810 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2811 netdev_dbg(dev, "transmit queue full\n");
2812 netif_stop_queue(dev);
2813 }
2814
2815 return NETDEV_TX_OK;
2816 }
2817
2818
2819 /* Free resources associated with this reing element */
2820 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2821 u32 control)
2822 {
2823 struct pci_dev *pdev = skge->hw->pdev;
2824
2825 /* skb header vs. fragment */
2826 if (control & BMU_STF)
2827 pci_unmap_single(pdev, dma_unmap_addr(e, mapaddr),
2828 dma_unmap_len(e, maplen),
2829 PCI_DMA_TODEVICE);
2830 else
2831 pci_unmap_page(pdev, dma_unmap_addr(e, mapaddr),
2832 dma_unmap_len(e, maplen),
2833 PCI_DMA_TODEVICE);
2834
2835 if (control & BMU_EOF) {
2836 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
2837 "tx done slot %td\n", e - skge->tx_ring.start);
2838
2839 dev_kfree_skb(e->skb);
2840 }
2841 }
2842
2843 /* Free all buffers in transmit ring */
2844 static void skge_tx_clean(struct net_device *dev)
2845 {
2846 struct skge_port *skge = netdev_priv(dev);
2847 struct skge_element *e;
2848
2849 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2850 struct skge_tx_desc *td = e->desc;
2851 skge_tx_free(skge, e, td->control);
2852 td->control = 0;
2853 }
2854
2855 skge->tx_ring.to_clean = e;
2856 }
2857
2858 static void skge_tx_timeout(struct net_device *dev)
2859 {
2860 struct skge_port *skge = netdev_priv(dev);
2861
2862 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
2863
2864 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2865 skge_tx_clean(dev);
2866 netif_wake_queue(dev);
2867 }
2868
2869 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2870 {
2871 int err;
2872
2873 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2874 return -EINVAL;
2875
2876 if (!netif_running(dev)) {
2877 dev->mtu = new_mtu;
2878 return 0;
2879 }
2880
2881 skge_down(dev);
2882
2883 dev->mtu = new_mtu;
2884
2885 err = skge_up(dev);
2886 if (err)
2887 dev_close(dev);
2888
2889 return err;
2890 }
2891
2892 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2893
2894 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2895 {
2896 u32 crc, bit;
2897
2898 crc = ether_crc_le(ETH_ALEN, addr);
2899 bit = ~crc & 0x3f;
2900 filter[bit/8] |= 1 << (bit%8);
2901 }
2902
2903 static void genesis_set_multicast(struct net_device *dev)
2904 {
2905 struct skge_port *skge = netdev_priv(dev);
2906 struct skge_hw *hw = skge->hw;
2907 int port = skge->port;
2908 struct netdev_hw_addr *ha;
2909 u32 mode;
2910 u8 filter[8];
2911
2912 mode = xm_read32(hw, port, XM_MODE);
2913 mode |= XM_MD_ENA_HASH;
2914 if (dev->flags & IFF_PROMISC)
2915 mode |= XM_MD_ENA_PROM;
2916 else
2917 mode &= ~XM_MD_ENA_PROM;
2918
2919 if (dev->flags & IFF_ALLMULTI)
2920 memset(filter, 0xff, sizeof(filter));
2921 else {
2922 memset(filter, 0, sizeof(filter));
2923
2924 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2925 skge->flow_status == FLOW_STAT_SYMMETRIC)
2926 genesis_add_filter(filter, pause_mc_addr);
2927
2928 netdev_for_each_mc_addr(ha, dev)
2929 genesis_add_filter(filter, ha->addr);
2930 }
2931
2932 xm_write32(hw, port, XM_MODE, mode);
2933 xm_outhash(hw, port, XM_HSM, filter);
2934 }
2935
2936 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2937 {
2938 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2939 filter[bit/8] |= 1 << (bit%8);
2940 }
2941
2942 static void yukon_set_multicast(struct net_device *dev)
2943 {
2944 struct skge_port *skge = netdev_priv(dev);
2945 struct skge_hw *hw = skge->hw;
2946 int port = skge->port;
2947 struct netdev_hw_addr *ha;
2948 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2949 skge->flow_status == FLOW_STAT_SYMMETRIC);
2950 u16 reg;
2951 u8 filter[8];
2952
2953 memset(filter, 0, sizeof(filter));
2954
2955 reg = gma_read16(hw, port, GM_RX_CTRL);
2956 reg |= GM_RXCR_UCF_ENA;
2957
2958 if (dev->flags & IFF_PROMISC) /* promiscuous */
2959 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2960 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2961 memset(filter, 0xff, sizeof(filter));
2962 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
2963 reg &= ~GM_RXCR_MCF_ENA;
2964 else {
2965 reg |= GM_RXCR_MCF_ENA;
2966
2967 if (rx_pause)
2968 yukon_add_filter(filter, pause_mc_addr);
2969
2970 netdev_for_each_mc_addr(ha, dev)
2971 yukon_add_filter(filter, ha->addr);
2972 }
2973
2974
2975 gma_write16(hw, port, GM_MC_ADDR_H1,
2976 (u16)filter[0] | ((u16)filter[1] << 8));
2977 gma_write16(hw, port, GM_MC_ADDR_H2,
2978 (u16)filter[2] | ((u16)filter[3] << 8));
2979 gma_write16(hw, port, GM_MC_ADDR_H3,
2980 (u16)filter[4] | ((u16)filter[5] << 8));
2981 gma_write16(hw, port, GM_MC_ADDR_H4,
2982 (u16)filter[6] | ((u16)filter[7] << 8));
2983
2984 gma_write16(hw, port, GM_RX_CTRL, reg);
2985 }
2986
2987 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2988 {
2989 if (is_genesis(hw))
2990 return status >> XMR_FS_LEN_SHIFT;
2991 else
2992 return status >> GMR_FS_LEN_SHIFT;
2993 }
2994
2995 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2996 {
2997 if (is_genesis(hw))
2998 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2999 else
3000 return (status & GMR_FS_ANY_ERR) ||
3001 (status & GMR_FS_RX_OK) == 0;
3002 }
3003
3004 static void skge_set_multicast(struct net_device *dev)
3005 {
3006 struct skge_port *skge = netdev_priv(dev);
3007
3008 if (is_genesis(skge->hw))
3009 genesis_set_multicast(dev);
3010 else
3011 yukon_set_multicast(dev);
3012
3013 }
3014
3015
3016 /* Get receive buffer from descriptor.
3017 * Handles copy of small buffers and reallocation failures
3018 */
3019 static struct sk_buff *skge_rx_get(struct net_device *dev,
3020 struct skge_element *e,
3021 u32 control, u32 status, u16 csum)
3022 {
3023 struct skge_port *skge = netdev_priv(dev);
3024 struct sk_buff *skb;
3025 u16 len = control & BMU_BBC;
3026
3027 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
3028 "rx slot %td status 0x%x len %d\n",
3029 e - skge->rx_ring.start, status, len);
3030
3031 if (len > skge->rx_buf_size)
3032 goto error;
3033
3034 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3035 goto error;
3036
3037 if (bad_phy_status(skge->hw, status))
3038 goto error;
3039
3040 if (phy_length(skge->hw, status) != len)
3041 goto error;
3042
3043 if (len < RX_COPY_THRESHOLD) {
3044 skb = netdev_alloc_skb_ip_align(dev, len);
3045 if (!skb)
3046 goto resubmit;
3047
3048 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3049 dma_unmap_addr(e, mapaddr),
3050 len, PCI_DMA_FROMDEVICE);
3051 skb_copy_from_linear_data(e->skb, skb->data, len);
3052 pci_dma_sync_single_for_device(skge->hw->pdev,
3053 dma_unmap_addr(e, mapaddr),
3054 len, PCI_DMA_FROMDEVICE);
3055 skge_rx_reuse(e, skge->rx_buf_size);
3056 } else {
3057 struct sk_buff *nskb;
3058
3059 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
3060 if (!nskb)
3061 goto resubmit;
3062
3063 pci_unmap_single(skge->hw->pdev,
3064 dma_unmap_addr(e, mapaddr),
3065 dma_unmap_len(e, maplen),
3066 PCI_DMA_FROMDEVICE);
3067 skb = e->skb;
3068 prefetch(skb->data);
3069 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
3070 }
3071
3072 skb_put(skb, len);
3073
3074 if (dev->features & NETIF_F_RXCSUM) {
3075 skb->csum = csum;
3076 skb->ip_summed = CHECKSUM_COMPLETE;
3077 }
3078
3079 skb->protocol = eth_type_trans(skb, dev);
3080
3081 return skb;
3082 error:
3083
3084 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3085 "rx err, slot %td control 0x%x status 0x%x\n",
3086 e - skge->rx_ring.start, control, status);
3087
3088 if (is_genesis(skge->hw)) {
3089 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3090 dev->stats.rx_length_errors++;
3091 if (status & XMR_FS_FRA_ERR)
3092 dev->stats.rx_frame_errors++;
3093 if (status & XMR_FS_FCS_ERR)
3094 dev->stats.rx_crc_errors++;
3095 } else {
3096 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3097 dev->stats.rx_length_errors++;
3098 if (status & GMR_FS_FRAGMENT)
3099 dev->stats.rx_frame_errors++;
3100 if (status & GMR_FS_CRC_ERR)
3101 dev->stats.rx_crc_errors++;
3102 }
3103
3104 resubmit:
3105 skge_rx_reuse(e, skge->rx_buf_size);
3106 return NULL;
3107 }
3108
3109 /* Free all buffers in Tx ring which are no longer owned by device */
3110 static void skge_tx_done(struct net_device *dev)
3111 {
3112 struct skge_port *skge = netdev_priv(dev);
3113 struct skge_ring *ring = &skge->tx_ring;
3114 struct skge_element *e;
3115
3116 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3117
3118 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3119 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3120
3121 if (control & BMU_OWN)
3122 break;
3123
3124 skge_tx_free(skge, e, control);
3125 }
3126 skge->tx_ring.to_clean = e;
3127
3128 /* Can run lockless until we need to synchronize to restart queue. */
3129 smp_mb();
3130
3131 if (unlikely(netif_queue_stopped(dev) &&
3132 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3133 netif_tx_lock(dev);
3134 if (unlikely(netif_queue_stopped(dev) &&
3135 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3136 netif_wake_queue(dev);
3137
3138 }
3139 netif_tx_unlock(dev);
3140 }
3141 }
3142
3143 static int skge_poll(struct napi_struct *napi, int to_do)
3144 {
3145 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3146 struct net_device *dev = skge->netdev;
3147 struct skge_hw *hw = skge->hw;
3148 struct skge_ring *ring = &skge->rx_ring;
3149 struct skge_element *e;
3150 int work_done = 0;
3151
3152 skge_tx_done(dev);
3153
3154 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3155
3156 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
3157 struct skge_rx_desc *rd = e->desc;
3158 struct sk_buff *skb;
3159 u32 control;
3160
3161 rmb();
3162 control = rd->control;
3163 if (control & BMU_OWN)
3164 break;
3165
3166 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3167 if (likely(skb)) {
3168 napi_gro_receive(napi, skb);
3169 ++work_done;
3170 }
3171 }
3172 ring->to_clean = e;
3173
3174 /* restart receiver */
3175 wmb();
3176 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3177
3178 if (work_done < to_do) {
3179 unsigned long flags;
3180
3181 napi_gro_flush(napi);
3182 spin_lock_irqsave(&hw->hw_lock, flags);
3183 __napi_complete(napi);
3184 hw->intr_mask |= napimask[skge->port];
3185 skge_write32(hw, B0_IMSK, hw->intr_mask);
3186 skge_read32(hw, B0_IMSK);
3187 spin_unlock_irqrestore(&hw->hw_lock, flags);
3188 }
3189
3190 return work_done;
3191 }
3192
3193 /* Parity errors seem to happen when Genesis is connected to a switch
3194 * with no other ports present. Heartbeat error??
3195 */
3196 static void skge_mac_parity(struct skge_hw *hw, int port)
3197 {
3198 struct net_device *dev = hw->dev[port];
3199
3200 ++dev->stats.tx_heartbeat_errors;
3201
3202 if (is_genesis(hw))
3203 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3204 MFF_CLR_PERR);
3205 else
3206 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3207 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3208 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3209 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3210 }
3211
3212 static void skge_mac_intr(struct skge_hw *hw, int port)
3213 {
3214 if (is_genesis(hw))
3215 genesis_mac_intr(hw, port);
3216 else
3217 yukon_mac_intr(hw, port);
3218 }
3219
3220 /* Handle device specific framing and timeout interrupts */
3221 static void skge_error_irq(struct skge_hw *hw)
3222 {
3223 struct pci_dev *pdev = hw->pdev;
3224 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3225
3226 if (is_genesis(hw)) {
3227 /* clear xmac errors */
3228 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3229 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3230 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3231 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3232 } else {
3233 /* Timestamp (unused) overflow */
3234 if (hwstatus & IS_IRQ_TIST_OV)
3235 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3236 }
3237
3238 if (hwstatus & IS_RAM_RD_PAR) {
3239 dev_err(&pdev->dev, "Ram read data parity error\n");
3240 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3241 }
3242
3243 if (hwstatus & IS_RAM_WR_PAR) {
3244 dev_err(&pdev->dev, "Ram write data parity error\n");
3245 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3246 }
3247
3248 if (hwstatus & IS_M1_PAR_ERR)
3249 skge_mac_parity(hw, 0);
3250
3251 if (hwstatus & IS_M2_PAR_ERR)
3252 skge_mac_parity(hw, 1);
3253
3254 if (hwstatus & IS_R1_PAR_ERR) {
3255 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3256 hw->dev[0]->name);
3257 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3258 }
3259
3260 if (hwstatus & IS_R2_PAR_ERR) {
3261 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3262 hw->dev[1]->name);
3263 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3264 }
3265
3266 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3267 u16 pci_status, pci_cmd;
3268
3269 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3270 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3271
3272 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3273 pci_cmd, pci_status);
3274
3275 /* Write the error bits back to clear them. */
3276 pci_status &= PCI_STATUS_ERROR_BITS;
3277 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3278 pci_write_config_word(pdev, PCI_COMMAND,
3279 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3280 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3281 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3282
3283 /* if error still set then just ignore it */
3284 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3285 if (hwstatus & IS_IRQ_STAT) {
3286 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3287 hw->intr_mask &= ~IS_HW_ERR;
3288 }
3289 }
3290 }
3291
3292 /*
3293 * Interrupt from PHY are handled in tasklet (softirq)
3294 * because accessing phy registers requires spin wait which might
3295 * cause excess interrupt latency.
3296 */
3297 static void skge_extirq(unsigned long arg)
3298 {
3299 struct skge_hw *hw = (struct skge_hw *) arg;
3300 int port;
3301
3302 for (port = 0; port < hw->ports; port++) {
3303 struct net_device *dev = hw->dev[port];
3304
3305 if (netif_running(dev)) {
3306 struct skge_port *skge = netdev_priv(dev);
3307
3308 spin_lock(&hw->phy_lock);
3309 if (!is_genesis(hw))
3310 yukon_phy_intr(skge);
3311 else if (hw->phy_type == SK_PHY_BCOM)
3312 bcom_phy_intr(skge);
3313 spin_unlock(&hw->phy_lock);
3314 }
3315 }
3316
3317 spin_lock_irq(&hw->hw_lock);
3318 hw->intr_mask |= IS_EXT_REG;
3319 skge_write32(hw, B0_IMSK, hw->intr_mask);
3320 skge_read32(hw, B0_IMSK);
3321 spin_unlock_irq(&hw->hw_lock);
3322 }
3323
3324 static irqreturn_t skge_intr(int irq, void *dev_id)
3325 {
3326 struct skge_hw *hw = dev_id;
3327 u32 status;
3328 int handled = 0;
3329
3330 spin_lock(&hw->hw_lock);
3331 /* Reading this register masks IRQ */
3332 status = skge_read32(hw, B0_SP_ISRC);
3333 if (status == 0 || status == ~0)
3334 goto out;
3335
3336 handled = 1;
3337 status &= hw->intr_mask;
3338 if (status & IS_EXT_REG) {
3339 hw->intr_mask &= ~IS_EXT_REG;
3340 tasklet_schedule(&hw->phy_task);
3341 }
3342
3343 if (status & (IS_XA1_F|IS_R1_F)) {
3344 struct skge_port *skge = netdev_priv(hw->dev[0]);
3345 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3346 napi_schedule(&skge->napi);
3347 }
3348
3349 if (status & IS_PA_TO_TX1)
3350 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3351
3352 if (status & IS_PA_TO_RX1) {
3353 ++hw->dev[0]->stats.rx_over_errors;
3354 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3355 }
3356
3357
3358 if (status & IS_MAC1)
3359 skge_mac_intr(hw, 0);
3360
3361 if (hw->dev[1]) {
3362 struct skge_port *skge = netdev_priv(hw->dev[1]);
3363
3364 if (status & (IS_XA2_F|IS_R2_F)) {
3365 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3366 napi_schedule(&skge->napi);
3367 }
3368
3369 if (status & IS_PA_TO_RX2) {
3370 ++hw->dev[1]->stats.rx_over_errors;
3371 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3372 }
3373
3374 if (status & IS_PA_TO_TX2)
3375 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3376
3377 if (status & IS_MAC2)
3378 skge_mac_intr(hw, 1);
3379 }
3380
3381 if (status & IS_HW_ERR)
3382 skge_error_irq(hw);
3383
3384 skge_write32(hw, B0_IMSK, hw->intr_mask);
3385 skge_read32(hw, B0_IMSK);
3386 out:
3387 spin_unlock(&hw->hw_lock);
3388
3389 return IRQ_RETVAL(handled);
3390 }
3391
3392 #ifdef CONFIG_NET_POLL_CONTROLLER
3393 static void skge_netpoll(struct net_device *dev)
3394 {
3395 struct skge_port *skge = netdev_priv(dev);
3396
3397 disable_irq(dev->irq);
3398 skge_intr(dev->irq, skge->hw);
3399 enable_irq(dev->irq);
3400 }
3401 #endif
3402
3403 static int skge_set_mac_address(struct net_device *dev, void *p)
3404 {
3405 struct skge_port *skge = netdev_priv(dev);
3406 struct skge_hw *hw = skge->hw;
3407 unsigned port = skge->port;
3408 const struct sockaddr *addr = p;
3409 u16 ctrl;
3410
3411 if (!is_valid_ether_addr(addr->sa_data))
3412 return -EADDRNOTAVAIL;
3413
3414 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3415
3416 if (!netif_running(dev)) {
3417 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3418 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3419 } else {
3420 /* disable Rx */
3421 spin_lock_bh(&hw->phy_lock);
3422 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3423 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3424
3425 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3426 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3427
3428 if (is_genesis(hw))
3429 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3430 else {
3431 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3432 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3433 }
3434
3435 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3436 spin_unlock_bh(&hw->phy_lock);
3437 }
3438
3439 return 0;
3440 }
3441
3442 static const struct {
3443 u8 id;
3444 const char *name;
3445 } skge_chips[] = {
3446 { CHIP_ID_GENESIS, "Genesis" },
3447 { CHIP_ID_YUKON, "Yukon" },
3448 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3449 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3450 };
3451
3452 static const char *skge_board_name(const struct skge_hw *hw)
3453 {
3454 int i;
3455 static char buf[16];
3456
3457 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3458 if (skge_chips[i].id == hw->chip_id)
3459 return skge_chips[i].name;
3460
3461 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3462 return buf;
3463 }
3464
3465
3466 /*
3467 * Setup the board data structure, but don't bring up
3468 * the port(s)
3469 */
3470 static int skge_reset(struct skge_hw *hw)
3471 {
3472 u32 reg;
3473 u16 ctst, pci_status;
3474 u8 t8, mac_cfg, pmd_type;
3475 int i;
3476
3477 ctst = skge_read16(hw, B0_CTST);
3478
3479 /* do a SW reset */
3480 skge_write8(hw, B0_CTST, CS_RST_SET);
3481 skge_write8(hw, B0_CTST, CS_RST_CLR);
3482
3483 /* clear PCI errors, if any */
3484 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3485 skge_write8(hw, B2_TST_CTRL2, 0);
3486
3487 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3488 pci_write_config_word(hw->pdev, PCI_STATUS,
3489 pci_status | PCI_STATUS_ERROR_BITS);
3490 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3491 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3492
3493 /* restore CLK_RUN bits (for Yukon-Lite) */
3494 skge_write16(hw, B0_CTST,
3495 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3496
3497 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3498 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3499 pmd_type = skge_read8(hw, B2_PMD_TYP);
3500 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3501
3502 switch (hw->chip_id) {
3503 case CHIP_ID_GENESIS:
3504 #ifdef CONFIG_SKGE_GENESIS
3505 switch (hw->phy_type) {
3506 case SK_PHY_XMAC:
3507 hw->phy_addr = PHY_ADDR_XMAC;
3508 break;
3509 case SK_PHY_BCOM:
3510 hw->phy_addr = PHY_ADDR_BCOM;
3511 break;
3512 default:
3513 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3514 hw->phy_type);
3515 return -EOPNOTSUPP;
3516 }
3517 break;
3518 #else
3519 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n");
3520 return -EOPNOTSUPP;
3521 #endif
3522
3523 case CHIP_ID_YUKON:
3524 case CHIP_ID_YUKON_LITE:
3525 case CHIP_ID_YUKON_LP:
3526 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3527 hw->copper = 1;
3528
3529 hw->phy_addr = PHY_ADDR_MARV;
3530 break;
3531
3532 default:
3533 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3534 hw->chip_id);
3535 return -EOPNOTSUPP;
3536 }
3537
3538 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3539 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3540 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3541
3542 /* read the adapters RAM size */
3543 t8 = skge_read8(hw, B2_E_0);
3544 if (is_genesis(hw)) {
3545 if (t8 == 3) {
3546 /* special case: 4 x 64k x 36, offset = 0x80000 */
3547 hw->ram_size = 0x100000;
3548 hw->ram_offset = 0x80000;
3549 } else
3550 hw->ram_size = t8 * 512;
3551 } else if (t8 == 0)
3552 hw->ram_size = 0x20000;
3553 else
3554 hw->ram_size = t8 * 4096;
3555
3556 hw->intr_mask = IS_HW_ERR;
3557
3558 /* Use PHY IRQ for all but fiber based Genesis board */
3559 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC))
3560 hw->intr_mask |= IS_EXT_REG;
3561
3562 if (is_genesis(hw))
3563 genesis_init(hw);
3564 else {
3565 /* switch power to VCC (WA for VAUX problem) */
3566 skge_write8(hw, B0_POWER_CTRL,
3567 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3568
3569 /* avoid boards with stuck Hardware error bits */
3570 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3571 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3572 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3573 hw->intr_mask &= ~IS_HW_ERR;
3574 }
3575
3576 /* Clear PHY COMA */
3577 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3578 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3579 reg &= ~PCI_PHY_COMA;
3580 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3581 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3582
3583
3584 for (i = 0; i < hw->ports; i++) {
3585 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3586 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3587 }
3588 }
3589
3590 /* turn off hardware timer (unused) */
3591 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3592 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3593 skge_write8(hw, B0_LED, LED_STAT_ON);
3594
3595 /* enable the Tx Arbiters */
3596 for (i = 0; i < hw->ports; i++)
3597 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3598
3599 /* Initialize ram interface */
3600 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3601
3602 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3603 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3604 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3605 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3606 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3607 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3608 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3609 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3610 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3611 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3612 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3613 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3614
3615 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3616
3617 /* Set interrupt moderation for Transmit only
3618 * Receive interrupts avoided by NAPI
3619 */
3620 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3621 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3622 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3623
3624 /* Leave irq disabled until first port is brought up. */
3625 skge_write32(hw, B0_IMSK, 0);
3626
3627 for (i = 0; i < hw->ports; i++) {
3628 if (is_genesis(hw))
3629 genesis_reset(hw, i);
3630 else
3631 yukon_reset(hw, i);
3632 }
3633
3634 return 0;
3635 }
3636
3637
3638 #ifdef CONFIG_SKGE_DEBUG
3639
3640 static struct dentry *skge_debug;
3641
3642 static int skge_debug_show(struct seq_file *seq, void *v)
3643 {
3644 struct net_device *dev = seq->private;
3645 const struct skge_port *skge = netdev_priv(dev);
3646 const struct skge_hw *hw = skge->hw;
3647 const struct skge_element *e;
3648
3649 if (!netif_running(dev))
3650 return -ENETDOWN;
3651
3652 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3653 skge_read32(hw, B0_IMSK));
3654
3655 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3656 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3657 const struct skge_tx_desc *t = e->desc;
3658 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3659 t->control, t->dma_hi, t->dma_lo, t->status,
3660 t->csum_offs, t->csum_write, t->csum_start);
3661 }
3662
3663 seq_printf(seq, "\nRx Ring:\n");
3664 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3665 const struct skge_rx_desc *r = e->desc;
3666
3667 if (r->control & BMU_OWN)
3668 break;
3669
3670 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3671 r->control, r->dma_hi, r->dma_lo, r->status,
3672 r->timestamp, r->csum1, r->csum1_start);
3673 }
3674
3675 return 0;
3676 }
3677
3678 static int skge_debug_open(struct inode *inode, struct file *file)
3679 {
3680 return single_open(file, skge_debug_show, inode->i_private);
3681 }
3682
3683 static const struct file_operations skge_debug_fops = {
3684 .owner = THIS_MODULE,
3685 .open = skge_debug_open,
3686 .read = seq_read,
3687 .llseek = seq_lseek,
3688 .release = single_release,
3689 };
3690
3691 /*
3692 * Use network device events to create/remove/rename
3693 * debugfs file entries
3694 */
3695 static int skge_device_event(struct notifier_block *unused,
3696 unsigned long event, void *ptr)
3697 {
3698 struct net_device *dev = ptr;
3699 struct skge_port *skge;
3700 struct dentry *d;
3701
3702 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
3703 goto done;
3704
3705 skge = netdev_priv(dev);
3706 switch (event) {
3707 case NETDEV_CHANGENAME:
3708 if (skge->debugfs) {
3709 d = debugfs_rename(skge_debug, skge->debugfs,
3710 skge_debug, dev->name);
3711 if (d)
3712 skge->debugfs = d;
3713 else {
3714 netdev_info(dev, "rename failed\n");
3715 debugfs_remove(skge->debugfs);
3716 }
3717 }
3718 break;
3719
3720 case NETDEV_GOING_DOWN:
3721 if (skge->debugfs) {
3722 debugfs_remove(skge->debugfs);
3723 skge->debugfs = NULL;
3724 }
3725 break;
3726
3727 case NETDEV_UP:
3728 d = debugfs_create_file(dev->name, S_IRUGO,
3729 skge_debug, dev,
3730 &skge_debug_fops);
3731 if (!d || IS_ERR(d))
3732 netdev_info(dev, "debugfs create failed\n");
3733 else
3734 skge->debugfs = d;
3735 break;
3736 }
3737
3738 done:
3739 return NOTIFY_DONE;
3740 }
3741
3742 static struct notifier_block skge_notifier = {
3743 .notifier_call = skge_device_event,
3744 };
3745
3746
3747 static __init void skge_debug_init(void)
3748 {
3749 struct dentry *ent;
3750
3751 ent = debugfs_create_dir("skge", NULL);
3752 if (!ent || IS_ERR(ent)) {
3753 pr_info("debugfs create directory failed\n");
3754 return;
3755 }
3756
3757 skge_debug = ent;
3758 register_netdevice_notifier(&skge_notifier);
3759 }
3760
3761 static __exit void skge_debug_cleanup(void)
3762 {
3763 if (skge_debug) {
3764 unregister_netdevice_notifier(&skge_notifier);
3765 debugfs_remove(skge_debug);
3766 skge_debug = NULL;
3767 }
3768 }
3769
3770 #else
3771 #define skge_debug_init()
3772 #define skge_debug_cleanup()
3773 #endif
3774
3775 static const struct net_device_ops skge_netdev_ops = {
3776 .ndo_open = skge_up,
3777 .ndo_stop = skge_down,
3778 .ndo_start_xmit = skge_xmit_frame,
3779 .ndo_do_ioctl = skge_ioctl,
3780 .ndo_get_stats = skge_get_stats,
3781 .ndo_tx_timeout = skge_tx_timeout,
3782 .ndo_change_mtu = skge_change_mtu,
3783 .ndo_validate_addr = eth_validate_addr,
3784 .ndo_set_rx_mode = skge_set_multicast,
3785 .ndo_set_mac_address = skge_set_mac_address,
3786 #ifdef CONFIG_NET_POLL_CONTROLLER
3787 .ndo_poll_controller = skge_netpoll,
3788 #endif
3789 };
3790
3791
3792 /* Initialize network device */
3793 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3794 int highmem)
3795 {
3796 struct skge_port *skge;
3797 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3798
3799 if (!dev) {
3800 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3801 return NULL;
3802 }
3803
3804 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3805 dev->netdev_ops = &skge_netdev_ops;
3806 dev->ethtool_ops = &skge_ethtool_ops;
3807 dev->watchdog_timeo = TX_WATCHDOG;
3808 dev->irq = hw->pdev->irq;
3809
3810 if (highmem)
3811 dev->features |= NETIF_F_HIGHDMA;
3812
3813 skge = netdev_priv(dev);
3814 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
3815 skge->netdev = dev;
3816 skge->hw = hw;
3817 skge->msg_enable = netif_msg_init(debug, default_msg);
3818
3819 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3820 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3821
3822 /* Auto speed and flow control */
3823 skge->autoneg = AUTONEG_ENABLE;
3824 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3825 skge->duplex = -1;
3826 skge->speed = -1;
3827 skge->advertising = skge_supported_modes(hw);
3828
3829 if (device_can_wakeup(&hw->pdev->dev)) {
3830 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3831 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3832 }
3833
3834 hw->dev[port] = dev;
3835
3836 skge->port = port;
3837
3838 /* Only used for Genesis XMAC */
3839 if (is_genesis(hw))
3840 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3841 else {
3842 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3843 NETIF_F_RXCSUM;
3844 dev->features |= dev->hw_features;
3845 }
3846
3847 /* read the mac address */
3848 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3849 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3850
3851 return dev;
3852 }
3853
3854 static void __devinit skge_show_addr(struct net_device *dev)
3855 {
3856 const struct skge_port *skge = netdev_priv(dev);
3857
3858 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
3859 }
3860
3861 static int only_32bit_dma;
3862
3863 static int __devinit skge_probe(struct pci_dev *pdev,
3864 const struct pci_device_id *ent)
3865 {
3866 struct net_device *dev, *dev1;
3867 struct skge_hw *hw;
3868 int err, using_dac = 0;
3869
3870 err = pci_enable_device(pdev);
3871 if (err) {
3872 dev_err(&pdev->dev, "cannot enable PCI device\n");
3873 goto err_out;
3874 }
3875
3876 err = pci_request_regions(pdev, DRV_NAME);
3877 if (err) {
3878 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3879 goto err_out_disable_pdev;
3880 }
3881
3882 pci_set_master(pdev);
3883
3884 if (!only_32bit_dma && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3885 using_dac = 1;
3886 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3887 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
3888 using_dac = 0;
3889 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3890 }
3891
3892 if (err) {
3893 dev_err(&pdev->dev, "no usable DMA configuration\n");
3894 goto err_out_free_regions;
3895 }
3896
3897 #ifdef __BIG_ENDIAN
3898 /* byte swap descriptors in hardware */
3899 {
3900 u32 reg;
3901
3902 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3903 reg |= PCI_REV_DESC;
3904 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3905 }
3906 #endif
3907
3908 err = -ENOMEM;
3909 /* space for skge@pci:0000:04:00.0 */
3910 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
3911 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
3912 if (!hw) {
3913 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3914 goto err_out_free_regions;
3915 }
3916 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
3917
3918 hw->pdev = pdev;
3919 spin_lock_init(&hw->hw_lock);
3920 spin_lock_init(&hw->phy_lock);
3921 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw);
3922
3923 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3924 if (!hw->regs) {
3925 dev_err(&pdev->dev, "cannot map device registers\n");
3926 goto err_out_free_hw;
3927 }
3928
3929 err = skge_reset(hw);
3930 if (err)
3931 goto err_out_iounmap;
3932
3933 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3934 DRV_VERSION,
3935 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3936 skge_board_name(hw), hw->chip_rev);
3937
3938 dev = skge_devinit(hw, 0, using_dac);
3939 if (!dev)
3940 goto err_out_led_off;
3941
3942 /* Some motherboards are broken and has zero in ROM. */
3943 if (!is_valid_ether_addr(dev->dev_addr))
3944 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3945
3946 err = register_netdev(dev);
3947 if (err) {
3948 dev_err(&pdev->dev, "cannot register net device\n");
3949 goto err_out_free_netdev;
3950 }
3951
3952 skge_show_addr(dev);
3953
3954 if (hw->ports > 1) {
3955 dev1 = skge_devinit(hw, 1, using_dac);
3956 if (!dev1) {
3957 err = -ENOMEM;
3958 goto err_out_unregister;
3959 }
3960
3961 err = register_netdev(dev1);
3962 if (err) {
3963 dev_err(&pdev->dev, "cannot register second net device\n");
3964 goto err_out_free_dev1;
3965 }
3966
3967 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED,
3968 hw->irq_name, hw);
3969 if (err) {
3970 dev_err(&pdev->dev, "cannot assign irq %d\n",
3971 pdev->irq);
3972 goto err_out_unregister_dev1;
3973 }
3974
3975 skge_show_addr(dev1);
3976 }
3977 pci_set_drvdata(pdev, hw);
3978
3979 return 0;
3980
3981 err_out_unregister_dev1:
3982 unregister_netdev(dev1);
3983 err_out_free_dev1:
3984 free_netdev(dev1);
3985 err_out_unregister:
3986 unregister_netdev(dev);
3987 err_out_free_netdev:
3988 free_netdev(dev);
3989 err_out_led_off:
3990 skge_write16(hw, B0_LED, LED_STAT_OFF);
3991 err_out_iounmap:
3992 iounmap(hw->regs);
3993 err_out_free_hw:
3994 kfree(hw);
3995 err_out_free_regions:
3996 pci_release_regions(pdev);
3997 err_out_disable_pdev:
3998 pci_disable_device(pdev);
3999 pci_set_drvdata(pdev, NULL);
4000 err_out:
4001 return err;
4002 }
4003
4004 static void __devexit skge_remove(struct pci_dev *pdev)
4005 {
4006 struct skge_hw *hw = pci_get_drvdata(pdev);
4007 struct net_device *dev0, *dev1;
4008
4009 if (!hw)
4010 return;
4011
4012 dev1 = hw->dev[1];
4013 if (dev1)
4014 unregister_netdev(dev1);
4015 dev0 = hw->dev[0];
4016 unregister_netdev(dev0);
4017
4018 tasklet_disable(&hw->phy_task);
4019
4020 spin_lock_irq(&hw->hw_lock);
4021 hw->intr_mask = 0;
4022
4023 if (hw->ports > 1) {
4024 skge_write32(hw, B0_IMSK, 0);
4025 skge_read32(hw, B0_IMSK);
4026 free_irq(pdev->irq, hw);
4027 }
4028 spin_unlock_irq(&hw->hw_lock);
4029
4030 skge_write16(hw, B0_LED, LED_STAT_OFF);
4031 skge_write8(hw, B0_CTST, CS_RST_SET);
4032
4033 if (hw->ports > 1)
4034 free_irq(pdev->irq, hw);
4035 pci_release_regions(pdev);
4036 pci_disable_device(pdev);
4037 if (dev1)
4038 free_netdev(dev1);
4039 free_netdev(dev0);
4040
4041 iounmap(hw->regs);
4042 kfree(hw);
4043 pci_set_drvdata(pdev, NULL);
4044 }
4045
4046 #ifdef CONFIG_PM
4047 static int skge_suspend(struct device *dev)
4048 {
4049 struct pci_dev *pdev = to_pci_dev(dev);
4050 struct skge_hw *hw = pci_get_drvdata(pdev);
4051 int i;
4052
4053 if (!hw)
4054 return 0;
4055
4056 for (i = 0; i < hw->ports; i++) {
4057 struct net_device *dev = hw->dev[i];
4058 struct skge_port *skge = netdev_priv(dev);
4059
4060 if (netif_running(dev))
4061 skge_down(dev);
4062
4063 if (skge->wol)
4064 skge_wol_init(skge);
4065 }
4066
4067 skge_write32(hw, B0_IMSK, 0);
4068
4069 return 0;
4070 }
4071
4072 static int skge_resume(struct device *dev)
4073 {
4074 struct pci_dev *pdev = to_pci_dev(dev);
4075 struct skge_hw *hw = pci_get_drvdata(pdev);
4076 int i, err;
4077
4078 if (!hw)
4079 return 0;
4080
4081 err = skge_reset(hw);
4082 if (err)
4083 goto out;
4084
4085 for (i = 0; i < hw->ports; i++) {
4086 struct net_device *dev = hw->dev[i];
4087
4088 if (netif_running(dev)) {
4089 err = skge_up(dev);
4090
4091 if (err) {
4092 netdev_err(dev, "could not up: %d\n", err);
4093 dev_close(dev);
4094 goto out;
4095 }
4096 }
4097 }
4098 out:
4099 return err;
4100 }
4101
4102 static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume);
4103 #define SKGE_PM_OPS (&skge_pm_ops)
4104
4105 #else
4106
4107 #define SKGE_PM_OPS NULL
4108 #endif
4109
4110 static void skge_shutdown(struct pci_dev *pdev)
4111 {
4112 struct skge_hw *hw = pci_get_drvdata(pdev);
4113 int i;
4114
4115 if (!hw)
4116 return;
4117
4118 for (i = 0; i < hw->ports; i++) {
4119 struct net_device *dev = hw->dev[i];
4120 struct skge_port *skge = netdev_priv(dev);
4121
4122 if (skge->wol)
4123 skge_wol_init(skge);
4124 }
4125
4126 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
4127 pci_set_power_state(pdev, PCI_D3hot);
4128 }
4129
4130 static struct pci_driver skge_driver = {
4131 .name = DRV_NAME,
4132 .id_table = skge_id_table,
4133 .probe = skge_probe,
4134 .remove = __devexit_p(skge_remove),
4135 .shutdown = skge_shutdown,
4136 .driver.pm = SKGE_PM_OPS,
4137 };
4138
4139 static struct dmi_system_id skge_32bit_dma_boards[] = {
4140 {
4141 .ident = "Gigabyte nForce boards",
4142 .matches = {
4143 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
4144 DMI_MATCH(DMI_BOARD_NAME, "nForce"),
4145 },
4146 },
4147 {}
4148 };
4149
4150 static int __init skge_init_module(void)
4151 {
4152 if (dmi_check_system(skge_32bit_dma_boards))
4153 only_32bit_dma = 1;
4154 skge_debug_init();
4155 return pci_register_driver(&skge_driver);
4156 }
4157
4158 static void __exit skge_cleanup_module(void)
4159 {
4160 pci_unregister_driver(&skge_driver);
4161 skge_debug_cleanup();
4162 }
4163
4164 module_init(skge_init_module);
4165 module_exit(skge_cleanup_module);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree