2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
55 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
56 static const int multicast_filter_limit
= 32;
58 /* MAC address length */
59 #define MAC_ADDR_LEN 6
61 #define MAX_READ_REQUEST_SHIFT 12
62 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
63 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
64 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
66 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
69 #define R8169_REGS_SIZE 256
70 #define R8169_NAPI_WEIGHT 64
71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
73 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
74 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
77 #define RTL8169_TX_TIMEOUT (6*HZ)
78 #define RTL8169_PHY_TIMEOUT (10*HZ)
80 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
81 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
82 #define RTL_EEPROM_SIG_ADDR 0x0000
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg) readb (ioaddr + (reg))
89 #define RTL_R16(reg) readw (ioaddr + (reg))
90 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
93 RTL_GIGA_MAC_NONE
= 0x00,
94 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
95 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
96 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
97 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
98 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
99 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
100 RTL_GIGA_MAC_VER_07
= 0x07, // 8102e
101 RTL_GIGA_MAC_VER_08
= 0x08, // 8102e
102 RTL_GIGA_MAC_VER_09
= 0x09, // 8102e
103 RTL_GIGA_MAC_VER_10
= 0x0a, // 8101e
104 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
105 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be
106 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb
107 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101 ?
108 RTL_GIGA_MAC_VER_15
= 0x0f, // 8101 ?
109 RTL_GIGA_MAC_VER_16
= 0x11, // 8101Ec
110 RTL_GIGA_MAC_VER_17
= 0x10, // 8168Bf
111 RTL_GIGA_MAC_VER_18
= 0x12, // 8168CP
112 RTL_GIGA_MAC_VER_19
= 0x13, // 8168C
113 RTL_GIGA_MAC_VER_20
= 0x14, // 8168C
114 RTL_GIGA_MAC_VER_21
= 0x15, // 8168C
115 RTL_GIGA_MAC_VER_22
= 0x16, // 8168C
116 RTL_GIGA_MAC_VER_23
= 0x17, // 8168CP
117 RTL_GIGA_MAC_VER_24
= 0x18, // 8168CP
118 RTL_GIGA_MAC_VER_25
= 0x19, // 8168D
119 RTL_GIGA_MAC_VER_26
= 0x1a, // 8168D
120 RTL_GIGA_MAC_VER_27
= 0x1b // 8168DP
123 #define _R(NAME,MAC,MASK) \
124 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
126 static const struct {
129 u32 RxConfigMask
; /* Clears the bits supported by this chip */
130 } rtl_chip_info
[] = {
131 _R("RTL8169", RTL_GIGA_MAC_VER_01
, 0xff7e1880), // 8169
132 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, 0xff7e1880), // 8169S
133 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, 0xff7e1880), // 8110S
134 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, 0xff7e1880), // 8169SB
135 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, 0xff7e1880), // 8110SCd
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, 0xff7e1880), // 8110SCe
137 _R("RTL8102e", RTL_GIGA_MAC_VER_07
, 0xff7e1880), // PCI-E
138 _R("RTL8102e", RTL_GIGA_MAC_VER_08
, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_09
, 0xff7e1880), // PCI-E
140 _R("RTL8101e", RTL_GIGA_MAC_VER_10
, 0xff7e1880), // PCI-E
141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, 0xff7e1880), // PCI-E
143 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, 0xff7e1880), // PCI-E 8139
144 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, 0xff7e1880), // PCI-E 8139
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17
, 0xff7e1880), // PCI-E
147 _R("RTL8101e", RTL_GIGA_MAC_VER_16
, 0xff7e1880), // PCI-E
148 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18
, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19
, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20
, 0xff7e1880), // PCI-E
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21
, 0xff7e1880), // PCI-E
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22
, 0xff7e1880), // PCI-E
153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23
, 0xff7e1880), // PCI-E
154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24
, 0xff7e1880), // PCI-E
155 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25
, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26
, 0xff7e1880), // PCI-E
157 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27
, 0xff7e1880) // PCI-E
167 static void rtl_hw_start_8169(struct net_device
*);
168 static void rtl_hw_start_8168(struct net_device
*);
169 static void rtl_hw_start_8101(struct net_device
*);
171 static struct pci_device_id rtl8169_pci_tbl
[] = {
172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
177 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
178 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
179 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
180 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
181 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
183 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
187 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
190 * we set our copybreak very high so that we don't have
191 * to allocate 16k frames all the time (see note in
194 static int rx_copybreak
= 16383;
201 MAC0
= 0, /* Ethernet hardware address. */
203 MAR0
= 8, /* Multicast filter. */
204 CounterAddrLow
= 0x10,
205 CounterAddrHigh
= 0x14,
206 TxDescStartAddrLow
= 0x20,
207 TxDescStartAddrHigh
= 0x24,
208 TxHDescStartAddrLow
= 0x28,
209 TxHDescStartAddrHigh
= 0x2c,
232 RxDescAddrLow
= 0xe4,
233 RxDescAddrHigh
= 0xe8,
236 FuncEventMask
= 0xf4,
237 FuncPresetState
= 0xf8,
238 FuncForceEvent
= 0xfc,
241 enum rtl8110_registers
{
247 enum rtl8168_8101_registers
{
250 #define CSIAR_FLAG 0x80000000
251 #define CSIAR_WRITE_CMD 0x80000000
252 #define CSIAR_BYTE_ENABLE 0x0f
253 #define CSIAR_BYTE_ENABLE_SHIFT 12
254 #define CSIAR_ADDR_MASK 0x0fff
257 #define EPHYAR_FLAG 0x80000000
258 #define EPHYAR_WRITE_CMD 0x80000000
259 #define EPHYAR_REG_MASK 0x1f
260 #define EPHYAR_REG_SHIFT 16
261 #define EPHYAR_DATA_MASK 0xffff
263 #define FIX_NAK_1 (1 << 4)
264 #define FIX_NAK_2 (1 << 3)
266 #define EFUSEAR_FLAG 0x80000000
267 #define EFUSEAR_WRITE_CMD 0x80000000
268 #define EFUSEAR_READ_CMD 0x00000000
269 #define EFUSEAR_REG_MASK 0x03ff
270 #define EFUSEAR_REG_SHIFT 8
271 #define EFUSEAR_DATA_MASK 0xff
274 enum rtl_register_content
{
275 /* InterruptStatusBits */
279 TxDescUnavail
= 0x0080,
301 /* TXPoll register p.5 */
302 HPQ
= 0x80, /* Poll cmd on the high prio queue */
303 NPQ
= 0x40, /* Poll cmd on the low prio queue */
304 FSWInt
= 0x01, /* Forced software interrupt */
308 Cfg9346_Unlock
= 0xc0,
313 AcceptBroadcast
= 0x08,
314 AcceptMulticast
= 0x04,
316 AcceptAllPhys
= 0x01,
323 TxInterFrameGapShift
= 24,
324 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
326 /* Config1 register p.24 */
329 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
330 Speed_down
= (1 << 4),
334 PMEnable
= (1 << 0), /* Power Management Enable */
336 /* Config2 register p. 25 */
337 PCI_Clock_66MHz
= 0x01,
338 PCI_Clock_33MHz
= 0x00,
340 /* Config3 register p.25 */
341 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
342 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
343 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
345 /* Config5 register p.27 */
346 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
347 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
348 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
349 LanWake
= (1 << 1), /* LanWake enable/disable */
350 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
353 TBIReset
= 0x80000000,
354 TBILoopback
= 0x40000000,
355 TBINwEnable
= 0x20000000,
356 TBINwRestart
= 0x10000000,
357 TBILinkOk
= 0x02000000,
358 TBINwComplete
= 0x01000000,
361 EnableBist
= (1 << 15), // 8168 8101
362 Mac_dbgo_oe
= (1 << 14), // 8168 8101
363 Normal_mode
= (1 << 13), // unused
364 Force_half_dup
= (1 << 12), // 8168 8101
365 Force_rxflow_en
= (1 << 11), // 8168 8101
366 Force_txflow_en
= (1 << 10), // 8168 8101
367 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
368 ASF
= (1 << 8), // 8168 8101
369 PktCntrDisable
= (1 << 7), // 8168 8101
370 Mac_dbgo_sel
= 0x001c, // 8168
375 INTT_0
= 0x0000, // 8168
376 INTT_1
= 0x0001, // 8168
377 INTT_2
= 0x0002, // 8168
378 INTT_3
= 0x0003, // 8168
380 /* rtl8169_PHYstatus */
391 TBILinkOK
= 0x02000000,
393 /* DumpCounterCommand */
397 enum desc_status_bit
{
398 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
399 RingEnd
= (1 << 30), /* End of descriptor ring */
400 FirstFrag
= (1 << 29), /* First segment of a packet */
401 LastFrag
= (1 << 28), /* Final segment of a packet */
404 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
405 MSSShift
= 16, /* MSS value position */
406 MSSMask
= 0xfff, /* MSS value + LargeSend bit: 12 bits */
407 IPCS
= (1 << 18), /* Calculate IP checksum */
408 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
409 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
410 TxVlanTag
= (1 << 17), /* Add VLAN tag */
413 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
414 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
416 #define RxProtoUDP (PID1)
417 #define RxProtoTCP (PID0)
418 #define RxProtoIP (PID1 | PID0)
419 #define RxProtoMask RxProtoIP
421 IPFail
= (1 << 16), /* IP checksum failed */
422 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
423 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
424 RxVlanTag
= (1 << 16), /* VLAN tag available */
427 #define RsvdMask 0x3fffc000
444 u8 __pad
[sizeof(void *) - sizeof(u32
)];
448 RTL_FEATURE_WOL
= (1 << 0),
449 RTL_FEATURE_MSI
= (1 << 1),
450 RTL_FEATURE_GMII
= (1 << 2),
453 struct rtl8169_counters
{
460 __le32 tx_one_collision
;
461 __le32 tx_multi_collision
;
469 struct rtl8169_private
{
470 void __iomem
*mmio_addr
; /* memory map physical address */
471 struct pci_dev
*pci_dev
; /* Index of PCI device */
472 struct net_device
*dev
;
473 struct napi_struct napi
;
474 spinlock_t lock
; /* spin lock flag */
478 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
479 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
482 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
483 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
484 dma_addr_t TxPhyAddr
;
485 dma_addr_t RxPhyAddr
;
486 struct sk_buff
*Rx_skbuff
[NUM_RX_DESC
]; /* Rx data buffers */
487 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
490 struct timer_list timer
;
495 int phy_1000_ctrl_reg
;
496 #ifdef CONFIG_R8169_VLAN
497 struct vlan_group
*vlgrp
;
499 int (*set_speed
)(struct net_device
*, u8 autoneg
, u16 speed
, u8 duplex
);
500 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
501 void (*phy_reset_enable
)(void __iomem
*);
502 void (*hw_start
)(struct net_device
*);
503 unsigned int (*phy_reset_pending
)(void __iomem
*);
504 unsigned int (*link_ok
)(void __iomem
*);
505 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
507 struct delayed_work task
;
510 struct mii_if_info mii
;
511 struct rtl8169_counters counters
;
514 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
515 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
516 module_param(rx_copybreak
, int, 0);
517 MODULE_PARM_DESC(rx_copybreak
, "Copy breakpoint for copy-only-tiny-frames");
518 module_param(use_dac
, int, 0);
519 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
520 module_param_named(debug
, debug
.msg_enable
, int, 0);
521 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
522 MODULE_LICENSE("GPL");
523 MODULE_VERSION(RTL8169_VERSION
);
525 static int rtl8169_open(struct net_device
*dev
);
526 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
527 struct net_device
*dev
);
528 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
529 static int rtl8169_init_ring(struct net_device
*dev
);
530 static void rtl_hw_start(struct net_device
*dev
);
531 static int rtl8169_close(struct net_device
*dev
);
532 static void rtl_set_rx_mode(struct net_device
*dev
);
533 static void rtl8169_tx_timeout(struct net_device
*dev
);
534 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
535 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
536 void __iomem
*, u32 budget
);
537 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
538 static void rtl8169_down(struct net_device
*dev
);
539 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
540 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
542 static const unsigned int rtl8169_rx_config
=
543 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
545 static void mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
549 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
551 for (i
= 20; i
> 0; i
--) {
553 * Check if the RTL8169 has completed writing to the specified
556 if (!(RTL_R32(PHYAR
) & 0x80000000))
562 static int mdio_read(void __iomem
*ioaddr
, int reg_addr
)
566 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
568 for (i
= 20; i
> 0; i
--) {
570 * Check if the RTL8169 has completed retrieving data from
571 * the specified MII register.
573 if (RTL_R32(PHYAR
) & 0x80000000) {
574 value
= RTL_R32(PHYAR
) & 0xffff;
582 static void mdio_patch(void __iomem
*ioaddr
, int reg_addr
, int value
)
584 mdio_write(ioaddr
, reg_addr
, mdio_read(ioaddr
, reg_addr
) | value
);
587 static void mdio_plus_minus(void __iomem
*ioaddr
, int reg_addr
, int p
, int m
)
591 val
= mdio_read(ioaddr
, reg_addr
);
592 mdio_write(ioaddr
, reg_addr
, (val
| p
) & ~m
);
595 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
598 struct rtl8169_private
*tp
= netdev_priv(dev
);
599 void __iomem
*ioaddr
= tp
->mmio_addr
;
601 mdio_write(ioaddr
, location
, val
);
604 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
606 struct rtl8169_private
*tp
= netdev_priv(dev
);
607 void __iomem
*ioaddr
= tp
->mmio_addr
;
609 return mdio_read(ioaddr
, location
);
612 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
616 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
617 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
619 for (i
= 0; i
< 100; i
++) {
620 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
626 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
631 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
633 for (i
= 0; i
< 100; i
++) {
634 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
635 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
644 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
648 RTL_W32(CSIDR
, value
);
649 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
650 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
652 for (i
= 0; i
< 100; i
++) {
653 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
659 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
664 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
665 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
667 for (i
= 0; i
< 100; i
++) {
668 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
669 value
= RTL_R32(CSIDR
);
678 static u8
rtl8168d_efuse_read(void __iomem
*ioaddr
, int reg_addr
)
683 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
685 for (i
= 0; i
< 300; i
++) {
686 if (RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
) {
687 value
= RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
;
696 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
698 RTL_W16(IntrMask
, 0x0000);
700 RTL_W16(IntrStatus
, 0xffff);
703 static void rtl8169_asic_down(void __iomem
*ioaddr
)
705 RTL_W8(ChipCmd
, 0x00);
706 rtl8169_irq_mask_and_ack(ioaddr
);
710 static unsigned int rtl8169_tbi_reset_pending(void __iomem
*ioaddr
)
712 return RTL_R32(TBICSR
) & TBIReset
;
715 static unsigned int rtl8169_xmii_reset_pending(void __iomem
*ioaddr
)
717 return mdio_read(ioaddr
, MII_BMCR
) & BMCR_RESET
;
720 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
722 return RTL_R32(TBICSR
) & TBILinkOk
;
725 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
727 return RTL_R8(PHYstatus
) & LinkStatus
;
730 static void rtl8169_tbi_reset_enable(void __iomem
*ioaddr
)
732 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
735 static void rtl8169_xmii_reset_enable(void __iomem
*ioaddr
)
739 val
= mdio_read(ioaddr
, MII_BMCR
) | BMCR_RESET
;
740 mdio_write(ioaddr
, MII_BMCR
, val
& 0xffff);
743 static void rtl8169_check_link_status(struct net_device
*dev
,
744 struct rtl8169_private
*tp
,
745 void __iomem
*ioaddr
)
749 spin_lock_irqsave(&tp
->lock
, flags
);
750 if (tp
->link_ok(ioaddr
)) {
751 netif_carrier_on(dev
);
752 if (netif_msg_ifup(tp
))
753 printk(KERN_INFO PFX
"%s: link up\n", dev
->name
);
755 if (netif_msg_ifdown(tp
))
756 printk(KERN_INFO PFX
"%s: link down\n", dev
->name
);
757 netif_carrier_off(dev
);
759 spin_unlock_irqrestore(&tp
->lock
, flags
);
762 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
764 struct rtl8169_private
*tp
= netdev_priv(dev
);
765 void __iomem
*ioaddr
= tp
->mmio_addr
;
770 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
771 wol
->supported
= WAKE_ANY
;
773 spin_lock_irq(&tp
->lock
);
775 options
= RTL_R8(Config1
);
776 if (!(options
& PMEnable
))
779 options
= RTL_R8(Config3
);
780 if (options
& LinkUp
)
781 wol
->wolopts
|= WAKE_PHY
;
782 if (options
& MagicPacket
)
783 wol
->wolopts
|= WAKE_MAGIC
;
785 options
= RTL_R8(Config5
);
787 wol
->wolopts
|= WAKE_UCAST
;
789 wol
->wolopts
|= WAKE_BCAST
;
791 wol
->wolopts
|= WAKE_MCAST
;
794 spin_unlock_irq(&tp
->lock
);
797 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
799 struct rtl8169_private
*tp
= netdev_priv(dev
);
800 void __iomem
*ioaddr
= tp
->mmio_addr
;
807 { WAKE_ANY
, Config1
, PMEnable
},
808 { WAKE_PHY
, Config3
, LinkUp
},
809 { WAKE_MAGIC
, Config3
, MagicPacket
},
810 { WAKE_UCAST
, Config5
, UWF
},
811 { WAKE_BCAST
, Config5
, BWF
},
812 { WAKE_MCAST
, Config5
, MWF
},
813 { WAKE_ANY
, Config5
, LanWake
}
816 spin_lock_irq(&tp
->lock
);
818 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
820 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
821 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
822 if (wol
->wolopts
& cfg
[i
].opt
)
823 options
|= cfg
[i
].mask
;
824 RTL_W8(cfg
[i
].reg
, options
);
827 RTL_W8(Cfg9346
, Cfg9346_Lock
);
830 tp
->features
|= RTL_FEATURE_WOL
;
832 tp
->features
&= ~RTL_FEATURE_WOL
;
833 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
835 spin_unlock_irq(&tp
->lock
);
840 static void rtl8169_get_drvinfo(struct net_device
*dev
,
841 struct ethtool_drvinfo
*info
)
843 struct rtl8169_private
*tp
= netdev_priv(dev
);
845 strcpy(info
->driver
, MODULENAME
);
846 strcpy(info
->version
, RTL8169_VERSION
);
847 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
850 static int rtl8169_get_regs_len(struct net_device
*dev
)
852 return R8169_REGS_SIZE
;
855 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
856 u8 autoneg
, u16 speed
, u8 duplex
)
858 struct rtl8169_private
*tp
= netdev_priv(dev
);
859 void __iomem
*ioaddr
= tp
->mmio_addr
;
863 reg
= RTL_R32(TBICSR
);
864 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
865 (duplex
== DUPLEX_FULL
)) {
866 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
867 } else if (autoneg
== AUTONEG_ENABLE
)
868 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
870 if (netif_msg_link(tp
)) {
871 printk(KERN_WARNING
"%s: "
872 "incorrect speed setting refused in TBI mode\n",
881 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
882 u8 autoneg
, u16 speed
, u8 duplex
)
884 struct rtl8169_private
*tp
= netdev_priv(dev
);
885 void __iomem
*ioaddr
= tp
->mmio_addr
;
888 if (autoneg
== AUTONEG_ENABLE
) {
891 auto_nego
= mdio_read(ioaddr
, MII_ADVERTISE
);
892 auto_nego
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
893 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
894 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
896 giga_ctrl
= mdio_read(ioaddr
, MII_CTRL1000
);
897 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
899 /* The 8100e/8101e/8102e do Fast Ethernet only. */
900 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_07
) &&
901 (tp
->mac_version
!= RTL_GIGA_MAC_VER_08
) &&
902 (tp
->mac_version
!= RTL_GIGA_MAC_VER_09
) &&
903 (tp
->mac_version
!= RTL_GIGA_MAC_VER_10
) &&
904 (tp
->mac_version
!= RTL_GIGA_MAC_VER_13
) &&
905 (tp
->mac_version
!= RTL_GIGA_MAC_VER_14
) &&
906 (tp
->mac_version
!= RTL_GIGA_MAC_VER_15
) &&
907 (tp
->mac_version
!= RTL_GIGA_MAC_VER_16
)) {
908 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
909 } else if (netif_msg_link(tp
)) {
910 printk(KERN_INFO
"%s: PHY does not support 1000Mbps.\n",
914 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
916 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
) ||
917 (tp
->mac_version
== RTL_GIGA_MAC_VER_12
) ||
918 (tp
->mac_version
>= RTL_GIGA_MAC_VER_17
)) {
921 * Vendor specific (0x1f) and reserved (0x0e) MII
924 mdio_write(ioaddr
, 0x1f, 0x0000);
925 mdio_write(ioaddr
, 0x0e, 0x0000);
928 mdio_write(ioaddr
, MII_ADVERTISE
, auto_nego
);
929 mdio_write(ioaddr
, MII_CTRL1000
, giga_ctrl
);
933 if (speed
== SPEED_10
)
935 else if (speed
== SPEED_100
)
936 bmcr
= BMCR_SPEED100
;
940 if (duplex
== DUPLEX_FULL
)
941 bmcr
|= BMCR_FULLDPLX
;
943 mdio_write(ioaddr
, 0x1f, 0x0000);
946 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
948 mdio_write(ioaddr
, MII_BMCR
, bmcr
);
950 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
951 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
952 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
953 mdio_write(ioaddr
, 0x17, 0x2138);
954 mdio_write(ioaddr
, 0x0e, 0x0260);
956 mdio_write(ioaddr
, 0x17, 0x2108);
957 mdio_write(ioaddr
, 0x0e, 0x0000);
964 static int rtl8169_set_speed(struct net_device
*dev
,
965 u8 autoneg
, u16 speed
, u8 duplex
)
967 struct rtl8169_private
*tp
= netdev_priv(dev
);
970 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
);
972 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
973 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
978 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
980 struct rtl8169_private
*tp
= netdev_priv(dev
);
984 spin_lock_irqsave(&tp
->lock
, flags
);
985 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
986 spin_unlock_irqrestore(&tp
->lock
, flags
);
991 static u32
rtl8169_get_rx_csum(struct net_device
*dev
)
993 struct rtl8169_private
*tp
= netdev_priv(dev
);
995 return tp
->cp_cmd
& RxChkSum
;
998 static int rtl8169_set_rx_csum(struct net_device
*dev
, u32 data
)
1000 struct rtl8169_private
*tp
= netdev_priv(dev
);
1001 void __iomem
*ioaddr
= tp
->mmio_addr
;
1002 unsigned long flags
;
1004 spin_lock_irqsave(&tp
->lock
, flags
);
1007 tp
->cp_cmd
|= RxChkSum
;
1009 tp
->cp_cmd
&= ~RxChkSum
;
1011 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1014 spin_unlock_irqrestore(&tp
->lock
, flags
);
1019 #ifdef CONFIG_R8169_VLAN
1021 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1022 struct sk_buff
*skb
)
1024 return (tp
->vlgrp
&& vlan_tx_tag_present(skb
)) ?
1025 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1028 static void rtl8169_vlan_rx_register(struct net_device
*dev
,
1029 struct vlan_group
*grp
)
1031 struct rtl8169_private
*tp
= netdev_priv(dev
);
1032 void __iomem
*ioaddr
= tp
->mmio_addr
;
1033 unsigned long flags
;
1035 spin_lock_irqsave(&tp
->lock
, flags
);
1038 * Do not disable RxVlan on 8110SCd.
1040 if (tp
->vlgrp
|| (tp
->mac_version
== RTL_GIGA_MAC_VER_05
))
1041 tp
->cp_cmd
|= RxVlan
;
1043 tp
->cp_cmd
&= ~RxVlan
;
1044 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1046 spin_unlock_irqrestore(&tp
->lock
, flags
);
1049 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1050 struct sk_buff
*skb
)
1052 u32 opts2
= le32_to_cpu(desc
->opts2
);
1053 struct vlan_group
*vlgrp
= tp
->vlgrp
;
1056 if (vlgrp
&& (opts2
& RxVlanTag
)) {
1057 vlan_hwaccel_receive_skb(skb
, vlgrp
, swab16(opts2
& 0xffff));
1065 #else /* !CONFIG_R8169_VLAN */
1067 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1068 struct sk_buff
*skb
)
1073 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1074 struct sk_buff
*skb
)
1081 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1083 struct rtl8169_private
*tp
= netdev_priv(dev
);
1084 void __iomem
*ioaddr
= tp
->mmio_addr
;
1088 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1089 cmd
->port
= PORT_FIBRE
;
1090 cmd
->transceiver
= XCVR_INTERNAL
;
1092 status
= RTL_R32(TBICSR
);
1093 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1094 cmd
->autoneg
= !!(status
& TBINwEnable
);
1096 cmd
->speed
= SPEED_1000
;
1097 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1102 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1104 struct rtl8169_private
*tp
= netdev_priv(dev
);
1106 return mii_ethtool_gset(&tp
->mii
, cmd
);
1109 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1111 struct rtl8169_private
*tp
= netdev_priv(dev
);
1112 unsigned long flags
;
1115 spin_lock_irqsave(&tp
->lock
, flags
);
1117 rc
= tp
->get_settings(dev
, cmd
);
1119 spin_unlock_irqrestore(&tp
->lock
, flags
);
1123 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1126 struct rtl8169_private
*tp
= netdev_priv(dev
);
1127 unsigned long flags
;
1129 if (regs
->len
> R8169_REGS_SIZE
)
1130 regs
->len
= R8169_REGS_SIZE
;
1132 spin_lock_irqsave(&tp
->lock
, flags
);
1133 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1134 spin_unlock_irqrestore(&tp
->lock
, flags
);
1137 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1139 struct rtl8169_private
*tp
= netdev_priv(dev
);
1141 return tp
->msg_enable
;
1144 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1146 struct rtl8169_private
*tp
= netdev_priv(dev
);
1148 tp
->msg_enable
= value
;
1151 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1158 "tx_single_collisions",
1159 "tx_multi_collisions",
1167 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1171 return ARRAY_SIZE(rtl8169_gstrings
);
1177 static void rtl8169_update_counters(struct net_device
*dev
)
1179 struct rtl8169_private
*tp
= netdev_priv(dev
);
1180 void __iomem
*ioaddr
= tp
->mmio_addr
;
1181 struct rtl8169_counters
*counters
;
1187 * Some chips are unable to dump tally counters when the receiver
1190 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1193 counters
= pci_alloc_consistent(tp
->pci_dev
, sizeof(*counters
), &paddr
);
1197 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1198 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1199 RTL_W32(CounterAddrLow
, cmd
);
1200 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1203 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1204 /* copy updated counters */
1205 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1211 RTL_W32(CounterAddrLow
, 0);
1212 RTL_W32(CounterAddrHigh
, 0);
1214 pci_free_consistent(tp
->pci_dev
, sizeof(*counters
), counters
, paddr
);
1217 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1218 struct ethtool_stats
*stats
, u64
*data
)
1220 struct rtl8169_private
*tp
= netdev_priv(dev
);
1224 rtl8169_update_counters(dev
);
1226 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1227 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1228 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1229 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1230 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1231 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1232 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1233 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1234 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1235 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1236 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1237 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1238 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1241 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1245 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1250 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1251 .get_drvinfo
= rtl8169_get_drvinfo
,
1252 .get_regs_len
= rtl8169_get_regs_len
,
1253 .get_link
= ethtool_op_get_link
,
1254 .get_settings
= rtl8169_get_settings
,
1255 .set_settings
= rtl8169_set_settings
,
1256 .get_msglevel
= rtl8169_get_msglevel
,
1257 .set_msglevel
= rtl8169_set_msglevel
,
1258 .get_rx_csum
= rtl8169_get_rx_csum
,
1259 .set_rx_csum
= rtl8169_set_rx_csum
,
1260 .set_tx_csum
= ethtool_op_set_tx_csum
,
1261 .set_sg
= ethtool_op_set_sg
,
1262 .set_tso
= ethtool_op_set_tso
,
1263 .get_regs
= rtl8169_get_regs
,
1264 .get_wol
= rtl8169_get_wol
,
1265 .set_wol
= rtl8169_set_wol
,
1266 .get_strings
= rtl8169_get_strings
,
1267 .get_sset_count
= rtl8169_get_sset_count
,
1268 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1271 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1272 void __iomem
*ioaddr
)
1275 * The driver currently handles the 8168Bf and the 8168Be identically
1276 * but they can be identified more specifically through the test below
1279 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1281 * Same thing for the 8101Eb and the 8101Ec:
1283 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1291 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
1292 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
1293 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27
},
1294 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
1297 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24
},
1298 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1299 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1300 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1301 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1302 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1303 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1304 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1305 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1308 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1309 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1310 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1311 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1314 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1315 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1316 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1317 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1318 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1319 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1320 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1321 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1322 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1323 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1324 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1325 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1326 /* FIXME: where did these entries come from ? -- FR */
1327 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1328 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1331 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1332 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1333 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1334 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1335 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1336 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1339 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1343 reg
= RTL_R32(TxConfig
);
1344 while ((reg
& p
->mask
) != p
->val
)
1346 tp
->mac_version
= p
->mac_version
;
1349 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1351 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1359 static void rtl_phy_write(void __iomem
*ioaddr
, struct phy_reg
*regs
, int len
)
1362 mdio_write(ioaddr
, regs
->reg
, regs
->val
);
1367 static void rtl8169s_hw_phy_config(void __iomem
*ioaddr
)
1369 struct phy_reg phy_reg_init
[] = {
1431 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1434 static void rtl8169sb_hw_phy_config(void __iomem
*ioaddr
)
1436 struct phy_reg phy_reg_init
[] = {
1442 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1445 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
,
1446 void __iomem
*ioaddr
)
1448 struct pci_dev
*pdev
= tp
->pci_dev
;
1449 u16 vendor_id
, device_id
;
1451 pci_read_config_word(pdev
, PCI_SUBSYSTEM_VENDOR_ID
, &vendor_id
);
1452 pci_read_config_word(pdev
, PCI_SUBSYSTEM_ID
, &device_id
);
1454 if ((vendor_id
!= PCI_VENDOR_ID_GIGABYTE
) || (device_id
!= 0xe000))
1457 mdio_write(ioaddr
, 0x1f, 0x0001);
1458 mdio_write(ioaddr
, 0x10, 0xf01b);
1459 mdio_write(ioaddr
, 0x1f, 0x0000);
1462 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
,
1463 void __iomem
*ioaddr
)
1465 struct phy_reg phy_reg_init
[] = {
1505 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1507 rtl8169scd_hw_phy_config_quirk(tp
, ioaddr
);
1510 static void rtl8169sce_hw_phy_config(void __iomem
*ioaddr
)
1512 struct phy_reg phy_reg_init
[] = {
1560 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1563 static void rtl8168bb_hw_phy_config(void __iomem
*ioaddr
)
1565 struct phy_reg phy_reg_init
[] = {
1570 mdio_write(ioaddr
, 0x1f, 0x0001);
1571 mdio_patch(ioaddr
, 0x16, 1 << 0);
1573 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1576 static void rtl8168bef_hw_phy_config(void __iomem
*ioaddr
)
1578 struct phy_reg phy_reg_init
[] = {
1584 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1587 static void rtl8168cp_1_hw_phy_config(void __iomem
*ioaddr
)
1589 struct phy_reg phy_reg_init
[] = {
1597 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1600 static void rtl8168cp_2_hw_phy_config(void __iomem
*ioaddr
)
1602 struct phy_reg phy_reg_init
[] = {
1608 mdio_write(ioaddr
, 0x1f, 0x0000);
1609 mdio_patch(ioaddr
, 0x14, 1 << 5);
1610 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1612 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1615 static void rtl8168c_1_hw_phy_config(void __iomem
*ioaddr
)
1617 struct phy_reg phy_reg_init
[] = {
1637 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1639 mdio_patch(ioaddr
, 0x14, 1 << 5);
1640 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1641 mdio_write(ioaddr
, 0x1f, 0x0000);
1644 static void rtl8168c_2_hw_phy_config(void __iomem
*ioaddr
)
1646 struct phy_reg phy_reg_init
[] = {
1664 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1666 mdio_patch(ioaddr
, 0x16, 1 << 0);
1667 mdio_patch(ioaddr
, 0x14, 1 << 5);
1668 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1669 mdio_write(ioaddr
, 0x1f, 0x0000);
1672 static void rtl8168c_3_hw_phy_config(void __iomem
*ioaddr
)
1674 struct phy_reg phy_reg_init
[] = {
1686 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1688 mdio_patch(ioaddr
, 0x16, 1 << 0);
1689 mdio_patch(ioaddr
, 0x14, 1 << 5);
1690 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1691 mdio_write(ioaddr
, 0x1f, 0x0000);
1694 static void rtl8168c_4_hw_phy_config(void __iomem
*ioaddr
)
1696 rtl8168c_3_hw_phy_config(ioaddr
);
1699 static void rtl8168d_1_hw_phy_config(void __iomem
*ioaddr
)
1701 static struct phy_reg phy_reg_init_0
[] = {
1720 static struct phy_reg phy_reg_init_1
[] = {
1727 static struct phy_reg phy_reg_init_2
[] = {
2083 rtl_phy_write(ioaddr
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2085 mdio_write(ioaddr
, 0x1f, 0x0002);
2086 mdio_plus_minus(ioaddr
, 0x0b, 0x0010, 0x00ef);
2087 mdio_plus_minus(ioaddr
, 0x0c, 0xa200, 0x5d00);
2089 rtl_phy_write(ioaddr
, phy_reg_init_1
, ARRAY_SIZE(phy_reg_init_1
));
2091 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2092 struct phy_reg phy_reg_init
[] = {
2102 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2104 val
= mdio_read(ioaddr
, 0x0d);
2106 if ((val
& 0x00ff) != 0x006c) {
2108 0x0065, 0x0066, 0x0067, 0x0068,
2109 0x0069, 0x006a, 0x006b, 0x006c
2113 mdio_write(ioaddr
, 0x1f, 0x0002);
2116 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2117 mdio_write(ioaddr
, 0x0d, val
| set
[i
]);
2120 struct phy_reg phy_reg_init
[] = {
2128 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2131 mdio_write(ioaddr
, 0x1f, 0x0002);
2132 mdio_patch(ioaddr
, 0x0d, 0x0300);
2133 mdio_patch(ioaddr
, 0x0f, 0x0010);
2135 mdio_write(ioaddr
, 0x1f, 0x0002);
2136 mdio_plus_minus(ioaddr
, 0x02, 0x0100, 0x0600);
2137 mdio_plus_minus(ioaddr
, 0x03, 0x0000, 0xe000);
2139 rtl_phy_write(ioaddr
, phy_reg_init_2
, ARRAY_SIZE(phy_reg_init_2
));
2142 static void rtl8168d_2_hw_phy_config(void __iomem
*ioaddr
)
2144 static struct phy_reg phy_reg_init_0
[] = {
2169 static struct phy_reg phy_reg_init_1
[] = {
2482 rtl_phy_write(ioaddr
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2484 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2485 struct phy_reg phy_reg_init
[] = {
2496 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2498 val
= mdio_read(ioaddr
, 0x0d);
2499 if ((val
& 0x00ff) != 0x006c) {
2501 0x0065, 0x0066, 0x0067, 0x0068,
2502 0x0069, 0x006a, 0x006b, 0x006c
2506 mdio_write(ioaddr
, 0x1f, 0x0002);
2509 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2510 mdio_write(ioaddr
, 0x0d, val
| set
[i
]);
2513 struct phy_reg phy_reg_init
[] = {
2521 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2524 mdio_write(ioaddr
, 0x1f, 0x0002);
2525 mdio_plus_minus(ioaddr
, 0x02, 0x0100, 0x0600);
2526 mdio_plus_minus(ioaddr
, 0x03, 0x0000, 0xe000);
2528 mdio_write(ioaddr
, 0x1f, 0x0001);
2529 mdio_write(ioaddr
, 0x17, 0x0cc0);
2531 mdio_write(ioaddr
, 0x1f, 0x0002);
2532 mdio_patch(ioaddr
, 0x0f, 0x0017);
2534 rtl_phy_write(ioaddr
, phy_reg_init_1
, ARRAY_SIZE(phy_reg_init_1
));
2537 static void rtl8168d_3_hw_phy_config(void __iomem
*ioaddr
)
2539 struct phy_reg phy_reg_init
[] = {
2595 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2598 static void rtl8102e_hw_phy_config(void __iomem
*ioaddr
)
2600 struct phy_reg phy_reg_init
[] = {
2607 mdio_write(ioaddr
, 0x1f, 0x0000);
2608 mdio_patch(ioaddr
, 0x11, 1 << 12);
2609 mdio_patch(ioaddr
, 0x19, 1 << 13);
2610 mdio_patch(ioaddr
, 0x10, 1 << 15);
2612 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2615 static void rtl_hw_phy_config(struct net_device
*dev
)
2617 struct rtl8169_private
*tp
= netdev_priv(dev
);
2618 void __iomem
*ioaddr
= tp
->mmio_addr
;
2620 rtl8169_print_mac_version(tp
);
2622 switch (tp
->mac_version
) {
2623 case RTL_GIGA_MAC_VER_01
:
2625 case RTL_GIGA_MAC_VER_02
:
2626 case RTL_GIGA_MAC_VER_03
:
2627 rtl8169s_hw_phy_config(ioaddr
);
2629 case RTL_GIGA_MAC_VER_04
:
2630 rtl8169sb_hw_phy_config(ioaddr
);
2632 case RTL_GIGA_MAC_VER_05
:
2633 rtl8169scd_hw_phy_config(tp
, ioaddr
);
2635 case RTL_GIGA_MAC_VER_06
:
2636 rtl8169sce_hw_phy_config(ioaddr
);
2638 case RTL_GIGA_MAC_VER_07
:
2639 case RTL_GIGA_MAC_VER_08
:
2640 case RTL_GIGA_MAC_VER_09
:
2641 rtl8102e_hw_phy_config(ioaddr
);
2643 case RTL_GIGA_MAC_VER_11
:
2644 rtl8168bb_hw_phy_config(ioaddr
);
2646 case RTL_GIGA_MAC_VER_12
:
2647 rtl8168bef_hw_phy_config(ioaddr
);
2649 case RTL_GIGA_MAC_VER_17
:
2650 rtl8168bef_hw_phy_config(ioaddr
);
2652 case RTL_GIGA_MAC_VER_18
:
2653 rtl8168cp_1_hw_phy_config(ioaddr
);
2655 case RTL_GIGA_MAC_VER_19
:
2656 rtl8168c_1_hw_phy_config(ioaddr
);
2658 case RTL_GIGA_MAC_VER_20
:
2659 rtl8168c_2_hw_phy_config(ioaddr
);
2661 case RTL_GIGA_MAC_VER_21
:
2662 rtl8168c_3_hw_phy_config(ioaddr
);
2664 case RTL_GIGA_MAC_VER_22
:
2665 rtl8168c_4_hw_phy_config(ioaddr
);
2667 case RTL_GIGA_MAC_VER_23
:
2668 case RTL_GIGA_MAC_VER_24
:
2669 rtl8168cp_2_hw_phy_config(ioaddr
);
2671 case RTL_GIGA_MAC_VER_25
:
2672 rtl8168d_1_hw_phy_config(ioaddr
);
2674 case RTL_GIGA_MAC_VER_26
:
2675 rtl8168d_2_hw_phy_config(ioaddr
);
2677 case RTL_GIGA_MAC_VER_27
:
2678 rtl8168d_3_hw_phy_config(ioaddr
);
2686 static void rtl8169_phy_timer(unsigned long __opaque
)
2688 struct net_device
*dev
= (struct net_device
*)__opaque
;
2689 struct rtl8169_private
*tp
= netdev_priv(dev
);
2690 struct timer_list
*timer
= &tp
->timer
;
2691 void __iomem
*ioaddr
= tp
->mmio_addr
;
2692 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
2694 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
2696 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
2699 spin_lock_irq(&tp
->lock
);
2701 if (tp
->phy_reset_pending(ioaddr
)) {
2703 * A busy loop could burn quite a few cycles on nowadays CPU.
2704 * Let's delay the execution of the timer for a few ticks.
2710 if (tp
->link_ok(ioaddr
))
2713 if (netif_msg_link(tp
))
2714 printk(KERN_WARNING
"%s: PHY reset until link up\n", dev
->name
);
2716 tp
->phy_reset_enable(ioaddr
);
2719 mod_timer(timer
, jiffies
+ timeout
);
2721 spin_unlock_irq(&tp
->lock
);
2724 static inline void rtl8169_delete_timer(struct net_device
*dev
)
2726 struct rtl8169_private
*tp
= netdev_priv(dev
);
2727 struct timer_list
*timer
= &tp
->timer
;
2729 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
2732 del_timer_sync(timer
);
2735 static inline void rtl8169_request_timer(struct net_device
*dev
)
2737 struct rtl8169_private
*tp
= netdev_priv(dev
);
2738 struct timer_list
*timer
= &tp
->timer
;
2740 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
2743 mod_timer(timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
2746 #ifdef CONFIG_NET_POLL_CONTROLLER
2748 * Polling 'interrupt' - used by things like netconsole to send skbs
2749 * without having to re-enable interrupts. It's not called while
2750 * the interrupt routine is executing.
2752 static void rtl8169_netpoll(struct net_device
*dev
)
2754 struct rtl8169_private
*tp
= netdev_priv(dev
);
2755 struct pci_dev
*pdev
= tp
->pci_dev
;
2757 disable_irq(pdev
->irq
);
2758 rtl8169_interrupt(pdev
->irq
, dev
);
2759 enable_irq(pdev
->irq
);
2763 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
2764 void __iomem
*ioaddr
)
2767 pci_release_regions(pdev
);
2768 pci_disable_device(pdev
);
2772 static void rtl8169_phy_reset(struct net_device
*dev
,
2773 struct rtl8169_private
*tp
)
2775 void __iomem
*ioaddr
= tp
->mmio_addr
;
2778 tp
->phy_reset_enable(ioaddr
);
2779 for (i
= 0; i
< 100; i
++) {
2780 if (!tp
->phy_reset_pending(ioaddr
))
2784 if (netif_msg_link(tp
))
2785 printk(KERN_ERR
"%s: PHY reset failed.\n", dev
->name
);
2788 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
2790 void __iomem
*ioaddr
= tp
->mmio_addr
;
2792 rtl_hw_phy_config(dev
);
2794 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
2795 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2799 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
2801 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
2802 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
2804 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
2805 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2807 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2808 mdio_write(ioaddr
, 0x0b, 0x0000); //w 0x0b 15 0 0
2811 rtl8169_phy_reset(dev
, tp
);
2814 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2815 * only 8101. Don't panic.
2817 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
);
2819 if ((RTL_R8(PHYstatus
) & TBI_Enable
) && netif_msg_link(tp
))
2820 printk(KERN_INFO PFX
"%s: TBI auto-negotiating\n", dev
->name
);
2823 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
2825 void __iomem
*ioaddr
= tp
->mmio_addr
;
2829 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
2830 high
= addr
[4] | (addr
[5] << 8);
2832 spin_lock_irq(&tp
->lock
);
2834 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2836 RTL_W32(MAC4
, high
);
2842 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2844 spin_unlock_irq(&tp
->lock
);
2847 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
2849 struct rtl8169_private
*tp
= netdev_priv(dev
);
2850 struct sockaddr
*addr
= p
;
2852 if (!is_valid_ether_addr(addr
->sa_data
))
2853 return -EADDRNOTAVAIL
;
2855 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
2857 rtl_rar_set(tp
, dev
->dev_addr
);
2862 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2864 struct rtl8169_private
*tp
= netdev_priv(dev
);
2865 struct mii_ioctl_data
*data
= if_mii(ifr
);
2867 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
2870 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
2874 data
->phy_id
= 32; /* Internal PHY */
2878 data
->val_out
= mdio_read(tp
->mmio_addr
, data
->reg_num
& 0x1f);
2882 mdio_write(tp
->mmio_addr
, data
->reg_num
& 0x1f, data
->val_in
);
2888 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
2893 static const struct rtl_cfg_info
{
2894 void (*hw_start
)(struct net_device
*);
2895 unsigned int region
;
2901 } rtl_cfg_infos
[] = {
2903 .hw_start
= rtl_hw_start_8169
,
2906 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2907 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2908 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2909 .features
= RTL_FEATURE_GMII
,
2910 .default_ver
= RTL_GIGA_MAC_VER_01
,
2913 .hw_start
= rtl_hw_start_8168
,
2916 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2917 TxErr
| TxOK
| RxOK
| RxErr
,
2918 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
2919 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
2920 .default_ver
= RTL_GIGA_MAC_VER_11
,
2923 .hw_start
= rtl_hw_start_8101
,
2926 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
2927 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2928 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2929 .features
= RTL_FEATURE_MSI
,
2930 .default_ver
= RTL_GIGA_MAC_VER_13
,
2934 /* Cfg9346_Unlock assumed. */
2935 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
2936 const struct rtl_cfg_info
*cfg
)
2941 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
2942 if (cfg
->features
& RTL_FEATURE_MSI
) {
2943 if (pci_enable_msi(pdev
)) {
2944 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
2947 msi
= RTL_FEATURE_MSI
;
2950 RTL_W8(Config2
, cfg2
);
2954 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
2956 if (tp
->features
& RTL_FEATURE_MSI
) {
2957 pci_disable_msi(pdev
);
2958 tp
->features
&= ~RTL_FEATURE_MSI
;
2962 static const struct net_device_ops rtl8169_netdev_ops
= {
2963 .ndo_open
= rtl8169_open
,
2964 .ndo_stop
= rtl8169_close
,
2965 .ndo_get_stats
= rtl8169_get_stats
,
2966 .ndo_start_xmit
= rtl8169_start_xmit
,
2967 .ndo_tx_timeout
= rtl8169_tx_timeout
,
2968 .ndo_validate_addr
= eth_validate_addr
,
2969 .ndo_change_mtu
= rtl8169_change_mtu
,
2970 .ndo_set_mac_address
= rtl_set_mac_address
,
2971 .ndo_do_ioctl
= rtl8169_ioctl
,
2972 .ndo_set_multicast_list
= rtl_set_rx_mode
,
2973 #ifdef CONFIG_R8169_VLAN
2974 .ndo_vlan_rx_register
= rtl8169_vlan_rx_register
,
2976 #ifdef CONFIG_NET_POLL_CONTROLLER
2977 .ndo_poll_controller
= rtl8169_netpoll
,
2982 static int __devinit
2983 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
2985 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
2986 const unsigned int region
= cfg
->region
;
2987 struct rtl8169_private
*tp
;
2988 struct mii_if_info
*mii
;
2989 struct net_device
*dev
;
2990 void __iomem
*ioaddr
;
2994 if (netif_msg_drv(&debug
)) {
2995 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
2996 MODULENAME
, RTL8169_VERSION
);
2999 dev
= alloc_etherdev(sizeof (*tp
));
3001 if (netif_msg_drv(&debug
))
3002 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
3007 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3008 dev
->netdev_ops
= &rtl8169_netdev_ops
;
3009 tp
= netdev_priv(dev
);
3012 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
3016 mii
->mdio_read
= rtl_mdio_read
;
3017 mii
->mdio_write
= rtl_mdio_write
;
3018 mii
->phy_id_mask
= 0x1f;
3019 mii
->reg_num_mask
= 0x1f;
3020 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
3022 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3023 rc
= pci_enable_device(pdev
);
3025 if (netif_msg_probe(tp
))
3026 dev_err(&pdev
->dev
, "enable failure\n");
3027 goto err_out_free_dev_1
;
3030 rc
= pci_set_mwi(pdev
);
3032 goto err_out_disable_2
;
3034 /* make sure PCI base addr 1 is MMIO */
3035 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
3036 if (netif_msg_probe(tp
)) {
3038 "region #%d not an MMIO resource, aborting\n",
3045 /* check for weird/broken PCI region reporting */
3046 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
3047 if (netif_msg_probe(tp
)) {
3049 "Invalid PCI region size(s), aborting\n");
3055 rc
= pci_request_regions(pdev
, MODULENAME
);
3057 if (netif_msg_probe(tp
))
3058 dev_err(&pdev
->dev
, "could not request regions.\n");
3062 tp
->cp_cmd
= PCIMulRW
| RxChkSum
;
3064 if ((sizeof(dma_addr_t
) > 4) &&
3065 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
3066 tp
->cp_cmd
|= PCIDAC
;
3067 dev
->features
|= NETIF_F_HIGHDMA
;
3069 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3071 if (netif_msg_probe(tp
)) {
3073 "DMA configuration failed.\n");
3075 goto err_out_free_res_4
;
3079 /* ioremap MMIO region */
3080 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
3082 if (netif_msg_probe(tp
))
3083 dev_err(&pdev
->dev
, "cannot remap MMIO, aborting\n");
3085 goto err_out_free_res_4
;
3088 tp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3089 if (!tp
->pcie_cap
&& netif_msg_probe(tp
))
3090 dev_info(&pdev
->dev
, "no PCI Express capability\n");
3092 RTL_W16(IntrMask
, 0x0000);
3094 /* Soft reset the chip. */
3095 RTL_W8(ChipCmd
, CmdReset
);
3097 /* Check that the chip has finished the reset. */
3098 for (i
= 0; i
< 100; i
++) {
3099 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3101 msleep_interruptible(1);
3104 RTL_W16(IntrStatus
, 0xffff);
3106 pci_set_master(pdev
);
3108 /* Identify chip attached to board */
3109 rtl8169_get_mac_version(tp
, ioaddr
);
3111 /* Use appropriate default if unknown */
3112 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
3113 if (netif_msg_probe(tp
)) {
3114 dev_notice(&pdev
->dev
,
3115 "unknown MAC, using family default\n");
3117 tp
->mac_version
= cfg
->default_ver
;
3120 rtl8169_print_mac_version(tp
);
3122 for (i
= 0; i
< ARRAY_SIZE(rtl_chip_info
); i
++) {
3123 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
3126 if (i
== ARRAY_SIZE(rtl_chip_info
)) {
3128 "driver bug, MAC version not found in rtl_chip_info\n");
3133 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3134 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
3135 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
3136 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
3137 tp
->features
|= RTL_FEATURE_WOL
;
3138 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
3139 tp
->features
|= RTL_FEATURE_WOL
;
3140 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
3141 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3143 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
3144 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
3145 tp
->set_speed
= rtl8169_set_speed_tbi
;
3146 tp
->get_settings
= rtl8169_gset_tbi
;
3147 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
3148 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
3149 tp
->link_ok
= rtl8169_tbi_link_ok
;
3150 tp
->do_ioctl
= rtl_tbi_ioctl
;
3152 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
3154 tp
->set_speed
= rtl8169_set_speed_xmii
;
3155 tp
->get_settings
= rtl8169_gset_xmii
;
3156 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
3157 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
3158 tp
->link_ok
= rtl8169_xmii_link_ok
;
3159 tp
->do_ioctl
= rtl_xmii_ioctl
;
3162 spin_lock_init(&tp
->lock
);
3164 tp
->mmio_addr
= ioaddr
;
3166 /* Get MAC address */
3167 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
3168 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
3169 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3171 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
3172 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
3173 dev
->irq
= pdev
->irq
;
3174 dev
->base_addr
= (unsigned long) ioaddr
;
3176 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
3178 #ifdef CONFIG_R8169_VLAN
3179 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3182 tp
->intr_mask
= 0xffff;
3183 tp
->align
= cfg
->align
;
3184 tp
->hw_start
= cfg
->hw_start
;
3185 tp
->intr_event
= cfg
->intr_event
;
3186 tp
->napi_event
= cfg
->napi_event
;
3188 init_timer(&tp
->timer
);
3189 tp
->timer
.data
= (unsigned long) dev
;
3190 tp
->timer
.function
= rtl8169_phy_timer
;
3192 rc
= register_netdev(dev
);
3196 pci_set_drvdata(pdev
, dev
);
3198 if (netif_msg_probe(tp
)) {
3199 u32 xid
= RTL_R32(TxConfig
) & 0x9cf0f8ff;
3201 printk(KERN_INFO
"%s: %s at 0x%lx, "
3202 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
3203 "XID %08x IRQ %d\n",
3205 rtl_chip_info
[tp
->chipset
].name
,
3207 dev
->dev_addr
[0], dev
->dev_addr
[1],
3208 dev
->dev_addr
[2], dev
->dev_addr
[3],
3209 dev
->dev_addr
[4], dev
->dev_addr
[5], xid
, dev
->irq
);
3212 rtl8169_init_phy(dev
, tp
);
3215 * Pretend we are using VLANs; This bypasses a nasty bug where
3216 * Interrupts stop flowing on high load on 8110SCd controllers.
3218 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3219 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | RxVlan
);
3221 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
3227 rtl_disable_msi(pdev
, tp
);
3230 pci_release_regions(pdev
);
3232 pci_clear_mwi(pdev
);
3234 pci_disable_device(pdev
);
3240 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
3242 struct net_device
*dev
= pci_get_drvdata(pdev
);
3243 struct rtl8169_private
*tp
= netdev_priv(dev
);
3245 flush_scheduled_work();
3247 unregister_netdev(dev
);
3249 /* restore original MAC address */
3250 rtl_rar_set(tp
, dev
->perm_addr
);
3252 rtl_disable_msi(pdev
, tp
);
3253 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
3254 pci_set_drvdata(pdev
, NULL
);
3257 static void rtl8169_set_rxbufsize(struct rtl8169_private
*tp
,
3260 unsigned int max_frame
= mtu
+ VLAN_ETH_HLEN
+ ETH_FCS_LEN
;
3262 if (max_frame
!= 16383)
3263 printk(KERN_WARNING PFX
"WARNING! Changing of MTU on this "
3264 "NIC may lead to frame reception errors!\n");
3266 tp
->rx_buf_sz
= (max_frame
> RX_BUF_SIZE
) ? max_frame
: RX_BUF_SIZE
;
3269 static int rtl8169_open(struct net_device
*dev
)
3271 struct rtl8169_private
*tp
= netdev_priv(dev
);
3272 struct pci_dev
*pdev
= tp
->pci_dev
;
3273 int retval
= -ENOMEM
;
3277 * Note that we use a magic value here, its wierd I know
3278 * its done because, some subset of rtl8169 hardware suffers from
3279 * a problem in which frames received that are longer than
3280 * the size set in RxMaxSize register return garbage sizes
3281 * when received. To avoid this we need to turn off filtering,
3282 * which is done by setting a value of 16383 in the RxMaxSize register
3283 * and allocating 16k frames to handle the largest possible rx value
3284 * thats what the magic math below does.
3286 rtl8169_set_rxbufsize(tp
, 16383 - VLAN_ETH_HLEN
- ETH_FCS_LEN
);
3289 * Rx and Tx desscriptors needs 256 bytes alignment.
3290 * pci_alloc_consistent provides more.
3292 tp
->TxDescArray
= pci_alloc_consistent(pdev
, R8169_TX_RING_BYTES
,
3294 if (!tp
->TxDescArray
)
3297 tp
->RxDescArray
= pci_alloc_consistent(pdev
, R8169_RX_RING_BYTES
,
3299 if (!tp
->RxDescArray
)
3302 retval
= rtl8169_init_ring(dev
);
3306 INIT_DELAYED_WORK(&tp
->task
, NULL
);
3310 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
3311 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
3314 goto err_release_ring_2
;
3316 napi_enable(&tp
->napi
);
3320 rtl8169_request_timer(dev
);
3322 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
3327 rtl8169_rx_clear(tp
);
3329 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3332 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3337 static void rtl8169_hw_reset(void __iomem
*ioaddr
)
3339 /* Disable interrupts */
3340 rtl8169_irq_mask_and_ack(ioaddr
);
3342 /* Reset the chipset */
3343 RTL_W8(ChipCmd
, CmdReset
);
3349 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
3351 void __iomem
*ioaddr
= tp
->mmio_addr
;
3352 u32 cfg
= rtl8169_rx_config
;
3354 cfg
|= (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
3355 RTL_W32(RxConfig
, cfg
);
3357 /* Set DMA burst size and Interframe Gap Time */
3358 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3359 (InterFrameGap
<< TxInterFrameGapShift
));
3362 static void rtl_hw_start(struct net_device
*dev
)
3364 struct rtl8169_private
*tp
= netdev_priv(dev
);
3365 void __iomem
*ioaddr
= tp
->mmio_addr
;
3368 /* Soft reset the chip. */
3369 RTL_W8(ChipCmd
, CmdReset
);
3371 /* Check that the chip has finished the reset. */
3372 for (i
= 0; i
< 100; i
++) {
3373 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3375 msleep_interruptible(1);
3380 netif_start_queue(dev
);
3384 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
3385 void __iomem
*ioaddr
)
3388 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3389 * register to be written before TxDescAddrLow to work.
3390 * Switching from MMIO to I/O access fixes the issue as well.
3392 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
3393 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
3394 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
3395 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
3398 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
3402 cmd
= RTL_R16(CPlusCmd
);
3403 RTL_W16(CPlusCmd
, cmd
);
3407 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
3409 /* Low hurts. Let's disable the filtering. */
3410 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
3413 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
3420 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
3421 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
3422 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
3423 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
3428 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
3429 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
3430 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
3431 RTL_W32(0x7c, p
->val
);
3437 static void rtl_hw_start_8169(struct net_device
*dev
)
3439 struct rtl8169_private
*tp
= netdev_priv(dev
);
3440 void __iomem
*ioaddr
= tp
->mmio_addr
;
3441 struct pci_dev
*pdev
= tp
->pci_dev
;
3443 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
3444 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
3445 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
3448 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3449 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
3450 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3451 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
3452 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
3453 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3455 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3457 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
3459 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
3460 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3461 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
3462 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
3463 rtl_set_rx_tx_config_registers(tp
);
3465 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
3467 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3468 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
3469 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3470 "Bit-3 and bit-14 MUST be 1\n");
3471 tp
->cp_cmd
|= (1 << 14);
3474 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3476 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
3479 * Undocumented corner. Supposedly:
3480 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3482 RTL_W16(IntrMitigate
, 0x0000);
3484 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3486 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) &&
3487 (tp
->mac_version
!= RTL_GIGA_MAC_VER_02
) &&
3488 (tp
->mac_version
!= RTL_GIGA_MAC_VER_03
) &&
3489 (tp
->mac_version
!= RTL_GIGA_MAC_VER_04
)) {
3490 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3491 rtl_set_rx_tx_config_registers(tp
);
3494 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3496 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3499 RTL_W32(RxMissed
, 0);
3501 rtl_set_rx_mode(dev
);
3503 /* no early-rx interrupts */
3504 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
3506 /* Enable all known interrupts by setting the interrupt mask. */
3507 RTL_W16(IntrMask
, tp
->intr_event
);
3510 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
3512 struct net_device
*dev
= pci_get_drvdata(pdev
);
3513 struct rtl8169_private
*tp
= netdev_priv(dev
);
3514 int cap
= tp
->pcie_cap
;
3519 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3520 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
3521 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
3525 static void rtl_csi_access_enable(void __iomem
*ioaddr
)
3529 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
3530 rtl_csi_write(ioaddr
, 0x070c, csi
| 0x27000000);
3534 unsigned int offset
;
3539 static void rtl_ephy_init(void __iomem
*ioaddr
, struct ephy_info
*e
, int len
)
3544 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
3545 rtl_ephy_write(ioaddr
, e
->offset
, w
);
3550 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
3552 struct net_device
*dev
= pci_get_drvdata(pdev
);
3553 struct rtl8169_private
*tp
= netdev_priv(dev
);
3554 int cap
= tp
->pcie_cap
;
3559 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
3560 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3561 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
3565 #define R8168_CPCMD_QUIRK_MASK (\
3576 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3578 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3580 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3582 rtl_tx_performance_tweak(pdev
,
3583 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
3586 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3588 rtl_hw_start_8168bb(ioaddr
, pdev
);
3590 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3592 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
3595 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3597 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
3599 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3601 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3603 rtl_disable_clock_request(pdev
);
3605 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3608 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3610 static struct ephy_info e_info_8168cp
[] = {
3611 { 0x01, 0, 0x0001 },
3612 { 0x02, 0x0800, 0x1000 },
3613 { 0x03, 0, 0x0042 },
3614 { 0x06, 0x0080, 0x0000 },
3618 rtl_csi_access_enable(ioaddr
);
3620 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
3622 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3625 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3627 rtl_csi_access_enable(ioaddr
);
3629 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3631 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3633 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3636 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3638 rtl_csi_access_enable(ioaddr
);
3640 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3643 RTL_W8(DBG_REG
, 0x20);
3645 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3647 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3649 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3652 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3654 static struct ephy_info e_info_8168c_1
[] = {
3655 { 0x02, 0x0800, 0x1000 },
3656 { 0x03, 0, 0x0002 },
3657 { 0x06, 0x0080, 0x0000 }
3660 rtl_csi_access_enable(ioaddr
);
3662 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
3664 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
3666 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3669 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3671 static struct ephy_info e_info_8168c_2
[] = {
3672 { 0x01, 0, 0x0001 },
3673 { 0x03, 0x0400, 0x0220 }
3676 rtl_csi_access_enable(ioaddr
);
3678 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
3680 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3683 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3685 rtl_hw_start_8168c_2(ioaddr
, pdev
);
3688 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3690 rtl_csi_access_enable(ioaddr
);
3692 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3695 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3697 rtl_csi_access_enable(ioaddr
);
3699 rtl_disable_clock_request(pdev
);
3701 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3703 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3705 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3708 static void rtl_hw_start_8168(struct net_device
*dev
)
3710 struct rtl8169_private
*tp
= netdev_priv(dev
);
3711 void __iomem
*ioaddr
= tp
->mmio_addr
;
3712 struct pci_dev
*pdev
= tp
->pci_dev
;
3714 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3716 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3718 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
3720 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
3722 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3724 RTL_W16(IntrMitigate
, 0x5151);
3726 /* Work around for RxFIFO overflow. */
3727 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
3728 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
3729 tp
->intr_event
&= ~RxOverflow
;
3732 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3734 rtl_set_rx_mode(dev
);
3736 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3737 (InterFrameGap
<< TxInterFrameGapShift
));
3741 switch (tp
->mac_version
) {
3742 case RTL_GIGA_MAC_VER_11
:
3743 rtl_hw_start_8168bb(ioaddr
, pdev
);
3746 case RTL_GIGA_MAC_VER_12
:
3747 case RTL_GIGA_MAC_VER_17
:
3748 rtl_hw_start_8168bef(ioaddr
, pdev
);
3751 case RTL_GIGA_MAC_VER_18
:
3752 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
3755 case RTL_GIGA_MAC_VER_19
:
3756 rtl_hw_start_8168c_1(ioaddr
, pdev
);
3759 case RTL_GIGA_MAC_VER_20
:
3760 rtl_hw_start_8168c_2(ioaddr
, pdev
);
3763 case RTL_GIGA_MAC_VER_21
:
3764 rtl_hw_start_8168c_3(ioaddr
, pdev
);
3767 case RTL_GIGA_MAC_VER_22
:
3768 rtl_hw_start_8168c_4(ioaddr
, pdev
);
3771 case RTL_GIGA_MAC_VER_23
:
3772 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
3775 case RTL_GIGA_MAC_VER_24
:
3776 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
3779 case RTL_GIGA_MAC_VER_25
:
3780 case RTL_GIGA_MAC_VER_26
:
3781 case RTL_GIGA_MAC_VER_27
:
3782 rtl_hw_start_8168d(ioaddr
, pdev
);
3786 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
3787 dev
->name
, tp
->mac_version
);
3791 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3793 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3795 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
3797 RTL_W16(IntrMask
, tp
->intr_event
);
3800 #define R810X_CPCMD_QUIRK_MASK (\
3812 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3814 static struct ephy_info e_info_8102e_1
[] = {
3815 { 0x01, 0, 0x6e65 },
3816 { 0x02, 0, 0x091f },
3817 { 0x03, 0, 0xc2f9 },
3818 { 0x06, 0, 0xafb5 },
3819 { 0x07, 0, 0x0e00 },
3820 { 0x19, 0, 0xec80 },
3821 { 0x01, 0, 0x2e65 },
3826 rtl_csi_access_enable(ioaddr
);
3828 RTL_W8(DBG_REG
, FIX_NAK_1
);
3830 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3833 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
3834 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3836 cfg1
= RTL_R8(Config1
);
3837 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
3838 RTL_W8(Config1
, cfg1
& ~LEDS0
);
3840 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
3842 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
3845 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3847 rtl_csi_access_enable(ioaddr
);
3849 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3851 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
3852 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3854 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
3857 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3859 rtl_hw_start_8102e_2(ioaddr
, pdev
);
3861 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
3864 static void rtl_hw_start_8101(struct net_device
*dev
)
3866 struct rtl8169_private
*tp
= netdev_priv(dev
);
3867 void __iomem
*ioaddr
= tp
->mmio_addr
;
3868 struct pci_dev
*pdev
= tp
->pci_dev
;
3870 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
3871 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
3872 int cap
= tp
->pcie_cap
;
3875 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
3876 PCI_EXP_DEVCTL_NOSNOOP_EN
);
3880 switch (tp
->mac_version
) {
3881 case RTL_GIGA_MAC_VER_07
:
3882 rtl_hw_start_8102e_1(ioaddr
, pdev
);
3885 case RTL_GIGA_MAC_VER_08
:
3886 rtl_hw_start_8102e_3(ioaddr
, pdev
);
3889 case RTL_GIGA_MAC_VER_09
:
3890 rtl_hw_start_8102e_2(ioaddr
, pdev
);
3894 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3896 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3898 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
3900 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
3902 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3904 RTL_W16(IntrMitigate
, 0x0000);
3906 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3908 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3909 rtl_set_rx_tx_config_registers(tp
);
3911 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3915 rtl_set_rx_mode(dev
);
3917 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3919 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
3921 RTL_W16(IntrMask
, tp
->intr_event
);
3924 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
3926 struct rtl8169_private
*tp
= netdev_priv(dev
);
3929 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
3934 if (!netif_running(dev
))
3939 rtl8169_set_rxbufsize(tp
, dev
->mtu
);
3941 ret
= rtl8169_init_ring(dev
);
3945 napi_enable(&tp
->napi
);
3949 rtl8169_request_timer(dev
);
3955 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
3957 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
3958 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
3961 static void rtl8169_free_rx_skb(struct rtl8169_private
*tp
,
3962 struct sk_buff
**sk_buff
, struct RxDesc
*desc
)
3964 struct pci_dev
*pdev
= tp
->pci_dev
;
3966 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), tp
->rx_buf_sz
,
3967 PCI_DMA_FROMDEVICE
);
3968 dev_kfree_skb(*sk_buff
);
3970 rtl8169_make_unusable_by_asic(desc
);
3973 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
3975 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
3977 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
3980 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
3983 desc
->addr
= cpu_to_le64(mapping
);
3985 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
3988 static struct sk_buff
*rtl8169_alloc_rx_skb(struct pci_dev
*pdev
,
3989 struct net_device
*dev
,
3990 struct RxDesc
*desc
, int rx_buf_sz
,
3993 struct sk_buff
*skb
;
3997 pad
= align
? align
: NET_IP_ALIGN
;
3999 skb
= netdev_alloc_skb(dev
, rx_buf_sz
+ pad
);
4003 skb_reserve(skb
, align
? ((pad
- 1) & (unsigned long)skb
->data
) : pad
);
4005 mapping
= pci_map_single(pdev
, skb
->data
, rx_buf_sz
,
4006 PCI_DMA_FROMDEVICE
);
4008 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
4013 rtl8169_make_unusable_by_asic(desc
);
4017 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
4021 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4022 if (tp
->Rx_skbuff
[i
]) {
4023 rtl8169_free_rx_skb(tp
, tp
->Rx_skbuff
+ i
,
4024 tp
->RxDescArray
+ i
);
4029 static u32
rtl8169_rx_fill(struct rtl8169_private
*tp
, struct net_device
*dev
,
4034 for (cur
= start
; end
- cur
!= 0; cur
++) {
4035 struct sk_buff
*skb
;
4036 unsigned int i
= cur
% NUM_RX_DESC
;
4038 WARN_ON((s32
)(end
- cur
) < 0);
4040 if (tp
->Rx_skbuff
[i
])
4043 skb
= rtl8169_alloc_rx_skb(tp
->pci_dev
, dev
,
4044 tp
->RxDescArray
+ i
,
4045 tp
->rx_buf_sz
, tp
->align
);
4049 tp
->Rx_skbuff
[i
] = skb
;
4054 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
4056 desc
->opts1
|= cpu_to_le32(RingEnd
);
4059 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
4061 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
4064 static int rtl8169_init_ring(struct net_device
*dev
)
4066 struct rtl8169_private
*tp
= netdev_priv(dev
);
4068 rtl8169_init_ring_indexes(tp
);
4070 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
4071 memset(tp
->Rx_skbuff
, 0x0, NUM_RX_DESC
* sizeof(struct sk_buff
*));
4073 if (rtl8169_rx_fill(tp
, dev
, 0, NUM_RX_DESC
) != NUM_RX_DESC
)
4076 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
4081 rtl8169_rx_clear(tp
);
4085 static void rtl8169_unmap_tx_skb(struct pci_dev
*pdev
, struct ring_info
*tx_skb
,
4086 struct TxDesc
*desc
)
4088 unsigned int len
= tx_skb
->len
;
4090 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), len
, PCI_DMA_TODEVICE
);
4097 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
4101 for (i
= tp
->dirty_tx
; i
< tp
->dirty_tx
+ NUM_TX_DESC
; i
++) {
4102 unsigned int entry
= i
% NUM_TX_DESC
;
4103 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4104 unsigned int len
= tx_skb
->len
;
4107 struct sk_buff
*skb
= tx_skb
->skb
;
4109 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
,
4110 tp
->TxDescArray
+ entry
);
4115 tp
->dev
->stats
.tx_dropped
++;
4118 tp
->cur_tx
= tp
->dirty_tx
= 0;
4121 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
4123 struct rtl8169_private
*tp
= netdev_priv(dev
);
4125 PREPARE_DELAYED_WORK(&tp
->task
, task
);
4126 schedule_delayed_work(&tp
->task
, 4);
4129 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
4131 struct rtl8169_private
*tp
= netdev_priv(dev
);
4132 void __iomem
*ioaddr
= tp
->mmio_addr
;
4134 synchronize_irq(dev
->irq
);
4136 /* Wait for any pending NAPI task to complete */
4137 napi_disable(&tp
->napi
);
4139 rtl8169_irq_mask_and_ack(ioaddr
);
4141 tp
->intr_mask
= 0xffff;
4142 RTL_W16(IntrMask
, tp
->intr_event
);
4143 napi_enable(&tp
->napi
);
4146 static void rtl8169_reinit_task(struct work_struct
*work
)
4148 struct rtl8169_private
*tp
=
4149 container_of(work
, struct rtl8169_private
, task
.work
);
4150 struct net_device
*dev
= tp
->dev
;
4155 if (!netif_running(dev
))
4158 rtl8169_wait_for_quiescence(dev
);
4161 ret
= rtl8169_open(dev
);
4162 if (unlikely(ret
< 0)) {
4163 if (net_ratelimit() && netif_msg_drv(tp
)) {
4164 printk(KERN_ERR PFX
"%s: reinit failure (status = %d)."
4165 " Rescheduling.\n", dev
->name
, ret
);
4167 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4174 static void rtl8169_reset_task(struct work_struct
*work
)
4176 struct rtl8169_private
*tp
=
4177 container_of(work
, struct rtl8169_private
, task
.work
);
4178 struct net_device
*dev
= tp
->dev
;
4182 if (!netif_running(dev
))
4185 rtl8169_wait_for_quiescence(dev
);
4187 rtl8169_rx_interrupt(dev
, tp
, tp
->mmio_addr
, ~(u32
)0);
4188 rtl8169_tx_clear(tp
);
4190 if (tp
->dirty_rx
== tp
->cur_rx
) {
4191 rtl8169_init_ring_indexes(tp
);
4193 netif_wake_queue(dev
);
4194 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
4196 if (net_ratelimit() && netif_msg_intr(tp
)) {
4197 printk(KERN_EMERG PFX
"%s: Rx buffers shortage\n",
4200 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4207 static void rtl8169_tx_timeout(struct net_device
*dev
)
4209 struct rtl8169_private
*tp
= netdev_priv(dev
);
4211 rtl8169_hw_reset(tp
->mmio_addr
);
4213 /* Let's wait a bit while any (async) irq lands on */
4214 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4217 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
4220 struct skb_shared_info
*info
= skb_shinfo(skb
);
4221 unsigned int cur_frag
, entry
;
4222 struct TxDesc
* uninitialized_var(txd
);
4225 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
4226 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
4231 entry
= (entry
+ 1) % NUM_TX_DESC
;
4233 txd
= tp
->TxDescArray
+ entry
;
4235 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
4236 mapping
= pci_map_single(tp
->pci_dev
, addr
, len
, PCI_DMA_TODEVICE
);
4238 /* anti gcc 2.95.3 bugware (sic) */
4239 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4241 txd
->opts1
= cpu_to_le32(status
);
4242 txd
->addr
= cpu_to_le64(mapping
);
4244 tp
->tx_skb
[entry
].len
= len
;
4248 tp
->tx_skb
[entry
].skb
= skb
;
4249 txd
->opts1
|= cpu_to_le32(LastFrag
);
4255 static inline u32
rtl8169_tso_csum(struct sk_buff
*skb
, struct net_device
*dev
)
4257 if (dev
->features
& NETIF_F_TSO
) {
4258 u32 mss
= skb_shinfo(skb
)->gso_size
;
4261 return LargeSend
| ((mss
& MSSMask
) << MSSShift
);
4263 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4264 const struct iphdr
*ip
= ip_hdr(skb
);
4266 if (ip
->protocol
== IPPROTO_TCP
)
4267 return IPCS
| TCPCS
;
4268 else if (ip
->protocol
== IPPROTO_UDP
)
4269 return IPCS
| UDPCS
;
4270 WARN_ON(1); /* we need a WARN() */
4275 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
4276 struct net_device
*dev
)
4278 struct rtl8169_private
*tp
= netdev_priv(dev
);
4279 unsigned int frags
, entry
= tp
->cur_tx
% NUM_TX_DESC
;
4280 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
4281 void __iomem
*ioaddr
= tp
->mmio_addr
;
4286 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
4287 if (netif_msg_drv(tp
)) {
4289 "%s: BUG! Tx Ring full when queue awake!\n",
4295 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
4298 opts1
= DescOwn
| rtl8169_tso_csum(skb
, dev
);
4300 frags
= rtl8169_xmit_frags(tp
, skb
, opts1
);
4302 len
= skb_headlen(skb
);
4306 opts1
|= FirstFrag
| LastFrag
;
4307 tp
->tx_skb
[entry
].skb
= skb
;
4310 mapping
= pci_map_single(tp
->pci_dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
4312 tp
->tx_skb
[entry
].len
= len
;
4313 txd
->addr
= cpu_to_le64(mapping
);
4314 txd
->opts2
= cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
4318 /* anti gcc 2.95.3 bugware (sic) */
4319 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4320 txd
->opts1
= cpu_to_le32(status
);
4322 tp
->cur_tx
+= frags
+ 1;
4326 RTL_W8(TxPoll
, NPQ
); /* set polling bit */
4328 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
4329 netif_stop_queue(dev
);
4331 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
4332 netif_wake_queue(dev
);
4335 return NETDEV_TX_OK
;
4338 netif_stop_queue(dev
);
4339 dev
->stats
.tx_dropped
++;
4340 return NETDEV_TX_BUSY
;
4343 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
4345 struct rtl8169_private
*tp
= netdev_priv(dev
);
4346 struct pci_dev
*pdev
= tp
->pci_dev
;
4347 void __iomem
*ioaddr
= tp
->mmio_addr
;
4348 u16 pci_status
, pci_cmd
;
4350 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
4351 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
4353 if (netif_msg_intr(tp
)) {
4355 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
4356 dev
->name
, pci_cmd
, pci_status
);
4360 * The recovery sequence below admits a very elaborated explanation:
4361 * - it seems to work;
4362 * - I did not see what else could be done;
4363 * - it makes iop3xx happy.
4365 * Feel free to adjust to your needs.
4367 if (pdev
->broken_parity_status
)
4368 pci_cmd
&= ~PCI_COMMAND_PARITY
;
4370 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
4372 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
4374 pci_write_config_word(pdev
, PCI_STATUS
,
4375 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
4376 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
4377 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
4379 /* The infamous DAC f*ckup only happens at boot time */
4380 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
4381 if (netif_msg_intr(tp
))
4382 printk(KERN_INFO
"%s: disabling PCI DAC.\n", dev
->name
);
4383 tp
->cp_cmd
&= ~PCIDAC
;
4384 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4385 dev
->features
&= ~NETIF_F_HIGHDMA
;
4388 rtl8169_hw_reset(ioaddr
);
4390 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4393 static void rtl8169_tx_interrupt(struct net_device
*dev
,
4394 struct rtl8169_private
*tp
,
4395 void __iomem
*ioaddr
)
4397 unsigned int dirty_tx
, tx_left
;
4399 dirty_tx
= tp
->dirty_tx
;
4401 tx_left
= tp
->cur_tx
- dirty_tx
;
4403 while (tx_left
> 0) {
4404 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
4405 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4406 u32 len
= tx_skb
->len
;
4410 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
4411 if (status
& DescOwn
)
4414 dev
->stats
.tx_bytes
+= len
;
4415 dev
->stats
.tx_packets
++;
4417 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
, tp
->TxDescArray
+ entry
);
4419 if (status
& LastFrag
) {
4420 dev_kfree_skb(tx_skb
->skb
);
4427 if (tp
->dirty_tx
!= dirty_tx
) {
4428 tp
->dirty_tx
= dirty_tx
;
4430 if (netif_queue_stopped(dev
) &&
4431 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
4432 netif_wake_queue(dev
);
4435 * 8168 hack: TxPoll requests are lost when the Tx packets are
4436 * too close. Let's kick an extra TxPoll request when a burst
4437 * of start_xmit activity is detected (if it is not detected,
4438 * it is slow enough). -- FR
4441 if (tp
->cur_tx
!= dirty_tx
)
4442 RTL_W8(TxPoll
, NPQ
);
4446 static inline int rtl8169_fragmented_frame(u32 status
)
4448 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
4451 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, struct RxDesc
*desc
)
4453 u32 opts1
= le32_to_cpu(desc
->opts1
);
4454 u32 status
= opts1
& RxProtoMask
;
4456 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
4457 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)) ||
4458 ((status
== RxProtoIP
) && !(opts1
& IPFail
)))
4459 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4461 skb
->ip_summed
= CHECKSUM_NONE
;
4464 static inline bool rtl8169_try_rx_copy(struct sk_buff
**sk_buff
,
4465 struct rtl8169_private
*tp
, int pkt_size
,
4468 struct sk_buff
*skb
;
4471 if (pkt_size
>= rx_copybreak
)
4474 skb
= netdev_alloc_skb(tp
->dev
, pkt_size
+ NET_IP_ALIGN
);
4478 pci_dma_sync_single_for_cpu(tp
->pci_dev
, addr
, pkt_size
,
4479 PCI_DMA_FROMDEVICE
);
4480 skb_reserve(skb
, NET_IP_ALIGN
);
4481 skb_copy_from_linear_data(*sk_buff
, skb
->data
, pkt_size
);
4488 static int rtl8169_rx_interrupt(struct net_device
*dev
,
4489 struct rtl8169_private
*tp
,
4490 void __iomem
*ioaddr
, u32 budget
)
4492 unsigned int cur_rx
, rx_left
;
4493 unsigned int delta
, count
;
4495 cur_rx
= tp
->cur_rx
;
4496 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
4497 rx_left
= min(rx_left
, budget
);
4499 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
4500 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
4501 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
4505 status
= le32_to_cpu(desc
->opts1
);
4507 if (status
& DescOwn
)
4509 if (unlikely(status
& RxRES
)) {
4510 if (netif_msg_rx_err(tp
)) {
4512 "%s: Rx ERROR. status = %08x\n",
4515 dev
->stats
.rx_errors
++;
4516 if (status
& (RxRWT
| RxRUNT
))
4517 dev
->stats
.rx_length_errors
++;
4519 dev
->stats
.rx_crc_errors
++;
4520 if (status
& RxFOVF
) {
4521 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4522 dev
->stats
.rx_fifo_errors
++;
4524 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
4526 struct sk_buff
*skb
= tp
->Rx_skbuff
[entry
];
4527 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
4528 int pkt_size
= (status
& 0x00001FFF) - 4;
4529 struct pci_dev
*pdev
= tp
->pci_dev
;
4532 * The driver does not support incoming fragmented
4533 * frames. They are seen as a symptom of over-mtu
4536 if (unlikely(rtl8169_fragmented_frame(status
))) {
4537 dev
->stats
.rx_dropped
++;
4538 dev
->stats
.rx_length_errors
++;
4539 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
4543 rtl8169_rx_csum(skb
, desc
);
4545 if (rtl8169_try_rx_copy(&skb
, tp
, pkt_size
, addr
)) {
4546 pci_dma_sync_single_for_device(pdev
, addr
,
4547 pkt_size
, PCI_DMA_FROMDEVICE
);
4548 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
4550 pci_unmap_single(pdev
, addr
, tp
->rx_buf_sz
,
4551 PCI_DMA_FROMDEVICE
);
4552 tp
->Rx_skbuff
[entry
] = NULL
;
4555 skb_put(skb
, pkt_size
);
4556 skb
->protocol
= eth_type_trans(skb
, dev
);
4558 if (rtl8169_rx_vlan_skb(tp
, desc
, skb
) < 0)
4559 netif_receive_skb(skb
);
4561 dev
->stats
.rx_bytes
+= pkt_size
;
4562 dev
->stats
.rx_packets
++;
4565 /* Work around for AMD plateform. */
4566 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
4567 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
4573 count
= cur_rx
- tp
->cur_rx
;
4574 tp
->cur_rx
= cur_rx
;
4576 delta
= rtl8169_rx_fill(tp
, dev
, tp
->dirty_rx
, tp
->cur_rx
);
4577 if (!delta
&& count
&& netif_msg_intr(tp
))
4578 printk(KERN_INFO
"%s: no Rx buffer allocated\n", dev
->name
);
4579 tp
->dirty_rx
+= delta
;
4582 * FIXME: until there is periodic timer to try and refill the ring,
4583 * a temporary shortage may definitely kill the Rx process.
4584 * - disable the asic to try and avoid an overflow and kick it again
4586 * - how do others driver handle this condition (Uh oh...).
4588 if ((tp
->dirty_rx
+ NUM_RX_DESC
== tp
->cur_rx
) && netif_msg_intr(tp
))
4589 printk(KERN_EMERG
"%s: Rx buffers exhausted\n", dev
->name
);
4594 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
4596 struct net_device
*dev
= dev_instance
;
4597 struct rtl8169_private
*tp
= netdev_priv(dev
);
4598 void __iomem
*ioaddr
= tp
->mmio_addr
;
4602 /* loop handling interrupts until we have no new ones or
4603 * we hit a invalid/hotplug case.
4605 status
= RTL_R16(IntrStatus
);
4606 while (status
&& status
!= 0xffff) {
4609 /* Handle all of the error cases first. These will reset
4610 * the chip, so just exit the loop.
4612 if (unlikely(!netif_running(dev
))) {
4613 rtl8169_asic_down(ioaddr
);
4617 /* Work around for rx fifo overflow */
4618 if (unlikely(status
& RxFIFOOver
) &&
4619 (tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
4620 netif_stop_queue(dev
);
4621 rtl8169_tx_timeout(dev
);
4625 if (unlikely(status
& SYSErr
)) {
4626 rtl8169_pcierr_interrupt(dev
);
4630 if (status
& LinkChg
)
4631 rtl8169_check_link_status(dev
, tp
, ioaddr
);
4633 /* We need to see the lastest version of tp->intr_mask to
4634 * avoid ignoring an MSI interrupt and having to wait for
4635 * another event which may never come.
4638 if (status
& tp
->intr_mask
& tp
->napi_event
) {
4639 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
4640 tp
->intr_mask
= ~tp
->napi_event
;
4642 if (likely(napi_schedule_prep(&tp
->napi
)))
4643 __napi_schedule(&tp
->napi
);
4644 else if (netif_msg_intr(tp
)) {
4645 printk(KERN_INFO
"%s: interrupt %04x in poll\n",
4650 /* We only get a new MSI interrupt when all active irq
4651 * sources on the chip have been acknowledged. So, ack
4652 * everything we've seen and check if new sources have become
4653 * active to avoid blocking all interrupts from the chip.
4656 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
4657 status
= RTL_R16(IntrStatus
);
4660 return IRQ_RETVAL(handled
);
4663 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
4665 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
4666 struct net_device
*dev
= tp
->dev
;
4667 void __iomem
*ioaddr
= tp
->mmio_addr
;
4670 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
4671 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
4673 if (work_done
< budget
) {
4674 napi_complete(napi
);
4676 /* We need for force the visibility of tp->intr_mask
4677 * for other CPUs, as we can loose an MSI interrupt
4678 * and potentially wait for a retransmit timeout if we don't.
4679 * The posted write to IntrMask is safe, as it will
4680 * eventually make it to the chip and we won't loose anything
4683 tp
->intr_mask
= 0xffff;
4685 RTL_W16(IntrMask
, tp
->intr_event
);
4691 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
4693 struct rtl8169_private
*tp
= netdev_priv(dev
);
4695 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
4698 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
4699 RTL_W32(RxMissed
, 0);
4702 static void rtl8169_down(struct net_device
*dev
)
4704 struct rtl8169_private
*tp
= netdev_priv(dev
);
4705 void __iomem
*ioaddr
= tp
->mmio_addr
;
4706 unsigned int intrmask
;
4708 rtl8169_delete_timer(dev
);
4710 netif_stop_queue(dev
);
4712 napi_disable(&tp
->napi
);
4715 spin_lock_irq(&tp
->lock
);
4717 rtl8169_asic_down(ioaddr
);
4719 rtl8169_rx_missed(dev
, ioaddr
);
4721 spin_unlock_irq(&tp
->lock
);
4723 synchronize_irq(dev
->irq
);
4725 /* Give a racing hard_start_xmit a few cycles to complete. */
4726 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4729 * And now for the 50k$ question: are IRQ disabled or not ?
4731 * Two paths lead here:
4733 * -> netif_running() is available to sync the current code and the
4734 * IRQ handler. See rtl8169_interrupt for details.
4735 * 2) dev->change_mtu
4736 * -> rtl8169_poll can not be issued again and re-enable the
4737 * interruptions. Let's simply issue the IRQ down sequence again.
4739 * No loop if hotpluged or major error (0xffff).
4741 intrmask
= RTL_R16(IntrMask
);
4742 if (intrmask
&& (intrmask
!= 0xffff))
4745 rtl8169_tx_clear(tp
);
4747 rtl8169_rx_clear(tp
);
4750 static int rtl8169_close(struct net_device
*dev
)
4752 struct rtl8169_private
*tp
= netdev_priv(dev
);
4753 struct pci_dev
*pdev
= tp
->pci_dev
;
4755 /* update counters before going down */
4756 rtl8169_update_counters(dev
);
4760 free_irq(dev
->irq
, dev
);
4762 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
4764 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
4766 tp
->TxDescArray
= NULL
;
4767 tp
->RxDescArray
= NULL
;
4772 static void rtl_set_rx_mode(struct net_device
*dev
)
4774 struct rtl8169_private
*tp
= netdev_priv(dev
);
4775 void __iomem
*ioaddr
= tp
->mmio_addr
;
4776 unsigned long flags
;
4777 u32 mc_filter
[2]; /* Multicast hash filter */
4781 if (dev
->flags
& IFF_PROMISC
) {
4782 /* Unconditionally log net taps. */
4783 if (netif_msg_link(tp
)) {
4784 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n",
4788 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
4790 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4791 } else if ((dev
->mc_count
> multicast_filter_limit
)
4792 || (dev
->flags
& IFF_ALLMULTI
)) {
4793 /* Too many to filter perfectly -- accept all multicasts. */
4794 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
4795 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4797 struct dev_mc_list
*mclist
;
4800 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
4801 mc_filter
[1] = mc_filter
[0] = 0;
4802 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
4803 i
++, mclist
= mclist
->next
) {
4804 int bit_nr
= ether_crc(ETH_ALEN
, mclist
->dmi_addr
) >> 26;
4805 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
4806 rx_mode
|= AcceptMulticast
;
4810 spin_lock_irqsave(&tp
->lock
, flags
);
4812 tmp
= rtl8169_rx_config
| rx_mode
|
4813 (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
4815 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
4816 u32 data
= mc_filter
[0];
4818 mc_filter
[0] = swab32(mc_filter
[1]);
4819 mc_filter
[1] = swab32(data
);
4822 RTL_W32(MAR0
+ 4, mc_filter
[1]);
4823 RTL_W32(MAR0
+ 0, mc_filter
[0]);
4825 RTL_W32(RxConfig
, tmp
);
4827 spin_unlock_irqrestore(&tp
->lock
, flags
);
4831 * rtl8169_get_stats - Get rtl8169 read/write statistics
4832 * @dev: The Ethernet Device to get statistics for
4834 * Get TX/RX statistics for rtl8169
4836 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
4838 struct rtl8169_private
*tp
= netdev_priv(dev
);
4839 void __iomem
*ioaddr
= tp
->mmio_addr
;
4840 unsigned long flags
;
4842 if (netif_running(dev
)) {
4843 spin_lock_irqsave(&tp
->lock
, flags
);
4844 rtl8169_rx_missed(dev
, ioaddr
);
4845 spin_unlock_irqrestore(&tp
->lock
, flags
);
4851 static void rtl8169_net_suspend(struct net_device
*dev
)
4853 if (!netif_running(dev
))
4856 netif_device_detach(dev
);
4857 netif_stop_queue(dev
);
4862 static int rtl8169_suspend(struct device
*device
)
4864 struct pci_dev
*pdev
= to_pci_dev(device
);
4865 struct net_device
*dev
= pci_get_drvdata(pdev
);
4867 rtl8169_net_suspend(dev
);
4872 static int rtl8169_resume(struct device
*device
)
4874 struct pci_dev
*pdev
= to_pci_dev(device
);
4875 struct net_device
*dev
= pci_get_drvdata(pdev
);
4877 if (!netif_running(dev
))
4880 netif_device_attach(dev
);
4882 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4887 static struct dev_pm_ops rtl8169_pm_ops
= {
4888 .suspend
= rtl8169_suspend
,
4889 .resume
= rtl8169_resume
,
4890 .freeze
= rtl8169_suspend
,
4891 .thaw
= rtl8169_resume
,
4892 .poweroff
= rtl8169_suspend
,
4893 .restore
= rtl8169_resume
,
4896 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4898 #else /* !CONFIG_PM */
4900 #define RTL8169_PM_OPS NULL
4902 #endif /* !CONFIG_PM */
4904 static void rtl_shutdown(struct pci_dev
*pdev
)
4906 struct net_device
*dev
= pci_get_drvdata(pdev
);
4907 struct rtl8169_private
*tp
= netdev_priv(dev
);
4908 void __iomem
*ioaddr
= tp
->mmio_addr
;
4910 rtl8169_net_suspend(dev
);
4912 /* restore original MAC address */
4913 rtl_rar_set(tp
, dev
->perm_addr
);
4915 spin_lock_irq(&tp
->lock
);
4917 rtl8169_asic_down(ioaddr
);
4919 spin_unlock_irq(&tp
->lock
);
4921 if (system_state
== SYSTEM_POWER_OFF
) {
4922 /* WoL fails with some 8168 when the receiver is disabled. */
4923 if (tp
->features
& RTL_FEATURE_WOL
) {
4924 pci_clear_master(pdev
);
4926 RTL_W8(ChipCmd
, CmdRxEnb
);
4931 pci_wake_from_d3(pdev
, true);
4932 pci_set_power_state(pdev
, PCI_D3hot
);
4936 static struct pci_driver rtl8169_pci_driver
= {
4938 .id_table
= rtl8169_pci_tbl
,
4939 .probe
= rtl8169_init_one
,
4940 .remove
= __devexit_p(rtl8169_remove_one
),
4941 .shutdown
= rtl_shutdown
,
4942 .driver
.pm
= RTL8169_PM_OPS
,
4945 static int __init
rtl8169_init_module(void)
4947 return pci_register_driver(&rtl8169_pci_driver
);
4950 static void __exit
rtl8169_cleanup_module(void)
4952 pci_unregister_driver(&rtl8169_pci_driver
);
4955 module_init(rtl8169_init_module
);
4956 module_exit(rtl8169_cleanup_module
);