2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/moduleparam.h>
44 #include <linux/stat.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/slab.h>
48 #include "musb_core.h"
51 /* MUSB PERIPHERAL status 3-mar-2006:
53 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
56 * + remote wakeup to Linux hosts work, but saw USBCV failures;
57 * in one test run (operator error?)
58 * + endpoint halt tests -- in both usbtest and usbcv -- seem
59 * to break when dma is enabled ... is something wrongly
62 * - Mass storage behaved ok when last tested. Network traffic patterns
63 * (with lots of short transfers etc) need retesting; they turn up the
64 * worst cases of the DMA, since short packets are typical but are not
68 * + both pio and dma behave in with network and g_zero tests
69 * + no cppi throughput issues other than no-hw-queueing
70 * + failed with FLAT_REG (DaVinci)
71 * + seems to behave with double buffering, PIO -and- CPPI
72 * + with gadgetfs + AIO, requests got lost?
75 * + both pio and dma behave in with network and g_zero tests
76 * + dma is slow in typical case (short_not_ok is clear)
77 * + double buffering ok with PIO
78 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
79 * + request lossage observed with gadgetfs
81 * - ISO not tested ... might work, but only weakly isochronous
83 * - Gadget driver disabling of softconnect during bind() is ignored; so
84 * drivers can't hold off host requests until userspace is ready.
85 * (Workaround: they can turn it off later.)
87 * - PORTABILITY (assumes PIO works):
88 * + DaVinci, basically works with cppi dma
89 * + OMAP 2430, ditto with mentor dma
90 * + TUSB 6010, platform-specific dma in the works
93 /* ----------------------------------------------------------------------- */
95 #define is_buffer_mapped(req) (is_dma_capable() && \
96 (req->map_state != UN_MAPPED))
98 /* Maps the buffer to dma */
100 static inline void map_dma_buffer(struct musb_request
*request
,
101 struct musb
*musb
, struct musb_ep
*musb_ep
)
103 int compatible
= true;
104 struct dma_controller
*dma
= musb
->dma_controller
;
106 request
->map_state
= UN_MAPPED
;
108 if (!is_dma_capable() || !musb_ep
->dma
)
111 /* Check if DMA engine can handle this request.
112 * DMA code must reject the USB request explicitly.
113 * Default behaviour is to map the request.
115 if (dma
->is_compatible
)
116 compatible
= dma
->is_compatible(musb_ep
->dma
,
117 musb_ep
->packet_sz
, request
->request
.buf
,
118 request
->request
.length
);
122 if (request
->request
.dma
== DMA_ADDR_INVALID
) {
123 request
->request
.dma
= dma_map_single(
125 request
->request
.buf
,
126 request
->request
.length
,
130 request
->map_state
= MUSB_MAPPED
;
132 dma_sync_single_for_device(musb
->controller
,
133 request
->request
.dma
,
134 request
->request
.length
,
138 request
->map_state
= PRE_MAPPED
;
142 /* Unmap the buffer from dma and maps it back to cpu */
143 static inline void unmap_dma_buffer(struct musb_request
*request
,
146 if (!is_buffer_mapped(request
))
149 if (request
->request
.dma
== DMA_ADDR_INVALID
) {
150 dev_vdbg(musb
->controller
,
151 "not unmapping a never mapped buffer\n");
154 if (request
->map_state
== MUSB_MAPPED
) {
155 dma_unmap_single(musb
->controller
,
156 request
->request
.dma
,
157 request
->request
.length
,
161 request
->request
.dma
= DMA_ADDR_INVALID
;
162 } else { /* PRE_MAPPED */
163 dma_sync_single_for_cpu(musb
->controller
,
164 request
->request
.dma
,
165 request
->request
.length
,
170 request
->map_state
= UN_MAPPED
;
174 * Immediately complete a request.
176 * @param request the request to complete
177 * @param status the status to complete the request with
178 * Context: controller locked, IRQs blocked.
180 void musb_g_giveback(
182 struct usb_request
*request
,
184 __releases(ep
->musb
->lock
)
185 __acquires(ep
->musb
->lock
)
187 struct musb_request
*req
;
191 req
= to_musb_request(request
);
193 list_del(&req
->list
);
194 if (req
->request
.status
== -EINPROGRESS
)
195 req
->request
.status
= status
;
199 spin_unlock(&musb
->lock
);
200 unmap_dma_buffer(req
, musb
);
201 if (request
->status
== 0)
202 dev_dbg(musb
->controller
, "%s done request %p, %d/%d\n",
203 ep
->end_point
.name
, request
,
204 req
->request
.actual
, req
->request
.length
);
206 dev_dbg(musb
->controller
, "%s request %p, %d/%d fault %d\n",
207 ep
->end_point
.name
, request
,
208 req
->request
.actual
, req
->request
.length
,
210 req
->request
.complete(&req
->ep
->end_point
, &req
->request
);
211 spin_lock(&musb
->lock
);
215 /* ----------------------------------------------------------------------- */
218 * Abort requests queued to an endpoint using the status. Synchronous.
219 * caller locked controller and blocked irqs, and selected this ep.
221 static void nuke(struct musb_ep
*ep
, const int status
)
223 struct musb
*musb
= ep
->musb
;
224 struct musb_request
*req
= NULL
;
225 void __iomem
*epio
= ep
->musb
->endpoints
[ep
->current_epnum
].regs
;
229 if (is_dma_capable() && ep
->dma
) {
230 struct dma_controller
*c
= ep
->musb
->dma_controller
;
235 * The programming guide says that we must not clear
236 * the DMAMODE bit before DMAENAB, so we only
237 * clear it in the second write...
239 musb_writew(epio
, MUSB_TXCSR
,
240 MUSB_TXCSR_DMAMODE
| MUSB_TXCSR_FLUSHFIFO
);
241 musb_writew(epio
, MUSB_TXCSR
,
242 0 | MUSB_TXCSR_FLUSHFIFO
);
244 musb_writew(epio
, MUSB_RXCSR
,
245 0 | MUSB_RXCSR_FLUSHFIFO
);
246 musb_writew(epio
, MUSB_RXCSR
,
247 0 | MUSB_RXCSR_FLUSHFIFO
);
250 value
= c
->channel_abort(ep
->dma
);
251 dev_dbg(musb
->controller
, "%s: abort DMA --> %d\n",
253 c
->channel_release(ep
->dma
);
257 while (!list_empty(&ep
->req_list
)) {
258 req
= list_first_entry(&ep
->req_list
, struct musb_request
, list
);
259 musb_g_giveback(ep
, &req
->request
, status
);
263 /* ----------------------------------------------------------------------- */
265 /* Data transfers - pure PIO, pure DMA, or mixed mode */
268 * This assumes the separate CPPI engine is responding to DMA requests
269 * from the usb core ... sequenced a bit differently from mentor dma.
272 static inline int max_ep_writesize(struct musb
*musb
, struct musb_ep
*ep
)
274 if (can_bulk_split(musb
, ep
->type
))
275 return ep
->hw_ep
->max_packet_sz_tx
;
277 return ep
->packet_sz
;
281 #ifdef CONFIG_USB_INVENTRA_DMA
283 /* Peripheral tx (IN) using Mentor DMA works as follows:
284 Only mode 0 is used for transfers <= wPktSize,
285 mode 1 is used for larger transfers,
287 One of the following happens:
288 - Host sends IN token which causes an endpoint interrupt
290 -> if DMA is currently busy, exit.
291 -> if queue is non-empty, txstate().
293 - Request is queued by the gadget driver.
294 -> if queue was previously empty, txstate()
299 | (data is transferred to the FIFO, then sent out when
300 | IN token(s) are recd from Host.
301 | -> DMA interrupt on completion
303 | -> stop DMA, ~DMAENAB,
304 | -> set TxPktRdy for last short pkt or zlp
305 | -> Complete Request
306 | -> Continue next request (call txstate)
307 |___________________________________|
309 * Non-Mentor DMA engines can of course work differently, such as by
310 * upleveling from irq-per-packet to irq-per-buffer.
316 * An endpoint is transmitting data. This can be called either from
317 * the IRQ routine or from ep.queue() to kickstart a request on an
320 * Context: controller locked, IRQs blocked, endpoint selected
322 static void txstate(struct musb
*musb
, struct musb_request
*req
)
324 u8 epnum
= req
->epnum
;
325 struct musb_ep
*musb_ep
;
326 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
327 struct usb_request
*request
;
328 u16 fifo_count
= 0, csr
;
333 /* we shouldn't get here while DMA is active ... but we do ... */
334 if (dma_channel_status(musb_ep
->dma
) == MUSB_DMA_STATUS_BUSY
) {
335 dev_dbg(musb
->controller
, "dma pending...\n");
339 /* read TXCSR before */
340 csr
= musb_readw(epio
, MUSB_TXCSR
);
342 request
= &req
->request
;
343 fifo_count
= min(max_ep_writesize(musb
, musb_ep
),
344 (int)(request
->length
- request
->actual
));
346 if (csr
& MUSB_TXCSR_TXPKTRDY
) {
347 dev_dbg(musb
->controller
, "%s old packet still ready , txcsr %03x\n",
348 musb_ep
->end_point
.name
, csr
);
352 if (csr
& MUSB_TXCSR_P_SENDSTALL
) {
353 dev_dbg(musb
->controller
, "%s stalling, txcsr %03x\n",
354 musb_ep
->end_point
.name
, csr
);
358 dev_dbg(musb
->controller
, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
359 epnum
, musb_ep
->packet_sz
, fifo_count
,
362 #ifndef CONFIG_MUSB_PIO_ONLY
363 if (is_buffer_mapped(req
)) {
364 struct dma_controller
*c
= musb
->dma_controller
;
367 /* setup DMA, then program endpoint CSR */
368 request_size
= min_t(size_t, request
->length
- request
->actual
,
369 musb_ep
->dma
->max_len
);
371 use_dma
= (request
->dma
!= DMA_ADDR_INVALID
);
373 /* MUSB_TXCSR_P_ISO is still set correctly */
375 #ifdef CONFIG_USB_INVENTRA_DMA
377 if (request_size
< musb_ep
->packet_sz
)
378 musb_ep
->dma
->desired_mode
= 0;
380 musb_ep
->dma
->desired_mode
= 1;
382 use_dma
= use_dma
&& c
->channel_program(
383 musb_ep
->dma
, musb_ep
->packet_sz
,
384 musb_ep
->dma
->desired_mode
,
385 request
->dma
+ request
->actual
, request_size
);
387 if (musb_ep
->dma
->desired_mode
== 0) {
389 * We must not clear the DMAMODE bit
390 * before the DMAENAB bit -- and the
391 * latter doesn't always get cleared
392 * before we get here...
394 csr
&= ~(MUSB_TXCSR_AUTOSET
395 | MUSB_TXCSR_DMAENAB
);
396 musb_writew(epio
, MUSB_TXCSR
, csr
397 | MUSB_TXCSR_P_WZC_BITS
);
398 csr
&= ~MUSB_TXCSR_DMAMODE
;
399 csr
|= (MUSB_TXCSR_DMAENAB
|
401 /* against programming guide */
403 csr
|= (MUSB_TXCSR_DMAENAB
406 if (!musb_ep
->hb_mult
)
407 csr
|= MUSB_TXCSR_AUTOSET
;
409 csr
&= ~MUSB_TXCSR_P_UNDERRUN
;
411 musb_writew(epio
, MUSB_TXCSR
, csr
);
415 #elif defined(CONFIG_USB_TI_CPPI_DMA)
416 /* program endpoint CSR first, then setup DMA */
417 csr
&= ~(MUSB_TXCSR_P_UNDERRUN
| MUSB_TXCSR_TXPKTRDY
);
418 csr
|= MUSB_TXCSR_DMAENAB
| MUSB_TXCSR_DMAMODE
|
420 musb_writew(epio
, MUSB_TXCSR
,
421 (MUSB_TXCSR_P_WZC_BITS
& ~MUSB_TXCSR_P_UNDERRUN
)
424 /* ensure writebuffer is empty */
425 csr
= musb_readw(epio
, MUSB_TXCSR
);
427 /* NOTE host side sets DMAENAB later than this; both are
428 * OK since the transfer dma glue (between CPPI and Mentor
429 * fifos) just tells CPPI it could start. Data only moves
430 * to the USB TX fifo when both fifos are ready.
433 /* "mode" is irrelevant here; handle terminating ZLPs like
434 * PIO does, since the hardware RNDIS mode seems unreliable
435 * except for the last-packet-is-already-short case.
437 use_dma
= use_dma
&& c
->channel_program(
438 musb_ep
->dma
, musb_ep
->packet_sz
,
440 request
->dma
+ request
->actual
,
443 c
->channel_release(musb_ep
->dma
);
445 csr
&= ~MUSB_TXCSR_DMAENAB
;
446 musb_writew(epio
, MUSB_TXCSR
, csr
);
447 /* invariant: prequest->buf is non-null */
449 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
450 use_dma
= use_dma
&& c
->channel_program(
451 musb_ep
->dma
, musb_ep
->packet_sz
,
453 request
->dma
+ request
->actual
,
461 * Unmap the dma buffer back to cpu if dma channel
464 unmap_dma_buffer(req
, musb
);
466 musb_write_fifo(musb_ep
->hw_ep
, fifo_count
,
467 (u8
*) (request
->buf
+ request
->actual
));
468 request
->actual
+= fifo_count
;
469 csr
|= MUSB_TXCSR_TXPKTRDY
;
470 csr
&= ~MUSB_TXCSR_P_UNDERRUN
;
471 musb_writew(epio
, MUSB_TXCSR
, csr
);
474 /* host may already have the data when this message shows... */
475 dev_dbg(musb
->controller
, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
476 musb_ep
->end_point
.name
, use_dma
? "dma" : "pio",
477 request
->actual
, request
->length
,
478 musb_readw(epio
, MUSB_TXCSR
),
480 musb_readw(epio
, MUSB_TXMAXP
));
484 * FIFO state update (e.g. data ready).
485 * Called from IRQ, with controller locked.
487 void musb_g_tx(struct musb
*musb
, u8 epnum
)
490 struct musb_request
*req
;
491 struct usb_request
*request
;
492 u8 __iomem
*mbase
= musb
->mregs
;
493 struct musb_ep
*musb_ep
= &musb
->endpoints
[epnum
].ep_in
;
494 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
495 struct dma_channel
*dma
;
497 musb_ep_select(mbase
, epnum
);
498 req
= next_request(musb_ep
);
499 request
= &req
->request
;
501 csr
= musb_readw(epio
, MUSB_TXCSR
);
502 dev_dbg(musb
->controller
, "<== %s, txcsr %04x\n", musb_ep
->end_point
.name
, csr
);
504 dma
= is_dma_capable() ? musb_ep
->dma
: NULL
;
507 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
508 * probably rates reporting as a host error.
510 if (csr
& MUSB_TXCSR_P_SENTSTALL
) {
511 csr
|= MUSB_TXCSR_P_WZC_BITS
;
512 csr
&= ~MUSB_TXCSR_P_SENTSTALL
;
513 musb_writew(epio
, MUSB_TXCSR
, csr
);
517 if (csr
& MUSB_TXCSR_P_UNDERRUN
) {
518 /* We NAKed, no big deal... little reason to care. */
519 csr
|= MUSB_TXCSR_P_WZC_BITS
;
520 csr
&= ~(MUSB_TXCSR_P_UNDERRUN
| MUSB_TXCSR_TXPKTRDY
);
521 musb_writew(epio
, MUSB_TXCSR
, csr
);
522 dev_vdbg(musb
->controller
, "underrun on ep%d, req %p\n",
526 if (dma_channel_status(dma
) == MUSB_DMA_STATUS_BUSY
) {
528 * SHOULD NOT HAPPEN... has with CPPI though, after
529 * changing SENDSTALL (and other cases); harmless?
531 dev_dbg(musb
->controller
, "%s dma still busy?\n", musb_ep
->end_point
.name
);
538 if (dma
&& (csr
& MUSB_TXCSR_DMAENAB
)) {
540 csr
|= MUSB_TXCSR_P_WZC_BITS
;
541 csr
&= ~(MUSB_TXCSR_DMAENAB
| MUSB_TXCSR_P_UNDERRUN
|
542 MUSB_TXCSR_TXPKTRDY
| MUSB_TXCSR_AUTOSET
);
543 musb_writew(epio
, MUSB_TXCSR
, csr
);
544 /* Ensure writebuffer is empty. */
545 csr
= musb_readw(epio
, MUSB_TXCSR
);
546 request
->actual
+= musb_ep
->dma
->actual_len
;
547 dev_dbg(musb
->controller
, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
548 epnum
, csr
, musb_ep
->dma
->actual_len
, request
);
552 * First, maybe a terminating short packet. Some DMA
553 * engines might handle this by themselves.
555 if ((request
->zero
&& request
->length
556 && (request
->length
% musb_ep
->packet_sz
== 0)
557 && (request
->actual
== request
->length
))
558 #ifdef CONFIG_USB_INVENTRA_DMA
559 || (is_dma
&& (!dma
->desired_mode
||
561 (musb_ep
->packet_sz
- 1))))
565 * On DMA completion, FIFO may not be
568 if (csr
& MUSB_TXCSR_TXPKTRDY
)
571 dev_dbg(musb
->controller
, "sending zero pkt\n");
572 musb_writew(epio
, MUSB_TXCSR
, MUSB_TXCSR_MODE
573 | MUSB_TXCSR_TXPKTRDY
);
577 if (request
->actual
== request
->length
) {
578 musb_g_giveback(musb_ep
, request
, 0);
579 req
= musb_ep
->desc
? next_request(musb_ep
) : NULL
;
581 dev_dbg(musb
->controller
, "%s idle now\n",
582 musb_ep
->end_point
.name
);
591 /* ------------------------------------------------------------ */
593 #ifdef CONFIG_USB_INVENTRA_DMA
595 /* Peripheral rx (OUT) using Mentor DMA works as follows:
596 - Only mode 0 is used.
598 - Request is queued by the gadget class driver.
599 -> if queue was previously empty, rxstate()
601 - Host sends OUT token which causes an endpoint interrupt
603 | -> if request queued, call rxstate
605 | | -> DMA interrupt on completion
609 | | -> if data recd = max expected
610 | | by the request, or host
611 | | sent a short packet,
612 | | complete the request,
613 | | and start the next one.
614 | |_____________________________________|
615 | else just wait for the host
616 | to send the next OUT token.
617 |__________________________________________________|
619 * Non-Mentor DMA engines can of course work differently.
625 * Context: controller locked, IRQs blocked, endpoint selected
627 static void rxstate(struct musb
*musb
, struct musb_request
*req
)
629 const u8 epnum
= req
->epnum
;
630 struct usb_request
*request
= &req
->request
;
631 struct musb_ep
*musb_ep
;
632 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
633 unsigned fifo_count
= 0;
635 u16 csr
= musb_readw(epio
, MUSB_RXCSR
);
636 struct musb_hw_ep
*hw_ep
= &musb
->endpoints
[epnum
];
638 if (hw_ep
->is_shared_fifo
)
639 musb_ep
= &hw_ep
->ep_in
;
641 musb_ep
= &hw_ep
->ep_out
;
643 len
= musb_ep
->packet_sz
;
645 /* We shouldn't get here while DMA is active, but we do... */
646 if (dma_channel_status(musb_ep
->dma
) == MUSB_DMA_STATUS_BUSY
) {
647 dev_dbg(musb
->controller
, "DMA pending...\n");
651 if (csr
& MUSB_RXCSR_P_SENDSTALL
) {
652 dev_dbg(musb
->controller
, "%s stalling, RXCSR %04x\n",
653 musb_ep
->end_point
.name
, csr
);
657 if (is_cppi_enabled() && is_buffer_mapped(req
)) {
658 struct dma_controller
*c
= musb
->dma_controller
;
659 struct dma_channel
*channel
= musb_ep
->dma
;
661 /* NOTE: CPPI won't actually stop advancing the DMA
662 * queue after short packet transfers, so this is almost
663 * always going to run as IRQ-per-packet DMA so that
664 * faults will be handled correctly.
666 if (c
->channel_program(channel
,
668 !request
->short_not_ok
,
669 request
->dma
+ request
->actual
,
670 request
->length
- request
->actual
)) {
672 /* make sure that if an rxpkt arrived after the irq,
673 * the cppi engine will be ready to take it as soon
676 csr
&= ~(MUSB_RXCSR_AUTOCLEAR
677 | MUSB_RXCSR_DMAMODE
);
678 csr
|= MUSB_RXCSR_DMAENAB
| MUSB_RXCSR_P_WZC_BITS
;
679 musb_writew(epio
, MUSB_RXCSR
, csr
);
684 if (csr
& MUSB_RXCSR_RXPKTRDY
) {
685 len
= musb_readw(epio
, MUSB_RXCOUNT
);
686 if (request
->actual
< request
->length
) {
687 #ifdef CONFIG_USB_INVENTRA_DMA
688 if (is_buffer_mapped(req
)) {
689 struct dma_controller
*c
;
690 struct dma_channel
*channel
;
693 c
= musb
->dma_controller
;
694 channel
= musb_ep
->dma
;
696 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
697 * mode 0 only. So we do not get endpoint interrupts due to DMA
698 * completion. We only get interrupts from DMA controller.
700 * We could operate in DMA mode 1 if we knew the size of the tranfer
701 * in advance. For mass storage class, request->length = what the host
702 * sends, so that'd work. But for pretty much everything else,
703 * request->length is routinely more than what the host sends. For
704 * most these gadgets, end of is signified either by a short packet,
705 * or filling the last byte of the buffer. (Sending extra data in
706 * that last pckate should trigger an overflow fault.) But in mode 1,
707 * we don't get DMA completion interrrupt for short packets.
709 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
710 * to get endpoint interrupt on every DMA req, but that didn't seem
713 * REVISIT an updated g_file_storage can set req->short_not_ok, which
714 * then becomes usable as a runtime "use mode 1" hint...
717 csr
|= MUSB_RXCSR_DMAENAB
;
719 csr
|= MUSB_RXCSR_AUTOCLEAR
;
720 /* csr |= MUSB_RXCSR_DMAMODE; */
722 /* this special sequence (enabling and then
723 * disabling MUSB_RXCSR_DMAMODE) is required
724 * to get DMAReq to activate
726 musb_writew(epio
, MUSB_RXCSR
,
727 csr
| MUSB_RXCSR_DMAMODE
);
729 if (!musb_ep
->hb_mult
&&
730 musb_ep
->hw_ep
->rx_double_buffered
)
731 csr
|= MUSB_RXCSR_AUTOCLEAR
;
733 musb_writew(epio
, MUSB_RXCSR
, csr
);
735 if (request
->actual
< request
->length
) {
736 int transfer_size
= 0;
738 transfer_size
= min(request
->length
- request
->actual
,
741 transfer_size
= min(request
->length
- request
->actual
,
744 if (transfer_size
<= musb_ep
->packet_sz
)
745 musb_ep
->dma
->desired_mode
= 0;
747 musb_ep
->dma
->desired_mode
= 1;
749 use_dma
= c
->channel_program(
752 channel
->desired_mode
,
761 #endif /* Mentor's DMA */
763 fifo_count
= request
->length
- request
->actual
;
764 dev_dbg(musb
->controller
, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
765 musb_ep
->end_point
.name
,
769 fifo_count
= min_t(unsigned, len
, fifo_count
);
771 #ifdef CONFIG_USB_TUSB_OMAP_DMA
772 if (tusb_dma_omap() && is_buffer_mapped(req
)) {
773 struct dma_controller
*c
= musb
->dma_controller
;
774 struct dma_channel
*channel
= musb_ep
->dma
;
775 u32 dma_addr
= request
->dma
+ request
->actual
;
778 ret
= c
->channel_program(channel
,
780 channel
->desired_mode
,
788 * Unmap the dma buffer back to cpu if dma channel
789 * programming fails. This buffer is mapped if the
790 * channel allocation is successful
792 if (is_buffer_mapped(req
)) {
793 unmap_dma_buffer(req
, musb
);
796 * Clear DMAENAB and AUTOCLEAR for the
799 csr
&= ~(MUSB_RXCSR_DMAENAB
| MUSB_RXCSR_AUTOCLEAR
);
800 musb_writew(epio
, MUSB_RXCSR
, csr
);
803 musb_read_fifo(musb_ep
->hw_ep
, fifo_count
, (u8
*)
804 (request
->buf
+ request
->actual
));
805 request
->actual
+= fifo_count
;
807 /* REVISIT if we left anything in the fifo, flush
808 * it and report -EOVERFLOW
812 csr
|= MUSB_RXCSR_P_WZC_BITS
;
813 csr
&= ~MUSB_RXCSR_RXPKTRDY
;
814 musb_writew(epio
, MUSB_RXCSR
, csr
);
818 /* reach the end or short packet detected */
819 if (request
->actual
== request
->length
|| len
< musb_ep
->packet_sz
)
820 musb_g_giveback(musb_ep
, request
, 0);
824 * Data ready for a request; called from IRQ
826 void musb_g_rx(struct musb
*musb
, u8 epnum
)
829 struct musb_request
*req
;
830 struct usb_request
*request
;
831 void __iomem
*mbase
= musb
->mregs
;
832 struct musb_ep
*musb_ep
;
833 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
834 struct dma_channel
*dma
;
835 struct musb_hw_ep
*hw_ep
= &musb
->endpoints
[epnum
];
837 if (hw_ep
->is_shared_fifo
)
838 musb_ep
= &hw_ep
->ep_in
;
840 musb_ep
= &hw_ep
->ep_out
;
842 musb_ep_select(mbase
, epnum
);
844 req
= next_request(musb_ep
);
848 request
= &req
->request
;
850 csr
= musb_readw(epio
, MUSB_RXCSR
);
851 dma
= is_dma_capable() ? musb_ep
->dma
: NULL
;
853 dev_dbg(musb
->controller
, "<== %s, rxcsr %04x%s %p\n", musb_ep
->end_point
.name
,
854 csr
, dma
? " (dma)" : "", request
);
856 if (csr
& MUSB_RXCSR_P_SENTSTALL
) {
857 csr
|= MUSB_RXCSR_P_WZC_BITS
;
858 csr
&= ~MUSB_RXCSR_P_SENTSTALL
;
859 musb_writew(epio
, MUSB_RXCSR
, csr
);
863 if (csr
& MUSB_RXCSR_P_OVERRUN
) {
864 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
865 csr
&= ~MUSB_RXCSR_P_OVERRUN
;
866 musb_writew(epio
, MUSB_RXCSR
, csr
);
868 dev_dbg(musb
->controller
, "%s iso overrun on %p\n", musb_ep
->name
, request
);
869 if (request
->status
== -EINPROGRESS
)
870 request
->status
= -EOVERFLOW
;
872 if (csr
& MUSB_RXCSR_INCOMPRX
) {
873 /* REVISIT not necessarily an error */
874 dev_dbg(musb
->controller
, "%s, incomprx\n", musb_ep
->end_point
.name
);
877 if (dma_channel_status(dma
) == MUSB_DMA_STATUS_BUSY
) {
878 /* "should not happen"; likely RXPKTRDY pending for DMA */
879 dev_dbg(musb
->controller
, "%s busy, csr %04x\n",
880 musb_ep
->end_point
.name
, csr
);
884 if (dma
&& (csr
& MUSB_RXCSR_DMAENAB
)) {
885 csr
&= ~(MUSB_RXCSR_AUTOCLEAR
887 | MUSB_RXCSR_DMAMODE
);
888 musb_writew(epio
, MUSB_RXCSR
,
889 MUSB_RXCSR_P_WZC_BITS
| csr
);
891 request
->actual
+= musb_ep
->dma
->actual_len
;
893 dev_dbg(musb
->controller
, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
895 musb_readw(epio
, MUSB_RXCSR
),
896 musb_ep
->dma
->actual_len
, request
);
898 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
899 /* Autoclear doesn't clear RxPktRdy for short packets */
900 if ((dma
->desired_mode
== 0 && !hw_ep
->rx_double_buffered
)
902 & (musb_ep
->packet_sz
- 1))) {
904 csr
&= ~MUSB_RXCSR_RXPKTRDY
;
905 musb_writew(epio
, MUSB_RXCSR
, csr
);
908 /* incomplete, and not short? wait for next IN packet */
909 if ((request
->actual
< request
->length
)
910 && (musb_ep
->dma
->actual_len
911 == musb_ep
->packet_sz
)) {
912 /* In double buffer case, continue to unload fifo if
913 * there is Rx packet in FIFO.
915 csr
= musb_readw(epio
, MUSB_RXCSR
);
916 if ((csr
& MUSB_RXCSR_RXPKTRDY
) &&
917 hw_ep
->rx_double_buffered
)
922 musb_g_giveback(musb_ep
, request
, 0);
924 req
= next_request(musb_ep
);
928 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
931 /* Analyze request */
935 /* ------------------------------------------------------------ */
937 static int musb_gadget_enable(struct usb_ep
*ep
,
938 const struct usb_endpoint_descriptor
*desc
)
941 struct musb_ep
*musb_ep
;
942 struct musb_hw_ep
*hw_ep
;
949 int status
= -EINVAL
;
954 musb_ep
= to_musb_ep(ep
);
955 hw_ep
= musb_ep
->hw_ep
;
957 musb
= musb_ep
->musb
;
959 epnum
= musb_ep
->current_epnum
;
961 spin_lock_irqsave(&musb
->lock
, flags
);
967 musb_ep
->type
= usb_endpoint_type(desc
);
969 /* check direction and (later) maxpacket size against endpoint */
970 if (usb_endpoint_num(desc
) != epnum
)
973 /* REVISIT this rules out high bandwidth periodic transfers */
974 tmp
= le16_to_cpu(desc
->wMaxPacketSize
);
978 if (usb_endpoint_dir_in(desc
))
979 ok
= musb
->hb_iso_tx
;
981 ok
= musb
->hb_iso_rx
;
984 dev_dbg(musb
->controller
, "no support for high bandwidth ISO\n");
987 musb_ep
->hb_mult
= (tmp
>> 11) & 3;
989 musb_ep
->hb_mult
= 0;
992 musb_ep
->packet_sz
= tmp
& 0x7ff;
993 tmp
= musb_ep
->packet_sz
* (musb_ep
->hb_mult
+ 1);
995 /* enable the interrupts for the endpoint, set the endpoint
996 * packet size (or fail), set the mode, clear the fifo
998 musb_ep_select(mbase
, epnum
);
999 if (usb_endpoint_dir_in(desc
)) {
1000 u16 int_txe
= musb_readw(mbase
, MUSB_INTRTXE
);
1002 if (hw_ep
->is_shared_fifo
)
1004 if (!musb_ep
->is_in
)
1007 if (tmp
> hw_ep
->max_packet_sz_tx
) {
1008 dev_dbg(musb
->controller
, "packet size beyond hardware FIFO size\n");
1012 int_txe
|= (1 << epnum
);
1013 musb_writew(mbase
, MUSB_INTRTXE
, int_txe
);
1015 /* REVISIT if can_bulk_split(), use by updating "tmp";
1016 * likewise high bandwidth periodic tx
1018 /* Set TXMAXP with the FIFO size of the endpoint
1019 * to disable double buffering mode.
1021 if (musb
->double_buffer_not_ok
)
1022 musb_writew(regs
, MUSB_TXMAXP
, hw_ep
->max_packet_sz_tx
);
1024 musb_writew(regs
, MUSB_TXMAXP
, musb_ep
->packet_sz
1025 | (musb_ep
->hb_mult
<< 11));
1027 csr
= MUSB_TXCSR_MODE
| MUSB_TXCSR_CLRDATATOG
;
1028 if (musb_readw(regs
, MUSB_TXCSR
)
1029 & MUSB_TXCSR_FIFONOTEMPTY
)
1030 csr
|= MUSB_TXCSR_FLUSHFIFO
;
1031 if (musb_ep
->type
== USB_ENDPOINT_XFER_ISOC
)
1032 csr
|= MUSB_TXCSR_P_ISO
;
1034 /* set twice in case of double buffering */
1035 musb_writew(regs
, MUSB_TXCSR
, csr
);
1036 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1037 musb_writew(regs
, MUSB_TXCSR
, csr
);
1040 u16 int_rxe
= musb_readw(mbase
, MUSB_INTRRXE
);
1042 if (hw_ep
->is_shared_fifo
)
1047 if (tmp
> hw_ep
->max_packet_sz_rx
) {
1048 dev_dbg(musb
->controller
, "packet size beyond hardware FIFO size\n");
1052 int_rxe
|= (1 << epnum
);
1053 musb_writew(mbase
, MUSB_INTRRXE
, int_rxe
);
1055 /* REVISIT if can_bulk_combine() use by updating "tmp"
1056 * likewise high bandwidth periodic rx
1058 /* Set RXMAXP with the FIFO size of the endpoint
1059 * to disable double buffering mode.
1061 if (musb
->double_buffer_not_ok
)
1062 musb_writew(regs
, MUSB_RXMAXP
, hw_ep
->max_packet_sz_tx
);
1064 musb_writew(regs
, MUSB_RXMAXP
, musb_ep
->packet_sz
1065 | (musb_ep
->hb_mult
<< 11));
1067 /* force shared fifo to OUT-only mode */
1068 if (hw_ep
->is_shared_fifo
) {
1069 csr
= musb_readw(regs
, MUSB_TXCSR
);
1070 csr
&= ~(MUSB_TXCSR_MODE
| MUSB_TXCSR_TXPKTRDY
);
1071 musb_writew(regs
, MUSB_TXCSR
, csr
);
1074 csr
= MUSB_RXCSR_FLUSHFIFO
| MUSB_RXCSR_CLRDATATOG
;
1075 if (musb_ep
->type
== USB_ENDPOINT_XFER_ISOC
)
1076 csr
|= MUSB_RXCSR_P_ISO
;
1077 else if (musb_ep
->type
== USB_ENDPOINT_XFER_INT
)
1078 csr
|= MUSB_RXCSR_DISNYET
;
1080 /* set twice in case of double buffering */
1081 musb_writew(regs
, MUSB_RXCSR
, csr
);
1082 musb_writew(regs
, MUSB_RXCSR
, csr
);
1085 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1086 * for some reason you run out of channels here.
1088 if (is_dma_capable() && musb
->dma_controller
) {
1089 struct dma_controller
*c
= musb
->dma_controller
;
1091 musb_ep
->dma
= c
->channel_alloc(c
, hw_ep
,
1092 (desc
->bEndpointAddress
& USB_DIR_IN
));
1094 musb_ep
->dma
= NULL
;
1096 musb_ep
->desc
= desc
;
1098 musb_ep
->wedged
= 0;
1101 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1102 musb_driver_name
, musb_ep
->end_point
.name
,
1103 ({ char *s
; switch (musb_ep
->type
) {
1104 case USB_ENDPOINT_XFER_BULK
: s
= "bulk"; break;
1105 case USB_ENDPOINT_XFER_INT
: s
= "int"; break;
1106 default: s
= "iso"; break;
1108 musb_ep
->is_in
? "IN" : "OUT",
1109 musb_ep
->dma
? "dma, " : "",
1110 musb_ep
->packet_sz
);
1112 schedule_work(&musb
->irq_work
);
1115 spin_unlock_irqrestore(&musb
->lock
, flags
);
1120 * Disable an endpoint flushing all requests queued.
1122 static int musb_gadget_disable(struct usb_ep
*ep
)
1124 unsigned long flags
;
1127 struct musb_ep
*musb_ep
;
1131 musb_ep
= to_musb_ep(ep
);
1132 musb
= musb_ep
->musb
;
1133 epnum
= musb_ep
->current_epnum
;
1134 epio
= musb
->endpoints
[epnum
].regs
;
1136 spin_lock_irqsave(&musb
->lock
, flags
);
1137 musb_ep_select(musb
->mregs
, epnum
);
1139 /* zero the endpoint sizes */
1140 if (musb_ep
->is_in
) {
1141 u16 int_txe
= musb_readw(musb
->mregs
, MUSB_INTRTXE
);
1142 int_txe
&= ~(1 << epnum
);
1143 musb_writew(musb
->mregs
, MUSB_INTRTXE
, int_txe
);
1144 musb_writew(epio
, MUSB_TXMAXP
, 0);
1146 u16 int_rxe
= musb_readw(musb
->mregs
, MUSB_INTRRXE
);
1147 int_rxe
&= ~(1 << epnum
);
1148 musb_writew(musb
->mregs
, MUSB_INTRRXE
, int_rxe
);
1149 musb_writew(epio
, MUSB_RXMAXP
, 0);
1152 musb_ep
->desc
= NULL
;
1154 /* abort all pending DMA and requests */
1155 nuke(musb_ep
, -ESHUTDOWN
);
1157 schedule_work(&musb
->irq_work
);
1159 spin_unlock_irqrestore(&(musb
->lock
), flags
);
1161 dev_dbg(musb
->controller
, "%s\n", musb_ep
->end_point
.name
);
1167 * Allocate a request for an endpoint.
1168 * Reused by ep0 code.
1170 struct usb_request
*musb_alloc_request(struct usb_ep
*ep
, gfp_t gfp_flags
)
1172 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1173 struct musb
*musb
= musb_ep
->musb
;
1174 struct musb_request
*request
= NULL
;
1176 request
= kzalloc(sizeof *request
, gfp_flags
);
1178 dev_dbg(musb
->controller
, "not enough memory\n");
1182 request
->request
.dma
= DMA_ADDR_INVALID
;
1183 request
->epnum
= musb_ep
->current_epnum
;
1184 request
->ep
= musb_ep
;
1186 return &request
->request
;
1191 * Reused by ep0 code.
1193 void musb_free_request(struct usb_ep
*ep
, struct usb_request
*req
)
1195 kfree(to_musb_request(req
));
1198 static LIST_HEAD(buffers
);
1200 struct free_record
{
1201 struct list_head list
;
1208 * Context: controller locked, IRQs blocked.
1210 void musb_ep_restart(struct musb
*musb
, struct musb_request
*req
)
1212 dev_dbg(musb
->controller
, "<== %s request %p len %u on hw_ep%d\n",
1213 req
->tx
? "TX/IN" : "RX/OUT",
1214 &req
->request
, req
->request
.length
, req
->epnum
);
1216 musb_ep_select(musb
->mregs
, req
->epnum
);
1223 static int musb_gadget_queue(struct usb_ep
*ep
, struct usb_request
*req
,
1226 struct musb_ep
*musb_ep
;
1227 struct musb_request
*request
;
1230 unsigned long lockflags
;
1237 musb_ep
= to_musb_ep(ep
);
1238 musb
= musb_ep
->musb
;
1240 request
= to_musb_request(req
);
1241 request
->musb
= musb
;
1243 if (request
->ep
!= musb_ep
)
1246 dev_dbg(musb
->controller
, "<== to %s request=%p\n", ep
->name
, req
);
1248 /* request is mine now... */
1249 request
->request
.actual
= 0;
1250 request
->request
.status
= -EINPROGRESS
;
1251 request
->epnum
= musb_ep
->current_epnum
;
1252 request
->tx
= musb_ep
->is_in
;
1254 map_dma_buffer(request
, musb
, musb_ep
);
1256 spin_lock_irqsave(&musb
->lock
, lockflags
);
1258 /* don't queue if the ep is down */
1259 if (!musb_ep
->desc
) {
1260 dev_dbg(musb
->controller
, "req %p queued to %s while ep %s\n",
1261 req
, ep
->name
, "disabled");
1262 status
= -ESHUTDOWN
;
1266 /* add request to the list */
1267 list_add_tail(&request
->list
, &musb_ep
->req_list
);
1269 /* it this is the head of the queue, start i/o ... */
1270 if (!musb_ep
->busy
&& &request
->list
== musb_ep
->req_list
.next
)
1271 musb_ep_restart(musb
, request
);
1274 spin_unlock_irqrestore(&musb
->lock
, lockflags
);
1278 static int musb_gadget_dequeue(struct usb_ep
*ep
, struct usb_request
*request
)
1280 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1281 struct musb_request
*req
= to_musb_request(request
);
1282 struct musb_request
*r
;
1283 unsigned long flags
;
1285 struct musb
*musb
= musb_ep
->musb
;
1287 if (!ep
|| !request
|| to_musb_request(request
)->ep
!= musb_ep
)
1290 spin_lock_irqsave(&musb
->lock
, flags
);
1292 list_for_each_entry(r
, &musb_ep
->req_list
, list
) {
1297 dev_dbg(musb
->controller
, "request %p not queued to %s\n", request
, ep
->name
);
1302 /* if the hardware doesn't have the request, easy ... */
1303 if (musb_ep
->req_list
.next
!= &req
->list
|| musb_ep
->busy
)
1304 musb_g_giveback(musb_ep
, request
, -ECONNRESET
);
1306 /* ... else abort the dma transfer ... */
1307 else if (is_dma_capable() && musb_ep
->dma
) {
1308 struct dma_controller
*c
= musb
->dma_controller
;
1310 musb_ep_select(musb
->mregs
, musb_ep
->current_epnum
);
1311 if (c
->channel_abort
)
1312 status
= c
->channel_abort(musb_ep
->dma
);
1316 musb_g_giveback(musb_ep
, request
, -ECONNRESET
);
1318 /* NOTE: by sticking to easily tested hardware/driver states,
1319 * we leave counting of in-flight packets imprecise.
1321 musb_g_giveback(musb_ep
, request
, -ECONNRESET
);
1325 spin_unlock_irqrestore(&musb
->lock
, flags
);
1330 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1331 * data but will queue requests.
1333 * exported to ep0 code
1335 static int musb_gadget_set_halt(struct usb_ep
*ep
, int value
)
1337 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1338 u8 epnum
= musb_ep
->current_epnum
;
1339 struct musb
*musb
= musb_ep
->musb
;
1340 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
1341 void __iomem
*mbase
;
1342 unsigned long flags
;
1344 struct musb_request
*request
;
1349 mbase
= musb
->mregs
;
1351 spin_lock_irqsave(&musb
->lock
, flags
);
1353 if ((USB_ENDPOINT_XFER_ISOC
== musb_ep
->type
)) {
1358 musb_ep_select(mbase
, epnum
);
1360 request
= next_request(musb_ep
);
1363 dev_dbg(musb
->controller
, "request in progress, cannot halt %s\n",
1368 /* Cannot portably stall with non-empty FIFO */
1369 if (musb_ep
->is_in
) {
1370 csr
= musb_readw(epio
, MUSB_TXCSR
);
1371 if (csr
& MUSB_TXCSR_FIFONOTEMPTY
) {
1372 dev_dbg(musb
->controller
, "FIFO busy, cannot halt %s\n", ep
->name
);
1378 musb_ep
->wedged
= 0;
1380 /* set/clear the stall and toggle bits */
1381 dev_dbg(musb
->controller
, "%s: %s stall\n", ep
->name
, value
? "set" : "clear");
1382 if (musb_ep
->is_in
) {
1383 csr
= musb_readw(epio
, MUSB_TXCSR
);
1384 csr
|= MUSB_TXCSR_P_WZC_BITS
1385 | MUSB_TXCSR_CLRDATATOG
;
1387 csr
|= MUSB_TXCSR_P_SENDSTALL
;
1389 csr
&= ~(MUSB_TXCSR_P_SENDSTALL
1390 | MUSB_TXCSR_P_SENTSTALL
);
1391 csr
&= ~MUSB_TXCSR_TXPKTRDY
;
1392 musb_writew(epio
, MUSB_TXCSR
, csr
);
1394 csr
= musb_readw(epio
, MUSB_RXCSR
);
1395 csr
|= MUSB_RXCSR_P_WZC_BITS
1396 | MUSB_RXCSR_FLUSHFIFO
1397 | MUSB_RXCSR_CLRDATATOG
;
1399 csr
|= MUSB_RXCSR_P_SENDSTALL
;
1401 csr
&= ~(MUSB_RXCSR_P_SENDSTALL
1402 | MUSB_RXCSR_P_SENTSTALL
);
1403 musb_writew(epio
, MUSB_RXCSR
, csr
);
1406 /* maybe start the first request in the queue */
1407 if (!musb_ep
->busy
&& !value
&& request
) {
1408 dev_dbg(musb
->controller
, "restarting the request\n");
1409 musb_ep_restart(musb
, request
);
1413 spin_unlock_irqrestore(&musb
->lock
, flags
);
1418 * Sets the halt feature with the clear requests ignored
1420 static int musb_gadget_set_wedge(struct usb_ep
*ep
)
1422 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1427 musb_ep
->wedged
= 1;
1429 return usb_ep_set_halt(ep
);
1432 static int musb_gadget_fifo_status(struct usb_ep
*ep
)
1434 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1435 void __iomem
*epio
= musb_ep
->hw_ep
->regs
;
1436 int retval
= -EINVAL
;
1438 if (musb_ep
->desc
&& !musb_ep
->is_in
) {
1439 struct musb
*musb
= musb_ep
->musb
;
1440 int epnum
= musb_ep
->current_epnum
;
1441 void __iomem
*mbase
= musb
->mregs
;
1442 unsigned long flags
;
1444 spin_lock_irqsave(&musb
->lock
, flags
);
1446 musb_ep_select(mbase
, epnum
);
1447 /* FIXME return zero unless RXPKTRDY is set */
1448 retval
= musb_readw(epio
, MUSB_RXCOUNT
);
1450 spin_unlock_irqrestore(&musb
->lock
, flags
);
1455 static void musb_gadget_fifo_flush(struct usb_ep
*ep
)
1457 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1458 struct musb
*musb
= musb_ep
->musb
;
1459 u8 epnum
= musb_ep
->current_epnum
;
1460 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
1461 void __iomem
*mbase
;
1462 unsigned long flags
;
1465 mbase
= musb
->mregs
;
1467 spin_lock_irqsave(&musb
->lock
, flags
);
1468 musb_ep_select(mbase
, (u8
) epnum
);
1470 /* disable interrupts */
1471 int_txe
= musb_readw(mbase
, MUSB_INTRTXE
);
1472 musb_writew(mbase
, MUSB_INTRTXE
, int_txe
& ~(1 << epnum
));
1474 if (musb_ep
->is_in
) {
1475 csr
= musb_readw(epio
, MUSB_TXCSR
);
1476 if (csr
& MUSB_TXCSR_FIFONOTEMPTY
) {
1477 csr
|= MUSB_TXCSR_FLUSHFIFO
| MUSB_TXCSR_P_WZC_BITS
;
1478 musb_writew(epio
, MUSB_TXCSR
, csr
);
1479 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1480 musb_writew(epio
, MUSB_TXCSR
, csr
);
1483 csr
= musb_readw(epio
, MUSB_RXCSR
);
1484 csr
|= MUSB_RXCSR_FLUSHFIFO
| MUSB_RXCSR_P_WZC_BITS
;
1485 musb_writew(epio
, MUSB_RXCSR
, csr
);
1486 musb_writew(epio
, MUSB_RXCSR
, csr
);
1489 /* re-enable interrupt */
1490 musb_writew(mbase
, MUSB_INTRTXE
, int_txe
);
1491 spin_unlock_irqrestore(&musb
->lock
, flags
);
1494 static const struct usb_ep_ops musb_ep_ops
= {
1495 .enable
= musb_gadget_enable
,
1496 .disable
= musb_gadget_disable
,
1497 .alloc_request
= musb_alloc_request
,
1498 .free_request
= musb_free_request
,
1499 .queue
= musb_gadget_queue
,
1500 .dequeue
= musb_gadget_dequeue
,
1501 .set_halt
= musb_gadget_set_halt
,
1502 .set_wedge
= musb_gadget_set_wedge
,
1503 .fifo_status
= musb_gadget_fifo_status
,
1504 .fifo_flush
= musb_gadget_fifo_flush
1507 /* ----------------------------------------------------------------------- */
1509 static int musb_gadget_get_frame(struct usb_gadget
*gadget
)
1511 struct musb
*musb
= gadget_to_musb(gadget
);
1513 return (int)musb_readw(musb
->mregs
, MUSB_FRAME
);
1516 static int musb_gadget_wakeup(struct usb_gadget
*gadget
)
1518 struct musb
*musb
= gadget_to_musb(gadget
);
1519 void __iomem
*mregs
= musb
->mregs
;
1520 unsigned long flags
;
1521 int status
= -EINVAL
;
1525 spin_lock_irqsave(&musb
->lock
, flags
);
1527 switch (musb
->xceiv
->state
) {
1528 case OTG_STATE_B_PERIPHERAL
:
1529 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1530 * that's part of the standard usb 1.1 state machine, and
1531 * doesn't affect OTG transitions.
1533 if (musb
->may_wakeup
&& musb
->is_suspended
)
1536 case OTG_STATE_B_IDLE
:
1537 /* Start SRP ... OTG not required. */
1538 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1539 dev_dbg(musb
->controller
, "Sending SRP: devctl: %02x\n", devctl
);
1540 devctl
|= MUSB_DEVCTL_SESSION
;
1541 musb_writeb(mregs
, MUSB_DEVCTL
, devctl
);
1542 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1544 while (!(devctl
& MUSB_DEVCTL_SESSION
)) {
1545 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1550 while (devctl
& MUSB_DEVCTL_SESSION
) {
1551 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1556 /* Block idling for at least 1s */
1557 musb_platform_try_idle(musb
,
1558 jiffies
+ msecs_to_jiffies(1 * HZ
));
1563 dev_dbg(musb
->controller
, "Unhandled wake: %s\n",
1564 otg_state_string(musb
->xceiv
->state
));
1570 power
= musb_readb(mregs
, MUSB_POWER
);
1571 power
|= MUSB_POWER_RESUME
;
1572 musb_writeb(mregs
, MUSB_POWER
, power
);
1573 dev_dbg(musb
->controller
, "issue wakeup\n");
1575 /* FIXME do this next chunk in a timer callback, no udelay */
1578 power
= musb_readb(mregs
, MUSB_POWER
);
1579 power
&= ~MUSB_POWER_RESUME
;
1580 musb_writeb(mregs
, MUSB_POWER
, power
);
1582 spin_unlock_irqrestore(&musb
->lock
, flags
);
1587 musb_gadget_set_self_powered(struct usb_gadget
*gadget
, int is_selfpowered
)
1589 struct musb
*musb
= gadget_to_musb(gadget
);
1591 musb
->is_self_powered
= !!is_selfpowered
;
1595 static void musb_pullup(struct musb
*musb
, int is_on
)
1599 power
= musb_readb(musb
->mregs
, MUSB_POWER
);
1601 power
|= MUSB_POWER_SOFTCONN
;
1603 power
&= ~MUSB_POWER_SOFTCONN
;
1605 /* FIXME if on, HdrcStart; if off, HdrcStop */
1607 dev_dbg(musb
->controller
, "gadget %s D+ pullup %s\n",
1608 musb
->gadget_driver
->function
, is_on
? "on" : "off");
1609 musb_writeb(musb
->mregs
, MUSB_POWER
, power
);
1613 static int musb_gadget_vbus_session(struct usb_gadget
*gadget
, int is_active
)
1615 dev_dbg(musb
->controller
, "<= %s =>\n", __func__
);
1618 * FIXME iff driver's softconnect flag is set (as it is during probe,
1619 * though that can clear it), just musb_pullup().
1626 static int musb_gadget_vbus_draw(struct usb_gadget
*gadget
, unsigned mA
)
1628 struct musb
*musb
= gadget_to_musb(gadget
);
1630 if (!musb
->xceiv
->set_power
)
1632 return otg_set_power(musb
->xceiv
, mA
);
1635 static int musb_gadget_pullup(struct usb_gadget
*gadget
, int is_on
)
1637 struct musb
*musb
= gadget_to_musb(gadget
);
1638 unsigned long flags
;
1642 /* NOTE: this assumes we are sensing vbus; we'd rather
1643 * not pullup unless the B-session is active.
1645 spin_lock_irqsave(&musb
->lock
, flags
);
1646 if (is_on
!= musb
->softconnect
) {
1647 musb
->softconnect
= is_on
;
1648 musb_pullup(musb
, is_on
);
1650 spin_unlock_irqrestore(&musb
->lock
, flags
);
1654 static const struct usb_gadget_ops musb_gadget_operations
= {
1655 .get_frame
= musb_gadget_get_frame
,
1656 .wakeup
= musb_gadget_wakeup
,
1657 .set_selfpowered
= musb_gadget_set_self_powered
,
1658 /* .vbus_session = musb_gadget_vbus_session, */
1659 .vbus_draw
= musb_gadget_vbus_draw
,
1660 .pullup
= musb_gadget_pullup
,
1663 /* ----------------------------------------------------------------------- */
1667 /* Only this registration code "knows" the rule (from USB standards)
1668 * about there being only one external upstream port. It assumes
1669 * all peripheral ports are external...
1671 static struct musb
*the_gadget
;
1673 static void musb_gadget_release(struct device
*dev
)
1675 /* kref_put(WHAT) */
1676 dev_dbg(dev
, "%s\n", __func__
);
1681 init_peripheral_ep(struct musb
*musb
, struct musb_ep
*ep
, u8 epnum
, int is_in
)
1683 struct musb_hw_ep
*hw_ep
= musb
->endpoints
+ epnum
;
1685 memset(ep
, 0, sizeof *ep
);
1687 ep
->current_epnum
= epnum
;
1692 INIT_LIST_HEAD(&ep
->req_list
);
1694 sprintf(ep
->name
, "ep%d%s", epnum
,
1695 (!epnum
|| hw_ep
->is_shared_fifo
) ? "" : (
1696 is_in
? "in" : "out"));
1697 ep
->end_point
.name
= ep
->name
;
1698 INIT_LIST_HEAD(&ep
->end_point
.ep_list
);
1700 ep
->end_point
.maxpacket
= 64;
1701 ep
->end_point
.ops
= &musb_g_ep0_ops
;
1702 musb
->g
.ep0
= &ep
->end_point
;
1705 ep
->end_point
.maxpacket
= hw_ep
->max_packet_sz_tx
;
1707 ep
->end_point
.maxpacket
= hw_ep
->max_packet_sz_rx
;
1708 ep
->end_point
.ops
= &musb_ep_ops
;
1709 list_add_tail(&ep
->end_point
.ep_list
, &musb
->g
.ep_list
);
1714 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1715 * to the rest of the driver state.
1717 static inline void __init
musb_g_init_endpoints(struct musb
*musb
)
1720 struct musb_hw_ep
*hw_ep
;
1723 /* initialize endpoint list just once */
1724 INIT_LIST_HEAD(&(musb
->g
.ep_list
));
1726 for (epnum
= 0, hw_ep
= musb
->endpoints
;
1727 epnum
< musb
->nr_endpoints
;
1729 if (hw_ep
->is_shared_fifo
/* || !epnum */) {
1730 init_peripheral_ep(musb
, &hw_ep
->ep_in
, epnum
, 0);
1733 if (hw_ep
->max_packet_sz_tx
) {
1734 init_peripheral_ep(musb
, &hw_ep
->ep_in
,
1738 if (hw_ep
->max_packet_sz_rx
) {
1739 init_peripheral_ep(musb
, &hw_ep
->ep_out
,
1747 /* called once during driver setup to initialize and link into
1748 * the driver model; memory is zeroed.
1750 int __init
musb_gadget_setup(struct musb
*musb
)
1754 /* REVISIT minor race: if (erroneously) setting up two
1755 * musb peripherals at the same time, only the bus lock
1762 musb
->g
.ops
= &musb_gadget_operations
;
1763 musb
->g
.is_dualspeed
= 1;
1764 musb
->g
.speed
= USB_SPEED_UNKNOWN
;
1766 /* this "gadget" abstracts/virtualizes the controller */
1767 dev_set_name(&musb
->g
.dev
, "gadget");
1768 musb
->g
.dev
.parent
= musb
->controller
;
1769 musb
->g
.dev
.dma_mask
= musb
->controller
->dma_mask
;
1770 musb
->g
.dev
.release
= musb_gadget_release
;
1771 musb
->g
.name
= musb_driver_name
;
1773 if (is_otg_enabled(musb
))
1776 musb_g_init_endpoints(musb
);
1778 musb
->is_active
= 0;
1779 musb_platform_try_idle(musb
, 0);
1781 status
= device_register(&musb
->g
.dev
);
1783 put_device(&musb
->g
.dev
);
1789 void musb_gadget_cleanup(struct musb
*musb
)
1791 if (musb
!= the_gadget
)
1794 device_unregister(&musb
->g
.dev
);
1799 * Register the gadget driver. Used by gadget drivers when
1800 * registering themselves with the controller.
1802 * -EINVAL something went wrong (not driver)
1803 * -EBUSY another gadget is already using the controller
1804 * -ENOMEM no memory to perform the operation
1806 * @param driver the gadget driver
1807 * @param bind the driver's bind function
1808 * @return <0 if error, 0 if everything is fine
1810 int usb_gadget_probe_driver(struct usb_gadget_driver
*driver
,
1811 int (*bind
)(struct usb_gadget
*))
1813 struct musb
*musb
= the_gadget
;
1814 unsigned long flags
;
1815 int retval
= -EINVAL
;
1818 || driver
->speed
!= USB_SPEED_HIGH
1819 || !bind
|| !driver
->setup
)
1822 /* driver must be initialized to support peripheral mode */
1824 dev_dbg(musb
->controller
, "no dev??\n");
1829 pm_runtime_get_sync(musb
->controller
);
1831 dev_dbg(musb
->controller
, "registering driver %s\n", driver
->function
);
1833 if (musb
->gadget_driver
) {
1834 dev_dbg(musb
->controller
, "%s is already bound to %s\n",
1836 musb
->gadget_driver
->driver
.name
);
1841 spin_lock_irqsave(&musb
->lock
, flags
);
1842 musb
->gadget_driver
= driver
;
1843 musb
->g
.dev
.driver
= &driver
->driver
;
1844 driver
->driver
.bus
= NULL
;
1845 musb
->softconnect
= 1;
1846 spin_unlock_irqrestore(&musb
->lock
, flags
);
1848 retval
= bind(&musb
->g
);
1850 dev_dbg(musb
->controller
, "bind to driver %s failed --> %d\n",
1851 driver
->driver
.name
, retval
);
1855 spin_lock_irqsave(&musb
->lock
, flags
);
1857 otg_set_peripheral(musb
->xceiv
, &musb
->g
);
1858 musb
->xceiv
->state
= OTG_STATE_B_IDLE
;
1859 musb
->is_active
= 1;
1862 * FIXME this ignores the softconnect flag. Drivers are
1863 * allowed hold the peripheral inactive until for example
1864 * userspace hooks up printer hardware or DSP codecs, so
1865 * hosts only see fully functional devices.
1868 if (!is_otg_enabled(musb
))
1871 otg_set_peripheral(musb
->xceiv
, &musb
->g
);
1873 spin_unlock_irqrestore(&musb
->lock
, flags
);
1875 if (is_otg_enabled(musb
)) {
1876 struct usb_hcd
*hcd
= musb_to_hcd(musb
);
1878 dev_dbg(musb
->controller
, "OTG startup...\n");
1880 /* REVISIT: funcall to other code, which also
1881 * handles power budgeting ... this way also
1882 * ensures HdrcStart is indirectly called.
1884 retval
= usb_add_hcd(musb_to_hcd(musb
), -1, 0);
1886 dev_dbg(musb
->controller
, "add_hcd failed, %d\n", retval
);
1890 if ((musb
->xceiv
->last_event
== USB_EVENT_ID
)
1891 && musb
->xceiv
->set_vbus
)
1892 otg_set_vbus(musb
->xceiv
, 1);
1894 hcd
->self
.uses_pio_for_control
= 1;
1896 if (musb
->xceiv
->last_event
== USB_EVENT_NONE
)
1897 pm_runtime_put(musb
->controller
);
1902 if (!is_otg_enabled(musb
))
1906 musb
->gadget_driver
= NULL
;
1907 musb
->g
.dev
.driver
= NULL
;
1912 EXPORT_SYMBOL(usb_gadget_probe_driver
);
1914 static void stop_activity(struct musb
*musb
, struct usb_gadget_driver
*driver
)
1917 struct musb_hw_ep
*hw_ep
;
1919 /* don't disconnect if it's not connected */
1920 if (musb
->g
.speed
== USB_SPEED_UNKNOWN
)
1923 musb
->g
.speed
= USB_SPEED_UNKNOWN
;
1925 /* deactivate the hardware */
1926 if (musb
->softconnect
) {
1927 musb
->softconnect
= 0;
1928 musb_pullup(musb
, 0);
1932 /* killing any outstanding requests will quiesce the driver;
1933 * then report disconnect
1936 for (i
= 0, hw_ep
= musb
->endpoints
;
1937 i
< musb
->nr_endpoints
;
1939 musb_ep_select(musb
->mregs
, i
);
1940 if (hw_ep
->is_shared_fifo
/* || !epnum */) {
1941 nuke(&hw_ep
->ep_in
, -ESHUTDOWN
);
1943 if (hw_ep
->max_packet_sz_tx
)
1944 nuke(&hw_ep
->ep_in
, -ESHUTDOWN
);
1945 if (hw_ep
->max_packet_sz_rx
)
1946 nuke(&hw_ep
->ep_out
, -ESHUTDOWN
);
1950 spin_unlock(&musb
->lock
);
1951 driver
->disconnect(&musb
->g
);
1952 spin_lock(&musb
->lock
);
1957 * Unregister the gadget driver. Used by gadget drivers when
1958 * unregistering themselves from the controller.
1960 * @param driver the gadget driver to unregister
1962 int usb_gadget_unregister_driver(struct usb_gadget_driver
*driver
)
1964 struct musb
*musb
= the_gadget
;
1965 unsigned long flags
;
1967 if (!driver
|| !driver
->unbind
|| !musb
)
1970 if (!musb
->gadget_driver
)
1973 if (musb
->xceiv
->last_event
== USB_EVENT_NONE
)
1974 pm_runtime_get_sync(musb
->controller
);
1977 * REVISIT always use otg_set_peripheral() here too;
1978 * this needs to shut down the OTG engine.
1981 spin_lock_irqsave(&musb
->lock
, flags
);
1983 #ifdef CONFIG_USB_MUSB_OTG
1984 musb_hnp_stop(musb
);
1987 (void) musb_gadget_vbus_draw(&musb
->g
, 0);
1989 musb
->xceiv
->state
= OTG_STATE_UNDEFINED
;
1990 stop_activity(musb
, driver
);
1991 otg_set_peripheral(musb
->xceiv
, NULL
);
1993 dev_dbg(musb
->controller
, "unregistering driver %s\n", driver
->function
);
1995 spin_unlock_irqrestore(&musb
->lock
, flags
);
1996 driver
->unbind(&musb
->g
);
1997 spin_lock_irqsave(&musb
->lock
, flags
);
1999 musb
->gadget_driver
= NULL
;
2000 musb
->g
.dev
.driver
= NULL
;
2002 musb
->is_active
= 0;
2003 musb_platform_try_idle(musb
, 0);
2004 spin_unlock_irqrestore(&musb
->lock
, flags
);
2006 if (is_otg_enabled(musb
)) {
2007 usb_remove_hcd(musb_to_hcd(musb
));
2008 /* FIXME we need to be able to register another
2009 * gadget driver here and have everything work;
2010 * that currently misbehaves.
2014 if (!is_otg_enabled(musb
))
2017 pm_runtime_put(musb
->controller
);
2021 EXPORT_SYMBOL(usb_gadget_unregister_driver
);
2024 /* ----------------------------------------------------------------------- */
2026 /* lifecycle operations called through plat_uds.c */
2028 void musb_g_resume(struct musb
*musb
)
2030 musb
->is_suspended
= 0;
2031 switch (musb
->xceiv
->state
) {
2032 case OTG_STATE_B_IDLE
:
2034 case OTG_STATE_B_WAIT_ACON
:
2035 case OTG_STATE_B_PERIPHERAL
:
2036 musb
->is_active
= 1;
2037 if (musb
->gadget_driver
&& musb
->gadget_driver
->resume
) {
2038 spin_unlock(&musb
->lock
);
2039 musb
->gadget_driver
->resume(&musb
->g
);
2040 spin_lock(&musb
->lock
);
2044 WARNING("unhandled RESUME transition (%s)\n",
2045 otg_state_string(musb
->xceiv
->state
));
2049 /* called when SOF packets stop for 3+ msec */
2050 void musb_g_suspend(struct musb
*musb
)
2054 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
2055 dev_dbg(musb
->controller
, "devctl %02x\n", devctl
);
2057 switch (musb
->xceiv
->state
) {
2058 case OTG_STATE_B_IDLE
:
2059 if ((devctl
& MUSB_DEVCTL_VBUS
) == MUSB_DEVCTL_VBUS
)
2060 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
2062 case OTG_STATE_B_PERIPHERAL
:
2063 musb
->is_suspended
= 1;
2064 if (musb
->gadget_driver
&& musb
->gadget_driver
->suspend
) {
2065 spin_unlock(&musb
->lock
);
2066 musb
->gadget_driver
->suspend(&musb
->g
);
2067 spin_lock(&musb
->lock
);
2071 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
2072 * A_PERIPHERAL may need care too
2074 WARNING("unhandled SUSPEND transition (%s)\n",
2075 otg_state_string(musb
->xceiv
->state
));
2079 /* Called during SRP */
2080 void musb_g_wakeup(struct musb
*musb
)
2082 musb_gadget_wakeup(&musb
->g
);
2085 /* called when VBUS drops below session threshold, and in other cases */
2086 void musb_g_disconnect(struct musb
*musb
)
2088 void __iomem
*mregs
= musb
->mregs
;
2089 u8 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
2091 dev_dbg(musb
->controller
, "devctl %02x\n", devctl
);
2094 musb_writeb(mregs
, MUSB_DEVCTL
, devctl
& MUSB_DEVCTL_SESSION
);
2096 /* don't draw vbus until new b-default session */
2097 (void) musb_gadget_vbus_draw(&musb
->g
, 0);
2099 musb
->g
.speed
= USB_SPEED_UNKNOWN
;
2100 if (musb
->gadget_driver
&& musb
->gadget_driver
->disconnect
) {
2101 spin_unlock(&musb
->lock
);
2102 musb
->gadget_driver
->disconnect(&musb
->g
);
2103 spin_lock(&musb
->lock
);
2106 switch (musb
->xceiv
->state
) {
2108 #ifdef CONFIG_USB_MUSB_OTG
2109 dev_dbg(musb
->controller
, "Unhandled disconnect %s, setting a_idle\n",
2110 otg_state_string(musb
->xceiv
->state
));
2111 musb
->xceiv
->state
= OTG_STATE_A_IDLE
;
2112 MUSB_HST_MODE(musb
);
2114 case OTG_STATE_A_PERIPHERAL
:
2115 musb
->xceiv
->state
= OTG_STATE_A_WAIT_BCON
;
2116 MUSB_HST_MODE(musb
);
2118 case OTG_STATE_B_WAIT_ACON
:
2119 case OTG_STATE_B_HOST
:
2121 case OTG_STATE_B_PERIPHERAL
:
2122 case OTG_STATE_B_IDLE
:
2123 musb
->xceiv
->state
= OTG_STATE_B_IDLE
;
2125 case OTG_STATE_B_SRP_INIT
:
2129 musb
->is_active
= 0;
2132 void musb_g_reset(struct musb
*musb
)
2133 __releases(musb
->lock
)
2134 __acquires(musb
->lock
)
2136 void __iomem
*mbase
= musb
->mregs
;
2137 u8 devctl
= musb_readb(mbase
, MUSB_DEVCTL
);
2140 dev_dbg(musb
->controller
, "<== %s addr=%x driver '%s'\n",
2141 (devctl
& MUSB_DEVCTL_BDEVICE
)
2142 ? "B-Device" : "A-Device",
2143 musb_readb(mbase
, MUSB_FADDR
),
2145 ? musb
->gadget_driver
->driver
.name
2149 /* report disconnect, if we didn't already (flushing EP state) */
2150 if (musb
->g
.speed
!= USB_SPEED_UNKNOWN
)
2151 musb_g_disconnect(musb
);
2154 else if (devctl
& MUSB_DEVCTL_HR
)
2155 musb_writeb(mbase
, MUSB_DEVCTL
, MUSB_DEVCTL_SESSION
);
2158 /* what speed did we negotiate? */
2159 power
= musb_readb(mbase
, MUSB_POWER
);
2160 musb
->g
.speed
= (power
& MUSB_POWER_HSMODE
)
2161 ? USB_SPEED_HIGH
: USB_SPEED_FULL
;
2163 /* start in USB_STATE_DEFAULT */
2164 musb
->is_active
= 1;
2165 musb
->is_suspended
= 0;
2166 MUSB_DEV_MODE(musb
);
2168 musb
->ep0_state
= MUSB_EP0_STAGE_SETUP
;
2170 musb
->may_wakeup
= 0;
2171 musb
->g
.b_hnp_enable
= 0;
2172 musb
->g
.a_alt_hnp_support
= 0;
2173 musb
->g
.a_hnp_support
= 0;
2175 /* Normal reset, as B-Device;
2176 * or else after HNP, as A-Device
2178 if (devctl
& MUSB_DEVCTL_BDEVICE
) {
2179 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
2180 musb
->g
.is_a_peripheral
= 0;
2181 } else if (is_otg_enabled(musb
)) {
2182 musb
->xceiv
->state
= OTG_STATE_A_PERIPHERAL
;
2183 musb
->g
.is_a_peripheral
= 1;
2187 /* start with default limits on VBUS power draw */
2188 (void) musb_gadget_vbus_draw(&musb
->g
,
2189 is_otg_enabled(musb
) ? 8 : 100);