2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/pci.h>
35 #include <linux/eeprom_93cx6.h>
38 #include "rt2x00pci.h"
42 * Allow hardware encryption to be disabled.
44 static int modparam_nohwcrypt
= 0;
45 module_param_named(nohwcrypt
, modparam_nohwcrypt
, bool, S_IRUGO
);
46 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attempt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
59 #define WAIT_FOR_BBP(__dev, __reg) \
60 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
61 #define WAIT_FOR_RF(__dev, __reg) \
62 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
63 #define WAIT_FOR_MCU(__dev, __reg) \
64 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
65 H2M_MAILBOX_CSR_OWNER, (__reg))
67 static void rt61pci_bbp_write(struct rt2x00_dev
*rt2x00dev
,
68 const unsigned int word
, const u8 value
)
72 mutex_lock(&rt2x00dev
->csr_mutex
);
75 * Wait until the BBP becomes available, afterwards we
76 * can safely write the new data into the register.
78 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
80 rt2x00_set_field32(®
, PHY_CSR3_VALUE
, value
);
81 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
82 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
83 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 0);
85 rt2x00pci_register_write(rt2x00dev
, PHY_CSR3
, reg
);
88 mutex_unlock(&rt2x00dev
->csr_mutex
);
91 static void rt61pci_bbp_read(struct rt2x00_dev
*rt2x00dev
,
92 const unsigned int word
, u8
*value
)
96 mutex_lock(&rt2x00dev
->csr_mutex
);
99 * Wait until the BBP becomes available, afterwards we
100 * can safely write the read request into the register.
101 * After the data has been written, we wait until hardware
102 * returns the correct value, if at any time the register
103 * doesn't become available in time, reg will be 0xffffffff
104 * which means we return 0xff to the caller.
106 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
108 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
109 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
110 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 1);
112 rt2x00pci_register_write(rt2x00dev
, PHY_CSR3
, reg
);
114 WAIT_FOR_BBP(rt2x00dev
, ®
);
117 *value
= rt2x00_get_field32(reg
, PHY_CSR3_VALUE
);
119 mutex_unlock(&rt2x00dev
->csr_mutex
);
122 static void rt61pci_rf_write(struct rt2x00_dev
*rt2x00dev
,
123 const unsigned int word
, const u32 value
)
127 mutex_lock(&rt2x00dev
->csr_mutex
);
130 * Wait until the RF becomes available, afterwards we
131 * can safely write the new data into the register.
133 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
135 rt2x00_set_field32(®
, PHY_CSR4_VALUE
, value
);
136 rt2x00_set_field32(®
, PHY_CSR4_NUMBER_OF_BITS
, 21);
137 rt2x00_set_field32(®
, PHY_CSR4_IF_SELECT
, 0);
138 rt2x00_set_field32(®
, PHY_CSR4_BUSY
, 1);
140 rt2x00pci_register_write(rt2x00dev
, PHY_CSR4
, reg
);
141 rt2x00_rf_write(rt2x00dev
, word
, value
);
144 mutex_unlock(&rt2x00dev
->csr_mutex
);
147 static void rt61pci_mcu_request(struct rt2x00_dev
*rt2x00dev
,
148 const u8 command
, const u8 token
,
149 const u8 arg0
, const u8 arg1
)
153 mutex_lock(&rt2x00dev
->csr_mutex
);
156 * Wait until the MCU becomes available, afterwards we
157 * can safely write the new data into the register.
159 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
160 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
161 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
162 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
163 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
164 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
166 rt2x00pci_register_read(rt2x00dev
, HOST_CMD_CSR
, ®
);
167 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
168 rt2x00_set_field32(®
, HOST_CMD_CSR_INTERRUPT_MCU
, 1);
169 rt2x00pci_register_write(rt2x00dev
, HOST_CMD_CSR
, reg
);
172 mutex_unlock(&rt2x00dev
->csr_mutex
);
176 static void rt61pci_eepromregister_read(struct eeprom_93cx6
*eeprom
)
178 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
181 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
183 eeprom
->reg_data_in
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_IN
);
184 eeprom
->reg_data_out
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_OUT
);
185 eeprom
->reg_data_clock
=
186 !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_CLOCK
);
187 eeprom
->reg_chip_select
=
188 !!rt2x00_get_field32(reg
, E2PROM_CSR_CHIP_SELECT
);
191 static void rt61pci_eepromregister_write(struct eeprom_93cx6
*eeprom
)
193 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
196 rt2x00_set_field32(®
, E2PROM_CSR_DATA_IN
, !!eeprom
->reg_data_in
);
197 rt2x00_set_field32(®
, E2PROM_CSR_DATA_OUT
, !!eeprom
->reg_data_out
);
198 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
,
199 !!eeprom
->reg_data_clock
);
200 rt2x00_set_field32(®
, E2PROM_CSR_CHIP_SELECT
,
201 !!eeprom
->reg_chip_select
);
203 rt2x00pci_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
206 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
207 static const struct rt2x00debug rt61pci_rt2x00debug
= {
208 .owner
= THIS_MODULE
,
210 .read
= rt2x00pci_register_read
,
211 .write
= rt2x00pci_register_write
,
212 .flags
= RT2X00DEBUGFS_OFFSET
,
213 .word_base
= CSR_REG_BASE
,
214 .word_size
= sizeof(u32
),
215 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
218 .read
= rt2x00_eeprom_read
,
219 .write
= rt2x00_eeprom_write
,
220 .word_base
= EEPROM_BASE
,
221 .word_size
= sizeof(u16
),
222 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
225 .read
= rt61pci_bbp_read
,
226 .write
= rt61pci_bbp_write
,
227 .word_base
= BBP_BASE
,
228 .word_size
= sizeof(u8
),
229 .word_count
= BBP_SIZE
/ sizeof(u8
),
232 .read
= rt2x00_rf_read
,
233 .write
= rt61pci_rf_write
,
234 .word_base
= RF_BASE
,
235 .word_size
= sizeof(u32
),
236 .word_count
= RF_SIZE
/ sizeof(u32
),
239 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
241 static int rt61pci_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
245 rt2x00pci_register_read(rt2x00dev
, MAC_CSR13
, ®
);
246 return rt2x00_get_field32(reg
, MAC_CSR13_BIT5
);
249 #ifdef CONFIG_RT2X00_LIB_LEDS
250 static void rt61pci_brightness_set(struct led_classdev
*led_cdev
,
251 enum led_brightness brightness
)
253 struct rt2x00_led
*led
=
254 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
255 unsigned int enabled
= brightness
!= LED_OFF
;
256 unsigned int a_mode
=
257 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
258 unsigned int bg_mode
=
259 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
261 if (led
->type
== LED_TYPE_RADIO
) {
262 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
263 MCU_LEDCS_RADIO_STATUS
, enabled
);
265 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff,
266 (led
->rt2x00dev
->led_mcu_reg
& 0xff),
267 ((led
->rt2x00dev
->led_mcu_reg
>> 8)));
268 } else if (led
->type
== LED_TYPE_ASSOC
) {
269 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
270 MCU_LEDCS_LINK_BG_STATUS
, bg_mode
);
271 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
272 MCU_LEDCS_LINK_A_STATUS
, a_mode
);
274 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff,
275 (led
->rt2x00dev
->led_mcu_reg
& 0xff),
276 ((led
->rt2x00dev
->led_mcu_reg
>> 8)));
277 } else if (led
->type
== LED_TYPE_QUALITY
) {
279 * The brightness is divided into 6 levels (0 - 5),
280 * this means we need to convert the brightness
281 * argument into the matching level within that range.
283 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
284 brightness
/ (LED_FULL
/ 6), 0);
288 static int rt61pci_blink_set(struct led_classdev
*led_cdev
,
289 unsigned long *delay_on
,
290 unsigned long *delay_off
)
292 struct rt2x00_led
*led
=
293 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
296 rt2x00pci_register_read(led
->rt2x00dev
, MAC_CSR14
, ®
);
297 rt2x00_set_field32(®
, MAC_CSR14_ON_PERIOD
, *delay_on
);
298 rt2x00_set_field32(®
, MAC_CSR14_OFF_PERIOD
, *delay_off
);
299 rt2x00pci_register_write(led
->rt2x00dev
, MAC_CSR14
, reg
);
304 static void rt61pci_init_led(struct rt2x00_dev
*rt2x00dev
,
305 struct rt2x00_led
*led
,
308 led
->rt2x00dev
= rt2x00dev
;
310 led
->led_dev
.brightness_set
= rt61pci_brightness_set
;
311 led
->led_dev
.blink_set
= rt61pci_blink_set
;
312 led
->flags
= LED_INITIALIZED
;
314 #endif /* CONFIG_RT2X00_LIB_LEDS */
317 * Configuration handlers.
319 static int rt61pci_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
320 struct rt2x00lib_crypto
*crypto
,
321 struct ieee80211_key_conf
*key
)
323 struct hw_key_entry key_entry
;
324 struct rt2x00_field32 field
;
328 if (crypto
->cmd
== SET_KEY
) {
330 * rt2x00lib can't determine the correct free
331 * key_idx for shared keys. We have 1 register
332 * with key valid bits. The goal is simple, read
333 * the register, if that is full we have no slots
335 * Note that each BSS is allowed to have up to 4
336 * shared keys, so put a mask over the allowed
339 mask
= (0xf << crypto
->bssidx
);
341 rt2x00pci_register_read(rt2x00dev
, SEC_CSR0
, ®
);
344 if (reg
&& reg
== mask
)
347 key
->hw_key_idx
+= reg
? ffz(reg
) : 0;
350 * Upload key to hardware
352 memcpy(key_entry
.key
, crypto
->key
,
353 sizeof(key_entry
.key
));
354 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
355 sizeof(key_entry
.tx_mic
));
356 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
357 sizeof(key_entry
.rx_mic
));
359 reg
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
360 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
361 &key_entry
, sizeof(key_entry
));
364 * The cipher types are stored over 2 registers.
365 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
366 * bssidx 1 and 2 keys are stored in SEC_CSR5.
367 * Using the correct defines correctly will cause overhead,
368 * so just calculate the correct offset.
370 if (key
->hw_key_idx
< 8) {
371 field
.bit_offset
= (3 * key
->hw_key_idx
);
372 field
.bit_mask
= 0x7 << field
.bit_offset
;
374 rt2x00pci_register_read(rt2x00dev
, SEC_CSR1
, ®
);
375 rt2x00_set_field32(®
, field
, crypto
->cipher
);
376 rt2x00pci_register_write(rt2x00dev
, SEC_CSR1
, reg
);
378 field
.bit_offset
= (3 * (key
->hw_key_idx
- 8));
379 field
.bit_mask
= 0x7 << field
.bit_offset
;
381 rt2x00pci_register_read(rt2x00dev
, SEC_CSR5
, ®
);
382 rt2x00_set_field32(®
, field
, crypto
->cipher
);
383 rt2x00pci_register_write(rt2x00dev
, SEC_CSR5
, reg
);
387 * The driver does not support the IV/EIV generation
388 * in hardware. However it doesn't support the IV/EIV
389 * inside the ieee80211 frame either, but requires it
390 * to be provided separately for the descriptor.
391 * rt2x00lib will cut the IV/EIV data out of all frames
392 * given to us by mac80211, but we must tell mac80211
393 * to generate the IV/EIV data.
395 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
399 * SEC_CSR0 contains only single-bit fields to indicate
400 * a particular key is valid. Because using the FIELD32()
401 * defines directly will cause a lot of overhead, we use
402 * a calculation to determine the correct bit directly.
404 mask
= 1 << key
->hw_key_idx
;
406 rt2x00pci_register_read(rt2x00dev
, SEC_CSR0
, ®
);
407 if (crypto
->cmd
== SET_KEY
)
409 else if (crypto
->cmd
== DISABLE_KEY
)
411 rt2x00pci_register_write(rt2x00dev
, SEC_CSR0
, reg
);
416 static int rt61pci_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
417 struct rt2x00lib_crypto
*crypto
,
418 struct ieee80211_key_conf
*key
)
420 struct hw_pairwise_ta_entry addr_entry
;
421 struct hw_key_entry key_entry
;
425 if (crypto
->cmd
== SET_KEY
) {
427 * rt2x00lib can't determine the correct free
428 * key_idx for pairwise keys. We have 2 registers
429 * with key valid bits. The goal is simple: read
430 * the first register. If that is full, move to
432 * When both registers are full, we drop the key.
433 * Otherwise, we use the first invalid entry.
435 rt2x00pci_register_read(rt2x00dev
, SEC_CSR2
, ®
);
436 if (reg
&& reg
== ~0) {
437 key
->hw_key_idx
= 32;
438 rt2x00pci_register_read(rt2x00dev
, SEC_CSR3
, ®
);
439 if (reg
&& reg
== ~0)
443 key
->hw_key_idx
+= reg
? ffz(reg
) : 0;
446 * Upload key to hardware
448 memcpy(key_entry
.key
, crypto
->key
,
449 sizeof(key_entry
.key
));
450 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
451 sizeof(key_entry
.tx_mic
));
452 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
453 sizeof(key_entry
.rx_mic
));
455 memset(&addr_entry
, 0, sizeof(addr_entry
));
456 memcpy(&addr_entry
, crypto
->address
, ETH_ALEN
);
457 addr_entry
.cipher
= crypto
->cipher
;
459 reg
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
460 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
461 &key_entry
, sizeof(key_entry
));
463 reg
= PAIRWISE_TA_ENTRY(key
->hw_key_idx
);
464 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
465 &addr_entry
, sizeof(addr_entry
));
468 * Enable pairwise lookup table for given BSS idx.
469 * Without this, received frames will not be decrypted
472 rt2x00pci_register_read(rt2x00dev
, SEC_CSR4
, ®
);
473 reg
|= (1 << crypto
->bssidx
);
474 rt2x00pci_register_write(rt2x00dev
, SEC_CSR4
, reg
);
477 * The driver does not support the IV/EIV generation
478 * in hardware. However it doesn't support the IV/EIV
479 * inside the ieee80211 frame either, but requires it
480 * to be provided separately for the descriptor.
481 * rt2x00lib will cut the IV/EIV data out of all frames
482 * given to us by mac80211, but we must tell mac80211
483 * to generate the IV/EIV data.
485 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
489 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
490 * a particular key is valid. Because using the FIELD32()
491 * defines directly will cause a lot of overhead, we use
492 * a calculation to determine the correct bit directly.
494 if (key
->hw_key_idx
< 32) {
495 mask
= 1 << key
->hw_key_idx
;
497 rt2x00pci_register_read(rt2x00dev
, SEC_CSR2
, ®
);
498 if (crypto
->cmd
== SET_KEY
)
500 else if (crypto
->cmd
== DISABLE_KEY
)
502 rt2x00pci_register_write(rt2x00dev
, SEC_CSR2
, reg
);
504 mask
= 1 << (key
->hw_key_idx
- 32);
506 rt2x00pci_register_read(rt2x00dev
, SEC_CSR3
, ®
);
507 if (crypto
->cmd
== SET_KEY
)
509 else if (crypto
->cmd
== DISABLE_KEY
)
511 rt2x00pci_register_write(rt2x00dev
, SEC_CSR3
, reg
);
517 static void rt61pci_config_filter(struct rt2x00_dev
*rt2x00dev
,
518 const unsigned int filter_flags
)
523 * Start configuration steps.
524 * Note that the version error will always be dropped
525 * and broadcast frames will always be accepted since
526 * there is no filter for it at this time.
528 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
529 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CRC
,
530 !(filter_flags
& FIF_FCSFAIL
));
531 rt2x00_set_field32(®
, TXRX_CSR0_DROP_PHYSICAL
,
532 !(filter_flags
& FIF_PLCPFAIL
));
533 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CONTROL
,
534 !(filter_flags
& (FIF_CONTROL
| FIF_PSPOLL
)));
535 rt2x00_set_field32(®
, TXRX_CSR0_DROP_NOT_TO_ME
,
536 !(filter_flags
& FIF_PROMISC_IN_BSS
));
537 rt2x00_set_field32(®
, TXRX_CSR0_DROP_TO_DS
,
538 !(filter_flags
& FIF_PROMISC_IN_BSS
) &&
539 !rt2x00dev
->intf_ap_count
);
540 rt2x00_set_field32(®
, TXRX_CSR0_DROP_VERSION_ERROR
, 1);
541 rt2x00_set_field32(®
, TXRX_CSR0_DROP_MULTICAST
,
542 !(filter_flags
& FIF_ALLMULTI
));
543 rt2x00_set_field32(®
, TXRX_CSR0_DROP_BROADCAST
, 0);
544 rt2x00_set_field32(®
, TXRX_CSR0_DROP_ACK_CTS
,
545 !(filter_flags
& FIF_CONTROL
));
546 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
549 static void rt61pci_config_intf(struct rt2x00_dev
*rt2x00dev
,
550 struct rt2x00_intf
*intf
,
551 struct rt2x00intf_conf
*conf
,
552 const unsigned int flags
)
554 unsigned int beacon_base
;
557 if (flags
& CONFIG_UPDATE_TYPE
) {
559 * Clear current synchronisation setup.
560 * For the Beacon base registers, we only need to clear
561 * the first byte since that byte contains the VALID and OWNER
562 * bits which (when set to 0) will invalidate the entire beacon.
564 beacon_base
= HW_BEACON_OFFSET(intf
->beacon
->entry_idx
);
565 rt2x00pci_register_write(rt2x00dev
, beacon_base
, 0);
568 * Enable synchronisation.
570 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
571 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
572 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, conf
->sync
);
573 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
574 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
577 if (flags
& CONFIG_UPDATE_MAC
) {
578 reg
= le32_to_cpu(conf
->mac
[1]);
579 rt2x00_set_field32(®
, MAC_CSR3_UNICAST_TO_ME_MASK
, 0xff);
580 conf
->mac
[1] = cpu_to_le32(reg
);
582 rt2x00pci_register_multiwrite(rt2x00dev
, MAC_CSR2
,
583 conf
->mac
, sizeof(conf
->mac
));
586 if (flags
& CONFIG_UPDATE_BSSID
) {
587 reg
= le32_to_cpu(conf
->bssid
[1]);
588 rt2x00_set_field32(®
, MAC_CSR5_BSS_ID_MASK
, 3);
589 conf
->bssid
[1] = cpu_to_le32(reg
);
591 rt2x00pci_register_multiwrite(rt2x00dev
, MAC_CSR4
,
592 conf
->bssid
, sizeof(conf
->bssid
));
596 static void rt61pci_config_erp(struct rt2x00_dev
*rt2x00dev
,
597 struct rt2x00lib_erp
*erp
)
601 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
602 rt2x00_set_field32(®
, TXRX_CSR0_RX_ACK_TIMEOUT
, 0x32);
603 rt2x00_set_field32(®
, TXRX_CSR0_TSF_OFFSET
, IEEE80211_HEADER
);
604 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
606 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
607 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_ENABLE
, 1);
608 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_PREAMBLE
,
609 !!erp
->short_preamble
);
610 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
612 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR5
, erp
->basic_rates
);
614 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
615 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
,
616 erp
->beacon_int
* 16);
617 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
619 rt2x00pci_register_read(rt2x00dev
, MAC_CSR9
, ®
);
620 rt2x00_set_field32(®
, MAC_CSR9_SLOT_TIME
, erp
->slot_time
);
621 rt2x00pci_register_write(rt2x00dev
, MAC_CSR9
, reg
);
623 rt2x00pci_register_read(rt2x00dev
, MAC_CSR8
, ®
);
624 rt2x00_set_field32(®
, MAC_CSR8_SIFS
, erp
->sifs
);
625 rt2x00_set_field32(®
, MAC_CSR8_SIFS_AFTER_RX_OFDM
, 3);
626 rt2x00_set_field32(®
, MAC_CSR8_EIFS
, erp
->eifs
);
627 rt2x00pci_register_write(rt2x00dev
, MAC_CSR8
, reg
);
630 static void rt61pci_config_antenna_5x(struct rt2x00_dev
*rt2x00dev
,
631 struct antenna_setup
*ant
)
637 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
638 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
639 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
641 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, rt2x00_rf(rt2x00dev
, RF5325
));
644 * Configure the RX antenna.
647 case ANTENNA_HW_DIVERSITY
:
648 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
649 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
650 (rt2x00dev
->curr_band
!= IEEE80211_BAND_5GHZ
));
653 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
654 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
655 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
656 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
658 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
662 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
663 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
664 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
665 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
667 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
671 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
672 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
673 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
676 static void rt61pci_config_antenna_2x(struct rt2x00_dev
*rt2x00dev
,
677 struct antenna_setup
*ant
)
683 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
684 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
685 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
687 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, rt2x00_rf(rt2x00dev
, RF2529
));
688 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
689 !test_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
));
692 * Configure the RX antenna.
695 case ANTENNA_HW_DIVERSITY
:
696 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
699 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
700 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
704 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
705 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
709 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
710 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
711 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
714 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev
*rt2x00dev
,
715 const int p1
, const int p2
)
719 rt2x00pci_register_read(rt2x00dev
, MAC_CSR13
, ®
);
721 rt2x00_set_field32(®
, MAC_CSR13_BIT4
, p1
);
722 rt2x00_set_field32(®
, MAC_CSR13_BIT12
, 0);
724 rt2x00_set_field32(®
, MAC_CSR13_BIT3
, !p2
);
725 rt2x00_set_field32(®
, MAC_CSR13_BIT11
, 0);
727 rt2x00pci_register_write(rt2x00dev
, MAC_CSR13
, reg
);
730 static void rt61pci_config_antenna_2529(struct rt2x00_dev
*rt2x00dev
,
731 struct antenna_setup
*ant
)
737 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
738 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
739 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
742 * Configure the RX antenna.
746 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
747 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
748 rt61pci_config_antenna_2529_rx(rt2x00dev
, 0, 0);
750 case ANTENNA_HW_DIVERSITY
:
752 * FIXME: Antenna selection for the rf 2529 is very confusing
753 * in the legacy driver. Just default to antenna B until the
754 * legacy code can be properly translated into rt2x00 code.
758 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
759 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
760 rt61pci_config_antenna_2529_rx(rt2x00dev
, 1, 1);
764 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
765 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
766 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
772 * value[0] -> non-LNA
778 static const struct antenna_sel antenna_sel_a
[] = {
779 { 96, { 0x58, 0x78 } },
780 { 104, { 0x38, 0x48 } },
781 { 75, { 0xfe, 0x80 } },
782 { 86, { 0xfe, 0x80 } },
783 { 88, { 0xfe, 0x80 } },
784 { 35, { 0x60, 0x60 } },
785 { 97, { 0x58, 0x58 } },
786 { 98, { 0x58, 0x58 } },
789 static const struct antenna_sel antenna_sel_bg
[] = {
790 { 96, { 0x48, 0x68 } },
791 { 104, { 0x2c, 0x3c } },
792 { 75, { 0xfe, 0x80 } },
793 { 86, { 0xfe, 0x80 } },
794 { 88, { 0xfe, 0x80 } },
795 { 35, { 0x50, 0x50 } },
796 { 97, { 0x48, 0x48 } },
797 { 98, { 0x48, 0x48 } },
800 static void rt61pci_config_ant(struct rt2x00_dev
*rt2x00dev
,
801 struct antenna_setup
*ant
)
803 const struct antenna_sel
*sel
;
809 * We should never come here because rt2x00lib is supposed
810 * to catch this and send us the correct antenna explicitely.
812 BUG_ON(ant
->rx
== ANTENNA_SW_DIVERSITY
||
813 ant
->tx
== ANTENNA_SW_DIVERSITY
);
815 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
817 lna
= test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
819 sel
= antenna_sel_bg
;
820 lna
= test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
823 for (i
= 0; i
< ARRAY_SIZE(antenna_sel_a
); i
++)
824 rt61pci_bbp_write(rt2x00dev
, sel
[i
].word
, sel
[i
].value
[lna
]);
826 rt2x00pci_register_read(rt2x00dev
, PHY_CSR0
, ®
);
828 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_BG
,
829 rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
830 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_A
,
831 rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
833 rt2x00pci_register_write(rt2x00dev
, PHY_CSR0
, reg
);
835 if (rt2x00_rf(rt2x00dev
, RF5225
) || rt2x00_rf(rt2x00dev
, RF5325
))
836 rt61pci_config_antenna_5x(rt2x00dev
, ant
);
837 else if (rt2x00_rf(rt2x00dev
, RF2527
))
838 rt61pci_config_antenna_2x(rt2x00dev
, ant
);
839 else if (rt2x00_rf(rt2x00dev
, RF2529
)) {
840 if (test_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
))
841 rt61pci_config_antenna_2x(rt2x00dev
, ant
);
843 rt61pci_config_antenna_2529(rt2x00dev
, ant
);
847 static void rt61pci_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
848 struct rt2x00lib_conf
*libconf
)
853 if (libconf
->conf
->channel
->band
== IEEE80211_BAND_2GHZ
) {
854 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
))
857 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &eeprom
);
858 lna_gain
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_BG_1
);
860 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
))
863 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &eeprom
);
864 lna_gain
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_A_1
);
867 rt2x00dev
->lna_gain
= lna_gain
;
870 static void rt61pci_config_channel(struct rt2x00_dev
*rt2x00dev
,
871 struct rf_channel
*rf
, const int txpower
)
877 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
878 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
880 smart
= !(rt2x00_rf(rt2x00dev
, RF5225
) || rt2x00_rf(rt2x00dev
, RF2527
));
882 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
883 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, smart
);
884 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
887 if (txpower
> MAX_TXPOWER
&& txpower
<= (MAX_TXPOWER
+ r94
))
888 r94
+= txpower
- MAX_TXPOWER
;
889 else if (txpower
< MIN_TXPOWER
&& txpower
>= (MIN_TXPOWER
- r94
))
891 rt61pci_bbp_write(rt2x00dev
, 94, r94
);
893 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
894 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
895 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
896 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
900 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
901 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
902 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
903 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
907 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
908 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
909 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
910 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
915 static void rt61pci_config_txpower(struct rt2x00_dev
*rt2x00dev
,
918 struct rf_channel rf
;
920 rt2x00_rf_read(rt2x00dev
, 1, &rf
.rf1
);
921 rt2x00_rf_read(rt2x00dev
, 2, &rf
.rf2
);
922 rt2x00_rf_read(rt2x00dev
, 3, &rf
.rf3
);
923 rt2x00_rf_read(rt2x00dev
, 4, &rf
.rf4
);
925 rt61pci_config_channel(rt2x00dev
, &rf
, txpower
);
928 static void rt61pci_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
929 struct rt2x00lib_conf
*libconf
)
933 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
934 rt2x00_set_field32(®
, TXRX_CSR4_LONG_RETRY_LIMIT
,
935 libconf
->conf
->long_frame_max_tx_count
);
936 rt2x00_set_field32(®
, TXRX_CSR4_SHORT_RETRY_LIMIT
,
937 libconf
->conf
->short_frame_max_tx_count
);
938 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
941 static void rt61pci_config_ps(struct rt2x00_dev
*rt2x00dev
,
942 struct rt2x00lib_conf
*libconf
)
944 enum dev_state state
=
945 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
946 STATE_SLEEP
: STATE_AWAKE
;
949 if (state
== STATE_SLEEP
) {
950 rt2x00pci_register_read(rt2x00dev
, MAC_CSR11
, ®
);
951 rt2x00_set_field32(®
, MAC_CSR11_DELAY_AFTER_TBCN
,
952 rt2x00dev
->beacon_int
- 10);
953 rt2x00_set_field32(®
, MAC_CSR11_TBCN_BEFORE_WAKEUP
,
954 libconf
->conf
->listen_interval
- 1);
955 rt2x00_set_field32(®
, MAC_CSR11_WAKEUP_LATENCY
, 5);
957 /* We must first disable autowake before it can be enabled */
958 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 0);
959 rt2x00pci_register_write(rt2x00dev
, MAC_CSR11
, reg
);
961 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 1);
962 rt2x00pci_register_write(rt2x00dev
, MAC_CSR11
, reg
);
964 rt2x00pci_register_write(rt2x00dev
, SOFT_RESET_CSR
, 0x00000005);
965 rt2x00pci_register_write(rt2x00dev
, IO_CNTL_CSR
, 0x0000001c);
966 rt2x00pci_register_write(rt2x00dev
, PCI_USEC_CSR
, 0x00000060);
968 rt61pci_mcu_request(rt2x00dev
, MCU_SLEEP
, 0xff, 0, 0);
970 rt2x00pci_register_read(rt2x00dev
, MAC_CSR11
, ®
);
971 rt2x00_set_field32(®
, MAC_CSR11_DELAY_AFTER_TBCN
, 0);
972 rt2x00_set_field32(®
, MAC_CSR11_TBCN_BEFORE_WAKEUP
, 0);
973 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 0);
974 rt2x00_set_field32(®
, MAC_CSR11_WAKEUP_LATENCY
, 0);
975 rt2x00pci_register_write(rt2x00dev
, MAC_CSR11
, reg
);
977 rt2x00pci_register_write(rt2x00dev
, SOFT_RESET_CSR
, 0x00000007);
978 rt2x00pci_register_write(rt2x00dev
, IO_CNTL_CSR
, 0x00000018);
979 rt2x00pci_register_write(rt2x00dev
, PCI_USEC_CSR
, 0x00000020);
981 rt61pci_mcu_request(rt2x00dev
, MCU_WAKEUP
, 0xff, 0, 0);
985 static void rt61pci_config(struct rt2x00_dev
*rt2x00dev
,
986 struct rt2x00lib_conf
*libconf
,
987 const unsigned int flags
)
989 /* Always recalculate LNA gain before changing configuration */
990 rt61pci_config_lna_gain(rt2x00dev
, libconf
);
992 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
)
993 rt61pci_config_channel(rt2x00dev
, &libconf
->rf
,
994 libconf
->conf
->power_level
);
995 if ((flags
& IEEE80211_CONF_CHANGE_POWER
) &&
996 !(flags
& IEEE80211_CONF_CHANGE_CHANNEL
))
997 rt61pci_config_txpower(rt2x00dev
, libconf
->conf
->power_level
);
998 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
999 rt61pci_config_retry_limit(rt2x00dev
, libconf
);
1000 if (flags
& IEEE80211_CONF_CHANGE_PS
)
1001 rt61pci_config_ps(rt2x00dev
, libconf
);
1007 static void rt61pci_link_stats(struct rt2x00_dev
*rt2x00dev
,
1008 struct link_qual
*qual
)
1013 * Update FCS error count from register.
1015 rt2x00pci_register_read(rt2x00dev
, STA_CSR0
, ®
);
1016 qual
->rx_failed
= rt2x00_get_field32(reg
, STA_CSR0_FCS_ERROR
);
1019 * Update False CCA count from register.
1021 rt2x00pci_register_read(rt2x00dev
, STA_CSR1
, ®
);
1022 qual
->false_cca
= rt2x00_get_field32(reg
, STA_CSR1_FALSE_CCA_ERROR
);
1025 static inline void rt61pci_set_vgc(struct rt2x00_dev
*rt2x00dev
,
1026 struct link_qual
*qual
, u8 vgc_level
)
1028 if (qual
->vgc_level
!= vgc_level
) {
1029 rt61pci_bbp_write(rt2x00dev
, 17, vgc_level
);
1030 qual
->vgc_level
= vgc_level
;
1031 qual
->vgc_level_reg
= vgc_level
;
1035 static void rt61pci_reset_tuner(struct rt2x00_dev
*rt2x00dev
,
1036 struct link_qual
*qual
)
1038 rt61pci_set_vgc(rt2x00dev
, qual
, 0x20);
1041 static void rt61pci_link_tuner(struct rt2x00_dev
*rt2x00dev
,
1042 struct link_qual
*qual
, const u32 count
)
1048 * Determine r17 bounds.
1050 if (rt2x00dev
->rx_status
.band
== IEEE80211_BAND_5GHZ
) {
1053 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
)) {
1060 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
)) {
1067 * If we are not associated, we should go straight to the
1068 * dynamic CCA tuning.
1070 if (!rt2x00dev
->intf_associated
)
1071 goto dynamic_cca_tune
;
1074 * Special big-R17 for very short distance
1076 if (qual
->rssi
>= -35) {
1077 rt61pci_set_vgc(rt2x00dev
, qual
, 0x60);
1082 * Special big-R17 for short distance
1084 if (qual
->rssi
>= -58) {
1085 rt61pci_set_vgc(rt2x00dev
, qual
, up_bound
);
1090 * Special big-R17 for middle-short distance
1092 if (qual
->rssi
>= -66) {
1093 rt61pci_set_vgc(rt2x00dev
, qual
, low_bound
+ 0x10);
1098 * Special mid-R17 for middle distance
1100 if (qual
->rssi
>= -74) {
1101 rt61pci_set_vgc(rt2x00dev
, qual
, low_bound
+ 0x08);
1106 * Special case: Change up_bound based on the rssi.
1107 * Lower up_bound when rssi is weaker then -74 dBm.
1109 up_bound
-= 2 * (-74 - qual
->rssi
);
1110 if (low_bound
> up_bound
)
1111 up_bound
= low_bound
;
1113 if (qual
->vgc_level
> up_bound
) {
1114 rt61pci_set_vgc(rt2x00dev
, qual
, up_bound
);
1121 * r17 does not yet exceed upper limit, continue and base
1122 * the r17 tuning on the false CCA count.
1124 if ((qual
->false_cca
> 512) && (qual
->vgc_level
< up_bound
))
1125 rt61pci_set_vgc(rt2x00dev
, qual
, ++qual
->vgc_level
);
1126 else if ((qual
->false_cca
< 100) && (qual
->vgc_level
> low_bound
))
1127 rt61pci_set_vgc(rt2x00dev
, qual
, --qual
->vgc_level
);
1131 * Firmware functions
1133 static char *rt61pci_get_firmware_name(struct rt2x00_dev
*rt2x00dev
)
1138 pci_read_config_word(to_pci_dev(rt2x00dev
->dev
), PCI_DEVICE_ID
, &chip
);
1141 fw_name
= FIRMWARE_RT2561
;
1143 case RT2561s_PCI_ID
:
1144 fw_name
= FIRMWARE_RT2561s
;
1147 fw_name
= FIRMWARE_RT2661
;
1157 static int rt61pci_check_firmware(struct rt2x00_dev
*rt2x00dev
,
1158 const u8
*data
, const size_t len
)
1164 * Only support 8kb firmware files.
1167 return FW_BAD_LENGTH
;
1170 * The last 2 bytes in the firmware array are the crc checksum itself.
1171 * This means that we should never pass those 2 bytes to the crc
1174 fw_crc
= (data
[len
- 2] << 8 | data
[len
- 1]);
1177 * Use the crc itu-t algorithm.
1179 crc
= crc_itu_t(0, data
, len
- 2);
1180 crc
= crc_itu_t_byte(crc
, 0);
1181 crc
= crc_itu_t_byte(crc
, 0);
1183 return (fw_crc
== crc
) ? FW_OK
: FW_BAD_CRC
;
1186 static int rt61pci_load_firmware(struct rt2x00_dev
*rt2x00dev
,
1187 const u8
*data
, const size_t len
)
1193 * Wait for stable hardware.
1195 for (i
= 0; i
< 100; i
++) {
1196 rt2x00pci_register_read(rt2x00dev
, MAC_CSR0
, ®
);
1203 ERROR(rt2x00dev
, "Unstable hardware.\n");
1208 * Prepare MCU and mailbox for firmware loading.
1211 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 1);
1212 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1213 rt2x00pci_register_write(rt2x00dev
, M2H_CMD_DONE_CSR
, 0xffffffff);
1214 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
1215 rt2x00pci_register_write(rt2x00dev
, HOST_CMD_CSR
, 0);
1218 * Write firmware to device.
1221 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 1);
1222 rt2x00_set_field32(®
, MCU_CNTL_CSR_SELECT_BANK
, 1);
1223 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1225 rt2x00pci_register_multiwrite(rt2x00dev
, FIRMWARE_IMAGE_BASE
,
1228 rt2x00_set_field32(®
, MCU_CNTL_CSR_SELECT_BANK
, 0);
1229 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1231 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 0);
1232 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1234 for (i
= 0; i
< 100; i
++) {
1235 rt2x00pci_register_read(rt2x00dev
, MCU_CNTL_CSR
, ®
);
1236 if (rt2x00_get_field32(reg
, MCU_CNTL_CSR_READY
))
1242 ERROR(rt2x00dev
, "MCU Control register not ready.\n");
1247 * Hardware needs another millisecond before it is ready.
1252 * Reset MAC and BBP registers.
1255 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1256 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1257 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1259 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1260 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1261 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1262 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1264 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1265 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1266 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1272 * Initialization functions.
1274 static bool rt61pci_get_entry_state(struct queue_entry
*entry
)
1276 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1279 if (entry
->queue
->qid
== QID_RX
) {
1280 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1282 return rt2x00_get_field32(word
, RXD_W0_OWNER_NIC
);
1284 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1286 return (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
1287 rt2x00_get_field32(word
, TXD_W0_VALID
));
1291 static void rt61pci_clear_entry(struct queue_entry
*entry
)
1293 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1294 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1297 if (entry
->queue
->qid
== QID_RX
) {
1298 rt2x00_desc_read(entry_priv
->desc
, 5, &word
);
1299 rt2x00_set_field32(&word
, RXD_W5_BUFFER_PHYSICAL_ADDRESS
,
1301 rt2x00_desc_write(entry_priv
->desc
, 5, word
);
1303 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1304 rt2x00_set_field32(&word
, RXD_W0_OWNER_NIC
, 1);
1305 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
1307 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1308 rt2x00_set_field32(&word
, TXD_W0_VALID
, 0);
1309 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 0);
1310 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
1314 static int rt61pci_init_queues(struct rt2x00_dev
*rt2x00dev
)
1316 struct queue_entry_priv_pci
*entry_priv
;
1320 * Initialize registers.
1322 rt2x00pci_register_read(rt2x00dev
, TX_RING_CSR0
, ®
);
1323 rt2x00_set_field32(®
, TX_RING_CSR0_AC0_RING_SIZE
,
1324 rt2x00dev
->tx
[0].limit
);
1325 rt2x00_set_field32(®
, TX_RING_CSR0_AC1_RING_SIZE
,
1326 rt2x00dev
->tx
[1].limit
);
1327 rt2x00_set_field32(®
, TX_RING_CSR0_AC2_RING_SIZE
,
1328 rt2x00dev
->tx
[2].limit
);
1329 rt2x00_set_field32(®
, TX_RING_CSR0_AC3_RING_SIZE
,
1330 rt2x00dev
->tx
[3].limit
);
1331 rt2x00pci_register_write(rt2x00dev
, TX_RING_CSR0
, reg
);
1333 rt2x00pci_register_read(rt2x00dev
, TX_RING_CSR1
, ®
);
1334 rt2x00_set_field32(®
, TX_RING_CSR1_TXD_SIZE
,
1335 rt2x00dev
->tx
[0].desc_size
/ 4);
1336 rt2x00pci_register_write(rt2x00dev
, TX_RING_CSR1
, reg
);
1338 entry_priv
= rt2x00dev
->tx
[0].entries
[0].priv_data
;
1339 rt2x00pci_register_read(rt2x00dev
, AC0_BASE_CSR
, ®
);
1340 rt2x00_set_field32(®
, AC0_BASE_CSR_RING_REGISTER
,
1341 entry_priv
->desc_dma
);
1342 rt2x00pci_register_write(rt2x00dev
, AC0_BASE_CSR
, reg
);
1344 entry_priv
= rt2x00dev
->tx
[1].entries
[0].priv_data
;
1345 rt2x00pci_register_read(rt2x00dev
, AC1_BASE_CSR
, ®
);
1346 rt2x00_set_field32(®
, AC1_BASE_CSR_RING_REGISTER
,
1347 entry_priv
->desc_dma
);
1348 rt2x00pci_register_write(rt2x00dev
, AC1_BASE_CSR
, reg
);
1350 entry_priv
= rt2x00dev
->tx
[2].entries
[0].priv_data
;
1351 rt2x00pci_register_read(rt2x00dev
, AC2_BASE_CSR
, ®
);
1352 rt2x00_set_field32(®
, AC2_BASE_CSR_RING_REGISTER
,
1353 entry_priv
->desc_dma
);
1354 rt2x00pci_register_write(rt2x00dev
, AC2_BASE_CSR
, reg
);
1356 entry_priv
= rt2x00dev
->tx
[3].entries
[0].priv_data
;
1357 rt2x00pci_register_read(rt2x00dev
, AC3_BASE_CSR
, ®
);
1358 rt2x00_set_field32(®
, AC3_BASE_CSR_RING_REGISTER
,
1359 entry_priv
->desc_dma
);
1360 rt2x00pci_register_write(rt2x00dev
, AC3_BASE_CSR
, reg
);
1362 rt2x00pci_register_read(rt2x00dev
, RX_RING_CSR
, ®
);
1363 rt2x00_set_field32(®
, RX_RING_CSR_RING_SIZE
, rt2x00dev
->rx
->limit
);
1364 rt2x00_set_field32(®
, RX_RING_CSR_RXD_SIZE
,
1365 rt2x00dev
->rx
->desc_size
/ 4);
1366 rt2x00_set_field32(®
, RX_RING_CSR_RXD_WRITEBACK_SIZE
, 4);
1367 rt2x00pci_register_write(rt2x00dev
, RX_RING_CSR
, reg
);
1369 entry_priv
= rt2x00dev
->rx
->entries
[0].priv_data
;
1370 rt2x00pci_register_read(rt2x00dev
, RX_BASE_CSR
, ®
);
1371 rt2x00_set_field32(®
, RX_BASE_CSR_RING_REGISTER
,
1372 entry_priv
->desc_dma
);
1373 rt2x00pci_register_write(rt2x00dev
, RX_BASE_CSR
, reg
);
1375 rt2x00pci_register_read(rt2x00dev
, TX_DMA_DST_CSR
, ®
);
1376 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC0
, 2);
1377 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC1
, 2);
1378 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC2
, 2);
1379 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC3
, 2);
1380 rt2x00pci_register_write(rt2x00dev
, TX_DMA_DST_CSR
, reg
);
1382 rt2x00pci_register_read(rt2x00dev
, LOAD_TX_RING_CSR
, ®
);
1383 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC0
, 1);
1384 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC1
, 1);
1385 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC2
, 1);
1386 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC3
, 1);
1387 rt2x00pci_register_write(rt2x00dev
, LOAD_TX_RING_CSR
, reg
);
1389 rt2x00pci_register_read(rt2x00dev
, RX_CNTL_CSR
, ®
);
1390 rt2x00_set_field32(®
, RX_CNTL_CSR_LOAD_RXD
, 1);
1391 rt2x00pci_register_write(rt2x00dev
, RX_CNTL_CSR
, reg
);
1396 static int rt61pci_init_registers(struct rt2x00_dev
*rt2x00dev
)
1400 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1401 rt2x00_set_field32(®
, TXRX_CSR0_AUTO_TX_SEQ
, 1);
1402 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
, 0);
1403 rt2x00_set_field32(®
, TXRX_CSR0_TX_WITHOUT_WAITING
, 0);
1404 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1406 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR1
, ®
);
1407 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0
, 47); /* CCK Signal */
1408 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0_VALID
, 1);
1409 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1
, 30); /* Rssi */
1410 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1_VALID
, 1);
1411 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2
, 42); /* OFDM Rate */
1412 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2_VALID
, 1);
1413 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3
, 30); /* Rssi */
1414 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3_VALID
, 1);
1415 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR1
, reg
);
1418 * CCK TXD BBP registers
1420 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR2
, ®
);
1421 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0
, 13);
1422 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0_VALID
, 1);
1423 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1
, 12);
1424 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1_VALID
, 1);
1425 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2
, 11);
1426 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2_VALID
, 1);
1427 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3
, 10);
1428 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3_VALID
, 1);
1429 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR2
, reg
);
1432 * OFDM TXD BBP registers
1434 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR3
, ®
);
1435 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0
, 7);
1436 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0_VALID
, 1);
1437 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1
, 6);
1438 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1_VALID
, 1);
1439 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2
, 5);
1440 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2_VALID
, 1);
1441 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR3
, reg
);
1443 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR7
, ®
);
1444 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_6MBS
, 59);
1445 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_9MBS
, 53);
1446 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_12MBS
, 49);
1447 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_18MBS
, 46);
1448 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR7
, reg
);
1450 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR8
, ®
);
1451 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_24MBS
, 44);
1452 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_36MBS
, 42);
1453 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_48MBS
, 42);
1454 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_54MBS
, 42);
1455 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR8
, reg
);
1457 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1458 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
, 0);
1459 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 0);
1460 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, 0);
1461 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 0);
1462 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1463 rt2x00_set_field32(®
, TXRX_CSR9_TIMESTAMP_COMPENSATE
, 0);
1464 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1466 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR15
, 0x0000000f);
1468 rt2x00pci_register_write(rt2x00dev
, MAC_CSR6
, 0x00000fff);
1470 rt2x00pci_register_read(rt2x00dev
, MAC_CSR9
, ®
);
1471 rt2x00_set_field32(®
, MAC_CSR9_CW_SELECT
, 0);
1472 rt2x00pci_register_write(rt2x00dev
, MAC_CSR9
, reg
);
1474 rt2x00pci_register_write(rt2x00dev
, MAC_CSR10
, 0x0000071c);
1476 if (rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, STATE_AWAKE
))
1479 rt2x00pci_register_write(rt2x00dev
, MAC_CSR13
, 0x0000e000);
1482 * Invalidate all Shared Keys (SEC_CSR0),
1483 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1485 rt2x00pci_register_write(rt2x00dev
, SEC_CSR0
, 0x00000000);
1486 rt2x00pci_register_write(rt2x00dev
, SEC_CSR1
, 0x00000000);
1487 rt2x00pci_register_write(rt2x00dev
, SEC_CSR5
, 0x00000000);
1489 rt2x00pci_register_write(rt2x00dev
, PHY_CSR1
, 0x000023b0);
1490 rt2x00pci_register_write(rt2x00dev
, PHY_CSR5
, 0x060a100c);
1491 rt2x00pci_register_write(rt2x00dev
, PHY_CSR6
, 0x00080606);
1492 rt2x00pci_register_write(rt2x00dev
, PHY_CSR7
, 0x00000a08);
1494 rt2x00pci_register_write(rt2x00dev
, PCI_CFG_CSR
, 0x28ca4404);
1496 rt2x00pci_register_write(rt2x00dev
, TEST_MODE_CSR
, 0x00000200);
1498 rt2x00pci_register_write(rt2x00dev
, M2H_CMD_DONE_CSR
, 0xffffffff);
1502 * For the Beacon base registers we only need to clear
1503 * the first byte since that byte contains the VALID and OWNER
1504 * bits which (when set to 0) will invalidate the entire beacon.
1506 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE0
, 0);
1507 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE1
, 0);
1508 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE2
, 0);
1509 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE3
, 0);
1512 * We must clear the error counters.
1513 * These registers are cleared on read,
1514 * so we may pass a useless variable to store the value.
1516 rt2x00pci_register_read(rt2x00dev
, STA_CSR0
, ®
);
1517 rt2x00pci_register_read(rt2x00dev
, STA_CSR1
, ®
);
1518 rt2x00pci_register_read(rt2x00dev
, STA_CSR2
, ®
);
1521 * Reset MAC and BBP registers.
1523 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1524 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1525 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1526 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1528 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1529 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1530 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1531 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1533 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1534 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1535 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1540 static int rt61pci_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
1545 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1546 rt61pci_bbp_read(rt2x00dev
, 0, &value
);
1547 if ((value
!= 0xff) && (value
!= 0x00))
1549 udelay(REGISTER_BUSY_DELAY
);
1552 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
1556 static int rt61pci_init_bbp(struct rt2x00_dev
*rt2x00dev
)
1563 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev
)))
1566 rt61pci_bbp_write(rt2x00dev
, 3, 0x00);
1567 rt61pci_bbp_write(rt2x00dev
, 15, 0x30);
1568 rt61pci_bbp_write(rt2x00dev
, 21, 0xc8);
1569 rt61pci_bbp_write(rt2x00dev
, 22, 0x38);
1570 rt61pci_bbp_write(rt2x00dev
, 23, 0x06);
1571 rt61pci_bbp_write(rt2x00dev
, 24, 0xfe);
1572 rt61pci_bbp_write(rt2x00dev
, 25, 0x0a);
1573 rt61pci_bbp_write(rt2x00dev
, 26, 0x0d);
1574 rt61pci_bbp_write(rt2x00dev
, 34, 0x12);
1575 rt61pci_bbp_write(rt2x00dev
, 37, 0x07);
1576 rt61pci_bbp_write(rt2x00dev
, 39, 0xf8);
1577 rt61pci_bbp_write(rt2x00dev
, 41, 0x60);
1578 rt61pci_bbp_write(rt2x00dev
, 53, 0x10);
1579 rt61pci_bbp_write(rt2x00dev
, 54, 0x18);
1580 rt61pci_bbp_write(rt2x00dev
, 60, 0x10);
1581 rt61pci_bbp_write(rt2x00dev
, 61, 0x04);
1582 rt61pci_bbp_write(rt2x00dev
, 62, 0x04);
1583 rt61pci_bbp_write(rt2x00dev
, 75, 0xfe);
1584 rt61pci_bbp_write(rt2x00dev
, 86, 0xfe);
1585 rt61pci_bbp_write(rt2x00dev
, 88, 0xfe);
1586 rt61pci_bbp_write(rt2x00dev
, 90, 0x0f);
1587 rt61pci_bbp_write(rt2x00dev
, 99, 0x00);
1588 rt61pci_bbp_write(rt2x00dev
, 102, 0x16);
1589 rt61pci_bbp_write(rt2x00dev
, 107, 0x04);
1591 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
1592 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
1594 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
1595 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
1596 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
1597 rt61pci_bbp_write(rt2x00dev
, reg_id
, value
);
1605 * Device state switch handlers.
1607 static void rt61pci_toggle_rx(struct rt2x00_dev
*rt2x00dev
,
1608 enum dev_state state
)
1612 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1613 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
,
1614 (state
== STATE_RADIO_RX_OFF
) ||
1615 (state
== STATE_RADIO_RX_OFF_LINK
));
1616 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1619 static void rt61pci_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
1620 enum dev_state state
)
1622 int mask
= (state
== STATE_RADIO_IRQ_OFF
);
1626 * When interrupts are being enabled, the interrupt registers
1627 * should clear the register to assure a clean state.
1629 if (state
== STATE_RADIO_IRQ_ON
) {
1630 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
1631 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
1633 rt2x00pci_register_read(rt2x00dev
, MCU_INT_SOURCE_CSR
, ®
);
1634 rt2x00pci_register_write(rt2x00dev
, MCU_INT_SOURCE_CSR
, reg
);
1638 * Only toggle the interrupts bits we are going to use.
1639 * Non-checked interrupt bits are disabled by default.
1641 rt2x00pci_register_read(rt2x00dev
, INT_MASK_CSR
, ®
);
1642 rt2x00_set_field32(®
, INT_MASK_CSR_TXDONE
, mask
);
1643 rt2x00_set_field32(®
, INT_MASK_CSR_RXDONE
, mask
);
1644 rt2x00_set_field32(®
, INT_MASK_CSR_ENABLE_MITIGATION
, mask
);
1645 rt2x00_set_field32(®
, INT_MASK_CSR_MITIGATION_PERIOD
, 0xff);
1646 rt2x00pci_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
1648 rt2x00pci_register_read(rt2x00dev
, MCU_INT_MASK_CSR
, ®
);
1649 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_0
, mask
);
1650 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_1
, mask
);
1651 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_2
, mask
);
1652 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_3
, mask
);
1653 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_4
, mask
);
1654 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_5
, mask
);
1655 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_6
, mask
);
1656 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_7
, mask
);
1657 rt2x00pci_register_write(rt2x00dev
, MCU_INT_MASK_CSR
, reg
);
1660 static int rt61pci_enable_radio(struct rt2x00_dev
*rt2x00dev
)
1665 * Initialize all registers.
1667 if (unlikely(rt61pci_init_queues(rt2x00dev
) ||
1668 rt61pci_init_registers(rt2x00dev
) ||
1669 rt61pci_init_bbp(rt2x00dev
)))
1675 rt2x00pci_register_read(rt2x00dev
, RX_CNTL_CSR
, ®
);
1676 rt2x00_set_field32(®
, RX_CNTL_CSR_ENABLE_RX_DMA
, 1);
1677 rt2x00pci_register_write(rt2x00dev
, RX_CNTL_CSR
, reg
);
1682 static void rt61pci_disable_radio(struct rt2x00_dev
*rt2x00dev
)
1687 rt2x00pci_register_write(rt2x00dev
, MAC_CSR10
, 0x00001818);
1690 static int rt61pci_set_state(struct rt2x00_dev
*rt2x00dev
, enum dev_state state
)
1696 put_to_sleep
= (state
!= STATE_AWAKE
);
1698 rt2x00pci_register_read(rt2x00dev
, MAC_CSR12
, ®
);
1699 rt2x00_set_field32(®
, MAC_CSR12_FORCE_WAKEUP
, !put_to_sleep
);
1700 rt2x00_set_field32(®
, MAC_CSR12_PUT_TO_SLEEP
, put_to_sleep
);
1701 rt2x00pci_register_write(rt2x00dev
, MAC_CSR12
, reg
);
1704 * Device is not guaranteed to be in the requested state yet.
1705 * We must wait until the register indicates that the
1706 * device has entered the correct state.
1708 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1709 rt2x00pci_register_read(rt2x00dev
, MAC_CSR12
, ®2
);
1710 state
= rt2x00_get_field32(reg2
, MAC_CSR12_BBP_CURRENT_STATE
);
1711 if (state
== !put_to_sleep
)
1713 rt2x00pci_register_write(rt2x00dev
, MAC_CSR12
, reg
);
1720 static int rt61pci_set_device_state(struct rt2x00_dev
*rt2x00dev
,
1721 enum dev_state state
)
1726 case STATE_RADIO_ON
:
1727 retval
= rt61pci_enable_radio(rt2x00dev
);
1729 case STATE_RADIO_OFF
:
1730 rt61pci_disable_radio(rt2x00dev
);
1732 case STATE_RADIO_RX_ON
:
1733 case STATE_RADIO_RX_ON_LINK
:
1734 case STATE_RADIO_RX_OFF
:
1735 case STATE_RADIO_RX_OFF_LINK
:
1736 rt61pci_toggle_rx(rt2x00dev
, state
);
1738 case STATE_RADIO_IRQ_ON
:
1739 case STATE_RADIO_IRQ_OFF
:
1740 rt61pci_toggle_irq(rt2x00dev
, state
);
1742 case STATE_DEEP_SLEEP
:
1746 retval
= rt61pci_set_state(rt2x00dev
, state
);
1753 if (unlikely(retval
))
1754 ERROR(rt2x00dev
, "Device failed to enter state %d (%d).\n",
1761 * TX descriptor initialization
1763 static void rt61pci_write_tx_desc(struct rt2x00_dev
*rt2x00dev
,
1764 struct sk_buff
*skb
,
1765 struct txentry_desc
*txdesc
)
1767 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(skb
);
1768 struct queue_entry_priv_pci
*entry_priv
= skbdesc
->entry
->priv_data
;
1769 __le32
*txd
= entry_priv
->desc
;
1773 * Start writing the descriptor words.
1775 rt2x00_desc_read(txd
, 1, &word
);
1776 rt2x00_set_field32(&word
, TXD_W1_HOST_Q_ID
, txdesc
->queue
);
1777 rt2x00_set_field32(&word
, TXD_W1_AIFSN
, txdesc
->aifs
);
1778 rt2x00_set_field32(&word
, TXD_W1_CWMIN
, txdesc
->cw_min
);
1779 rt2x00_set_field32(&word
, TXD_W1_CWMAX
, txdesc
->cw_max
);
1780 rt2x00_set_field32(&word
, TXD_W1_IV_OFFSET
, txdesc
->iv_offset
);
1781 rt2x00_set_field32(&word
, TXD_W1_HW_SEQUENCE
,
1782 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
1783 rt2x00_set_field32(&word
, TXD_W1_BUFFER_COUNT
, 1);
1784 rt2x00_desc_write(txd
, 1, word
);
1786 rt2x00_desc_read(txd
, 2, &word
);
1787 rt2x00_set_field32(&word
, TXD_W2_PLCP_SIGNAL
, txdesc
->signal
);
1788 rt2x00_set_field32(&word
, TXD_W2_PLCP_SERVICE
, txdesc
->service
);
1789 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_LOW
, txdesc
->length_low
);
1790 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_HIGH
, txdesc
->length_high
);
1791 rt2x00_desc_write(txd
, 2, word
);
1793 if (test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
)) {
1794 _rt2x00_desc_write(txd
, 3, skbdesc
->iv
[0]);
1795 _rt2x00_desc_write(txd
, 4, skbdesc
->iv
[1]);
1798 rt2x00_desc_read(txd
, 5, &word
);
1799 rt2x00_set_field32(&word
, TXD_W5_PID_TYPE
, skbdesc
->entry
->queue
->qid
);
1800 rt2x00_set_field32(&word
, TXD_W5_PID_SUBTYPE
,
1801 skbdesc
->entry
->entry_idx
);
1802 rt2x00_set_field32(&word
, TXD_W5_TX_POWER
,
1803 TXPOWER_TO_DEV(rt2x00dev
->tx_power
));
1804 rt2x00_set_field32(&word
, TXD_W5_WAITING_DMA_DONE_INT
, 1);
1805 rt2x00_desc_write(txd
, 5, word
);
1807 if (txdesc
->queue
!= QID_BEACON
) {
1808 rt2x00_desc_read(txd
, 6, &word
);
1809 rt2x00_set_field32(&word
, TXD_W6_BUFFER_PHYSICAL_ADDRESS
,
1811 rt2x00_desc_write(txd
, 6, word
);
1813 rt2x00_desc_read(txd
, 11, &word
);
1814 rt2x00_set_field32(&word
, TXD_W11_BUFFER_LENGTH0
,
1816 rt2x00_desc_write(txd
, 11, word
);
1820 * Writing TXD word 0 must the last to prevent a race condition with
1821 * the device, whereby the device may take hold of the TXD before we
1822 * finished updating it.
1824 rt2x00_desc_read(txd
, 0, &word
);
1825 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 1);
1826 rt2x00_set_field32(&word
, TXD_W0_VALID
, 1);
1827 rt2x00_set_field32(&word
, TXD_W0_MORE_FRAG
,
1828 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
1829 rt2x00_set_field32(&word
, TXD_W0_ACK
,
1830 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
1831 rt2x00_set_field32(&word
, TXD_W0_TIMESTAMP
,
1832 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
1833 rt2x00_set_field32(&word
, TXD_W0_OFDM
,
1834 (txdesc
->rate_mode
== RATE_MODE_OFDM
));
1835 rt2x00_set_field32(&word
, TXD_W0_IFS
, txdesc
->ifs
);
1836 rt2x00_set_field32(&word
, TXD_W0_RETRY_MODE
,
1837 test_bit(ENTRY_TXD_RETRY_MODE
, &txdesc
->flags
));
1838 rt2x00_set_field32(&word
, TXD_W0_TKIP_MIC
,
1839 test_bit(ENTRY_TXD_ENCRYPT_MMIC
, &txdesc
->flags
));
1840 rt2x00_set_field32(&word
, TXD_W0_KEY_TABLE
,
1841 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE
, &txdesc
->flags
));
1842 rt2x00_set_field32(&word
, TXD_W0_KEY_INDEX
, txdesc
->key_idx
);
1843 rt2x00_set_field32(&word
, TXD_W0_DATABYTE_COUNT
, txdesc
->length
);
1844 rt2x00_set_field32(&word
, TXD_W0_BURST
,
1845 test_bit(ENTRY_TXD_BURST
, &txdesc
->flags
));
1846 rt2x00_set_field32(&word
, TXD_W0_CIPHER_ALG
, txdesc
->cipher
);
1847 rt2x00_desc_write(txd
, 0, word
);
1850 * Register descriptor details in skb frame descriptor.
1852 skbdesc
->desc
= txd
;
1854 (txdesc
->queue
== QID_BEACON
) ? TXINFO_SIZE
: TXD_DESC_SIZE
;
1858 * TX data initialization
1860 static void rt61pci_write_beacon(struct queue_entry
*entry
,
1861 struct txentry_desc
*txdesc
)
1863 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1864 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1865 unsigned int beacon_base
;
1869 * Disable beaconing while we are reloading the beacon data,
1870 * otherwise we might be sending out invalid data.
1872 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1873 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1874 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1877 * Write the TX descriptor for the beacon.
1879 rt61pci_write_tx_desc(rt2x00dev
, entry
->skb
, txdesc
);
1882 * Dump beacon to userspace through debugfs.
1884 rt2x00debug_dump_frame(rt2x00dev
, DUMP_FRAME_BEACON
, entry
->skb
);
1887 * Write entire beacon with descriptor to register.
1889 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
1890 rt2x00pci_register_multiwrite(rt2x00dev
, beacon_base
,
1891 entry_priv
->desc
, TXINFO_SIZE
);
1892 rt2x00pci_register_multiwrite(rt2x00dev
, beacon_base
+ TXINFO_SIZE
,
1893 entry
->skb
->data
, entry
->skb
->len
);
1896 * Enable beaconing again.
1898 * For Wi-Fi faily generated beacons between participating
1899 * stations. Set TBTT phase adaptive adjustment step to 8us.
1901 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR10
, 0x00001008);
1903 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
1904 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
1905 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 1);
1906 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1909 * Clean up beacon skb.
1911 dev_kfree_skb_any(entry
->skb
);
1915 static void rt61pci_kick_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1916 const enum data_queue_qid queue
)
1920 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1921 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC0
, (queue
== QID_AC_BE
));
1922 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC1
, (queue
== QID_AC_BK
));
1923 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC2
, (queue
== QID_AC_VI
));
1924 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC3
, (queue
== QID_AC_VO
));
1925 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1928 static void rt61pci_kill_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1929 const enum data_queue_qid qid
)
1933 if (qid
== QID_BEACON
) {
1934 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, 0);
1938 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1939 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC0
, (qid
== QID_AC_BE
));
1940 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC1
, (qid
== QID_AC_BK
));
1941 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC2
, (qid
== QID_AC_VI
));
1942 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC3
, (qid
== QID_AC_VO
));
1943 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1947 * RX control handlers
1949 static int rt61pci_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, int rxd_w1
)
1951 u8 offset
= rt2x00dev
->lna_gain
;
1954 lna
= rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_LNA
);
1969 if (rt2x00dev
->rx_status
.band
== IEEE80211_BAND_5GHZ
) {
1970 if (lna
== 3 || lna
== 2)
1974 return rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_AGC
) * 2 - offset
;
1977 static void rt61pci_fill_rxdone(struct queue_entry
*entry
,
1978 struct rxdone_entry_desc
*rxdesc
)
1980 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1981 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1985 rt2x00_desc_read(entry_priv
->desc
, 0, &word0
);
1986 rt2x00_desc_read(entry_priv
->desc
, 1, &word1
);
1988 if (rt2x00_get_field32(word0
, RXD_W0_CRC_ERROR
))
1989 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
1991 rxdesc
->cipher
= rt2x00_get_field32(word0
, RXD_W0_CIPHER_ALG
);
1992 rxdesc
->cipher_status
= rt2x00_get_field32(word0
, RXD_W0_CIPHER_ERROR
);
1994 if (rxdesc
->cipher
!= CIPHER_NONE
) {
1995 _rt2x00_desc_read(entry_priv
->desc
, 2, &rxdesc
->iv
[0]);
1996 _rt2x00_desc_read(entry_priv
->desc
, 3, &rxdesc
->iv
[1]);
1997 rxdesc
->dev_flags
|= RXDONE_CRYPTO_IV
;
1999 _rt2x00_desc_read(entry_priv
->desc
, 4, &rxdesc
->icv
);
2000 rxdesc
->dev_flags
|= RXDONE_CRYPTO_ICV
;
2003 * Hardware has stripped IV/EIV data from 802.11 frame during
2004 * decryption. It has provided the data separately but rt2x00lib
2005 * should decide if it should be reinserted.
2007 rxdesc
->flags
|= RX_FLAG_IV_STRIPPED
;
2010 * FIXME: Legacy driver indicates that the frame does
2011 * contain the Michael Mic. Unfortunately, in rt2x00
2012 * the MIC seems to be missing completely...
2014 rxdesc
->flags
|= RX_FLAG_MMIC_STRIPPED
;
2016 if (rxdesc
->cipher_status
== RX_CRYPTO_SUCCESS
)
2017 rxdesc
->flags
|= RX_FLAG_DECRYPTED
;
2018 else if (rxdesc
->cipher_status
== RX_CRYPTO_FAIL_MIC
)
2019 rxdesc
->flags
|= RX_FLAG_MMIC_ERROR
;
2023 * Obtain the status about this packet.
2024 * When frame was received with an OFDM bitrate,
2025 * the signal is the PLCP value. If it was received with
2026 * a CCK bitrate the signal is the rate in 100kbit/s.
2028 rxdesc
->signal
= rt2x00_get_field32(word1
, RXD_W1_SIGNAL
);
2029 rxdesc
->rssi
= rt61pci_agc_to_rssi(rt2x00dev
, word1
);
2030 rxdesc
->size
= rt2x00_get_field32(word0
, RXD_W0_DATABYTE_COUNT
);
2032 if (rt2x00_get_field32(word0
, RXD_W0_OFDM
))
2033 rxdesc
->dev_flags
|= RXDONE_SIGNAL_PLCP
;
2035 rxdesc
->dev_flags
|= RXDONE_SIGNAL_BITRATE
;
2036 if (rt2x00_get_field32(word0
, RXD_W0_MY_BSS
))
2037 rxdesc
->dev_flags
|= RXDONE_MY_BSS
;
2041 * Interrupt functions.
2043 static void rt61pci_txdone(struct rt2x00_dev
*rt2x00dev
)
2045 struct data_queue
*queue
;
2046 struct queue_entry
*entry
;
2047 struct queue_entry
*entry_done
;
2048 struct queue_entry_priv_pci
*entry_priv
;
2049 struct txdone_entry_desc txdesc
;
2057 * During each loop we will compare the freshly read
2058 * STA_CSR4 register value with the value read from
2059 * the previous loop. If the 2 values are equal then
2060 * we should stop processing because the chance is
2061 * quite big that the device has been unplugged and
2062 * we risk going into an endless loop.
2067 rt2x00pci_register_read(rt2x00dev
, STA_CSR4
, ®
);
2068 if (!rt2x00_get_field32(reg
, STA_CSR4_VALID
))
2076 * Skip this entry when it contains an invalid
2077 * queue identication number.
2079 type
= rt2x00_get_field32(reg
, STA_CSR4_PID_TYPE
);
2080 queue
= rt2x00queue_get_queue(rt2x00dev
, type
);
2081 if (unlikely(!queue
))
2085 * Skip this entry when it contains an invalid
2088 index
= rt2x00_get_field32(reg
, STA_CSR4_PID_SUBTYPE
);
2089 if (unlikely(index
>= queue
->limit
))
2092 entry
= &queue
->entries
[index
];
2093 entry_priv
= entry
->priv_data
;
2094 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
2096 if (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
2097 !rt2x00_get_field32(word
, TXD_W0_VALID
))
2100 entry_done
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
2101 while (entry
!= entry_done
) {
2103 * Just report any entries we missed as failed.
2106 "TX status report missed for entry %d\n",
2107 entry_done
->entry_idx
);
2110 __set_bit(TXDONE_UNKNOWN
, &txdesc
.flags
);
2113 rt2x00lib_txdone(entry_done
, &txdesc
);
2114 entry_done
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
2118 * Obtain the status about this packet.
2121 switch (rt2x00_get_field32(reg
, STA_CSR4_TX_RESULT
)) {
2122 case 0: /* Success, maybe with retry */
2123 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
2125 case 6: /* Failure, excessive retries */
2126 __set_bit(TXDONE_EXCESSIVE_RETRY
, &txdesc
.flags
);
2127 /* Don't break, this is a failed frame! */
2128 default: /* Failure */
2129 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
2131 txdesc
.retry
= rt2x00_get_field32(reg
, STA_CSR4_RETRY_COUNT
);
2133 rt2x00lib_txdone(entry
, &txdesc
);
2137 static void rt61pci_wakeup(struct rt2x00_dev
*rt2x00dev
)
2139 struct ieee80211_conf conf
= { .flags
= 0 };
2140 struct rt2x00lib_conf libconf
= { .conf
= &conf
};
2142 rt61pci_config(rt2x00dev
, &libconf
, IEEE80211_CONF_CHANGE_PS
);
2145 static irqreturn_t
rt61pci_interrupt(int irq
, void *dev_instance
)
2147 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
2152 * Get the interrupt sources & saved to local variable.
2153 * Write register value back to clear pending interrupts.
2155 rt2x00pci_register_read(rt2x00dev
, MCU_INT_SOURCE_CSR
, ®_mcu
);
2156 rt2x00pci_register_write(rt2x00dev
, MCU_INT_SOURCE_CSR
, reg_mcu
);
2158 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
2159 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
2161 if (!reg
&& !reg_mcu
)
2164 if (!test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
2168 * Handle interrupts, walk through all bits
2169 * and run the tasks, the bits are checked in order of
2174 * 1 - Rx ring done interrupt.
2176 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_RXDONE
))
2177 rt2x00pci_rxdone(rt2x00dev
);
2180 * 2 - Tx ring done interrupt.
2182 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_TXDONE
))
2183 rt61pci_txdone(rt2x00dev
);
2186 * 3 - Handle MCU command done.
2189 rt2x00pci_register_write(rt2x00dev
,
2190 M2H_CMD_DONE_CSR
, 0xffffffff);
2193 * 4 - MCU Autowakeup interrupt.
2195 if (rt2x00_get_field32(reg_mcu
, MCU_INT_SOURCE_CSR_TWAKEUP
))
2196 rt61pci_wakeup(rt2x00dev
);
2202 * Device probe functions.
2204 static int rt61pci_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
2206 struct eeprom_93cx6 eeprom
;
2212 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
2214 eeprom
.data
= rt2x00dev
;
2215 eeprom
.register_read
= rt61pci_eepromregister_read
;
2216 eeprom
.register_write
= rt61pci_eepromregister_write
;
2217 eeprom
.width
= rt2x00_get_field32(reg
, E2PROM_CSR_TYPE_93C46
) ?
2218 PCI_EEPROM_WIDTH_93C46
: PCI_EEPROM_WIDTH_93C66
;
2219 eeprom
.reg_data_in
= 0;
2220 eeprom
.reg_data_out
= 0;
2221 eeprom
.reg_data_clock
= 0;
2222 eeprom
.reg_chip_select
= 0;
2224 eeprom_93cx6_multiread(&eeprom
, EEPROM_BASE
, rt2x00dev
->eeprom
,
2225 EEPROM_SIZE
/ sizeof(u16
));
2228 * Start validation of the data that has been read.
2230 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
2231 if (!is_valid_ether_addr(mac
)) {
2232 random_ether_addr(mac
);
2233 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
2236 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
2237 if (word
== 0xffff) {
2238 rt2x00_set_field16(&word
, EEPROM_ANTENNA_NUM
, 2);
2239 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TX_DEFAULT
,
2241 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RX_DEFAULT
,
2243 rt2x00_set_field16(&word
, EEPROM_ANTENNA_FRAME_TYPE
, 0);
2244 rt2x00_set_field16(&word
, EEPROM_ANTENNA_DYN_TXAGC
, 0);
2245 rt2x00_set_field16(&word
, EEPROM_ANTENNA_HARDWARE_RADIO
, 0);
2246 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF5225
);
2247 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
2248 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
2251 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
2252 if (word
== 0xffff) {
2253 rt2x00_set_field16(&word
, EEPROM_NIC_ENABLE_DIVERSITY
, 0);
2254 rt2x00_set_field16(&word
, EEPROM_NIC_TX_DIVERSITY
, 0);
2255 rt2x00_set_field16(&word
, EEPROM_NIC_RX_FIXED
, 0);
2256 rt2x00_set_field16(&word
, EEPROM_NIC_TX_FIXED
, 0);
2257 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_BG
, 0);
2258 rt2x00_set_field16(&word
, EEPROM_NIC_CARDBUS_ACCEL
, 0);
2259 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_A
, 0);
2260 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
2261 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
2264 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &word
);
2265 if (word
== 0xffff) {
2266 rt2x00_set_field16(&word
, EEPROM_LED_LED_MODE
,
2268 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED
, word
);
2269 EEPROM(rt2x00dev
, "Led: 0x%04x\n", word
);
2272 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
2273 if (word
== 0xffff) {
2274 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
2275 rt2x00_set_field16(&word
, EEPROM_FREQ_SEQ
, 0);
2276 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
2277 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
2280 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &word
);
2281 if (word
== 0xffff) {
2282 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
2283 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
2284 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
2285 EEPROM(rt2x00dev
, "RSSI OFFSET BG: 0x%04x\n", word
);
2287 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_1
);
2288 if (value
< -10 || value
> 10)
2289 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
2290 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_2
);
2291 if (value
< -10 || value
> 10)
2292 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
2293 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
2296 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &word
);
2297 if (word
== 0xffff) {
2298 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
2299 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
2300 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
2301 EEPROM(rt2x00dev
, "RSSI OFFSET A: 0x%04x\n", word
);
2303 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_1
);
2304 if (value
< -10 || value
> 10)
2305 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
2306 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_2
);
2307 if (value
< -10 || value
> 10)
2308 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
2309 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
2315 static int rt61pci_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
2322 * Read EEPROM word for configuration.
2324 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2327 * Identify RF chipset.
2329 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
2330 rt2x00pci_register_read(rt2x00dev
, MAC_CSR0
, ®
);
2331 rt2x00_set_chip(rt2x00dev
, rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
),
2332 value
, rt2x00_get_field32(reg
, MAC_CSR0_REVISION
));
2334 if (!rt2x00_rf(rt2x00dev
, RF5225
) &&
2335 !rt2x00_rf(rt2x00dev
, RF5325
) &&
2336 !rt2x00_rf(rt2x00dev
, RF2527
) &&
2337 !rt2x00_rf(rt2x00dev
, RF2529
)) {
2338 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
2343 * Determine number of antennas.
2345 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_NUM
) == 2)
2346 __set_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
);
2349 * Identify default antenna configuration.
2351 rt2x00dev
->default_ant
.tx
=
2352 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TX_DEFAULT
);
2353 rt2x00dev
->default_ant
.rx
=
2354 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_DEFAULT
);
2357 * Read the Frame type.
2359 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_FRAME_TYPE
))
2360 __set_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
);
2363 * Detect if this device has a hardware controlled radio.
2365 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_HARDWARE_RADIO
))
2366 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
2369 * Read frequency offset and RF programming sequence.
2371 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
2372 if (rt2x00_get_field16(eeprom
, EEPROM_FREQ_SEQ
))
2373 __set_bit(CONFIG_RF_SEQUENCE
, &rt2x00dev
->flags
);
2375 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
2378 * Read external LNA informations.
2380 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
2382 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_A
))
2383 __set_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
2384 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_BG
))
2385 __set_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
2388 * When working with a RF2529 chip without double antenna,
2389 * the antenna settings should be gathered from the NIC
2392 if (rt2x00_rf(rt2x00dev
, RF2529
) &&
2393 !test_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
)) {
2394 rt2x00dev
->default_ant
.rx
=
2395 ANTENNA_A
+ rt2x00_get_field16(eeprom
, EEPROM_NIC_RX_FIXED
);
2396 rt2x00dev
->default_ant
.tx
=
2397 ANTENNA_B
- rt2x00_get_field16(eeprom
, EEPROM_NIC_TX_FIXED
);
2399 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_TX_DIVERSITY
))
2400 rt2x00dev
->default_ant
.tx
= ANTENNA_SW_DIVERSITY
;
2401 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_ENABLE_DIVERSITY
))
2402 rt2x00dev
->default_ant
.rx
= ANTENNA_SW_DIVERSITY
;
2406 * Store led settings, for correct led behaviour.
2407 * If the eeprom value is invalid,
2408 * switch to default led mode.
2410 #ifdef CONFIG_RT2X00_LIB_LEDS
2411 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &eeprom
);
2412 value
= rt2x00_get_field16(eeprom
, EEPROM_LED_LED_MODE
);
2414 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
2415 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
2416 if (value
== LED_MODE_SIGNAL_STRENGTH
)
2417 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_qual
,
2420 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_LED_MODE
, value
);
2421 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_0
,
2422 rt2x00_get_field16(eeprom
,
2423 EEPROM_LED_POLARITY_GPIO_0
));
2424 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_1
,
2425 rt2x00_get_field16(eeprom
,
2426 EEPROM_LED_POLARITY_GPIO_1
));
2427 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_2
,
2428 rt2x00_get_field16(eeprom
,
2429 EEPROM_LED_POLARITY_GPIO_2
));
2430 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_3
,
2431 rt2x00_get_field16(eeprom
,
2432 EEPROM_LED_POLARITY_GPIO_3
));
2433 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_4
,
2434 rt2x00_get_field16(eeprom
,
2435 EEPROM_LED_POLARITY_GPIO_4
));
2436 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_ACT
,
2437 rt2x00_get_field16(eeprom
, EEPROM_LED_POLARITY_ACT
));
2438 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_BG
,
2439 rt2x00_get_field16(eeprom
,
2440 EEPROM_LED_POLARITY_RDY_G
));
2441 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_A
,
2442 rt2x00_get_field16(eeprom
,
2443 EEPROM_LED_POLARITY_RDY_A
));
2444 #endif /* CONFIG_RT2X00_LIB_LEDS */
2450 * RF value list for RF5225 & RF5325
2451 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2453 static const struct rf_channel rf_vals_noseq
[] = {
2454 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2455 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2456 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2457 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2458 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2459 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2460 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2461 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2462 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2463 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2464 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2465 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2466 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2467 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2469 /* 802.11 UNI / HyperLan 2 */
2470 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2471 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2472 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2473 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2474 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2475 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2476 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2477 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2479 /* 802.11 HyperLan 2 */
2480 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2481 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2482 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2483 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2484 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2485 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2486 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2487 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2488 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2489 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2492 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2493 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2494 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2495 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2496 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2497 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2499 /* MMAC(Japan)J52 ch 34,38,42,46 */
2500 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2501 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2502 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2503 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2507 * RF value list for RF5225 & RF5325
2508 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2510 static const struct rf_channel rf_vals_seq
[] = {
2511 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2512 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2513 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2514 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2515 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2516 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2517 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2518 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2519 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2520 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2521 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2522 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2523 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2524 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2526 /* 802.11 UNI / HyperLan 2 */
2527 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2528 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2529 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2530 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2531 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2532 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2533 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2534 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2536 /* 802.11 HyperLan 2 */
2537 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2538 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2539 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2540 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2541 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2542 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2543 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2544 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2545 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2546 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2549 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2550 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2551 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2552 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2553 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2554 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2556 /* MMAC(Japan)J52 ch 34,38,42,46 */
2557 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2558 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2559 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2560 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2563 static int rt61pci_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
2565 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
2566 struct channel_info
*info
;
2571 * Disable powersaving as default.
2573 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
2576 * Initialize all hw fields.
2578 rt2x00dev
->hw
->flags
=
2579 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
2580 IEEE80211_HW_SIGNAL_DBM
|
2581 IEEE80211_HW_SUPPORTS_PS
|
2582 IEEE80211_HW_PS_NULLFUNC_STACK
;
2584 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
2585 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
2586 rt2x00_eeprom_addr(rt2x00dev
,
2587 EEPROM_MAC_ADDR_0
));
2590 * Initialize hw_mode information.
2592 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
2593 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
2595 if (!test_bit(CONFIG_RF_SEQUENCE
, &rt2x00dev
->flags
)) {
2596 spec
->num_channels
= 14;
2597 spec
->channels
= rf_vals_noseq
;
2599 spec
->num_channels
= 14;
2600 spec
->channels
= rf_vals_seq
;
2603 if (rt2x00_rf(rt2x00dev
, RF5225
) || rt2x00_rf(rt2x00dev
, RF5325
)) {
2604 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
2605 spec
->num_channels
= ARRAY_SIZE(rf_vals_seq
);
2609 * Create channel information array
2611 info
= kzalloc(spec
->num_channels
* sizeof(*info
), GFP_KERNEL
);
2615 spec
->channels_info
= info
;
2617 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_G_START
);
2618 for (i
= 0; i
< 14; i
++)
2619 info
[i
].tx_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
2621 if (spec
->num_channels
> 14) {
2622 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A_START
);
2623 for (i
= 14; i
< spec
->num_channels
; i
++)
2624 info
[i
].tx_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
2630 static int rt61pci_probe_hw(struct rt2x00_dev
*rt2x00dev
)
2635 * Disable power saving.
2637 rt2x00pci_register_write(rt2x00dev
, SOFT_RESET_CSR
, 0x00000007);
2640 * Allocate eeprom data.
2642 retval
= rt61pci_validate_eeprom(rt2x00dev
);
2646 retval
= rt61pci_init_eeprom(rt2x00dev
);
2651 * Initialize hw specifications.
2653 retval
= rt61pci_probe_hw_mode(rt2x00dev
);
2658 * This device has multiple filters for control frames,
2659 * but has no a separate filter for PS Poll frames.
2661 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS
, &rt2x00dev
->flags
);
2664 * This device requires firmware and DMA mapped skbs.
2666 __set_bit(DRIVER_REQUIRE_FIRMWARE
, &rt2x00dev
->flags
);
2667 __set_bit(DRIVER_REQUIRE_DMA
, &rt2x00dev
->flags
);
2668 if (!modparam_nohwcrypt
)
2669 __set_bit(CONFIG_SUPPORT_HW_CRYPTO
, &rt2x00dev
->flags
);
2672 * Set the rssi offset.
2674 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
2680 * IEEE80211 stack callback functions.
2682 static int rt61pci_conf_tx(struct ieee80211_hw
*hw
, u16 queue_idx
,
2683 const struct ieee80211_tx_queue_params
*params
)
2685 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2686 struct data_queue
*queue
;
2687 struct rt2x00_field32 field
;
2693 * First pass the configuration through rt2x00lib, that will
2694 * update the queue settings and validate the input. After that
2695 * we are free to update the registers based on the value
2696 * in the queue parameter.
2698 retval
= rt2x00mac_conf_tx(hw
, queue_idx
, params
);
2703 * We only need to perform additional register initialization
2709 queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
2711 /* Update WMM TXOP register */
2712 offset
= AC_TXOP_CSR0
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
2713 field
.bit_offset
= (queue_idx
& 1) * 16;
2714 field
.bit_mask
= 0xffff << field
.bit_offset
;
2716 rt2x00pci_register_read(rt2x00dev
, offset
, ®
);
2717 rt2x00_set_field32(®
, field
, queue
->txop
);
2718 rt2x00pci_register_write(rt2x00dev
, offset
, reg
);
2720 /* Update WMM registers */
2721 field
.bit_offset
= queue_idx
* 4;
2722 field
.bit_mask
= 0xf << field
.bit_offset
;
2724 rt2x00pci_register_read(rt2x00dev
, AIFSN_CSR
, ®
);
2725 rt2x00_set_field32(®
, field
, queue
->aifs
);
2726 rt2x00pci_register_write(rt2x00dev
, AIFSN_CSR
, reg
);
2728 rt2x00pci_register_read(rt2x00dev
, CWMIN_CSR
, ®
);
2729 rt2x00_set_field32(®
, field
, queue
->cw_min
);
2730 rt2x00pci_register_write(rt2x00dev
, CWMIN_CSR
, reg
);
2732 rt2x00pci_register_read(rt2x00dev
, CWMAX_CSR
, ®
);
2733 rt2x00_set_field32(®
, field
, queue
->cw_max
);
2734 rt2x00pci_register_write(rt2x00dev
, CWMAX_CSR
, reg
);
2739 static u64
rt61pci_get_tsf(struct ieee80211_hw
*hw
)
2741 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2745 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR13
, ®
);
2746 tsf
= (u64
) rt2x00_get_field32(reg
, TXRX_CSR13_HIGH_TSFTIMER
) << 32;
2747 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR12
, ®
);
2748 tsf
|= rt2x00_get_field32(reg
, TXRX_CSR12_LOW_TSFTIMER
);
2753 static const struct ieee80211_ops rt61pci_mac80211_ops
= {
2755 .start
= rt2x00mac_start
,
2756 .stop
= rt2x00mac_stop
,
2757 .add_interface
= rt2x00mac_add_interface
,
2758 .remove_interface
= rt2x00mac_remove_interface
,
2759 .config
= rt2x00mac_config
,
2760 .configure_filter
= rt2x00mac_configure_filter
,
2761 .set_tim
= rt2x00mac_set_tim
,
2762 .set_key
= rt2x00mac_set_key
,
2763 .get_stats
= rt2x00mac_get_stats
,
2764 .bss_info_changed
= rt2x00mac_bss_info_changed
,
2765 .conf_tx
= rt61pci_conf_tx
,
2766 .get_tsf
= rt61pci_get_tsf
,
2767 .rfkill_poll
= rt2x00mac_rfkill_poll
,
2770 static const struct rt2x00lib_ops rt61pci_rt2x00_ops
= {
2771 .irq_handler
= rt61pci_interrupt
,
2772 .probe_hw
= rt61pci_probe_hw
,
2773 .get_firmware_name
= rt61pci_get_firmware_name
,
2774 .check_firmware
= rt61pci_check_firmware
,
2775 .load_firmware
= rt61pci_load_firmware
,
2776 .initialize
= rt2x00pci_initialize
,
2777 .uninitialize
= rt2x00pci_uninitialize
,
2778 .get_entry_state
= rt61pci_get_entry_state
,
2779 .clear_entry
= rt61pci_clear_entry
,
2780 .set_device_state
= rt61pci_set_device_state
,
2781 .rfkill_poll
= rt61pci_rfkill_poll
,
2782 .link_stats
= rt61pci_link_stats
,
2783 .reset_tuner
= rt61pci_reset_tuner
,
2784 .link_tuner
= rt61pci_link_tuner
,
2785 .write_tx_desc
= rt61pci_write_tx_desc
,
2786 .write_tx_data
= rt2x00pci_write_tx_data
,
2787 .write_beacon
= rt61pci_write_beacon
,
2788 .kick_tx_queue
= rt61pci_kick_tx_queue
,
2789 .kill_tx_queue
= rt61pci_kill_tx_queue
,
2790 .fill_rxdone
= rt61pci_fill_rxdone
,
2791 .config_shared_key
= rt61pci_config_shared_key
,
2792 .config_pairwise_key
= rt61pci_config_pairwise_key
,
2793 .config_filter
= rt61pci_config_filter
,
2794 .config_intf
= rt61pci_config_intf
,
2795 .config_erp
= rt61pci_config_erp
,
2796 .config_ant
= rt61pci_config_ant
,
2797 .config
= rt61pci_config
,
2800 static const struct data_queue_desc rt61pci_queue_rx
= {
2801 .entry_num
= RX_ENTRIES
,
2802 .data_size
= DATA_FRAME_SIZE
,
2803 .desc_size
= RXD_DESC_SIZE
,
2804 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2807 static const struct data_queue_desc rt61pci_queue_tx
= {
2808 .entry_num
= TX_ENTRIES
,
2809 .data_size
= DATA_FRAME_SIZE
,
2810 .desc_size
= TXD_DESC_SIZE
,
2811 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2814 static const struct data_queue_desc rt61pci_queue_bcn
= {
2815 .entry_num
= 4 * BEACON_ENTRIES
,
2816 .data_size
= 0, /* No DMA required for beacons */
2817 .desc_size
= TXINFO_SIZE
,
2818 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2821 static const struct rt2x00_ops rt61pci_ops
= {
2822 .name
= KBUILD_MODNAME
,
2825 .eeprom_size
= EEPROM_SIZE
,
2827 .tx_queues
= NUM_TX_QUEUES
,
2828 .extra_tx_headroom
= 0,
2829 .rx
= &rt61pci_queue_rx
,
2830 .tx
= &rt61pci_queue_tx
,
2831 .bcn
= &rt61pci_queue_bcn
,
2832 .lib
= &rt61pci_rt2x00_ops
,
2833 .hw
= &rt61pci_mac80211_ops
,
2834 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2835 .debugfs
= &rt61pci_rt2x00debug
,
2836 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2840 * RT61pci module information.
2842 static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table
) = {
2844 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops
) },
2846 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops
) },
2848 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops
) },
2852 MODULE_AUTHOR(DRV_PROJECT
);
2853 MODULE_VERSION(DRV_VERSION
);
2854 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2855 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2856 "PCI & PCMCIA chipset based cards");
2857 MODULE_DEVICE_TABLE(pci
, rt61pci_device_table
);
2858 MODULE_FIRMWARE(FIRMWARE_RT2561
);
2859 MODULE_FIRMWARE(FIRMWARE_RT2561s
);
2860 MODULE_FIRMWARE(FIRMWARE_RT2661
);
2861 MODULE_LICENSE("GPL");
2863 static struct pci_driver rt61pci_driver
= {
2864 .name
= KBUILD_MODNAME
,
2865 .id_table
= rt61pci_device_table
,
2866 .probe
= rt2x00pci_probe
,
2867 .remove
= __devexit_p(rt2x00pci_remove
),
2868 .suspend
= rt2x00pci_suspend
,
2869 .resume
= rt2x00pci_resume
,
2872 static int __init
rt61pci_init(void)
2874 return pci_register_driver(&rt61pci_driver
);
2877 static void __exit
rt61pci_exit(void)
2879 pci_unregister_driver(&rt61pci_driver
);
2882 module_init(rt61pci_init
);
2883 module_exit(rt61pci_exit
);