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rt2x00: Push beacon TX descriptor writing to drivers.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
blob1582cabd3a1ea6d6c9159e621de7baebcc9ee168
1 /*
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34 #include <linux/slab.h>
35
36 #include "rt2x00.h"
37 #include "rt2x00pci.h"
38 #include "rt2500pci.h"
39
40 /*
41 * Register access.
42 * All access to the CSR registers will go through the methods
43 * rt2x00pci_register_read and rt2x00pci_register_write.
44 * BBP and RF register require indirect register access,
45 * and use the CSR registers BBPCSR and RFCSR to achieve this.
46 * These indirect registers work with busy bits,
47 * and we will try maximal REGISTER_BUSY_COUNT times to access
48 * the register while taking a REGISTER_BUSY_DELAY us delay
49 * between each attampt. When the busy bit is still set at that time,
50 * the access attempt is considered to have failed,
51 * and we will print an error.
52 */
53 #define WAIT_FOR_BBP(__dev, __reg) \
54 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
55 #define WAIT_FOR_RF(__dev, __reg) \
56 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
57
58 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
59 const unsigned int word, const u8 value)
60 {
61 u32 reg;
62
63 mutex_lock(&rt2x00dev->csr_mutex);
64
65 /*
66 * Wait until the BBP becomes available, afterwards we
67 * can safely write the new data into the register.
68 */
69 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
70 reg = 0;
71 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
72 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
73 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
74 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
75
76 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
77 }
78
79 mutex_unlock(&rt2x00dev->csr_mutex);
80 }
81
82 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
83 const unsigned int word, u8 *value)
84 {
85 u32 reg;
86
87 mutex_lock(&rt2x00dev->csr_mutex);
88
89 /*
90 * Wait until the BBP becomes available, afterwards we
91 * can safely write the read request into the register.
92 * After the data has been written, we wait until hardware
93 * returns the correct value, if at any time the register
94 * doesn't become available in time, reg will be 0xffffffff
95 * which means we return 0xff to the caller.
96 */
97 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
98 reg = 0;
99 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
100 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
101 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
102
103 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
104
105 WAIT_FOR_BBP(rt2x00dev, &reg);
106 }
107
108 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
109
110 mutex_unlock(&rt2x00dev->csr_mutex);
111 }
112
113 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
114 const unsigned int word, const u32 value)
115 {
116 u32 reg;
117
118 mutex_lock(&rt2x00dev->csr_mutex);
119
120 /*
121 * Wait until the RF becomes available, afterwards we
122 * can safely write the new data into the register.
123 */
124 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
125 reg = 0;
126 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
127 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
128 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
129 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
130
131 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
132 rt2x00_rf_write(rt2x00dev, word, value);
133 }
134
135 mutex_unlock(&rt2x00dev->csr_mutex);
136 }
137
138 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
139 {
140 struct rt2x00_dev *rt2x00dev = eeprom->data;
141 u32 reg;
142
143 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
144
145 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
146 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
147 eeprom->reg_data_clock =
148 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
149 eeprom->reg_chip_select =
150 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
151 }
152
153 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
154 {
155 struct rt2x00_dev *rt2x00dev = eeprom->data;
156 u32 reg = 0;
157
158 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
159 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
160 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
161 !!eeprom->reg_data_clock);
162 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
163 !!eeprom->reg_chip_select);
164
165 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
166 }
167
168 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
169 static const struct rt2x00debug rt2500pci_rt2x00debug = {
170 .owner = THIS_MODULE,
171 .csr = {
172 .read = rt2x00pci_register_read,
173 .write = rt2x00pci_register_write,
174 .flags = RT2X00DEBUGFS_OFFSET,
175 .word_base = CSR_REG_BASE,
176 .word_size = sizeof(u32),
177 .word_count = CSR_REG_SIZE / sizeof(u32),
178 },
179 .eeprom = {
180 .read = rt2x00_eeprom_read,
181 .write = rt2x00_eeprom_write,
182 .word_base = EEPROM_BASE,
183 .word_size = sizeof(u16),
184 .word_count = EEPROM_SIZE / sizeof(u16),
185 },
186 .bbp = {
187 .read = rt2500pci_bbp_read,
188 .write = rt2500pci_bbp_write,
189 .word_base = BBP_BASE,
190 .word_size = sizeof(u8),
191 .word_count = BBP_SIZE / sizeof(u8),
192 },
193 .rf = {
194 .read = rt2x00_rf_read,
195 .write = rt2500pci_rf_write,
196 .word_base = RF_BASE,
197 .word_size = sizeof(u32),
198 .word_count = RF_SIZE / sizeof(u32),
199 },
200 };
201 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
202
203 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
204 {
205 u32 reg;
206
207 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
208 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
209 }
210
211 #ifdef CONFIG_RT2X00_LIB_LEDS
212 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
213 enum led_brightness brightness)
214 {
215 struct rt2x00_led *led =
216 container_of(led_cdev, struct rt2x00_led, led_dev);
217 unsigned int enabled = brightness != LED_OFF;
218 u32 reg;
219
220 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
221
222 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
223 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
224 else if (led->type == LED_TYPE_ACTIVITY)
225 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
226
227 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
228 }
229
230 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
231 unsigned long *delay_on,
232 unsigned long *delay_off)
233 {
234 struct rt2x00_led *led =
235 container_of(led_cdev, struct rt2x00_led, led_dev);
236 u32 reg;
237
238 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
239 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
240 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
241 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
242
243 return 0;
244 }
245
246 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
247 struct rt2x00_led *led,
248 enum led_type type)
249 {
250 led->rt2x00dev = rt2x00dev;
251 led->type = type;
252 led->led_dev.brightness_set = rt2500pci_brightness_set;
253 led->led_dev.blink_set = rt2500pci_blink_set;
254 led->flags = LED_INITIALIZED;
255 }
256 #endif /* CONFIG_RT2X00_LIB_LEDS */
257
258 /*
259 * Configuration handlers.
260 */
261 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
262 const unsigned int filter_flags)
263 {
264 u32 reg;
265
266 /*
267 * Start configuration steps.
268 * Note that the version error will always be dropped
269 * and broadcast frames will always be accepted since
270 * there is no filter for it at this time.
271 */
272 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
273 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
274 !(filter_flags & FIF_FCSFAIL));
275 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
276 !(filter_flags & FIF_PLCPFAIL));
277 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
278 !(filter_flags & FIF_CONTROL));
279 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
280 !(filter_flags & FIF_PROMISC_IN_BSS));
281 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
282 !(filter_flags & FIF_PROMISC_IN_BSS) &&
283 !rt2x00dev->intf_ap_count);
284 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
285 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
286 !(filter_flags & FIF_ALLMULTI));
287 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
288 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
289 }
290
291 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
292 struct rt2x00_intf *intf,
293 struct rt2x00intf_conf *conf,
294 const unsigned int flags)
295 {
296 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
297 unsigned int bcn_preload;
298 u32 reg;
299
300 if (flags & CONFIG_UPDATE_TYPE) {
301 /*
302 * Enable beacon config
303 */
304 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
305 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
306 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
307 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
308 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
309
310 /*
311 * Enable synchronisation.
312 */
313 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
314 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
315 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
316 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
317 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
318 }
319
320 if (flags & CONFIG_UPDATE_MAC)
321 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
322 conf->mac, sizeof(conf->mac));
323
324 if (flags & CONFIG_UPDATE_BSSID)
325 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
326 conf->bssid, sizeof(conf->bssid));
327 }
328
329 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
330 struct rt2x00lib_erp *erp)
331 {
332 int preamble_mask;
333 u32 reg;
334
335 /*
336 * When short preamble is enabled, we should set bit 0x08
337 */
338 preamble_mask = erp->short_preamble << 3;
339
340 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
341 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162);
342 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2);
343 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
344 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
345 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
346
347 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
348 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
349 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
350 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
351 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
352
353 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
354 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
355 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
356 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
357 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
358
359 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
360 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
361 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
362 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
363 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
364
365 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
366 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
367 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
368 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
369 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
370
371 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
372
373 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
374 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
375 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
376
377 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
378 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
379 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
380 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
381
382 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
383 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
384 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
385 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
386
387 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
388 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
389 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
390 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
391 }
392
393 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
394 struct antenna_setup *ant)
395 {
396 u32 reg;
397 u8 r14;
398 u8 r2;
399
400 /*
401 * We should never come here because rt2x00lib is supposed
402 * to catch this and send us the correct antenna explicitely.
403 */
404 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
405 ant->tx == ANTENNA_SW_DIVERSITY);
406
407 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
408 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
409 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
410
411 /*
412 * Configure the TX antenna.
413 */
414 switch (ant->tx) {
415 case ANTENNA_A:
416 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
417 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
418 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
419 break;
420 case ANTENNA_B:
421 default:
422 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
423 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
424 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
425 break;
426 }
427
428 /*
429 * Configure the RX antenna.
430 */
431 switch (ant->rx) {
432 case ANTENNA_A:
433 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
434 break;
435 case ANTENNA_B:
436 default:
437 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
438 break;
439 }
440
441 /*
442 * RT2525E and RT5222 need to flip TX I/Q
443 */
444 if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
445 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
446 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
447 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
448
449 /*
450 * RT2525E does not need RX I/Q Flip.
451 */
452 if (rt2x00_rf(rt2x00dev, RF2525E))
453 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
454 } else {
455 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
456 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
457 }
458
459 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
460 rt2500pci_bbp_write(rt2x00dev, 14, r14);
461 rt2500pci_bbp_write(rt2x00dev, 2, r2);
462 }
463
464 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
465 struct rf_channel *rf, const int txpower)
466 {
467 u8 r70;
468
469 /*
470 * Set TXpower.
471 */
472 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
473
474 /*
475 * Switch on tuning bits.
476 * For RT2523 devices we do not need to update the R1 register.
477 */
478 if (!rt2x00_rf(rt2x00dev, RF2523))
479 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
480 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
481
482 /*
483 * For RT2525 we should first set the channel to half band higher.
484 */
485 if (rt2x00_rf(rt2x00dev, RF2525)) {
486 static const u32 vals[] = {
487 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
488 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
489 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
490 0x00080d2e, 0x00080d3a
491 };
492
493 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
494 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
495 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
496 if (rf->rf4)
497 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
498 }
499
500 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
501 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
502 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
503 if (rf->rf4)
504 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
505
506 /*
507 * Channel 14 requires the Japan filter bit to be set.
508 */
509 r70 = 0x46;
510 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
511 rt2500pci_bbp_write(rt2x00dev, 70, r70);
512
513 msleep(1);
514
515 /*
516 * Switch off tuning bits.
517 * For RT2523 devices we do not need to update the R1 register.
518 */
519 if (!rt2x00_rf(rt2x00dev, RF2523)) {
520 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
521 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
522 }
523
524 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
525 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
526
527 /*
528 * Clear false CRC during channel switch.
529 */
530 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
531 }
532
533 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
534 const int txpower)
535 {
536 u32 rf3;
537
538 rt2x00_rf_read(rt2x00dev, 3, &rf3);
539 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
540 rt2500pci_rf_write(rt2x00dev, 3, rf3);
541 }
542
543 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
544 struct rt2x00lib_conf *libconf)
545 {
546 u32 reg;
547
548 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
549 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
550 libconf->conf->long_frame_max_tx_count);
551 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
552 libconf->conf->short_frame_max_tx_count);
553 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
554 }
555
556 static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
557 struct rt2x00lib_conf *libconf)
558 {
559 enum dev_state state =
560 (libconf->conf->flags & IEEE80211_CONF_PS) ?
561 STATE_SLEEP : STATE_AWAKE;
562 u32 reg;
563
564 if (state == STATE_SLEEP) {
565 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
566 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
567 (rt2x00dev->beacon_int - 20) * 16);
568 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
569 libconf->conf->listen_interval - 1);
570
571 /* We must first disable autowake before it can be enabled */
572 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
573 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
574
575 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
576 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
577 } else {
578 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
579 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
580 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
581 }
582
583 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
584 }
585
586 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
587 struct rt2x00lib_conf *libconf,
588 const unsigned int flags)
589 {
590 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
591 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
592 libconf->conf->power_level);
593 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
594 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
595 rt2500pci_config_txpower(rt2x00dev,
596 libconf->conf->power_level);
597 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
598 rt2500pci_config_retry_limit(rt2x00dev, libconf);
599 if (flags & IEEE80211_CONF_CHANGE_PS)
600 rt2500pci_config_ps(rt2x00dev, libconf);
601 }
602
603 /*
604 * Link tuning
605 */
606 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
607 struct link_qual *qual)
608 {
609 u32 reg;
610
611 /*
612 * Update FCS error count from register.
613 */
614 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
615 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
616
617 /*
618 * Update False CCA count from register.
619 */
620 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
621 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
622 }
623
624 static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
625 struct link_qual *qual, u8 vgc_level)
626 {
627 if (qual->vgc_level_reg != vgc_level) {
628 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
629 qual->vgc_level_reg = vgc_level;
630 }
631 }
632
633 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
634 struct link_qual *qual)
635 {
636 rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
637 }
638
639 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
640 struct link_qual *qual, const u32 count)
641 {
642 /*
643 * To prevent collisions with MAC ASIC on chipsets
644 * up to version C the link tuning should halt after 20
645 * seconds while being associated.
646 */
647 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D &&
648 rt2x00dev->intf_associated && count > 20)
649 return;
650
651 /*
652 * Chipset versions C and lower should directly continue
653 * to the dynamic CCA tuning. Chipset version D and higher
654 * should go straight to dynamic CCA tuning when they
655 * are not associated.
656 */
657 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D ||
658 !rt2x00dev->intf_associated)
659 goto dynamic_cca_tune;
660
661 /*
662 * A too low RSSI will cause too much false CCA which will
663 * then corrupt the R17 tuning. To remidy this the tuning should
664 * be stopped (While making sure the R17 value will not exceed limits)
665 */
666 if (qual->rssi < -80 && count > 20) {
667 if (qual->vgc_level_reg >= 0x41)
668 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
669 return;
670 }
671
672 /*
673 * Special big-R17 for short distance
674 */
675 if (qual->rssi >= -58) {
676 rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
677 return;
678 }
679
680 /*
681 * Special mid-R17 for middle distance
682 */
683 if (qual->rssi >= -74) {
684 rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
685 return;
686 }
687
688 /*
689 * Leave short or middle distance condition, restore r17
690 * to the dynamic tuning range.
691 */
692 if (qual->vgc_level_reg >= 0x41) {
693 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
694 return;
695 }
696
697 dynamic_cca_tune:
698
699 /*
700 * R17 is inside the dynamic tuning range,
701 * start tuning the link based on the false cca counter.
702 */
703 if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40) {
704 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
705 qual->vgc_level = qual->vgc_level_reg;
706 } else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32) {
707 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
708 qual->vgc_level = qual->vgc_level_reg;
709 }
710 }
711
712 /*
713 * Initialization functions.
714 */
715 static bool rt2500pci_get_entry_state(struct queue_entry *entry)
716 {
717 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
718 u32 word;
719
720 if (entry->queue->qid == QID_RX) {
721 rt2x00_desc_read(entry_priv->desc, 0, &word);
722
723 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
724 } else {
725 rt2x00_desc_read(entry_priv->desc, 0, &word);
726
727 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
728 rt2x00_get_field32(word, TXD_W0_VALID));
729 }
730 }
731
732 static void rt2500pci_clear_entry(struct queue_entry *entry)
733 {
734 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
735 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
736 u32 word;
737
738 if (entry->queue->qid == QID_RX) {
739 rt2x00_desc_read(entry_priv->desc, 1, &word);
740 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
741 rt2x00_desc_write(entry_priv->desc, 1, word);
742
743 rt2x00_desc_read(entry_priv->desc, 0, &word);
744 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
745 rt2x00_desc_write(entry_priv->desc, 0, word);
746 } else {
747 rt2x00_desc_read(entry_priv->desc, 0, &word);
748 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
749 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
750 rt2x00_desc_write(entry_priv->desc, 0, word);
751 }
752 }
753
754 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
755 {
756 struct queue_entry_priv_pci *entry_priv;
757 u32 reg;
758
759 /*
760 * Initialize registers.
761 */
762 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
763 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
764 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
765 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
766 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
767 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
768
769 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
770 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
771 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
772 entry_priv->desc_dma);
773 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
774
775 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
776 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
777 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
778 entry_priv->desc_dma);
779 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
780
781 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
782 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
783 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
784 entry_priv->desc_dma);
785 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
786
787 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
788 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
789 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
790 entry_priv->desc_dma);
791 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
792
793 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
794 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
795 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
796 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
797
798 entry_priv = rt2x00dev->rx->entries[0].priv_data;
799 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
800 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
801 entry_priv->desc_dma);
802 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
803
804 return 0;
805 }
806
807 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
808 {
809 u32 reg;
810
811 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
812 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
813 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
814 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
815
816 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
817 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
818 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
819 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
820 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
821
822 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
823 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
824 rt2x00dev->rx->data_size / 128);
825 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
826
827 /*
828 * Always use CWmin and CWmax set in descriptor.
829 */
830 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
831 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
832 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
833
834 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
835 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
836 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
837 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
838 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
839 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
840 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
841 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
842 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
843 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
844
845 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
846
847 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
848 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
849 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
850 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
851 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
852 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
853 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
854 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
855 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
856 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
857
858 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
859 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
860 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
861 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
862 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
863 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
864
865 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
866 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
867 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
868 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
869 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
870 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
871
872 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
873 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
874 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
875 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
876 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
877 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
878
879 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
880 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
881 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
882 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
883 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
884 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
885 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
886 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
887 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
888 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
889
890 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
891 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
892 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
893 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
894 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
895 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
896 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
897 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
898 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
899
900 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
901
902 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
903 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
904
905 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
906 return -EBUSY;
907
908 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
909 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
910
911 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
912 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
913 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
914
915 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
916 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
917 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
918 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
919 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
920 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
921 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
922 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
923
924 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
925
926 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
927
928 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
929 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
930 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
931 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
932 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
933
934 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
935 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
936 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
937 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
938
939 /*
940 * We must clear the FCS and FIFO error count.
941 * These registers are cleared on read,
942 * so we may pass a useless variable to store the value.
943 */
944 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
945 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
946
947 return 0;
948 }
949
950 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
951 {
952 unsigned int i;
953 u8 value;
954
955 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
956 rt2500pci_bbp_read(rt2x00dev, 0, &value);
957 if ((value != 0xff) && (value != 0x00))
958 return 0;
959 udelay(REGISTER_BUSY_DELAY);
960 }
961
962 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
963 return -EACCES;
964 }
965
966 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
967 {
968 unsigned int i;
969 u16 eeprom;
970 u8 reg_id;
971 u8 value;
972
973 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
974 return -EACCES;
975
976 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
977 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
978 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
979 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
980 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
981 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
982 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
983 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
984 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
985 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
986 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
987 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
988 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
989 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
990 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
991 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
992 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
993 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
994 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
995 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
996 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
997 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
998 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
999 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1000 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1001 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1002 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1003 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1004 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1005 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1006
1007 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1008 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1009
1010 if (eeprom != 0xffff && eeprom != 0x0000) {
1011 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1012 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1013 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1014 }
1015 }
1016
1017 return 0;
1018 }
1019
1020 /*
1021 * Device state switch handlers.
1022 */
1023 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1024 enum dev_state state)
1025 {
1026 u32 reg;
1027
1028 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1029 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1030 (state == STATE_RADIO_RX_OFF) ||
1031 (state == STATE_RADIO_RX_OFF_LINK));
1032 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1033 }
1034
1035 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1036 enum dev_state state)
1037 {
1038 int mask = (state == STATE_RADIO_IRQ_OFF);
1039 u32 reg;
1040
1041 /*
1042 * When interrupts are being enabled, the interrupt registers
1043 * should clear the register to assure a clean state.
1044 */
1045 if (state == STATE_RADIO_IRQ_ON) {
1046 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1047 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1048 }
1049
1050 /*
1051 * Only toggle the interrupts bits we are going to use.
1052 * Non-checked interrupt bits are disabled by default.
1053 */
1054 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1055 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1056 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1057 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1058 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1059 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1060 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1061 }
1062
1063 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1064 {
1065 /*
1066 * Initialize all registers.
1067 */
1068 if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1069 rt2500pci_init_registers(rt2x00dev) ||
1070 rt2500pci_init_bbp(rt2x00dev)))
1071 return -EIO;
1072
1073 return 0;
1074 }
1075
1076 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1077 {
1078 /*
1079 * Disable power
1080 */
1081 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1082 }
1083
1084 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1085 enum dev_state state)
1086 {
1087 u32 reg, reg2;
1088 unsigned int i;
1089 char put_to_sleep;
1090 char bbp_state;
1091 char rf_state;
1092
1093 put_to_sleep = (state != STATE_AWAKE);
1094
1095 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1096 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1097 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1098 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1099 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1100 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1101
1102 /*
1103 * Device is not guaranteed to be in the requested state yet.
1104 * We must wait until the register indicates that the
1105 * device has entered the correct state.
1106 */
1107 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1108 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg2);
1109 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1110 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
1111 if (bbp_state == state && rf_state == state)
1112 return 0;
1113 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1114 msleep(10);
1115 }
1116
1117 return -EBUSY;
1118 }
1119
1120 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1121 enum dev_state state)
1122 {
1123 int retval = 0;
1124
1125 switch (state) {
1126 case STATE_RADIO_ON:
1127 retval = rt2500pci_enable_radio(rt2x00dev);
1128 break;
1129 case STATE_RADIO_OFF:
1130 rt2500pci_disable_radio(rt2x00dev);
1131 break;
1132 case STATE_RADIO_RX_ON:
1133 case STATE_RADIO_RX_ON_LINK:
1134 case STATE_RADIO_RX_OFF:
1135 case STATE_RADIO_RX_OFF_LINK:
1136 rt2500pci_toggle_rx(rt2x00dev, state);
1137 break;
1138 case STATE_RADIO_IRQ_ON:
1139 case STATE_RADIO_IRQ_OFF:
1140 rt2500pci_toggle_irq(rt2x00dev, state);
1141 break;
1142 case STATE_DEEP_SLEEP:
1143 case STATE_SLEEP:
1144 case STATE_STANDBY:
1145 case STATE_AWAKE:
1146 retval = rt2500pci_set_state(rt2x00dev, state);
1147 break;
1148 default:
1149 retval = -ENOTSUPP;
1150 break;
1151 }
1152
1153 if (unlikely(retval))
1154 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1155 state, retval);
1156
1157 return retval;
1158 }
1159
1160 /*
1161 * TX descriptor initialization
1162 */
1163 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1164 struct sk_buff *skb,
1165 struct txentry_desc *txdesc)
1166 {
1167 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1168 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1169 __le32 *txd = entry_priv->desc;
1170 u32 word;
1171
1172 /*
1173 * Start writing the descriptor words.
1174 */
1175 rt2x00_desc_read(txd, 1, &word);
1176 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1177 rt2x00_desc_write(txd, 1, word);
1178
1179 rt2x00_desc_read(txd, 2, &word);
1180 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1181 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1182 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1183 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1184 rt2x00_desc_write(txd, 2, word);
1185
1186 rt2x00_desc_read(txd, 3, &word);
1187 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1188 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1189 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1190 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1191 rt2x00_desc_write(txd, 3, word);
1192
1193 rt2x00_desc_read(txd, 10, &word);
1194 rt2x00_set_field32(&word, TXD_W10_RTS,
1195 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1196 rt2x00_desc_write(txd, 10, word);
1197
1198 /*
1199 * Writing TXD word 0 must the last to prevent a race condition with
1200 * the device, whereby the device may take hold of the TXD before we
1201 * finished updating it.
1202 */
1203 rt2x00_desc_read(txd, 0, &word);
1204 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1205 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1206 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1207 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1208 rt2x00_set_field32(&word, TXD_W0_ACK,
1209 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1210 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1211 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1212 rt2x00_set_field32(&word, TXD_W0_OFDM,
1213 (txdesc->rate_mode == RATE_MODE_OFDM));
1214 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1215 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1216 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1217 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1218 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1219 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1220 rt2x00_desc_write(txd, 0, word);
1221
1222 /*
1223 * Register descriptor details in skb frame descriptor.
1224 */
1225 skbdesc->desc = txd;
1226 skbdesc->desc_len = TXD_DESC_SIZE;
1227 }
1228
1229 /*
1230 * TX data initialization
1231 */
1232 static void rt2500pci_write_beacon(struct queue_entry *entry,
1233 struct txentry_desc *txdesc)
1234 {
1235 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1236 u32 reg;
1237
1238 /*
1239 * Disable beaconing while we are reloading the beacon data,
1240 * otherwise we might be sending out invalid data.
1241 */
1242 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1243 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1244 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1245
1246 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1247
1248 /*
1249 * Write the TX descriptor for the beacon.
1250 */
1251 rt2500pci_write_tx_desc(rt2x00dev, entry->skb, txdesc);
1252
1253 /*
1254 * Dump beacon to userspace through debugfs.
1255 */
1256 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1257
1258 /*
1259 * Enable beaconing again.
1260 */
1261 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1262 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1263 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1264 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1265 }
1266
1267 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1268 const enum data_queue_qid queue)
1269 {
1270 u32 reg;
1271
1272 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1273 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1274 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1275 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1276 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1277 }
1278
1279 static void rt2500pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1280 const enum data_queue_qid qid)
1281 {
1282 u32 reg;
1283
1284 if (qid == QID_BEACON) {
1285 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1286 } else {
1287 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1288 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1289 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1290 }
1291 }
1292
1293 /*
1294 * RX control handlers
1295 */
1296 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1297 struct rxdone_entry_desc *rxdesc)
1298 {
1299 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1300 u32 word0;
1301 u32 word2;
1302
1303 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1304 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1305
1306 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1307 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1308 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1309 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1310
1311 /*
1312 * Obtain the status about this packet.
1313 * When frame was received with an OFDM bitrate,
1314 * the signal is the PLCP value. If it was received with
1315 * a CCK bitrate the signal is the rate in 100kbit/s.
1316 */
1317 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1318 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1319 entry->queue->rt2x00dev->rssi_offset;
1320 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1321
1322 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1323 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1324 else
1325 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1326 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1327 rxdesc->dev_flags |= RXDONE_MY_BSS;
1328 }
1329
1330 /*
1331 * Interrupt functions.
1332 */
1333 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1334 const enum data_queue_qid queue_idx)
1335 {
1336 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1337 struct queue_entry_priv_pci *entry_priv;
1338 struct queue_entry *entry;
1339 struct txdone_entry_desc txdesc;
1340 u32 word;
1341
1342 while (!rt2x00queue_empty(queue)) {
1343 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1344 entry_priv = entry->priv_data;
1345 rt2x00_desc_read(entry_priv->desc, 0, &word);
1346
1347 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1348 !rt2x00_get_field32(word, TXD_W0_VALID))
1349 break;
1350
1351 /*
1352 * Obtain the status about this packet.
1353 */
1354 txdesc.flags = 0;
1355 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1356 case 0: /* Success */
1357 case 1: /* Success with retry */
1358 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1359 break;
1360 case 2: /* Failure, excessive retries */
1361 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1362 /* Don't break, this is a failed frame! */
1363 default: /* Failure */
1364 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1365 }
1366 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1367
1368 rt2x00lib_txdone(entry, &txdesc);
1369 }
1370 }
1371
1372 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1373 {
1374 struct rt2x00_dev *rt2x00dev = dev_instance;
1375 u32 reg;
1376
1377 /*
1378 * Get the interrupt sources & saved to local variable.
1379 * Write register value back to clear pending interrupts.
1380 */
1381 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1382 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1383
1384 if (!reg)
1385 return IRQ_NONE;
1386
1387 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1388 return IRQ_HANDLED;
1389
1390 /*
1391 * Handle interrupts, walk through all bits
1392 * and run the tasks, the bits are checked in order of
1393 * priority.
1394 */
1395
1396 /*
1397 * 1 - Beacon timer expired interrupt.
1398 */
1399 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1400 rt2x00lib_beacondone(rt2x00dev);
1401
1402 /*
1403 * 2 - Rx ring done interrupt.
1404 */
1405 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1406 rt2x00pci_rxdone(rt2x00dev);
1407
1408 /*
1409 * 3 - Atim ring transmit done interrupt.
1410 */
1411 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1412 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1413
1414 /*
1415 * 4 - Priority ring transmit done interrupt.
1416 */
1417 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1418 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1419
1420 /*
1421 * 5 - Tx ring transmit done interrupt.
1422 */
1423 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1424 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1425
1426 return IRQ_HANDLED;
1427 }
1428
1429 /*
1430 * Device probe functions.
1431 */
1432 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1433 {
1434 struct eeprom_93cx6 eeprom;
1435 u32 reg;
1436 u16 word;
1437 u8 *mac;
1438
1439 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1440
1441 eeprom.data = rt2x00dev;
1442 eeprom.register_read = rt2500pci_eepromregister_read;
1443 eeprom.register_write = rt2500pci_eepromregister_write;
1444 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1445 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1446 eeprom.reg_data_in = 0;
1447 eeprom.reg_data_out = 0;
1448 eeprom.reg_data_clock = 0;
1449 eeprom.reg_chip_select = 0;
1450
1451 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1452 EEPROM_SIZE / sizeof(u16));
1453
1454 /*
1455 * Start validation of the data that has been read.
1456 */
1457 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1458 if (!is_valid_ether_addr(mac)) {
1459 random_ether_addr(mac);
1460 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1461 }
1462
1463 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1464 if (word == 0xffff) {
1465 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1466 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1467 ANTENNA_SW_DIVERSITY);
1468 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1469 ANTENNA_SW_DIVERSITY);
1470 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1471 LED_MODE_DEFAULT);
1472 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1473 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1474 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1475 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1476 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1477 }
1478
1479 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1480 if (word == 0xffff) {
1481 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1482 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1483 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1484 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1485 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1486 }
1487
1488 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1489 if (word == 0xffff) {
1490 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1491 DEFAULT_RSSI_OFFSET);
1492 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1493 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1494 }
1495
1496 return 0;
1497 }
1498
1499 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1500 {
1501 u32 reg;
1502 u16 value;
1503 u16 eeprom;
1504
1505 /*
1506 * Read EEPROM word for configuration.
1507 */
1508 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1509
1510 /*
1511 * Identify RF chipset.
1512 */
1513 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1514 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1515 rt2x00_set_chip(rt2x00dev, RT2560, value,
1516 rt2x00_get_field32(reg, CSR0_REVISION));
1517
1518 if (!rt2x00_rf(rt2x00dev, RF2522) &&
1519 !rt2x00_rf(rt2x00dev, RF2523) &&
1520 !rt2x00_rf(rt2x00dev, RF2524) &&
1521 !rt2x00_rf(rt2x00dev, RF2525) &&
1522 !rt2x00_rf(rt2x00dev, RF2525E) &&
1523 !rt2x00_rf(rt2x00dev, RF5222)) {
1524 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1525 return -ENODEV;
1526 }
1527
1528 /*
1529 * Identify default antenna configuration.
1530 */
1531 rt2x00dev->default_ant.tx =
1532 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1533 rt2x00dev->default_ant.rx =
1534 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1535
1536 /*
1537 * Store led mode, for correct led behaviour.
1538 */
1539 #ifdef CONFIG_RT2X00_LIB_LEDS
1540 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1541
1542 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1543 if (value == LED_MODE_TXRX_ACTIVITY ||
1544 value == LED_MODE_DEFAULT ||
1545 value == LED_MODE_ASUS)
1546 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1547 LED_TYPE_ACTIVITY);
1548 #endif /* CONFIG_RT2X00_LIB_LEDS */
1549
1550 /*
1551 * Detect if this device has an hardware controlled radio.
1552 */
1553 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1554 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1555
1556 /*
1557 * Check if the BBP tuning should be enabled.
1558 */
1559 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1560
1561 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1562 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1563
1564 /*
1565 * Read the RSSI <-> dBm offset information.
1566 */
1567 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1568 rt2x00dev->rssi_offset =
1569 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1570
1571 return 0;
1572 }
1573
1574 /*
1575 * RF value list for RF2522
1576 * Supports: 2.4 GHz
1577 */
1578 static const struct rf_channel rf_vals_bg_2522[] = {
1579 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1580 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1581 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1582 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1583 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1584 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1585 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1586 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1587 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1588 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1589 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1590 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1591 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1592 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1593 };
1594
1595 /*
1596 * RF value list for RF2523
1597 * Supports: 2.4 GHz
1598 */
1599 static const struct rf_channel rf_vals_bg_2523[] = {
1600 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1601 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1602 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1603 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1604 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1605 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1606 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1607 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1608 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1609 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1610 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1611 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1612 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1613 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1614 };
1615
1616 /*
1617 * RF value list for RF2524
1618 * Supports: 2.4 GHz
1619 */
1620 static const struct rf_channel rf_vals_bg_2524[] = {
1621 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1622 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1623 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1624 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1625 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1626 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1627 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1628 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1629 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1630 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1631 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1632 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1633 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1634 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1635 };
1636
1637 /*
1638 * RF value list for RF2525
1639 * Supports: 2.4 GHz
1640 */
1641 static const struct rf_channel rf_vals_bg_2525[] = {
1642 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1643 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1644 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1645 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1646 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1647 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1648 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1649 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1650 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1651 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1652 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1653 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1654 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1655 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1656 };
1657
1658 /*
1659 * RF value list for RF2525e
1660 * Supports: 2.4 GHz
1661 */
1662 static const struct rf_channel rf_vals_bg_2525e[] = {
1663 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1664 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1665 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1666 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1667 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1668 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1669 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1670 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1671 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1672 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1673 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1674 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1675 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1676 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1677 };
1678
1679 /*
1680 * RF value list for RF5222
1681 * Supports: 2.4 GHz & 5.2 GHz
1682 */
1683 static const struct rf_channel rf_vals_5222[] = {
1684 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1685 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1686 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1687 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1688 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1689 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1690 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1691 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1692 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1693 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1694 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1695 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1696 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1697 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1698
1699 /* 802.11 UNI / HyperLan 2 */
1700 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1701 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1702 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1703 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1704 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1705 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1706 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1707 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1708
1709 /* 802.11 HyperLan 2 */
1710 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1711 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1712 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1713 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1714 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1715 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1716 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1717 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1718 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1719 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1720
1721 /* 802.11 UNII */
1722 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1723 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1724 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1725 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1726 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1727 };
1728
1729 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1730 {
1731 struct hw_mode_spec *spec = &rt2x00dev->spec;
1732 struct channel_info *info;
1733 char *tx_power;
1734 unsigned int i;
1735
1736 /*
1737 * Initialize all hw fields.
1738 */
1739 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1740 IEEE80211_HW_SIGNAL_DBM |
1741 IEEE80211_HW_SUPPORTS_PS |
1742 IEEE80211_HW_PS_NULLFUNC_STACK;
1743
1744 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1745 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1746 rt2x00_eeprom_addr(rt2x00dev,
1747 EEPROM_MAC_ADDR_0));
1748
1749 /*
1750 * Initialize hw_mode information.
1751 */
1752 spec->supported_bands = SUPPORT_BAND_2GHZ;
1753 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1754
1755 if (rt2x00_rf(rt2x00dev, RF2522)) {
1756 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1757 spec->channels = rf_vals_bg_2522;
1758 } else if (rt2x00_rf(rt2x00dev, RF2523)) {
1759 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1760 spec->channels = rf_vals_bg_2523;
1761 } else if (rt2x00_rf(rt2x00dev, RF2524)) {
1762 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1763 spec->channels = rf_vals_bg_2524;
1764 } else if (rt2x00_rf(rt2x00dev, RF2525)) {
1765 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1766 spec->channels = rf_vals_bg_2525;
1767 } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
1768 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1769 spec->channels = rf_vals_bg_2525e;
1770 } else if (rt2x00_rf(rt2x00dev, RF5222)) {
1771 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1772 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1773 spec->channels = rf_vals_5222;
1774 }
1775
1776 /*
1777 * Create channel information array
1778 */
1779 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1780 if (!info)
1781 return -ENOMEM;
1782
1783 spec->channels_info = info;
1784
1785 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1786 for (i = 0; i < 14; i++)
1787 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1788
1789 if (spec->num_channels > 14) {
1790 for (i = 14; i < spec->num_channels; i++)
1791 info[i].tx_power1 = DEFAULT_TXPOWER;
1792 }
1793
1794 return 0;
1795 }
1796
1797 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1798 {
1799 int retval;
1800
1801 /*
1802 * Allocate eeprom data.
1803 */
1804 retval = rt2500pci_validate_eeprom(rt2x00dev);
1805 if (retval)
1806 return retval;
1807
1808 retval = rt2500pci_init_eeprom(rt2x00dev);
1809 if (retval)
1810 return retval;
1811
1812 /*
1813 * Initialize hw specifications.
1814 */
1815 retval = rt2500pci_probe_hw_mode(rt2x00dev);
1816 if (retval)
1817 return retval;
1818
1819 /*
1820 * This device requires the atim queue and DMA-mapped skbs.
1821 */
1822 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1823 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1824
1825 /*
1826 * Set the rssi offset.
1827 */
1828 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1829
1830 return 0;
1831 }
1832
1833 /*
1834 * IEEE80211 stack callback functions.
1835 */
1836 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1837 {
1838 struct rt2x00_dev *rt2x00dev = hw->priv;
1839 u64 tsf;
1840 u32 reg;
1841
1842 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1843 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1844 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1845 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1846
1847 return tsf;
1848 }
1849
1850 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1851 {
1852 struct rt2x00_dev *rt2x00dev = hw->priv;
1853 u32 reg;
1854
1855 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1856 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1857 }
1858
1859 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1860 .tx = rt2x00mac_tx,
1861 .start = rt2x00mac_start,
1862 .stop = rt2x00mac_stop,
1863 .add_interface = rt2x00mac_add_interface,
1864 .remove_interface = rt2x00mac_remove_interface,
1865 .config = rt2x00mac_config,
1866 .configure_filter = rt2x00mac_configure_filter,
1867 .set_tim = rt2x00mac_set_tim,
1868 .get_stats = rt2x00mac_get_stats,
1869 .bss_info_changed = rt2x00mac_bss_info_changed,
1870 .conf_tx = rt2x00mac_conf_tx,
1871 .get_tsf = rt2500pci_get_tsf,
1872 .tx_last_beacon = rt2500pci_tx_last_beacon,
1873 .rfkill_poll = rt2x00mac_rfkill_poll,
1874 };
1875
1876 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1877 .irq_handler = rt2500pci_interrupt,
1878 .probe_hw = rt2500pci_probe_hw,
1879 .initialize = rt2x00pci_initialize,
1880 .uninitialize = rt2x00pci_uninitialize,
1881 .get_entry_state = rt2500pci_get_entry_state,
1882 .clear_entry = rt2500pci_clear_entry,
1883 .set_device_state = rt2500pci_set_device_state,
1884 .rfkill_poll = rt2500pci_rfkill_poll,
1885 .link_stats = rt2500pci_link_stats,
1886 .reset_tuner = rt2500pci_reset_tuner,
1887 .link_tuner = rt2500pci_link_tuner,
1888 .write_tx_desc = rt2500pci_write_tx_desc,
1889 .write_tx_data = rt2x00pci_write_tx_data,
1890 .write_beacon = rt2500pci_write_beacon,
1891 .kick_tx_queue = rt2500pci_kick_tx_queue,
1892 .kill_tx_queue = rt2500pci_kill_tx_queue,
1893 .fill_rxdone = rt2500pci_fill_rxdone,
1894 .config_filter = rt2500pci_config_filter,
1895 .config_intf = rt2500pci_config_intf,
1896 .config_erp = rt2500pci_config_erp,
1897 .config_ant = rt2500pci_config_ant,
1898 .config = rt2500pci_config,
1899 };
1900
1901 static const struct data_queue_desc rt2500pci_queue_rx = {
1902 .entry_num = RX_ENTRIES,
1903 .data_size = DATA_FRAME_SIZE,
1904 .desc_size = RXD_DESC_SIZE,
1905 .priv_size = sizeof(struct queue_entry_priv_pci),
1906 };
1907
1908 static const struct data_queue_desc rt2500pci_queue_tx = {
1909 .entry_num = TX_ENTRIES,
1910 .data_size = DATA_FRAME_SIZE,
1911 .desc_size = TXD_DESC_SIZE,
1912 .priv_size = sizeof(struct queue_entry_priv_pci),
1913 };
1914
1915 static const struct data_queue_desc rt2500pci_queue_bcn = {
1916 .entry_num = BEACON_ENTRIES,
1917 .data_size = MGMT_FRAME_SIZE,
1918 .desc_size = TXD_DESC_SIZE,
1919 .priv_size = sizeof(struct queue_entry_priv_pci),
1920 };
1921
1922 static const struct data_queue_desc rt2500pci_queue_atim = {
1923 .entry_num = ATIM_ENTRIES,
1924 .data_size = DATA_FRAME_SIZE,
1925 .desc_size = TXD_DESC_SIZE,
1926 .priv_size = sizeof(struct queue_entry_priv_pci),
1927 };
1928
1929 static const struct rt2x00_ops rt2500pci_ops = {
1930 .name = KBUILD_MODNAME,
1931 .max_sta_intf = 1,
1932 .max_ap_intf = 1,
1933 .eeprom_size = EEPROM_SIZE,
1934 .rf_size = RF_SIZE,
1935 .tx_queues = NUM_TX_QUEUES,
1936 .extra_tx_headroom = 0,
1937 .rx = &rt2500pci_queue_rx,
1938 .tx = &rt2500pci_queue_tx,
1939 .bcn = &rt2500pci_queue_bcn,
1940 .atim = &rt2500pci_queue_atim,
1941 .lib = &rt2500pci_rt2x00_ops,
1942 .hw = &rt2500pci_mac80211_ops,
1943 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1944 .debugfs = &rt2500pci_rt2x00debug,
1945 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1946 };
1947
1948 /*
1949 * RT2500pci module information.
1950 */
1951 static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table) = {
1952 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1953 { 0, }
1954 };
1955
1956 MODULE_AUTHOR(DRV_PROJECT);
1957 MODULE_VERSION(DRV_VERSION);
1958 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1959 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1960 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1961 MODULE_LICENSE("GPL");
1962
1963 static struct pci_driver rt2500pci_driver = {
1964 .name = KBUILD_MODNAME,
1965 .id_table = rt2500pci_device_table,
1966 .probe = rt2x00pci_probe,
1967 .remove = __devexit_p(rt2x00pci_remove),
1968 .suspend = rt2x00pci_suspend,
1969 .resume = rt2x00pci_resume,
1970 };
1971
1972 static int __init rt2500pci_init(void)
1973 {
1974 return pci_register_driver(&rt2500pci_driver);
1975 }
1976
1977 static void __exit rt2500pci_exit(void)
1978 {
1979 pci_unregister_driver(&rt2500pci_driver);
1980 }
1981
1982 module_init(rt2500pci_init);
1983 module_exit(rt2500pci_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree