arch/arm/plat-nomadik/include/plat/ste_dma40.h

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2007-2010
   3  * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
   4  * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
   5  * License terms: GNU General Public License (GPL) version 2
   6  */
   7
   8
   9 #ifndef STE_DMA40_H
  10 #define STE_DMA40_H
  11
  12 #include <linux/dmaengine.h>
  13 #include <linux/workqueue.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/dmaengine.h>
  16
  17 /* dev types for memcpy */
  18 #define STEDMA40_DEV_DST_MEMORY (-1)
  19 #define STEDMA40_DEV_SRC_MEMORY (-1)
  20
  21 enum stedma40_mode {
  22         STEDMA40_MODE_LOGICAL = 0,
  23         STEDMA40_MODE_PHYSICAL,
  24         STEDMA40_MODE_OPERATION,
  25 };
  26
  27 enum stedma40_mode_opt {
  28         STEDMA40_PCHAN_BASIC_MODE = 0,
  29         STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
  30         STEDMA40_PCHAN_MODULO_MODE,
  31         STEDMA40_PCHAN_DOUBLE_DST_MODE,
  32         STEDMA40_LCHAN_SRC_PHY_DST_LOG,
  33         STEDMA40_LCHAN_SRC_LOG_DST_PHY,
  34 };
  35
  36 #define STEDMA40_ESIZE_8_BIT  0x0
  37 #define STEDMA40_ESIZE_16_BIT 0x1
  38 #define STEDMA40_ESIZE_32_BIT 0x2
  39 #define STEDMA40_ESIZE_64_BIT 0x3
  40
  41 /* The value 4 indicates that PEN-reg shall be set to 0 */
  42 #define STEDMA40_PSIZE_PHY_1  0x4
  43 #define STEDMA40_PSIZE_PHY_2  0x0
  44 #define STEDMA40_PSIZE_PHY_4  0x1
  45 #define STEDMA40_PSIZE_PHY_8  0x2
  46 #define STEDMA40_PSIZE_PHY_16 0x3
  47
  48 /*
  49  * The number of elements differ in logical and
  50  * physical mode
  51  */
  52 #define STEDMA40_PSIZE_LOG_1  STEDMA40_PSIZE_PHY_2
  53 #define STEDMA40_PSIZE_LOG_4  STEDMA40_PSIZE_PHY_4
  54 #define STEDMA40_PSIZE_LOG_8  STEDMA40_PSIZE_PHY_8
  55 #define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
  56
  57 /* Maximum number of possible physical channels */
  58 #define STEDMA40_MAX_PHYS 32
  59
  60 enum stedma40_flow_ctrl {
  61         STEDMA40_NO_FLOW_CTRL,
  62         STEDMA40_FLOW_CTRL,
  63 };
  64
  65 enum stedma40_periph_data_width {
  66         STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
  67         STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
  68         STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
  69         STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
  70 };
  71
  72 enum stedma40_xfer_dir {
  73         STEDMA40_MEM_TO_MEM = 1,
  74         STEDMA40_MEM_TO_PERIPH,
  75         STEDMA40_PERIPH_TO_MEM,
  76         STEDMA40_PERIPH_TO_PERIPH
  77 };
  78
  79
  80 /**
  81  * struct stedma40_chan_cfg - dst/src channel configuration
  82  *
  83  * @big_endian: true if the src/dst should be read as big endian
  84  * @data_width: Data width of the src/dst hardware
  85  * @p_size: Burst size
  86  * @flow_ctrl: Flow control on/off.
  87  */
  88 struct stedma40_half_channel_info {
  89         bool big_endian;
  90         enum stedma40_periph_data_width data_width;
  91         int psize;
  92         enum stedma40_flow_ctrl flow_ctrl;
  93 };
  94
  95 /**
  96  * struct stedma40_chan_cfg - Structure to be filled by client drivers.
  97  *
  98  * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
  99  * @high_priority: true if high-priority
 100  * @mode: channel mode: physical, logical, or operation
 101  * @mode_opt: options for the chosen channel mode
 102  * @src_dev_type: Src device type
 103  * @dst_dev_type: Dst device type
 104  * @src_info: Parameters for dst half channel
 105  * @dst_info: Parameters for dst half channel
 106  *
 107  *
 108  * This structure has to be filled by the client drivers.
 109  * It is recommended to do all dma configurations for clients in the machine.
 110  *
 111  */
 112 struct stedma40_chan_cfg {
 113         enum stedma40_xfer_dir                   dir;
 114         bool                                     high_priority;
 115         enum stedma40_mode                       mode;
 116         enum stedma40_mode_opt                   mode_opt;
 117         int                                      src_dev_type;
 118         int                                      dst_dev_type;
 119         struct stedma40_half_channel_info        src_info;
 120         struct stedma40_half_channel_info        dst_info;
 121 };
 122
 123 /**
 124  * struct stedma40_platform_data - Configuration struct for the dma device.
 125  *
 126  * @dev_len: length of dev_tx and dev_rx
 127  * @dev_tx: mapping between destination event line and io address
 128  * @dev_rx: mapping between source event line and io address
 129  * @memcpy: list of memcpy event lines
 130  * @memcpy_len: length of memcpy
 131  * @memcpy_conf_phy: default configuration of physical channel memcpy
 132  * @memcpy_conf_log: default configuration of logical channel memcpy
 133  * @disabled_channels: A vector, ending with -1, that marks physical channels
 134  * that are for different reasons not available for the driver.
 135  */
 136 struct stedma40_platform_data {
 137         u32                              dev_len;
 138         const dma_addr_t                *dev_tx;
 139         const dma_addr_t                *dev_rx;
 140         int                             *memcpy;
 141         u32                              memcpy_len;
 142         struct stedma40_chan_cfg        *memcpy_conf_phy;
 143         struct stedma40_chan_cfg        *memcpy_conf_log;
 144         int                              disabled_channels[STEDMA40_MAX_PHYS];
 145 };
 146
 147 #ifdef CONFIG_STE_DMA40
 148
 149 /**
 150  * stedma40_filter() - Provides stedma40_chan_cfg to the
 151  * ste_dma40 dma driver via the dmaengine framework.
 152  * does some checking of what's provided.
 153  *
 154  * Never directly called by client. It used by dmaengine.
 155  * @chan: dmaengine handle.
 156  * @data: Must be of type: struct stedma40_chan_cfg and is
 157  * the configuration of the framework.
 158  *
 159  *
 160  */
 161
 162 bool stedma40_filter(struct dma_chan *chan, void *data);
 163
 164 /**
 165  * stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from
 166  * scattergatter lists.
 167  *
 168  * @chan: dmaengine handle
 169  * @sgl_dst: Destination scatter list
 170  * @sgl_src: Source scatter list
 171  * @sgl_len: The length of each scatterlist. Both lists must be of equal length
 172  * and each element must match the corresponding element in the other scatter
 173  * list.
 174  * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
 175  */
 176
 177 struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
 178                                                    struct scatterlist *sgl_dst,
 179                                                    struct scatterlist *sgl_src,
 180                                                    unsigned int sgl_len,
 181                                                    unsigned long flags);
 182
 183 /**
 184  * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
 185  * (=device)
 186  *
 187  * @chan: dmaengine handle
 188  * @addr: source or destination physicall address.
 189  * @size: bytes to transfer
 190  * @direction: direction of transfer
 191  * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
 192  */
 193
 194 static inline struct
 195 dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
 196                                             dma_addr_t addr,
 197                                             unsigned int size,
 198                                             enum dma_data_direction direction,
 199                                             unsigned long flags)
 200 {
 201         struct scatterlist sg;
 202         sg_init_table(&sg, 1);
 203         sg.dma_address = addr;
 204         sg.length = size;
 205
 206         return chan->device->device_prep_slave_sg(chan, &sg, 1,
 207                                                   direction, flags);
 208 }
 209
 210 #else
 211 static inline bool stedma40_filter(struct dma_chan *chan, void *data)
 212 {
 213         return false;
 214 }
 215
 216 static inline struct
 217 dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
 218                                             dma_addr_t addr,
 219                                             unsigned int size,
 220                                             enum dma_data_direction direction,
 221                                             unsigned long flags)
 222 {
 223         return NULL;
 224 }
 225 #endif
 226
 227 #endif