2 * arch/blackfin/kernel/kgdb.c - Blackfin kgdb pieces
4 * Copyright 2005-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
9 #include <linux/string.h>
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <linux/smp.h>
13 #include <linux/spinlock.h>
14 #include <linux/delay.h>
15 #include <linux/ptrace.h> /* for linux pt_regs struct */
16 #include <linux/kgdb.h>
17 #include <linux/console.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/irq.h>
21 #include <linux/uaccess.h>
22 #include <asm/system.h>
23 #include <asm/traps.h>
24 #include <asm/blackfin.h>
27 /* Put the error code here just in case the user cares. */
29 /* Likewise, the vector number here (since GDB only gets the signal
30 number through the usual means, and that's not very specific). */
31 int gdb_bfin_vector
= -1;
33 #if KGDB_MAX_NO_CPUS != 8
34 #error change the definition of slavecpulocks
37 #ifdef CONFIG_BFIN_WDT
38 # error "Please unselect blackfin watchdog driver before build KGDB."
41 void pt_regs_to_gdb_regs(unsigned long *gdb_regs
, struct pt_regs
*regs
)
43 gdb_regs
[BFIN_R0
] = regs
->r0
;
44 gdb_regs
[BFIN_R1
] = regs
->r1
;
45 gdb_regs
[BFIN_R2
] = regs
->r2
;
46 gdb_regs
[BFIN_R3
] = regs
->r3
;
47 gdb_regs
[BFIN_R4
] = regs
->r4
;
48 gdb_regs
[BFIN_R5
] = regs
->r5
;
49 gdb_regs
[BFIN_R6
] = regs
->r6
;
50 gdb_regs
[BFIN_R7
] = regs
->r7
;
51 gdb_regs
[BFIN_P0
] = regs
->p0
;
52 gdb_regs
[BFIN_P1
] = regs
->p1
;
53 gdb_regs
[BFIN_P2
] = regs
->p2
;
54 gdb_regs
[BFIN_P3
] = regs
->p3
;
55 gdb_regs
[BFIN_P4
] = regs
->p4
;
56 gdb_regs
[BFIN_P5
] = regs
->p5
;
57 gdb_regs
[BFIN_SP
] = regs
->reserved
;
58 gdb_regs
[BFIN_FP
] = regs
->fp
;
59 gdb_regs
[BFIN_I0
] = regs
->i0
;
60 gdb_regs
[BFIN_I1
] = regs
->i1
;
61 gdb_regs
[BFIN_I2
] = regs
->i2
;
62 gdb_regs
[BFIN_I3
] = regs
->i3
;
63 gdb_regs
[BFIN_M0
] = regs
->m0
;
64 gdb_regs
[BFIN_M1
] = regs
->m1
;
65 gdb_regs
[BFIN_M2
] = regs
->m2
;
66 gdb_regs
[BFIN_M3
] = regs
->m3
;
67 gdb_regs
[BFIN_B0
] = regs
->b0
;
68 gdb_regs
[BFIN_B1
] = regs
->b1
;
69 gdb_regs
[BFIN_B2
] = regs
->b2
;
70 gdb_regs
[BFIN_B3
] = regs
->b3
;
71 gdb_regs
[BFIN_L0
] = regs
->l0
;
72 gdb_regs
[BFIN_L1
] = regs
->l1
;
73 gdb_regs
[BFIN_L2
] = regs
->l2
;
74 gdb_regs
[BFIN_L3
] = regs
->l3
;
75 gdb_regs
[BFIN_A0_DOT_X
] = regs
->a0x
;
76 gdb_regs
[BFIN_A0_DOT_W
] = regs
->a0w
;
77 gdb_regs
[BFIN_A1_DOT_X
] = regs
->a1x
;
78 gdb_regs
[BFIN_A1_DOT_W
] = regs
->a1w
;
79 gdb_regs
[BFIN_ASTAT
] = regs
->astat
;
80 gdb_regs
[BFIN_RETS
] = regs
->rets
;
81 gdb_regs
[BFIN_LC0
] = regs
->lc0
;
82 gdb_regs
[BFIN_LT0
] = regs
->lt0
;
83 gdb_regs
[BFIN_LB0
] = regs
->lb0
;
84 gdb_regs
[BFIN_LC1
] = regs
->lc1
;
85 gdb_regs
[BFIN_LT1
] = regs
->lt1
;
86 gdb_regs
[BFIN_LB1
] = regs
->lb1
;
87 gdb_regs
[BFIN_CYCLES
] = 0;
88 gdb_regs
[BFIN_CYCLES2
] = 0;
89 gdb_regs
[BFIN_USP
] = regs
->usp
;
90 gdb_regs
[BFIN_SEQSTAT
] = regs
->seqstat
;
91 gdb_regs
[BFIN_SYSCFG
] = regs
->syscfg
;
92 gdb_regs
[BFIN_RETI
] = regs
->pc
;
93 gdb_regs
[BFIN_RETX
] = regs
->retx
;
94 gdb_regs
[BFIN_RETN
] = regs
->retn
;
95 gdb_regs
[BFIN_RETE
] = regs
->rete
;
96 gdb_regs
[BFIN_PC
] = regs
->pc
;
97 gdb_regs
[BFIN_CC
] = 0;
98 gdb_regs
[BFIN_EXTRA1
] = 0;
99 gdb_regs
[BFIN_EXTRA2
] = 0;
100 gdb_regs
[BFIN_EXTRA3
] = 0;
101 gdb_regs
[BFIN_IPEND
] = regs
->ipend
;
105 * Extracts ebp, esp and eip values understandable by gdb from the values
106 * saved by switch_to.
107 * thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
108 * prior to entering switch_to is 8 greater then the value that is saved.
109 * If switch_to changes, change following code appropriately.
111 void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs
, struct task_struct
*p
)
113 gdb_regs
[BFIN_SP
] = p
->thread
.ksp
;
114 gdb_regs
[BFIN_PC
] = p
->thread
.pc
;
115 gdb_regs
[BFIN_SEQSTAT
] = p
->thread
.seqstat
;
118 void gdb_regs_to_pt_regs(unsigned long *gdb_regs
, struct pt_regs
*regs
)
120 regs
->r0
= gdb_regs
[BFIN_R0
];
121 regs
->r1
= gdb_regs
[BFIN_R1
];
122 regs
->r2
= gdb_regs
[BFIN_R2
];
123 regs
->r3
= gdb_regs
[BFIN_R3
];
124 regs
->r4
= gdb_regs
[BFIN_R4
];
125 regs
->r5
= gdb_regs
[BFIN_R5
];
126 regs
->r6
= gdb_regs
[BFIN_R6
];
127 regs
->r7
= gdb_regs
[BFIN_R7
];
128 regs
->p0
= gdb_regs
[BFIN_P0
];
129 regs
->p1
= gdb_regs
[BFIN_P1
];
130 regs
->p2
= gdb_regs
[BFIN_P2
];
131 regs
->p3
= gdb_regs
[BFIN_P3
];
132 regs
->p4
= gdb_regs
[BFIN_P4
];
133 regs
->p5
= gdb_regs
[BFIN_P5
];
134 regs
->fp
= gdb_regs
[BFIN_FP
];
135 regs
->i0
= gdb_regs
[BFIN_I0
];
136 regs
->i1
= gdb_regs
[BFIN_I1
];
137 regs
->i2
= gdb_regs
[BFIN_I2
];
138 regs
->i3
= gdb_regs
[BFIN_I3
];
139 regs
->m0
= gdb_regs
[BFIN_M0
];
140 regs
->m1
= gdb_regs
[BFIN_M1
];
141 regs
->m2
= gdb_regs
[BFIN_M2
];
142 regs
->m3
= gdb_regs
[BFIN_M3
];
143 regs
->b0
= gdb_regs
[BFIN_B0
];
144 regs
->b1
= gdb_regs
[BFIN_B1
];
145 regs
->b2
= gdb_regs
[BFIN_B2
];
146 regs
->b3
= gdb_regs
[BFIN_B3
];
147 regs
->l0
= gdb_regs
[BFIN_L0
];
148 regs
->l1
= gdb_regs
[BFIN_L1
];
149 regs
->l2
= gdb_regs
[BFIN_L2
];
150 regs
->l3
= gdb_regs
[BFIN_L3
];
151 regs
->a0x
= gdb_regs
[BFIN_A0_DOT_X
];
152 regs
->a0w
= gdb_regs
[BFIN_A0_DOT_W
];
153 regs
->a1x
= gdb_regs
[BFIN_A1_DOT_X
];
154 regs
->a1w
= gdb_regs
[BFIN_A1_DOT_W
];
155 regs
->rets
= gdb_regs
[BFIN_RETS
];
156 regs
->lc0
= gdb_regs
[BFIN_LC0
];
157 regs
->lt0
= gdb_regs
[BFIN_LT0
];
158 regs
->lb0
= gdb_regs
[BFIN_LB0
];
159 regs
->lc1
= gdb_regs
[BFIN_LC1
];
160 regs
->lt1
= gdb_regs
[BFIN_LT1
];
161 regs
->lb1
= gdb_regs
[BFIN_LB1
];
162 regs
->usp
= gdb_regs
[BFIN_USP
];
163 regs
->syscfg
= gdb_regs
[BFIN_SYSCFG
];
164 regs
->retx
= gdb_regs
[BFIN_PC
];
165 regs
->retn
= gdb_regs
[BFIN_RETN
];
166 regs
->rete
= gdb_regs
[BFIN_RETE
];
167 regs
->pc
= gdb_regs
[BFIN_PC
];
169 #if 0 /* can't change these */
170 regs
->astat
= gdb_regs
[BFIN_ASTAT
];
171 regs
->seqstat
= gdb_regs
[BFIN_SEQSTAT
];
172 regs
->ipend
= gdb_regs
[BFIN_IPEND
];
176 struct hw_breakpoint
{
177 unsigned int occupied
:1;
179 unsigned int enabled
:1;
181 unsigned int dataacc
:2;
182 unsigned short count
;
184 } breakinfo
[HW_WATCHPOINT_NUM
];
186 int bfin_set_hw_break(unsigned long addr
, int len
, enum kgdb_bptype type
)
193 case BP_HARDWARE_BREAKPOINT
:
194 bfin_type
= TYPE_INST_WATCHPOINT
;
196 case BP_WRITE_WATCHPOINT
:
198 bfin_type
= TYPE_DATA_WATCHPOINT
;
200 case BP_READ_WATCHPOINT
:
202 bfin_type
= TYPE_DATA_WATCHPOINT
;
204 case BP_ACCESS_WATCHPOINT
:
206 bfin_type
= TYPE_DATA_WATCHPOINT
;
212 /* Becasue hardware data watchpoint impelemented in current
213 * Blackfin can not trigger an exception event as the hardware
214 * instrction watchpoint does, we ignaore all data watch point here.
215 * They can be turned on easily after future blackfin design
216 * supports this feature.
218 for (breakno
= 0; breakno
< HW_INST_WATCHPOINT_NUM
; breakno
++)
219 if (bfin_type
== breakinfo
[breakno
].type
220 && !breakinfo
[breakno
].occupied
) {
221 breakinfo
[breakno
].occupied
= 1;
222 breakinfo
[breakno
].enabled
= 1;
223 breakinfo
[breakno
].addr
= addr
;
224 breakinfo
[breakno
].dataacc
= dataacc
;
225 breakinfo
[breakno
].count
= 0;
232 int bfin_remove_hw_break(unsigned long addr
, int len
, enum kgdb_bptype type
)
238 case BP_HARDWARE_BREAKPOINT
:
239 bfin_type
= TYPE_INST_WATCHPOINT
;
241 case BP_WRITE_WATCHPOINT
:
242 case BP_READ_WATCHPOINT
:
243 case BP_ACCESS_WATCHPOINT
:
244 bfin_type
= TYPE_DATA_WATCHPOINT
;
249 for (breakno
= 0; breakno
< HW_WATCHPOINT_NUM
; breakno
++)
250 if (bfin_type
== breakinfo
[breakno
].type
251 && breakinfo
[breakno
].occupied
252 && breakinfo
[breakno
].addr
== addr
) {
253 breakinfo
[breakno
].occupied
= 0;
254 breakinfo
[breakno
].enabled
= 0;
260 void bfin_remove_all_hw_break(void)
264 memset(breakinfo
, 0, sizeof(struct hw_breakpoint
)*HW_WATCHPOINT_NUM
);
266 for (breakno
= 0; breakno
< HW_INST_WATCHPOINT_NUM
; breakno
++)
267 breakinfo
[breakno
].type
= TYPE_INST_WATCHPOINT
;
268 for (; breakno
< HW_WATCHPOINT_NUM
; breakno
++)
269 breakinfo
[breakno
].type
= TYPE_DATA_WATCHPOINT
;
272 void bfin_correct_hw_break(void)
275 unsigned int wpiactl
= 0;
276 unsigned int wpdactl
= 0;
279 for (breakno
= 0; breakno
< HW_WATCHPOINT_NUM
; breakno
++)
280 if (breakinfo
[breakno
].enabled
) {
285 wpiactl
|= WPIAEN0
|WPICNTEN0
;
286 bfin_write_WPIA0(breakinfo
[breakno
].addr
);
287 bfin_write_WPIACNT0(breakinfo
[breakno
].count
291 wpiactl
|= WPIAEN1
|WPICNTEN1
;
292 bfin_write_WPIA1(breakinfo
[breakno
].addr
);
293 bfin_write_WPIACNT1(breakinfo
[breakno
].count
297 wpiactl
|= WPIAEN2
|WPICNTEN2
;
298 bfin_write_WPIA2(breakinfo
[breakno
].addr
);
299 bfin_write_WPIACNT2(breakinfo
[breakno
].count
303 wpiactl
|= WPIAEN3
|WPICNTEN3
;
304 bfin_write_WPIA3(breakinfo
[breakno
].addr
);
305 bfin_write_WPIACNT3(breakinfo
[breakno
].count
309 wpiactl
|= WPIAEN4
|WPICNTEN4
;
310 bfin_write_WPIA4(breakinfo
[breakno
].addr
);
311 bfin_write_WPIACNT4(breakinfo
[breakno
].count
315 wpiactl
|= WPIAEN5
|WPICNTEN5
;
316 bfin_write_WPIA5(breakinfo
[breakno
].addr
);
317 bfin_write_WPIACNT5(breakinfo
[breakno
].count
321 wpdactl
|= WPDAEN0
|WPDCNTEN0
|WPDSRC0
;
322 wpdactl
|= breakinfo
[breakno
].dataacc
324 bfin_write_WPDA0(breakinfo
[breakno
].addr
);
325 bfin_write_WPDACNT0(breakinfo
[breakno
].count
329 wpdactl
|= WPDAEN1
|WPDCNTEN1
|WPDSRC1
;
330 wpdactl
|= breakinfo
[breakno
].dataacc
332 bfin_write_WPDA1(breakinfo
[breakno
].addr
);
333 bfin_write_WPDACNT1(breakinfo
[breakno
].count
339 /* Should enable WPPWR bit first before set any other
340 * WPIACTL and WPDACTL bits */
342 bfin_write_WPIACTL(WPPWR
);
344 bfin_write_WPIACTL(wpiactl
|WPPWR
);
345 bfin_write_WPDACTL(wpdactl
);
350 void kgdb_disable_hw_debug(struct pt_regs
*regs
)
352 /* Disable hardware debugging while we are in kgdb */
353 bfin_write_WPIACTL(0);
354 bfin_write_WPDACTL(0);
359 void kgdb_passive_cpu_callback(void *info
)
361 kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
364 void kgdb_roundup_cpus(unsigned long flags
)
366 smp_call_function(kgdb_passive_cpu_callback
, NULL
, 0, 0);
369 void kgdb_roundup_cpu(int cpu
, unsigned long flags
)
371 smp_call_function_single(cpu
, kgdb_passive_cpu_callback
, NULL
, 0, 0);
375 void kgdb_post_primary_code(struct pt_regs
*regs
, int eVector
, int err_code
)
377 /* Master processor is completely in the debugger */
378 gdb_bfin_vector
= eVector
;
379 gdb_bfin_errcode
= err_code
;
382 int kgdb_arch_handle_exception(int vector
, int signo
,
383 int err_code
, char *remcom_in_buffer
,
384 char *remcom_out_buffer
,
385 struct pt_regs
*regs
)
394 switch (remcom_in_buffer
[0]) {
397 if (kgdb_contthread
&& kgdb_contthread
!= current
) {
398 strcpy(remcom_out_buffer
, "E00");
402 kgdb_contthread
= NULL
;
404 /* try to read optional parameter, pc unchanged if no parm */
405 ptr
= &remcom_in_buffer
[1];
406 if (kgdb_hex2long(&ptr
, &addr
)) {
411 /* clear the trace bit */
412 regs
->syscfg
&= 0xfffffffe;
414 /* set the trace bit if we're stepping */
415 if (remcom_in_buffer
[0] == 's') {
417 kgdb_single_step
= regs
->ipend
;
418 kgdb_single_step
>>= 6;
419 for (i
= 10; i
> 0; i
--, kgdb_single_step
>>= 1)
420 if (kgdb_single_step
& 1)
422 /* i indicate event priority of current stopped instruction
423 * user space instruction is 0, IVG15 is 1, IVTMR is 10.
424 * kgdb_single_step > 0 means in single step mode
426 kgdb_single_step
= i
+ 1;
429 if (vector
== VEC_WATCH
) {
430 wp_status
= bfin_read_WPSTAT();
431 for (breakno
= 0; breakno
< HW_WATCHPOINT_NUM
; breakno
++) {
432 if (wp_status
& (1 << breakno
)) {
437 bfin_write_WPSTAT(0);
440 bfin_correct_hw_break();
444 return -1; /* this means that we do not want to exit from the handler */
447 struct kgdb_arch arch_kgdb_ops
= {
448 .gdb_bpt_instr
= {0xa1},
450 .flags
= KGDB_HW_BREAKPOINT
|KGDB_THR_PROC_SWAP
,
452 .flags
= KGDB_HW_BREAKPOINT
,
454 .set_hw_breakpoint
= bfin_set_hw_break
,
455 .remove_hw_breakpoint
= bfin_remove_hw_break
,
456 .remove_all_hw_break
= bfin_remove_all_hw_break
,
457 .correct_hw_break
= bfin_correct_hw_break
,
460 static int hex(char ch
)
462 if ((ch
>= 'a') && (ch
<= 'f'))
463 return ch
- 'a' + 10;
464 if ((ch
>= '0') && (ch
<= '9'))
466 if ((ch
>= 'A') && (ch
<= 'F'))
467 return ch
- 'A' + 10;
471 static int validate_memory_access_address(unsigned long addr
, int size
)
473 int cpu
= raw_smp_processor_id();
477 if (addr
>= 0x1000 && (addr
+ size
) <= physical_mem_end
)
479 if (addr
>= SYSMMR_BASE
)
481 if (addr
>= ASYNC_BANK0_BASE
482 && addr
+ size
<= ASYNC_BANK3_BASE
+ ASYNC_BANK3_SIZE
)
485 if (addr
>= L1_SCRATCH_START
486 && (addr
+ size
<= L1_SCRATCH_START
+ L1_SCRATCH_LENGTH
))
488 #if L1_CODE_LENGTH != 0
489 if (addr
>= L1_CODE_START
490 && (addr
+ size
<= L1_CODE_START
+ L1_CODE_LENGTH
))
493 #if L1_DATA_A_LENGTH != 0
494 if (addr
>= L1_DATA_A_START
495 && (addr
+ size
<= L1_DATA_A_START
+ L1_DATA_A_LENGTH
))
498 #if L1_DATA_B_LENGTH != 0
499 if (addr
>= L1_DATA_B_START
500 && (addr
+ size
<= L1_DATA_B_START
+ L1_DATA_B_LENGTH
))
504 } else if (cpu
== 1) {
505 if (addr
>= COREB_L1_SCRATCH_START
506 && (addr
+ size
<= COREB_L1_SCRATCH_START
507 + L1_SCRATCH_LENGTH
))
509 # if L1_CODE_LENGTH != 0
510 if (addr
>= COREB_L1_CODE_START
511 && (addr
+ size
<= COREB_L1_CODE_START
+ L1_CODE_LENGTH
))
514 # if L1_DATA_A_LENGTH != 0
515 if (addr
>= COREB_L1_DATA_A_START
516 && (addr
+ size
<= COREB_L1_DATA_A_START
+ L1_DATA_A_LENGTH
))
519 # if L1_DATA_B_LENGTH != 0
520 if (addr
>= COREB_L1_DATA_B_START
521 && (addr
+ size
<= COREB_L1_DATA_B_START
+ L1_DATA_B_LENGTH
))
529 && addr
+ size
<= L2_START
+ L2_LENGTH
)
537 * Convert the memory pointed to by mem into hex, placing result in buf.
538 * Return a pointer to the last char put in buf (null). May return an error.
540 int kgdb_mem2hex(char *mem
, char *buf
, int count
)
545 unsigned short mmr16
;
547 int cpu
= raw_smp_processor_id();
549 if (validate_memory_access_address((unsigned long)mem
, count
))
553 * We use the upper half of buf as an intermediate buffer for the
554 * raw memory copy. Hex conversion will work against this one.
558 if ((unsigned int)mem
>= SYSMMR_BASE
) { /*access MMR registers*/
561 if ((unsigned int)mem
% 2 == 0) {
562 mmr16
= *(unsigned short *)mem
;
563 pch
= (unsigned char *)&mmr16
;
571 if ((unsigned int)mem
% 4 == 0) {
572 mmr32
= *(unsigned long *)mem
;
573 pch
= (unsigned char *)&mmr32
;
585 } else if (cpu
== 0 && (unsigned int)mem
>= L1_CODE_START
&&
586 (unsigned int)(mem
+ count
) <= L1_CODE_START
+ L1_CODE_LENGTH
588 || cpu
== 1 && (unsigned int)mem
>= COREB_L1_CODE_START
&&
589 (unsigned int)(mem
+ count
) <=
590 COREB_L1_CODE_START
+ L1_CODE_LENGTH
593 /* access L1 instruction SRAM*/
594 if (dma_memcpy(tmp
, mem
, count
) == NULL
)
597 err
= probe_kernel_read(tmp
, mem
, count
);
601 buf
= pack_hex_byte(buf
, *tmp
);
613 * Copy the binary array pointed to by buf into mem. Fix $, #, and
614 * 0x7d escaped with 0x7d. Return a pointer to the character after
615 * the last byte written.
617 int kgdb_ebin2mem(char *buf
, char *mem
, int count
)
621 unsigned short *mmr16
;
622 unsigned long *mmr32
;
625 int cpu
= raw_smp_processor_id();
627 tmp_old
= tmp_new
= buf
;
629 while (count
-- > 0) {
630 if (*tmp_old
== 0x7d)
631 *tmp_new
= *(++tmp_old
) ^ 0x20;
639 if (validate_memory_access_address((unsigned long)mem
, size
))
642 if ((unsigned int)mem
>= SYSMMR_BASE
) { /*access MMR registers*/
645 if ((unsigned int)mem
% 2 == 0) {
646 mmr16
= (unsigned short *)buf
;
647 *(unsigned short *)mem
= *mmr16
;
652 if ((unsigned int)mem
% 4 == 0) {
653 mmr32
= (unsigned long *)buf
;
654 *(unsigned long *)mem
= *mmr32
;
661 } else if (cpu
== 0 && (unsigned int)mem
>= L1_CODE_START
&&
662 (unsigned int)(mem
+ count
) < L1_CODE_START
+ L1_CODE_LENGTH
664 || cpu
== 1 && (unsigned int)mem
>= COREB_L1_CODE_START
&&
665 (unsigned int)(mem
+ count
) <=
666 COREB_L1_CODE_START
+ L1_CODE_LENGTH
669 /* access L1 instruction SRAM */
670 if (dma_memcpy(mem
, buf
, size
) == NULL
)
673 err
= probe_kernel_write(mem
, buf
, size
);
679 * Convert the hex array pointed to by buf into binary to be placed in mem.
680 * Return a pointer to the character AFTER the last byte written.
681 * May return an error.
683 int kgdb_hex2mem(char *buf
, char *mem
, int count
)
687 unsigned short *mmr16
;
688 unsigned long *mmr32
;
689 int cpu
= raw_smp_processor_id();
691 if (validate_memory_access_address((unsigned long)mem
, count
))
695 * We use the upper half of buf as an intermediate buffer for the
696 * raw memory that is converted from hex.
698 tmp_raw
= buf
+ count
* 2;
700 tmp_hex
= tmp_raw
- 1;
701 while (tmp_hex
>= buf
) {
703 *tmp_raw
= hex(*tmp_hex
--);
704 *tmp_raw
|= hex(*tmp_hex
--) << 4;
707 if ((unsigned int)mem
>= SYSMMR_BASE
) { /*access MMR registers*/
710 if ((unsigned int)mem
% 2 == 0) {
711 mmr16
= (unsigned short *)tmp_raw
;
712 *(unsigned short *)mem
= *mmr16
;
717 if ((unsigned int)mem
% 4 == 0) {
718 mmr32
= (unsigned long *)tmp_raw
;
719 *(unsigned long *)mem
= *mmr32
;
726 } else if (cpu
== 0 && (unsigned int)mem
>= L1_CODE_START
&&
727 (unsigned int)(mem
+ count
) <= L1_CODE_START
+ L1_CODE_LENGTH
729 || cpu
== 1 && (unsigned int)mem
>= COREB_L1_CODE_START
&&
730 (unsigned int)(mem
+ count
) <=
731 COREB_L1_CODE_START
+ L1_CODE_LENGTH
734 /* access L1 instruction SRAM */
735 if (dma_memcpy(mem
, tmp_raw
, count
) == NULL
)
738 return probe_kernel_write(mem
, tmp_raw
, count
);
742 int kgdb_validate_break_address(unsigned long addr
)
744 int cpu
= raw_smp_processor_id();
746 if (addr
>= 0x1000 && (addr
+ BREAK_INSTR_SIZE
) <= physical_mem_end
)
748 if (addr
>= ASYNC_BANK0_BASE
749 && addr
+ BREAK_INSTR_SIZE
<= ASYNC_BANK3_BASE
+ ASYNC_BANK3_BASE
)
751 #if L1_CODE_LENGTH != 0
752 if (cpu
== 0 && addr
>= L1_CODE_START
753 && addr
+ BREAK_INSTR_SIZE
<= L1_CODE_START
+ L1_CODE_LENGTH
)
756 else if (cpu
== 1 && addr
>= COREB_L1_CODE_START
757 && addr
+ BREAK_INSTR_SIZE
<= COREB_L1_CODE_START
+ L1_CODE_LENGTH
)
763 && addr
+ BREAK_INSTR_SIZE
<= L2_START
+ L2_LENGTH
)
770 int kgdb_arch_set_breakpoint(unsigned long addr
, char *saved_instr
)
773 int cpu
= raw_smp_processor_id();
775 if ((cpu
== 0 && (unsigned int)addr
>= L1_CODE_START
776 && (unsigned int)(addr
+ BREAK_INSTR_SIZE
)
777 < L1_CODE_START
+ L1_CODE_LENGTH
)
779 || (cpu
== 1 && (unsigned int)addr
>= COREB_L1_CODE_START
780 && (unsigned int)(addr
+ BREAK_INSTR_SIZE
)
781 < COREB_L1_CODE_START
+ L1_CODE_LENGTH
)
784 /* access L1 instruction SRAM */
785 if (dma_memcpy(saved_instr
, (void *)addr
, BREAK_INSTR_SIZE
)
789 if (dma_memcpy((void *)addr
, arch_kgdb_ops
.gdb_bpt_instr
,
790 BREAK_INSTR_SIZE
) == NULL
)
795 err
= probe_kernel_read(saved_instr
, (char *)addr
,
800 return probe_kernel_write((char *)addr
,
801 arch_kgdb_ops
.gdb_bpt_instr
, BREAK_INSTR_SIZE
);
805 int kgdb_arch_remove_breakpoint(unsigned long addr
, char *bundle
)
807 if ((unsigned int)addr
>= L1_CODE_START
&&
808 (unsigned int)(addr
+ BREAK_INSTR_SIZE
) <
809 L1_CODE_START
+ L1_CODE_LENGTH
) {
810 /* access L1 instruction SRAM */
811 if (dma_memcpy((void *)addr
, bundle
, BREAK_INSTR_SIZE
) == NULL
)
816 return probe_kernel_write((char *)addr
,
817 (char *)bundle
, BREAK_INSTR_SIZE
);
820 int kgdb_arch_init(void)
822 kgdb_single_step
= 0;
824 bfin_remove_all_hw_break();
828 void kgdb_arch_exit(void)