iwlwifi: rename generic iwlagn functions that had a HW specific name
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / starfire.c
blob0358809f409c8d8522d983fd54966b54be78b5ef
1 /* starfire.c: Linux device driver for the Adaptec Starfire network adapter. */
2 /*
3 Written 1998-2000 by Donald Becker.
5 Current maintainer is Ion Badulescu <ionut ta badula tod org>. Please
6 send all bug reports to me, and not to Donald Becker, as this code
7 has been heavily modified from Donald's original version.
9 This software may be used and distributed according to the terms of
10 the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on or derived from this code fall under the GPL and must
12 retain the authorship, copyright and license notice. This file is not
13 a complete program and may only be used when the entire operating
14 system is licensed under the GPL.
16 The information below comes from Donald Becker's original driver:
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
21 Annapolis MD 21403
23 Support and updates available at
24 http://www.scyld.com/network/starfire.html
25 [link no longer provides useful info -jgarzik]
29 #define DRV_NAME "starfire"
30 #define DRV_VERSION "2.1"
31 #define DRV_RELDATE "July 6, 2008"
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/crc32.h>
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/if_vlan.h>
44 #include <linux/mm.h>
45 #include <asm/processor.h> /* Processor type for cache alignment. */
46 #include <asm/uaccess.h>
47 #include <asm/io.h>
49 #include "starfire_firmware.h"
51 * The current frame processor firmware fails to checksum a fragment
52 * of length 1. If and when this is fixed, the #define below can be removed.
54 #define HAS_BROKEN_FIRMWARE
57 * If using the broken firmware, data must be padded to the next 32-bit boundary.
59 #ifdef HAS_BROKEN_FIRMWARE
60 #define PADDING_MASK 3
61 #endif
64 * Define this if using the driver with the zero-copy patch
66 #define ZEROCOPY
68 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
69 #define VLAN_SUPPORT
70 #endif
72 /* The user-configurable values.
73 These may be modified when a driver module is loaded.*/
75 /* Used for tuning interrupt latency vs. overhead. */
76 static int intr_latency;
77 static int small_frames;
79 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
80 static int max_interrupt_work = 20;
81 static int mtu;
82 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
83 The Starfire has a 512 element hash table based on the Ethernet CRC. */
84 static const int multicast_filter_limit = 512;
85 /* Whether to do TCP/UDP checksums in hardware */
86 static int enable_hw_cksum = 1;
88 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
90 * Set the copy breakpoint for the copy-only-tiny-frames scheme.
91 * Setting to > 1518 effectively disables this feature.
93 * NOTE:
94 * The ia64 doesn't allow for unaligned loads even of integers being
95 * misaligned on a 2 byte boundary. Thus always force copying of
96 * packets as the starfire doesn't allow for misaligned DMAs ;-(
97 * 23/10/2000 - Jes
99 * The Alpha and the Sparc don't like unaligned loads, either. On Sparc64,
100 * at least, having unaligned frames leads to a rather serious performance
101 * penalty. -Ion
103 #if defined(__ia64__) || defined(__alpha__) || defined(__sparc__)
104 static int rx_copybreak = PKT_BUF_SZ;
105 #else
106 static int rx_copybreak /* = 0 */;
107 #endif
109 /* PCI DMA burst size -- on sparc64 we want to force it to 64 bytes, on the others the default of 128 is fine. */
110 #ifdef __sparc__
111 #define DMA_BURST_SIZE 64
112 #else
113 #define DMA_BURST_SIZE 128
114 #endif
116 /* Used to pass the media type, etc.
117 Both 'options[]' and 'full_duplex[]' exist for driver interoperability.
118 The media type is usually passed in 'options[]'.
119 These variables are deprecated, use ethtool instead. -Ion
121 #define MAX_UNITS 8 /* More are supported, limit only on options */
122 static int options[MAX_UNITS] = {0, };
123 static int full_duplex[MAX_UNITS] = {0, };
125 /* Operational parameters that are set at compile time. */
127 /* The "native" ring sizes are either 256 or 2048.
128 However in some modes a descriptor may be marked to wrap the ring earlier.
130 #define RX_RING_SIZE 256
131 #define TX_RING_SIZE 32
132 /* The completion queues are fixed at 1024 entries i.e. 4K or 8KB. */
133 #define DONE_Q_SIZE 1024
134 /* All queues must be aligned on a 256-byte boundary */
135 #define QUEUE_ALIGN 256
137 #if RX_RING_SIZE > 256
138 #define RX_Q_ENTRIES Rx2048QEntries
139 #else
140 #define RX_Q_ENTRIES Rx256QEntries
141 #endif
143 /* Operational parameters that usually are not changed. */
144 /* Time in jiffies before concluding the transmitter is hung. */
145 #define TX_TIMEOUT (2 * HZ)
148 * This SUCKS.
149 * We need a much better method to determine if dma_addr_t is 64-bit.
151 #if (defined(__i386__) && defined(CONFIG_HIGHMEM64G)) || defined(__x86_64__) || defined (__ia64__) || defined(__alpha__) || defined(__mips64__) || (defined(__mips__) && defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR))
152 /* 64-bit dma_addr_t */
153 #define ADDR_64BITS /* This chip uses 64 bit addresses. */
154 #define netdrv_addr_t __le64
155 #define cpu_to_dma(x) cpu_to_le64(x)
156 #define dma_to_cpu(x) le64_to_cpu(x)
157 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit
158 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr64bit
159 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr64bit
160 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit
161 #define RX_DESC_ADDR_SIZE RxDescAddr64bit
162 #else /* 32-bit dma_addr_t */
163 #define netdrv_addr_t __le32
164 #define cpu_to_dma(x) cpu_to_le32(x)
165 #define dma_to_cpu(x) le32_to_cpu(x)
166 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit
167 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr32bit
168 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr32bit
169 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr32bit
170 #define RX_DESC_ADDR_SIZE RxDescAddr32bit
171 #endif
173 #define skb_first_frag_len(skb) skb_headlen(skb)
174 #define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1)
176 /* These identify the driver base version and may not be removed. */
177 static char version[] =
178 KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n"
179 KERN_INFO " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
181 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
182 MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver");
183 MODULE_LICENSE("GPL");
184 MODULE_VERSION(DRV_VERSION);
186 module_param(max_interrupt_work, int, 0);
187 module_param(mtu, int, 0);
188 module_param(debug, int, 0);
189 module_param(rx_copybreak, int, 0);
190 module_param(intr_latency, int, 0);
191 module_param(small_frames, int, 0);
192 module_param_array(options, int, NULL, 0);
193 module_param_array(full_duplex, int, NULL, 0);
194 module_param(enable_hw_cksum, int, 0);
195 MODULE_PARM_DESC(max_interrupt_work, "Maximum events handled per interrupt");
196 MODULE_PARM_DESC(mtu, "MTU (all boards)");
197 MODULE_PARM_DESC(debug, "Debug level (0-6)");
198 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
199 MODULE_PARM_DESC(intr_latency, "Maximum interrupt latency, in microseconds");
200 MODULE_PARM_DESC(small_frames, "Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)");
201 MODULE_PARM_DESC(options, "Deprecated: Bits 0-3: media type, bit 17: full duplex");
202 MODULE_PARM_DESC(full_duplex, "Deprecated: Forced full-duplex setting (0/1)");
203 MODULE_PARM_DESC(enable_hw_cksum, "Enable/disable hardware cksum support (0/1)");
206 Theory of Operation
208 I. Board Compatibility
210 This driver is for the Adaptec 6915 "Starfire" 64 bit PCI Ethernet adapter.
212 II. Board-specific settings
214 III. Driver operation
216 IIIa. Ring buffers
218 The Starfire hardware uses multiple fixed-size descriptor queues/rings. The
219 ring sizes are set fixed by the hardware, but may optionally be wrapped
220 earlier by the END bit in the descriptor.
221 This driver uses that hardware queue size for the Rx ring, where a large
222 number of entries has no ill effect beyond increases the potential backlog.
223 The Tx ring is wrapped with the END bit, since a large hardware Tx queue
224 disables the queue layer priority ordering and we have no mechanism to
225 utilize the hardware two-level priority queue. When modifying the
226 RX/TX_RING_SIZE pay close attention to page sizes and the ring-empty warning
227 levels.
229 IIIb/c. Transmit/Receive Structure
231 See the Adaptec manual for the many possible structures, and options for
232 each structure. There are far too many to document all of them here.
234 For transmit this driver uses type 0/1 transmit descriptors (depending
235 on the 32/64 bitness of the architecture), and relies on automatic
236 minimum-length padding. It does not use the completion queue
237 consumer index, but instead checks for non-zero status entries.
239 For receive this driver uses type 2/3 receive descriptors. The driver
240 allocates full frame size skbuffs for the Rx ring buffers, so all frames
241 should fit in a single descriptor. The driver does not use the completion
242 queue consumer index, but instead checks for non-zero status entries.
244 When an incoming frame is less than RX_COPYBREAK bytes long, a fresh skbuff
245 is allocated and the frame is copied to the new skbuff. When the incoming
246 frame is larger, the skbuff is passed directly up the protocol stack.
247 Buffers consumed this way are replaced by newly allocated skbuffs in a later
248 phase of receive.
250 A notable aspect of operation is that unaligned buffers are not permitted by
251 the Starfire hardware. Thus the IP header at offset 14 in an ethernet frame
252 isn't longword aligned, which may cause problems on some machine
253 e.g. Alphas and IA64. For these architectures, the driver is forced to copy
254 the frame into a new skbuff unconditionally. Copied frames are put into the
255 skbuff at an offset of "+2", thus 16-byte aligning the IP header.
257 IIId. Synchronization
259 The driver runs as two independent, single-threaded flows of control. One
260 is the send-packet routine, which enforces single-threaded use by the
261 dev->tbusy flag. The other thread is the interrupt handler, which is single
262 threaded by the hardware and interrupt handling software.
264 The send packet thread has partial control over the Tx ring and the netif_queue
265 status. If the number of free Tx slots in the ring falls below a certain number
266 (currently hardcoded to 4), it signals the upper layer to stop the queue.
268 The interrupt handler has exclusive control over the Rx ring and records stats
269 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
270 empty by incrementing the dirty_tx mark. Iff the netif_queue is stopped and the
271 number of free Tx slow is above the threshold, it signals the upper layer to
272 restart the queue.
274 IV. Notes
276 IVb. References
278 The Adaptec Starfire manuals, available only from Adaptec.
279 http://www.scyld.com/expert/100mbps.html
280 http://www.scyld.com/expert/NWay.html
282 IVc. Errata
284 - StopOnPerr is broken, don't enable
285 - Hardware ethernet padding exposes random data, perform software padding
286 instead (unverified -- works correctly for all the hardware I have)
292 enum chip_capability_flags {CanHaveMII=1, };
294 enum chipset {
295 CH_6915 = 0,
298 static struct pci_device_id starfire_pci_tbl[] = {
299 { 0x9004, 0x6915, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_6915 },
300 { 0, }
302 MODULE_DEVICE_TABLE(pci, starfire_pci_tbl);
304 /* A chip capabilities table, matching the CH_xxx entries in xxx_pci_tbl[] above. */
305 static const struct chip_info {
306 const char *name;
307 int drv_flags;
308 } netdrv_tbl[] __devinitdata = {
309 { "Adaptec Starfire 6915", CanHaveMII },
313 /* Offsets to the device registers.
314 Unlike software-only systems, device drivers interact with complex hardware.
315 It's not useful to define symbolic names for every register bit in the
316 device. The name can only partially document the semantics and make
317 the driver longer and more difficult to read.
318 In general, only the important configuration values or bits changed
319 multiple times should be defined symbolically.
321 enum register_offsets {
322 PCIDeviceConfig=0x50040, GenCtrl=0x50070, IntrTimerCtrl=0x50074,
323 IntrClear=0x50080, IntrStatus=0x50084, IntrEnable=0x50088,
324 MIICtrl=0x52000, TxStationAddr=0x50120, EEPROMCtrl=0x51000,
325 GPIOCtrl=0x5008C, TxDescCtrl=0x50090,
326 TxRingPtr=0x50098, HiPriTxRingPtr=0x50094, /* Low and High priority. */
327 TxRingHiAddr=0x5009C, /* 64 bit address extension. */
328 TxProducerIdx=0x500A0, TxConsumerIdx=0x500A4,
329 TxThreshold=0x500B0,
330 CompletionHiAddr=0x500B4, TxCompletionAddr=0x500B8,
331 RxCompletionAddr=0x500BC, RxCompletionQ2Addr=0x500C0,
332 CompletionQConsumerIdx=0x500C4, RxDMACtrl=0x500D0,
333 RxDescQCtrl=0x500D4, RxDescQHiAddr=0x500DC, RxDescQAddr=0x500E0,
334 RxDescQIdx=0x500E8, RxDMAStatus=0x500F0, RxFilterMode=0x500F4,
335 TxMode=0x55000, VlanType=0x55064,
336 PerfFilterTable=0x56000, HashTable=0x56100,
337 TxGfpMem=0x58000, RxGfpMem=0x5a000,
341 * Bits in the interrupt status/mask registers.
342 * Warning: setting Intr[Ab]NormalSummary in the IntrEnable register
343 * enables all the interrupt sources that are or'ed into those status bits.
345 enum intr_status_bits {
346 IntrLinkChange=0xf0000000, IntrStatsMax=0x08000000,
347 IntrAbnormalSummary=0x02000000, IntrGeneralTimer=0x01000000,
348 IntrSoftware=0x800000, IntrRxComplQ1Low=0x400000,
349 IntrTxComplQLow=0x200000, IntrPCI=0x100000,
350 IntrDMAErr=0x080000, IntrTxDataLow=0x040000,
351 IntrRxComplQ2Low=0x020000, IntrRxDescQ1Low=0x010000,
352 IntrNormalSummary=0x8000, IntrTxDone=0x4000,
353 IntrTxDMADone=0x2000, IntrTxEmpty=0x1000,
354 IntrEarlyRxQ2=0x0800, IntrEarlyRxQ1=0x0400,
355 IntrRxQ2Done=0x0200, IntrRxQ1Done=0x0100,
356 IntrRxGFPDead=0x80, IntrRxDescQ2Low=0x40,
357 IntrNoTxCsum=0x20, IntrTxBadID=0x10,
358 IntrHiPriTxBadID=0x08, IntrRxGfp=0x04,
359 IntrTxGfp=0x02, IntrPCIPad=0x01,
360 /* not quite bits */
361 IntrRxDone=IntrRxQ2Done | IntrRxQ1Done,
362 IntrRxEmpty=IntrRxDescQ1Low | IntrRxDescQ2Low,
363 IntrNormalMask=0xff00, IntrAbnormalMask=0x3ff00fe,
366 /* Bits in the RxFilterMode register. */
367 enum rx_mode_bits {
368 AcceptBroadcast=0x04, AcceptAllMulticast=0x02, AcceptAll=0x01,
369 AcceptMulticast=0x10, PerfectFilter=0x40, HashFilter=0x30,
370 PerfectFilterVlan=0x80, MinVLANPrio=0xE000, VlanMode=0x0200,
371 WakeupOnGFP=0x0800,
374 /* Bits in the TxMode register */
375 enum tx_mode_bits {
376 MiiSoftReset=0x8000, MIILoopback=0x4000,
377 TxFlowEnable=0x0800, RxFlowEnable=0x0400,
378 PadEnable=0x04, FullDuplex=0x02, HugeFrame=0x01,
381 /* Bits in the TxDescCtrl register. */
382 enum tx_ctrl_bits {
383 TxDescSpaceUnlim=0x00, TxDescSpace32=0x10, TxDescSpace64=0x20,
384 TxDescSpace128=0x30, TxDescSpace256=0x40,
385 TxDescType0=0x00, TxDescType1=0x01, TxDescType2=0x02,
386 TxDescType3=0x03, TxDescType4=0x04,
387 TxNoDMACompletion=0x08,
388 TxDescQAddr64bit=0x80, TxDescQAddr32bit=0,
389 TxHiPriFIFOThreshShift=24, TxPadLenShift=16,
390 TxDMABurstSizeShift=8,
393 /* Bits in the RxDescQCtrl register. */
394 enum rx_ctrl_bits {
395 RxBufferLenShift=16, RxMinDescrThreshShift=0,
396 RxPrefetchMode=0x8000, RxVariableQ=0x2000,
397 Rx2048QEntries=0x4000, Rx256QEntries=0,
398 RxDescAddr64bit=0x1000, RxDescAddr32bit=0,
399 RxDescQAddr64bit=0x0100, RxDescQAddr32bit=0,
400 RxDescSpace4=0x000, RxDescSpace8=0x100,
401 RxDescSpace16=0x200, RxDescSpace32=0x300,
402 RxDescSpace64=0x400, RxDescSpace128=0x500,
403 RxConsumerWrEn=0x80,
406 /* Bits in the RxDMACtrl register. */
407 enum rx_dmactrl_bits {
408 RxReportBadFrames=0x80000000, RxDMAShortFrames=0x40000000,
409 RxDMABadFrames=0x20000000, RxDMACrcErrorFrames=0x10000000,
410 RxDMAControlFrame=0x08000000, RxDMAPauseFrame=0x04000000,
411 RxChecksumIgnore=0, RxChecksumRejectTCPUDP=0x02000000,
412 RxChecksumRejectTCPOnly=0x01000000,
413 RxCompletionQ2Enable=0x800000,
414 RxDMAQ2Disable=0, RxDMAQ2FPOnly=0x100000,
415 RxDMAQ2SmallPkt=0x200000, RxDMAQ2HighPrio=0x300000,
416 RxDMAQ2NonIP=0x400000,
417 RxUseBackupQueue=0x080000, RxDMACRC=0x040000,
418 RxEarlyIntThreshShift=12, RxHighPrioThreshShift=8,
419 RxBurstSizeShift=0,
422 /* Bits in the RxCompletionAddr register */
423 enum rx_compl_bits {
424 RxComplQAddr64bit=0x80, RxComplQAddr32bit=0,
425 RxComplProducerWrEn=0x40,
426 RxComplType0=0x00, RxComplType1=0x10,
427 RxComplType2=0x20, RxComplType3=0x30,
428 RxComplThreshShift=0,
431 /* Bits in the TxCompletionAddr register */
432 enum tx_compl_bits {
433 TxComplQAddr64bit=0x80, TxComplQAddr32bit=0,
434 TxComplProducerWrEn=0x40,
435 TxComplIntrStatus=0x20,
436 CommonQueueMode=0x10,
437 TxComplThreshShift=0,
440 /* Bits in the GenCtrl register */
441 enum gen_ctrl_bits {
442 RxEnable=0x05, TxEnable=0x0a,
443 RxGFPEnable=0x10, TxGFPEnable=0x20,
446 /* Bits in the IntrTimerCtrl register */
447 enum intr_ctrl_bits {
448 Timer10X=0x800, EnableIntrMasking=0x60, SmallFrameBypass=0x100,
449 SmallFrame64=0, SmallFrame128=0x200, SmallFrame256=0x400, SmallFrame512=0x600,
450 IntrLatencyMask=0x1f,
453 /* The Rx and Tx buffer descriptors. */
454 struct starfire_rx_desc {
455 netdrv_addr_t rxaddr;
457 enum rx_desc_bits {
458 RxDescValid=1, RxDescEndRing=2,
461 /* Completion queue entry. */
462 struct short_rx_done_desc {
463 __le32 status; /* Low 16 bits is length. */
465 struct basic_rx_done_desc {
466 __le32 status; /* Low 16 bits is length. */
467 __le16 vlanid;
468 __le16 status2;
470 struct csum_rx_done_desc {
471 __le32 status; /* Low 16 bits is length. */
472 __le16 csum; /* Partial checksum */
473 __le16 status2;
475 struct full_rx_done_desc {
476 __le32 status; /* Low 16 bits is length. */
477 __le16 status3;
478 __le16 status2;
479 __le16 vlanid;
480 __le16 csum; /* partial checksum */
481 __le32 timestamp;
483 /* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */
484 #ifdef VLAN_SUPPORT
485 typedef struct full_rx_done_desc rx_done_desc;
486 #define RxComplType RxComplType3
487 #else /* not VLAN_SUPPORT */
488 typedef struct csum_rx_done_desc rx_done_desc;
489 #define RxComplType RxComplType2
490 #endif /* not VLAN_SUPPORT */
492 enum rx_done_bits {
493 RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000,
496 /* Type 1 Tx descriptor. */
497 struct starfire_tx_desc_1 {
498 __le32 status; /* Upper bits are status, lower 16 length. */
499 __le32 addr;
502 /* Type 2 Tx descriptor. */
503 struct starfire_tx_desc_2 {
504 __le32 status; /* Upper bits are status, lower 16 length. */
505 __le32 reserved;
506 __le64 addr;
509 #ifdef ADDR_64BITS
510 typedef struct starfire_tx_desc_2 starfire_tx_desc;
511 #define TX_DESC_TYPE TxDescType2
512 #else /* not ADDR_64BITS */
513 typedef struct starfire_tx_desc_1 starfire_tx_desc;
514 #define TX_DESC_TYPE TxDescType1
515 #endif /* not ADDR_64BITS */
516 #define TX_DESC_SPACING TxDescSpaceUnlim
518 enum tx_desc_bits {
519 TxDescID=0xB0000000,
520 TxCRCEn=0x01000000, TxDescIntr=0x08000000,
521 TxRingWrap=0x04000000, TxCalTCP=0x02000000,
523 struct tx_done_desc {
524 __le32 status; /* timestamp, index. */
525 #if 0
526 __le32 intrstatus; /* interrupt status */
527 #endif
530 struct rx_ring_info {
531 struct sk_buff *skb;
532 dma_addr_t mapping;
534 struct tx_ring_info {
535 struct sk_buff *skb;
536 dma_addr_t mapping;
537 unsigned int used_slots;
540 #define PHY_CNT 2
541 struct netdev_private {
542 /* Descriptor rings first for alignment. */
543 struct starfire_rx_desc *rx_ring;
544 starfire_tx_desc *tx_ring;
545 dma_addr_t rx_ring_dma;
546 dma_addr_t tx_ring_dma;
547 /* The addresses of rx/tx-in-place skbuffs. */
548 struct rx_ring_info rx_info[RX_RING_SIZE];
549 struct tx_ring_info tx_info[TX_RING_SIZE];
550 /* Pointers to completion queues (full pages). */
551 rx_done_desc *rx_done_q;
552 dma_addr_t rx_done_q_dma;
553 unsigned int rx_done;
554 struct tx_done_desc *tx_done_q;
555 dma_addr_t tx_done_q_dma;
556 unsigned int tx_done;
557 struct napi_struct napi;
558 struct net_device *dev;
559 struct net_device_stats stats;
560 struct pci_dev *pci_dev;
561 #ifdef VLAN_SUPPORT
562 struct vlan_group *vlgrp;
563 #endif
564 void *queue_mem;
565 dma_addr_t queue_mem_dma;
566 size_t queue_mem_size;
568 /* Frequently used values: keep some adjacent for cache effect. */
569 spinlock_t lock;
570 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
571 unsigned int cur_tx, dirty_tx, reap_tx;
572 unsigned int rx_buf_sz; /* Based on MTU+slack. */
573 /* These values keep track of the transceiver/media in use. */
574 int speed100; /* Set if speed == 100MBit. */
575 u32 tx_mode;
576 u32 intr_timer_ctrl;
577 u8 tx_threshold;
578 /* MII transceiver section. */
579 struct mii_if_info mii_if; /* MII lib hooks/info */
580 int phy_cnt; /* MII device addresses. */
581 unsigned char phys[PHY_CNT]; /* MII device addresses. */
582 void __iomem *base;
586 static int mdio_read(struct net_device *dev, int phy_id, int location);
587 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
588 static int netdev_open(struct net_device *dev);
589 static void check_duplex(struct net_device *dev);
590 static void tx_timeout(struct net_device *dev);
591 static void init_ring(struct net_device *dev);
592 static int start_tx(struct sk_buff *skb, struct net_device *dev);
593 static irqreturn_t intr_handler(int irq, void *dev_instance);
594 static void netdev_error(struct net_device *dev, int intr_status);
595 static int __netdev_rx(struct net_device *dev, int *quota);
596 static int netdev_poll(struct napi_struct *napi, int budget);
597 static void refill_rx_ring(struct net_device *dev);
598 static void netdev_error(struct net_device *dev, int intr_status);
599 static void set_rx_mode(struct net_device *dev);
600 static struct net_device_stats *get_stats(struct net_device *dev);
601 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
602 static int netdev_close(struct net_device *dev);
603 static void netdev_media_change(struct net_device *dev);
604 static const struct ethtool_ops ethtool_ops;
607 #ifdef VLAN_SUPPORT
608 static void netdev_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
610 struct netdev_private *np = netdev_priv(dev);
612 spin_lock(&np->lock);
613 if (debug > 2)
614 printk("%s: Setting vlgrp to %p\n", dev->name, grp);
615 np->vlgrp = grp;
616 set_rx_mode(dev);
617 spin_unlock(&np->lock);
620 static void netdev_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
622 struct netdev_private *np = netdev_priv(dev);
624 spin_lock(&np->lock);
625 if (debug > 1)
626 printk("%s: Adding vlanid %d to vlan filter\n", dev->name, vid);
627 set_rx_mode(dev);
628 spin_unlock(&np->lock);
631 static void netdev_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
633 struct netdev_private *np = netdev_priv(dev);
635 spin_lock(&np->lock);
636 if (debug > 1)
637 printk("%s: removing vlanid %d from vlan filter\n", dev->name, vid);
638 vlan_group_set_device(np->vlgrp, vid, NULL);
639 set_rx_mode(dev);
640 spin_unlock(&np->lock);
642 #endif /* VLAN_SUPPORT */
645 static int __devinit starfire_init_one(struct pci_dev *pdev,
646 const struct pci_device_id *ent)
648 struct netdev_private *np;
649 int i, irq, option, chip_idx = ent->driver_data;
650 struct net_device *dev;
651 static int card_idx = -1;
652 long ioaddr;
653 void __iomem *base;
654 int drv_flags, io_size;
655 int boguscnt;
657 /* when built into the kernel, we only print version if device is found */
658 #ifndef MODULE
659 static int printed_version;
660 if (!printed_version++)
661 printk(version);
662 #endif
664 card_idx++;
666 if (pci_enable_device (pdev))
667 return -EIO;
669 ioaddr = pci_resource_start(pdev, 0);
670 io_size = pci_resource_len(pdev, 0);
671 if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_MEM) == 0)) {
672 printk(KERN_ERR DRV_NAME " %d: no PCI MEM resources, aborting\n", card_idx);
673 return -ENODEV;
676 dev = alloc_etherdev(sizeof(*np));
677 if (!dev) {
678 printk(KERN_ERR DRV_NAME " %d: cannot alloc etherdev, aborting\n", card_idx);
679 return -ENOMEM;
681 SET_NETDEV_DEV(dev, &pdev->dev);
683 irq = pdev->irq;
685 if (pci_request_regions (pdev, DRV_NAME)) {
686 printk(KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", card_idx);
687 goto err_out_free_netdev;
690 base = ioremap(ioaddr, io_size);
691 if (!base) {
692 printk(KERN_ERR DRV_NAME " %d: cannot remap %#x @ %#lx, aborting\n",
693 card_idx, io_size, ioaddr);
694 goto err_out_free_res;
697 pci_set_master(pdev);
699 /* enable MWI -- it vastly improves Rx performance on sparc64 */
700 pci_try_set_mwi(pdev);
702 #ifdef ZEROCOPY
703 /* Starfire can do TCP/UDP checksumming */
704 if (enable_hw_cksum)
705 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
706 #endif /* ZEROCOPY */
707 #ifdef VLAN_SUPPORT
708 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
709 dev->vlan_rx_register = netdev_vlan_rx_register;
710 dev->vlan_rx_add_vid = netdev_vlan_rx_add_vid;
711 dev->vlan_rx_kill_vid = netdev_vlan_rx_kill_vid;
712 #endif /* VLAN_RX_KILL_VID */
713 #ifdef ADDR_64BITS
714 dev->features |= NETIF_F_HIGHDMA;
715 #endif /* ADDR_64BITS */
717 /* Serial EEPROM reads are hidden by the hardware. */
718 for (i = 0; i < 6; i++)
719 dev->dev_addr[i] = readb(base + EEPROMCtrl + 20 - i);
721 #if ! defined(final_version) /* Dump the EEPROM contents during development. */
722 if (debug > 4)
723 for (i = 0; i < 0x20; i++)
724 printk("%2.2x%s",
725 (unsigned int)readb(base + EEPROMCtrl + i),
726 i % 16 != 15 ? " " : "\n");
727 #endif
729 /* Issue soft reset */
730 writel(MiiSoftReset, base + TxMode);
731 udelay(1000);
732 writel(0, base + TxMode);
734 /* Reset the chip to erase previous misconfiguration. */
735 writel(1, base + PCIDeviceConfig);
736 boguscnt = 1000;
737 while (--boguscnt > 0) {
738 udelay(10);
739 if ((readl(base + PCIDeviceConfig) & 1) == 0)
740 break;
742 if (boguscnt == 0)
743 printk("%s: chipset reset never completed!\n", dev->name);
744 /* wait a little longer */
745 udelay(1000);
747 dev->base_addr = (unsigned long)base;
748 dev->irq = irq;
750 np = netdev_priv(dev);
751 np->dev = dev;
752 np->base = base;
753 spin_lock_init(&np->lock);
754 pci_set_drvdata(pdev, dev);
756 np->pci_dev = pdev;
758 np->mii_if.dev = dev;
759 np->mii_if.mdio_read = mdio_read;
760 np->mii_if.mdio_write = mdio_write;
761 np->mii_if.phy_id_mask = 0x1f;
762 np->mii_if.reg_num_mask = 0x1f;
764 drv_flags = netdrv_tbl[chip_idx].drv_flags;
766 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
767 if (dev->mem_start)
768 option = dev->mem_start;
770 /* The lower four bits are the media type. */
771 if (option & 0x200)
772 np->mii_if.full_duplex = 1;
774 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
775 np->mii_if.full_duplex = 1;
777 if (np->mii_if.full_duplex)
778 np->mii_if.force_media = 1;
779 else
780 np->mii_if.force_media = 0;
781 np->speed100 = 1;
783 /* timer resolution is 128 * 0.8us */
784 np->intr_timer_ctrl = (((intr_latency * 10) / 1024) & IntrLatencyMask) |
785 Timer10X | EnableIntrMasking;
787 if (small_frames > 0) {
788 np->intr_timer_ctrl |= SmallFrameBypass;
789 switch (small_frames) {
790 case 1 ... 64:
791 np->intr_timer_ctrl |= SmallFrame64;
792 break;
793 case 65 ... 128:
794 np->intr_timer_ctrl |= SmallFrame128;
795 break;
796 case 129 ... 256:
797 np->intr_timer_ctrl |= SmallFrame256;
798 break;
799 default:
800 np->intr_timer_ctrl |= SmallFrame512;
801 if (small_frames > 512)
802 printk("Adjusting small_frames down to 512\n");
803 break;
807 /* The chip-specific entries in the device structure. */
808 dev->open = &netdev_open;
809 dev->hard_start_xmit = &start_tx;
810 dev->tx_timeout = tx_timeout;
811 dev->watchdog_timeo = TX_TIMEOUT;
812 netif_napi_add(dev, &np->napi, netdev_poll, max_interrupt_work);
813 dev->stop = &netdev_close;
814 dev->get_stats = &get_stats;
815 dev->set_multicast_list = &set_rx_mode;
816 dev->do_ioctl = &netdev_ioctl;
817 SET_ETHTOOL_OPS(dev, &ethtool_ops);
819 if (mtu)
820 dev->mtu = mtu;
822 if (register_netdev(dev))
823 goto err_out_cleardev;
825 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
826 dev->name, netdrv_tbl[chip_idx].name, base,
827 dev->dev_addr, irq);
829 if (drv_flags & CanHaveMII) {
830 int phy, phy_idx = 0;
831 int mii_status;
832 for (phy = 0; phy < 32 && phy_idx < PHY_CNT; phy++) {
833 mdio_write(dev, phy, MII_BMCR, BMCR_RESET);
834 mdelay(100);
835 boguscnt = 1000;
836 while (--boguscnt > 0)
837 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0)
838 break;
839 if (boguscnt == 0) {
840 printk("%s: PHY#%d reset never completed!\n", dev->name, phy);
841 continue;
843 mii_status = mdio_read(dev, phy, MII_BMSR);
844 if (mii_status != 0) {
845 np->phys[phy_idx++] = phy;
846 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
847 printk(KERN_INFO "%s: MII PHY found at address %d, status "
848 "%#4.4x advertising %#4.4x.\n",
849 dev->name, phy, mii_status, np->mii_if.advertising);
850 /* there can be only one PHY on-board */
851 break;
854 np->phy_cnt = phy_idx;
855 if (np->phy_cnt > 0)
856 np->mii_if.phy_id = np->phys[0];
857 else
858 memset(&np->mii_if, 0, sizeof(np->mii_if));
861 printk(KERN_INFO "%s: scatter-gather and hardware TCP cksumming %s.\n",
862 dev->name, enable_hw_cksum ? "enabled" : "disabled");
863 return 0;
865 err_out_cleardev:
866 pci_set_drvdata(pdev, NULL);
867 iounmap(base);
868 err_out_free_res:
869 pci_release_regions (pdev);
870 err_out_free_netdev:
871 free_netdev(dev);
872 return -ENODEV;
876 /* Read the MII Management Data I/O (MDIO) interfaces. */
877 static int mdio_read(struct net_device *dev, int phy_id, int location)
879 struct netdev_private *np = netdev_priv(dev);
880 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
881 int result, boguscnt=1000;
882 /* ??? Should we add a busy-wait here? */
884 result = readl(mdio_addr);
885 while ((result & 0xC0000000) != 0x80000000 && --boguscnt > 0);
886 if (boguscnt == 0)
887 return 0;
888 if ((result & 0xffff) == 0xffff)
889 return 0;
890 return result & 0xffff;
894 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
896 struct netdev_private *np = netdev_priv(dev);
897 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
898 writel(value, mdio_addr);
899 /* The busy-wait will occur before a read. */
903 static int netdev_open(struct net_device *dev)
905 struct netdev_private *np = netdev_priv(dev);
906 void __iomem *ioaddr = np->base;
907 int i, retval;
908 size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size;
910 /* Do we ever need to reset the chip??? */
912 retval = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
913 if (retval)
914 return retval;
916 /* Disable the Rx and Tx, and reset the chip. */
917 writel(0, ioaddr + GenCtrl);
918 writel(1, ioaddr + PCIDeviceConfig);
919 if (debug > 1)
920 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
921 dev->name, dev->irq);
923 /* Allocate the various queues. */
924 if (!np->queue_mem) {
925 tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
926 rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
927 tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
928 rx_ring_size = sizeof(struct starfire_rx_desc) * RX_RING_SIZE;
929 np->queue_mem_size = tx_done_q_size + rx_done_q_size + tx_ring_size + rx_ring_size;
930 np->queue_mem = pci_alloc_consistent(np->pci_dev, np->queue_mem_size, &np->queue_mem_dma);
931 if (np->queue_mem == NULL) {
932 free_irq(dev->irq, dev);
933 return -ENOMEM;
936 np->tx_done_q = np->queue_mem;
937 np->tx_done_q_dma = np->queue_mem_dma;
938 np->rx_done_q = (void *) np->tx_done_q + tx_done_q_size;
939 np->rx_done_q_dma = np->tx_done_q_dma + tx_done_q_size;
940 np->tx_ring = (void *) np->rx_done_q + rx_done_q_size;
941 np->tx_ring_dma = np->rx_done_q_dma + rx_done_q_size;
942 np->rx_ring = (void *) np->tx_ring + tx_ring_size;
943 np->rx_ring_dma = np->tx_ring_dma + tx_ring_size;
946 /* Start with no carrier, it gets adjusted later */
947 netif_carrier_off(dev);
948 init_ring(dev);
949 /* Set the size of the Rx buffers. */
950 writel((np->rx_buf_sz << RxBufferLenShift) |
951 (0 << RxMinDescrThreshShift) |
952 RxPrefetchMode | RxVariableQ |
953 RX_Q_ENTRIES |
954 RX_DESC_Q_ADDR_SIZE | RX_DESC_ADDR_SIZE |
955 RxDescSpace4,
956 ioaddr + RxDescQCtrl);
958 /* Set up the Rx DMA controller. */
959 writel(RxChecksumIgnore |
960 (0 << RxEarlyIntThreshShift) |
961 (6 << RxHighPrioThreshShift) |
962 ((DMA_BURST_SIZE / 32) << RxBurstSizeShift),
963 ioaddr + RxDMACtrl);
965 /* Set Tx descriptor */
966 writel((2 << TxHiPriFIFOThreshShift) |
967 (0 << TxPadLenShift) |
968 ((DMA_BURST_SIZE / 32) << TxDMABurstSizeShift) |
969 TX_DESC_Q_ADDR_SIZE |
970 TX_DESC_SPACING | TX_DESC_TYPE,
971 ioaddr + TxDescCtrl);
973 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr);
974 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr);
975 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr);
976 writel(np->rx_ring_dma, ioaddr + RxDescQAddr);
977 writel(np->tx_ring_dma, ioaddr + TxRingPtr);
979 writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr);
980 writel(np->rx_done_q_dma |
981 RxComplType |
982 (0 << RxComplThreshShift),
983 ioaddr + RxCompletionAddr);
985 if (debug > 1)
986 printk(KERN_DEBUG "%s: Filling in the station address.\n", dev->name);
988 /* Fill both the Tx SA register and the Rx perfect filter. */
989 for (i = 0; i < 6; i++)
990 writeb(dev->dev_addr[i], ioaddr + TxStationAddr + 5 - i);
991 /* The first entry is special because it bypasses the VLAN filter.
992 Don't use it. */
993 writew(0, ioaddr + PerfFilterTable);
994 writew(0, ioaddr + PerfFilterTable + 4);
995 writew(0, ioaddr + PerfFilterTable + 8);
996 for (i = 1; i < 16; i++) {
997 __be16 *eaddrs = (__be16 *)dev->dev_addr;
998 void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16;
999 writew(be16_to_cpu(eaddrs[2]), setup_frm); setup_frm += 4;
1000 writew(be16_to_cpu(eaddrs[1]), setup_frm); setup_frm += 4;
1001 writew(be16_to_cpu(eaddrs[0]), setup_frm); setup_frm += 8;
1004 /* Initialize other registers. */
1005 /* Configure the PCI bus bursts and FIFO thresholds. */
1006 np->tx_mode = TxFlowEnable|RxFlowEnable|PadEnable; /* modified when link is up. */
1007 writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode);
1008 udelay(1000);
1009 writel(np->tx_mode, ioaddr + TxMode);
1010 np->tx_threshold = 4;
1011 writel(np->tx_threshold, ioaddr + TxThreshold);
1013 writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1015 napi_enable(&np->napi);
1017 netif_start_queue(dev);
1019 if (debug > 1)
1020 printk(KERN_DEBUG "%s: Setting the Rx and Tx modes.\n", dev->name);
1021 set_rx_mode(dev);
1023 np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1024 check_duplex(dev);
1026 /* Enable GPIO interrupts on link change */
1027 writel(0x0f00ff00, ioaddr + GPIOCtrl);
1029 /* Set the interrupt mask */
1030 writel(IntrRxDone | IntrRxEmpty | IntrDMAErr |
1031 IntrTxDMADone | IntrStatsMax | IntrLinkChange |
1032 IntrRxGFPDead | IntrNoTxCsum | IntrTxBadID,
1033 ioaddr + IntrEnable);
1034 /* Enable PCI interrupts. */
1035 writel(0x00800000 | readl(ioaddr + PCIDeviceConfig),
1036 ioaddr + PCIDeviceConfig);
1038 #ifdef VLAN_SUPPORT
1039 /* Set VLAN type to 802.1q */
1040 writel(ETH_P_8021Q, ioaddr + VlanType);
1041 #endif /* VLAN_SUPPORT */
1043 /* Load Rx/Tx firmware into the frame processors */
1044 for (i = 0; i < FIRMWARE_RX_SIZE * 2; i++)
1045 writel(firmware_rx[i], ioaddr + RxGfpMem + i * 4);
1046 for (i = 0; i < FIRMWARE_TX_SIZE * 2; i++)
1047 writel(firmware_tx[i], ioaddr + TxGfpMem + i * 4);
1048 if (enable_hw_cksum)
1049 /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */
1050 writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl);
1051 else
1052 /* Enable the Rx and Tx units only. */
1053 writel(TxEnable|RxEnable, ioaddr + GenCtrl);
1055 if (debug > 1)
1056 printk(KERN_DEBUG "%s: Done netdev_open().\n",
1057 dev->name);
1059 return 0;
1063 static void check_duplex(struct net_device *dev)
1065 struct netdev_private *np = netdev_priv(dev);
1066 u16 reg0;
1067 int silly_count = 1000;
1069 mdio_write(dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising);
1070 mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET);
1071 udelay(500);
1072 while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET)
1073 /* do nothing */;
1074 if (!silly_count) {
1075 printk("%s: MII reset failed!\n", dev->name);
1076 return;
1079 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1081 if (!np->mii_if.force_media) {
1082 reg0 |= BMCR_ANENABLE | BMCR_ANRESTART;
1083 } else {
1084 reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART);
1085 if (np->speed100)
1086 reg0 |= BMCR_SPEED100;
1087 if (np->mii_if.full_duplex)
1088 reg0 |= BMCR_FULLDPLX;
1089 printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n",
1090 dev->name,
1091 np->speed100 ? "100" : "10",
1092 np->mii_if.full_duplex ? "full" : "half");
1094 mdio_write(dev, np->phys[0], MII_BMCR, reg0);
1098 static void tx_timeout(struct net_device *dev)
1100 struct netdev_private *np = netdev_priv(dev);
1101 void __iomem *ioaddr = np->base;
1102 int old_debug;
1104 printk(KERN_WARNING "%s: Transmit timed out, status %#8.8x, "
1105 "resetting...\n", dev->name, (int) readl(ioaddr + IntrStatus));
1107 /* Perhaps we should reinitialize the hardware here. */
1110 * Stop and restart the interface.
1111 * Cheat and increase the debug level temporarily.
1113 old_debug = debug;
1114 debug = 2;
1115 netdev_close(dev);
1116 netdev_open(dev);
1117 debug = old_debug;
1119 /* Trigger an immediate transmit demand. */
1121 dev->trans_start = jiffies;
1122 np->stats.tx_errors++;
1123 netif_wake_queue(dev);
1127 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1128 static void init_ring(struct net_device *dev)
1130 struct netdev_private *np = netdev_priv(dev);
1131 int i;
1133 np->cur_rx = np->cur_tx = np->reap_tx = 0;
1134 np->dirty_rx = np->dirty_tx = np->rx_done = np->tx_done = 0;
1136 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1138 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1139 for (i = 0; i < RX_RING_SIZE; i++) {
1140 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1141 np->rx_info[i].skb = skb;
1142 if (skb == NULL)
1143 break;
1144 np->rx_info[i].mapping = pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1145 skb->dev = dev; /* Mark as being used by this device. */
1146 /* Grrr, we cannot offset to correctly align the IP header. */
1147 np->rx_ring[i].rxaddr = cpu_to_dma(np->rx_info[i].mapping | RxDescValid);
1149 writew(i - 1, np->base + RxDescQIdx);
1150 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1152 /* Clear the remainder of the Rx buffer ring. */
1153 for ( ; i < RX_RING_SIZE; i++) {
1154 np->rx_ring[i].rxaddr = 0;
1155 np->rx_info[i].skb = NULL;
1156 np->rx_info[i].mapping = 0;
1158 /* Mark the last entry as wrapping the ring. */
1159 np->rx_ring[RX_RING_SIZE - 1].rxaddr |= cpu_to_dma(RxDescEndRing);
1161 /* Clear the completion rings. */
1162 for (i = 0; i < DONE_Q_SIZE; i++) {
1163 np->rx_done_q[i].status = 0;
1164 np->tx_done_q[i].status = 0;
1167 for (i = 0; i < TX_RING_SIZE; i++)
1168 memset(&np->tx_info[i], 0, sizeof(np->tx_info[i]));
1170 return;
1174 static int start_tx(struct sk_buff *skb, struct net_device *dev)
1176 struct netdev_private *np = netdev_priv(dev);
1177 unsigned int entry;
1178 u32 status;
1179 int i;
1182 * be cautious here, wrapping the queue has weird semantics
1183 * and we may not have enough slots even when it seems we do.
1185 if ((np->cur_tx - np->dirty_tx) + skb_num_frags(skb) * 2 > TX_RING_SIZE) {
1186 netif_stop_queue(dev);
1187 return 1;
1190 #if defined(ZEROCOPY) && defined(HAS_BROKEN_FIRMWARE)
1191 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1192 if (skb_padto(skb, (skb->len + PADDING_MASK) & ~PADDING_MASK))
1193 return NETDEV_TX_OK;
1195 #endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */
1197 entry = np->cur_tx % TX_RING_SIZE;
1198 for (i = 0; i < skb_num_frags(skb); i++) {
1199 int wrap_ring = 0;
1200 status = TxDescID;
1202 if (i == 0) {
1203 np->tx_info[entry].skb = skb;
1204 status |= TxCRCEn;
1205 if (entry >= TX_RING_SIZE - skb_num_frags(skb)) {
1206 status |= TxRingWrap;
1207 wrap_ring = 1;
1209 if (np->reap_tx) {
1210 status |= TxDescIntr;
1211 np->reap_tx = 0;
1213 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1214 status |= TxCalTCP;
1215 np->stats.tx_compressed++;
1217 status |= skb_first_frag_len(skb) | (skb_num_frags(skb) << 16);
1219 np->tx_info[entry].mapping =
1220 pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1221 } else {
1222 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1];
1223 status |= this_frag->size;
1224 np->tx_info[entry].mapping =
1225 pci_map_single(np->pci_dev, page_address(this_frag->page) + this_frag->page_offset, this_frag->size, PCI_DMA_TODEVICE);
1228 np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping);
1229 np->tx_ring[entry].status = cpu_to_le32(status);
1230 if (debug > 3)
1231 printk(KERN_DEBUG "%s: Tx #%d/#%d slot %d status %#8.8x.\n",
1232 dev->name, np->cur_tx, np->dirty_tx,
1233 entry, status);
1234 if (wrap_ring) {
1235 np->tx_info[entry].used_slots = TX_RING_SIZE - entry;
1236 np->cur_tx += np->tx_info[entry].used_slots;
1237 entry = 0;
1238 } else {
1239 np->tx_info[entry].used_slots = 1;
1240 np->cur_tx += np->tx_info[entry].used_slots;
1241 entry++;
1243 /* scavenge the tx descriptors twice per TX_RING_SIZE */
1244 if (np->cur_tx % (TX_RING_SIZE / 2) == 0)
1245 np->reap_tx = 1;
1248 /* Non-x86: explicitly flush descriptor cache lines here. */
1249 /* Ensure all descriptors are written back before the transmit is
1250 initiated. - Jes */
1251 wmb();
1253 /* Update the producer index. */
1254 writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx);
1256 /* 4 is arbitrary, but should be ok */
1257 if ((np->cur_tx - np->dirty_tx) + 4 > TX_RING_SIZE)
1258 netif_stop_queue(dev);
1260 dev->trans_start = jiffies;
1262 return 0;
1266 /* The interrupt handler does all of the Rx thread work and cleans up
1267 after the Tx thread. */
1268 static irqreturn_t intr_handler(int irq, void *dev_instance)
1270 struct net_device *dev = dev_instance;
1271 struct netdev_private *np = netdev_priv(dev);
1272 void __iomem *ioaddr = np->base;
1273 int boguscnt = max_interrupt_work;
1274 int consumer;
1275 int tx_status;
1276 int handled = 0;
1278 do {
1279 u32 intr_status = readl(ioaddr + IntrClear);
1281 if (debug > 4)
1282 printk(KERN_DEBUG "%s: Interrupt status %#8.8x.\n",
1283 dev->name, intr_status);
1285 if (intr_status == 0 || intr_status == (u32) -1)
1286 break;
1288 handled = 1;
1290 if (intr_status & (IntrRxDone | IntrRxEmpty)) {
1291 u32 enable;
1293 if (likely(netif_rx_schedule_prep(dev, &np->napi))) {
1294 __netif_rx_schedule(dev, &np->napi);
1295 enable = readl(ioaddr + IntrEnable);
1296 enable &= ~(IntrRxDone | IntrRxEmpty);
1297 writel(enable, ioaddr + IntrEnable);
1298 /* flush PCI posting buffers */
1299 readl(ioaddr + IntrEnable);
1300 } else {
1301 /* Paranoia check */
1302 enable = readl(ioaddr + IntrEnable);
1303 if (enable & (IntrRxDone | IntrRxEmpty)) {
1304 printk(KERN_INFO
1305 "%s: interrupt while in poll!\n",
1306 dev->name);
1307 enable &= ~(IntrRxDone | IntrRxEmpty);
1308 writel(enable, ioaddr + IntrEnable);
1313 /* Scavenge the skbuff list based on the Tx-done queue.
1314 There are redundant checks here that may be cleaned up
1315 after the driver has proven to be reliable. */
1316 consumer = readl(ioaddr + TxConsumerIdx);
1317 if (debug > 3)
1318 printk(KERN_DEBUG "%s: Tx Consumer index is %d.\n",
1319 dev->name, consumer);
1321 while ((tx_status = le32_to_cpu(np->tx_done_q[np->tx_done].status)) != 0) {
1322 if (debug > 3)
1323 printk(KERN_DEBUG "%s: Tx completion #%d entry %d is %#8.8x.\n",
1324 dev->name, np->dirty_tx, np->tx_done, tx_status);
1325 if ((tx_status & 0xe0000000) == 0xa0000000) {
1326 np->stats.tx_packets++;
1327 } else if ((tx_status & 0xe0000000) == 0x80000000) {
1328 u16 entry = (tx_status & 0x7fff) / sizeof(starfire_tx_desc);
1329 struct sk_buff *skb = np->tx_info[entry].skb;
1330 np->tx_info[entry].skb = NULL;
1331 pci_unmap_single(np->pci_dev,
1332 np->tx_info[entry].mapping,
1333 skb_first_frag_len(skb),
1334 PCI_DMA_TODEVICE);
1335 np->tx_info[entry].mapping = 0;
1336 np->dirty_tx += np->tx_info[entry].used_slots;
1337 entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE;
1339 int i;
1340 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1341 pci_unmap_single(np->pci_dev,
1342 np->tx_info[entry].mapping,
1343 skb_shinfo(skb)->frags[i].size,
1344 PCI_DMA_TODEVICE);
1345 np->dirty_tx++;
1346 entry++;
1350 dev_kfree_skb_irq(skb);
1352 np->tx_done_q[np->tx_done].status = 0;
1353 np->tx_done = (np->tx_done + 1) % DONE_Q_SIZE;
1355 writew(np->tx_done, ioaddr + CompletionQConsumerIdx + 2);
1357 if (netif_queue_stopped(dev) &&
1358 (np->cur_tx - np->dirty_tx + 4 < TX_RING_SIZE)) {
1359 /* The ring is no longer full, wake the queue. */
1360 netif_wake_queue(dev);
1363 /* Stats overflow */
1364 if (intr_status & IntrStatsMax)
1365 get_stats(dev);
1367 /* Media change interrupt. */
1368 if (intr_status & IntrLinkChange)
1369 netdev_media_change(dev);
1371 /* Abnormal error summary/uncommon events handlers. */
1372 if (intr_status & IntrAbnormalSummary)
1373 netdev_error(dev, intr_status);
1375 if (--boguscnt < 0) {
1376 if (debug > 1)
1377 printk(KERN_WARNING "%s: Too much work at interrupt, "
1378 "status=%#8.8x.\n",
1379 dev->name, intr_status);
1380 break;
1382 } while (1);
1384 if (debug > 4)
1385 printk(KERN_DEBUG "%s: exiting interrupt, status=%#8.8x.\n",
1386 dev->name, (int) readl(ioaddr + IntrStatus));
1387 return IRQ_RETVAL(handled);
1392 * This routine is logically part of the interrupt/poll handler, but separated
1393 * for clarity and better register allocation.
1395 static int __netdev_rx(struct net_device *dev, int *quota)
1397 struct netdev_private *np = netdev_priv(dev);
1398 u32 desc_status;
1399 int retcode = 0;
1401 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1402 while ((desc_status = le32_to_cpu(np->rx_done_q[np->rx_done].status)) != 0) {
1403 struct sk_buff *skb;
1404 u16 pkt_len;
1405 int entry;
1406 rx_done_desc *desc = &np->rx_done_q[np->rx_done];
1408 if (debug > 4)
1409 printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status);
1410 if (!(desc_status & RxOK)) {
1411 /* There was an error. */
1412 if (debug > 2)
1413 printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status);
1414 np->stats.rx_errors++;
1415 if (desc_status & RxFIFOErr)
1416 np->stats.rx_fifo_errors++;
1417 goto next_rx;
1420 if (*quota <= 0) { /* out of rx quota */
1421 retcode = 1;
1422 goto out;
1424 (*quota)--;
1426 pkt_len = desc_status; /* Implicitly Truncate */
1427 entry = (desc_status >> 16) & 0x7ff;
1429 if (debug > 4)
1430 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d, quota %d.\n", pkt_len, *quota);
1431 /* Check if the packet is long enough to accept without copying
1432 to a minimally-sized skbuff. */
1433 if (pkt_len < rx_copybreak
1434 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1435 skb_reserve(skb, 2); /* 16 byte align the IP header */
1436 pci_dma_sync_single_for_cpu(np->pci_dev,
1437 np->rx_info[entry].mapping,
1438 pkt_len, PCI_DMA_FROMDEVICE);
1439 skb_copy_to_linear_data(skb, np->rx_info[entry].skb->data, pkt_len);
1440 pci_dma_sync_single_for_device(np->pci_dev,
1441 np->rx_info[entry].mapping,
1442 pkt_len, PCI_DMA_FROMDEVICE);
1443 skb_put(skb, pkt_len);
1444 } else {
1445 pci_unmap_single(np->pci_dev, np->rx_info[entry].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1446 skb = np->rx_info[entry].skb;
1447 skb_put(skb, pkt_len);
1448 np->rx_info[entry].skb = NULL;
1449 np->rx_info[entry].mapping = 0;
1451 #ifndef final_version /* Remove after testing. */
1452 /* You will want this info for the initial debug. */
1453 if (debug > 5) {
1454 printk(KERN_DEBUG " Rx data %pM %pM %2.2x%2.2x.\n",
1455 skb->data, skb->data + 6,
1456 skb->data[12], skb->data[13]);
1458 #endif
1460 skb->protocol = eth_type_trans(skb, dev);
1461 #ifdef VLAN_SUPPORT
1462 if (debug > 4)
1463 printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2));
1464 #endif
1465 if (le16_to_cpu(desc->status2) & 0x0100) {
1466 skb->ip_summed = CHECKSUM_UNNECESSARY;
1467 np->stats.rx_compressed++;
1470 * This feature doesn't seem to be working, at least
1471 * with the two firmware versions I have. If the GFP sees
1472 * an IP fragment, it either ignores it completely, or reports
1473 * "bad checksum" on it.
1475 * Maybe I missed something -- corrections are welcome.
1476 * Until then, the printk stays. :-) -Ion
1478 else if (le16_to_cpu(desc->status2) & 0x0040) {
1479 skb->ip_summed = CHECKSUM_COMPLETE;
1480 skb->csum = le16_to_cpu(desc->csum);
1481 printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2));
1483 #ifdef VLAN_SUPPORT
1484 if (np->vlgrp && le16_to_cpu(desc->status2) & 0x0200) {
1485 u16 vlid = le16_to_cpu(desc->vlanid);
1487 if (debug > 4) {
1488 printk(KERN_DEBUG " netdev_rx() vlanid = %d\n",
1489 vlid);
1492 * vlan_hwaccel_rx expects a packet with the VLAN tag
1493 * stripped out.
1495 vlan_hwaccel_rx(skb, np->vlgrp, vlid);
1496 } else
1497 #endif /* VLAN_SUPPORT */
1498 netif_receive_skb(skb);
1499 np->stats.rx_packets++;
1501 next_rx:
1502 np->cur_rx++;
1503 desc->status = 0;
1504 np->rx_done = (np->rx_done + 1) % DONE_Q_SIZE;
1506 writew(np->rx_done, np->base + CompletionQConsumerIdx);
1508 out:
1509 refill_rx_ring(dev);
1510 if (debug > 5)
1511 printk(KERN_DEBUG " exiting netdev_rx(): %d, status of %d was %#8.8x.\n",
1512 retcode, np->rx_done, desc_status);
1513 return retcode;
1516 static int netdev_poll(struct napi_struct *napi, int budget)
1518 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
1519 struct net_device *dev = np->dev;
1520 u32 intr_status;
1521 void __iomem *ioaddr = np->base;
1522 int quota = budget;
1524 do {
1525 writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear);
1527 if (__netdev_rx(dev, &quota))
1528 goto out;
1530 intr_status = readl(ioaddr + IntrStatus);
1531 } while (intr_status & (IntrRxDone | IntrRxEmpty));
1533 netif_rx_complete(dev, napi);
1534 intr_status = readl(ioaddr + IntrEnable);
1535 intr_status |= IntrRxDone | IntrRxEmpty;
1536 writel(intr_status, ioaddr + IntrEnable);
1538 out:
1539 if (debug > 5)
1540 printk(KERN_DEBUG " exiting netdev_poll(): %d.\n",
1541 budget - quota);
1543 /* Restart Rx engine if stopped. */
1544 return budget - quota;
1547 static void refill_rx_ring(struct net_device *dev)
1549 struct netdev_private *np = netdev_priv(dev);
1550 struct sk_buff *skb;
1551 int entry = -1;
1553 /* Refill the Rx ring buffers. */
1554 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1555 entry = np->dirty_rx % RX_RING_SIZE;
1556 if (np->rx_info[entry].skb == NULL) {
1557 skb = dev_alloc_skb(np->rx_buf_sz);
1558 np->rx_info[entry].skb = skb;
1559 if (skb == NULL)
1560 break; /* Better luck next round. */
1561 np->rx_info[entry].mapping =
1562 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1563 skb->dev = dev; /* Mark as being used by this device. */
1564 np->rx_ring[entry].rxaddr =
1565 cpu_to_dma(np->rx_info[entry].mapping | RxDescValid);
1567 if (entry == RX_RING_SIZE - 1)
1568 np->rx_ring[entry].rxaddr |= cpu_to_dma(RxDescEndRing);
1570 if (entry >= 0)
1571 writew(entry, np->base + RxDescQIdx);
1575 static void netdev_media_change(struct net_device *dev)
1577 struct netdev_private *np = netdev_priv(dev);
1578 void __iomem *ioaddr = np->base;
1579 u16 reg0, reg1, reg4, reg5;
1580 u32 new_tx_mode;
1581 u32 new_intr_timer_ctrl;
1583 /* reset status first */
1584 mdio_read(dev, np->phys[0], MII_BMCR);
1585 mdio_read(dev, np->phys[0], MII_BMSR);
1587 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1588 reg1 = mdio_read(dev, np->phys[0], MII_BMSR);
1590 if (reg1 & BMSR_LSTATUS) {
1591 /* link is up */
1592 if (reg0 & BMCR_ANENABLE) {
1593 /* autonegotiation is enabled */
1594 reg4 = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1595 reg5 = mdio_read(dev, np->phys[0], MII_LPA);
1596 if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) {
1597 np->speed100 = 1;
1598 np->mii_if.full_duplex = 1;
1599 } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) {
1600 np->speed100 = 1;
1601 np->mii_if.full_duplex = 0;
1602 } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) {
1603 np->speed100 = 0;
1604 np->mii_if.full_duplex = 1;
1605 } else {
1606 np->speed100 = 0;
1607 np->mii_if.full_duplex = 0;
1609 } else {
1610 /* autonegotiation is disabled */
1611 if (reg0 & BMCR_SPEED100)
1612 np->speed100 = 1;
1613 else
1614 np->speed100 = 0;
1615 if (reg0 & BMCR_FULLDPLX)
1616 np->mii_if.full_duplex = 1;
1617 else
1618 np->mii_if.full_duplex = 0;
1620 netif_carrier_on(dev);
1621 printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n",
1622 dev->name,
1623 np->speed100 ? "100" : "10",
1624 np->mii_if.full_duplex ? "full" : "half");
1626 new_tx_mode = np->tx_mode & ~FullDuplex; /* duplex setting */
1627 if (np->mii_if.full_duplex)
1628 new_tx_mode |= FullDuplex;
1629 if (np->tx_mode != new_tx_mode) {
1630 np->tx_mode = new_tx_mode;
1631 writel(np->tx_mode | MiiSoftReset, ioaddr + TxMode);
1632 udelay(1000);
1633 writel(np->tx_mode, ioaddr + TxMode);
1636 new_intr_timer_ctrl = np->intr_timer_ctrl & ~Timer10X;
1637 if (np->speed100)
1638 new_intr_timer_ctrl |= Timer10X;
1639 if (np->intr_timer_ctrl != new_intr_timer_ctrl) {
1640 np->intr_timer_ctrl = new_intr_timer_ctrl;
1641 writel(new_intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1643 } else {
1644 netif_carrier_off(dev);
1645 printk(KERN_DEBUG "%s: Link is down\n", dev->name);
1650 static void netdev_error(struct net_device *dev, int intr_status)
1652 struct netdev_private *np = netdev_priv(dev);
1654 /* Came close to underrunning the Tx FIFO, increase threshold. */
1655 if (intr_status & IntrTxDataLow) {
1656 if (np->tx_threshold <= PKT_BUF_SZ / 16) {
1657 writel(++np->tx_threshold, np->base + TxThreshold);
1658 printk(KERN_NOTICE "%s: PCI bus congestion, increasing Tx FIFO threshold to %d bytes\n",
1659 dev->name, np->tx_threshold * 16);
1660 } else
1661 printk(KERN_WARNING "%s: PCI Tx underflow -- adapter is probably malfunctioning\n", dev->name);
1663 if (intr_status & IntrRxGFPDead) {
1664 np->stats.rx_fifo_errors++;
1665 np->stats.rx_errors++;
1667 if (intr_status & (IntrNoTxCsum | IntrDMAErr)) {
1668 np->stats.tx_fifo_errors++;
1669 np->stats.tx_errors++;
1671 if ((intr_status & ~(IntrNormalMask | IntrAbnormalSummary | IntrLinkChange | IntrStatsMax | IntrTxDataLow | IntrRxGFPDead | IntrNoTxCsum | IntrPCIPad)) && debug)
1672 printk(KERN_ERR "%s: Something Wicked happened! %#8.8x.\n",
1673 dev->name, intr_status);
1677 static struct net_device_stats *get_stats(struct net_device *dev)
1679 struct netdev_private *np = netdev_priv(dev);
1680 void __iomem *ioaddr = np->base;
1682 /* This adapter architecture needs no SMP locks. */
1683 np->stats.tx_bytes = readl(ioaddr + 0x57010);
1684 np->stats.rx_bytes = readl(ioaddr + 0x57044);
1685 np->stats.tx_packets = readl(ioaddr + 0x57000);
1686 np->stats.tx_aborted_errors =
1687 readl(ioaddr + 0x57024) + readl(ioaddr + 0x57028);
1688 np->stats.tx_window_errors = readl(ioaddr + 0x57018);
1689 np->stats.collisions =
1690 readl(ioaddr + 0x57004) + readl(ioaddr + 0x57008);
1692 /* The chip only need report frame silently dropped. */
1693 np->stats.rx_dropped += readw(ioaddr + RxDMAStatus);
1694 writew(0, ioaddr + RxDMAStatus);
1695 np->stats.rx_crc_errors = readl(ioaddr + 0x5703C);
1696 np->stats.rx_frame_errors = readl(ioaddr + 0x57040);
1697 np->stats.rx_length_errors = readl(ioaddr + 0x57058);
1698 np->stats.rx_missed_errors = readl(ioaddr + 0x5707C);
1700 return &np->stats;
1704 static void set_rx_mode(struct net_device *dev)
1706 struct netdev_private *np = netdev_priv(dev);
1707 void __iomem *ioaddr = np->base;
1708 u32 rx_mode = MinVLANPrio;
1709 struct dev_mc_list *mclist;
1710 int i;
1711 #ifdef VLAN_SUPPORT
1713 rx_mode |= VlanMode;
1714 if (np->vlgrp) {
1715 int vlan_count = 0;
1716 void __iomem *filter_addr = ioaddr + HashTable + 8;
1717 for (i = 0; i < VLAN_VID_MASK; i++) {
1718 if (vlan_group_get_device(np->vlgrp, i)) {
1719 if (vlan_count >= 32)
1720 break;
1721 writew(i, filter_addr);
1722 filter_addr += 16;
1723 vlan_count++;
1726 if (i == VLAN_VID_MASK) {
1727 rx_mode |= PerfectFilterVlan;
1728 while (vlan_count < 32) {
1729 writew(0, filter_addr);
1730 filter_addr += 16;
1731 vlan_count++;
1735 #endif /* VLAN_SUPPORT */
1737 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1738 rx_mode |= AcceptAll;
1739 } else if ((dev->mc_count > multicast_filter_limit)
1740 || (dev->flags & IFF_ALLMULTI)) {
1741 /* Too many to match, or accept all multicasts. */
1742 rx_mode |= AcceptBroadcast|AcceptAllMulticast|PerfectFilter;
1743 } else if (dev->mc_count <= 14) {
1744 /* Use the 16 element perfect filter, skip first two entries. */
1745 void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1746 __be16 *eaddrs;
1747 for (i = 2, mclist = dev->mc_list; mclist && i < dev->mc_count + 2;
1748 i++, mclist = mclist->next) {
1749 eaddrs = (__be16 *)mclist->dmi_addr;
1750 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 4;
1751 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1752 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 8;
1754 eaddrs = (__be16 *)dev->dev_addr;
1755 while (i++ < 16) {
1756 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1757 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1758 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1760 rx_mode |= AcceptBroadcast|PerfectFilter;
1761 } else {
1762 /* Must use a multicast hash table. */
1763 void __iomem *filter_addr;
1764 __be16 *eaddrs;
1765 __le16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */
1767 memset(mc_filter, 0, sizeof(mc_filter));
1768 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1769 i++, mclist = mclist->next) {
1770 /* The chip uses the upper 9 CRC bits
1771 as index into the hash table */
1772 int bit_nr = ether_crc_le(ETH_ALEN, mclist->dmi_addr) >> 23;
1773 __le32 *fptr = (__le32 *) &mc_filter[(bit_nr >> 4) & ~1];
1775 *fptr |= cpu_to_le32(1 << (bit_nr & 31));
1777 /* Clear the perfect filter list, skip first two entries. */
1778 filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1779 eaddrs = (__be16 *)dev->dev_addr;
1780 for (i = 2; i < 16; i++) {
1781 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1782 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1783 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1785 for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++)
1786 writew(mc_filter[i], filter_addr);
1787 rx_mode |= AcceptBroadcast|PerfectFilter|HashFilter;
1789 writel(rx_mode, ioaddr + RxFilterMode);
1792 static int check_if_running(struct net_device *dev)
1794 if (!netif_running(dev))
1795 return -EINVAL;
1796 return 0;
1799 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1801 struct netdev_private *np = netdev_priv(dev);
1802 strcpy(info->driver, DRV_NAME);
1803 strcpy(info->version, DRV_VERSION);
1804 strcpy(info->bus_info, pci_name(np->pci_dev));
1807 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1809 struct netdev_private *np = netdev_priv(dev);
1810 spin_lock_irq(&np->lock);
1811 mii_ethtool_gset(&np->mii_if, ecmd);
1812 spin_unlock_irq(&np->lock);
1813 return 0;
1816 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1818 struct netdev_private *np = netdev_priv(dev);
1819 int res;
1820 spin_lock_irq(&np->lock);
1821 res = mii_ethtool_sset(&np->mii_if, ecmd);
1822 spin_unlock_irq(&np->lock);
1823 check_duplex(dev);
1824 return res;
1827 static int nway_reset(struct net_device *dev)
1829 struct netdev_private *np = netdev_priv(dev);
1830 return mii_nway_restart(&np->mii_if);
1833 static u32 get_link(struct net_device *dev)
1835 struct netdev_private *np = netdev_priv(dev);
1836 return mii_link_ok(&np->mii_if);
1839 static u32 get_msglevel(struct net_device *dev)
1841 return debug;
1844 static void set_msglevel(struct net_device *dev, u32 val)
1846 debug = val;
1849 static const struct ethtool_ops ethtool_ops = {
1850 .begin = check_if_running,
1851 .get_drvinfo = get_drvinfo,
1852 .get_settings = get_settings,
1853 .set_settings = set_settings,
1854 .nway_reset = nway_reset,
1855 .get_link = get_link,
1856 .get_msglevel = get_msglevel,
1857 .set_msglevel = set_msglevel,
1860 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1862 struct netdev_private *np = netdev_priv(dev);
1863 struct mii_ioctl_data *data = if_mii(rq);
1864 int rc;
1866 if (!netif_running(dev))
1867 return -EINVAL;
1869 spin_lock_irq(&np->lock);
1870 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
1871 spin_unlock_irq(&np->lock);
1873 if ((cmd == SIOCSMIIREG) && (data->phy_id == np->phys[0]))
1874 check_duplex(dev);
1876 return rc;
1879 static int netdev_close(struct net_device *dev)
1881 struct netdev_private *np = netdev_priv(dev);
1882 void __iomem *ioaddr = np->base;
1883 int i;
1885 netif_stop_queue(dev);
1887 napi_disable(&np->napi);
1889 if (debug > 1) {
1890 printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n",
1891 dev->name, (int) readl(ioaddr + IntrStatus));
1892 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1893 dev->name, np->cur_tx, np->dirty_tx,
1894 np->cur_rx, np->dirty_rx);
1897 /* Disable interrupts by clearing the interrupt mask. */
1898 writel(0, ioaddr + IntrEnable);
1900 /* Stop the chip's Tx and Rx processes. */
1901 writel(0, ioaddr + GenCtrl);
1902 readl(ioaddr + GenCtrl);
1904 if (debug > 5) {
1905 printk(KERN_DEBUG" Tx ring at %#llx:\n",
1906 (long long) np->tx_ring_dma);
1907 for (i = 0; i < 8 /* TX_RING_SIZE is huge! */; i++)
1908 printk(KERN_DEBUG " #%d desc. %#8.8x %#llx -> %#8.8x.\n",
1909 i, le32_to_cpu(np->tx_ring[i].status),
1910 (long long) dma_to_cpu(np->tx_ring[i].addr),
1911 le32_to_cpu(np->tx_done_q[i].status));
1912 printk(KERN_DEBUG " Rx ring at %#llx -> %p:\n",
1913 (long long) np->rx_ring_dma, np->rx_done_q);
1914 if (np->rx_done_q)
1915 for (i = 0; i < 8 /* RX_RING_SIZE */; i++) {
1916 printk(KERN_DEBUG " #%d desc. %#llx -> %#8.8x\n",
1917 i, (long long) dma_to_cpu(np->rx_ring[i].rxaddr), le32_to_cpu(np->rx_done_q[i].status));
1921 free_irq(dev->irq, dev);
1923 /* Free all the skbuffs in the Rx queue. */
1924 for (i = 0; i < RX_RING_SIZE; i++) {
1925 np->rx_ring[i].rxaddr = cpu_to_dma(0xBADF00D0); /* An invalid address. */
1926 if (np->rx_info[i].skb != NULL) {
1927 pci_unmap_single(np->pci_dev, np->rx_info[i].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1928 dev_kfree_skb(np->rx_info[i].skb);
1930 np->rx_info[i].skb = NULL;
1931 np->rx_info[i].mapping = 0;
1933 for (i = 0; i < TX_RING_SIZE; i++) {
1934 struct sk_buff *skb = np->tx_info[i].skb;
1935 if (skb == NULL)
1936 continue;
1937 pci_unmap_single(np->pci_dev,
1938 np->tx_info[i].mapping,
1939 skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1940 np->tx_info[i].mapping = 0;
1941 dev_kfree_skb(skb);
1942 np->tx_info[i].skb = NULL;
1945 return 0;
1948 #ifdef CONFIG_PM
1949 static int starfire_suspend(struct pci_dev *pdev, pm_message_t state)
1951 struct net_device *dev = pci_get_drvdata(pdev);
1953 if (netif_running(dev)) {
1954 netif_device_detach(dev);
1955 netdev_close(dev);
1958 pci_save_state(pdev);
1959 pci_set_power_state(pdev, pci_choose_state(pdev,state));
1961 return 0;
1964 static int starfire_resume(struct pci_dev *pdev)
1966 struct net_device *dev = pci_get_drvdata(pdev);
1968 pci_set_power_state(pdev, PCI_D0);
1969 pci_restore_state(pdev);
1971 if (netif_running(dev)) {
1972 netdev_open(dev);
1973 netif_device_attach(dev);
1976 return 0;
1978 #endif /* CONFIG_PM */
1981 static void __devexit starfire_remove_one (struct pci_dev *pdev)
1983 struct net_device *dev = pci_get_drvdata(pdev);
1984 struct netdev_private *np = netdev_priv(dev);
1986 BUG_ON(!dev);
1988 unregister_netdev(dev);
1990 if (np->queue_mem)
1991 pci_free_consistent(pdev, np->queue_mem_size, np->queue_mem, np->queue_mem_dma);
1994 /* XXX: add wakeup code -- requires firmware for MagicPacket */
1995 pci_set_power_state(pdev, PCI_D3hot); /* go to sleep in D3 mode */
1996 pci_disable_device(pdev);
1998 iounmap(np->base);
1999 pci_release_regions(pdev);
2001 pci_set_drvdata(pdev, NULL);
2002 free_netdev(dev); /* Will also free np!! */
2006 static struct pci_driver starfire_driver = {
2007 .name = DRV_NAME,
2008 .probe = starfire_init_one,
2009 .remove = __devexit_p(starfire_remove_one),
2010 #ifdef CONFIG_PM
2011 .suspend = starfire_suspend,
2012 .resume = starfire_resume,
2013 #endif /* CONFIG_PM */
2014 .id_table = starfire_pci_tbl,
2018 static int __init starfire_init (void)
2020 /* when a module, this is printed whether or not devices are found in probe */
2021 #ifdef MODULE
2022 printk(version);
2024 printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n");
2025 #endif
2027 /* we can do this test only at run-time... sigh */
2028 if (sizeof(dma_addr_t) != sizeof(netdrv_addr_t)) {
2029 printk("This driver has dma_addr_t issues, please send email to maintainer\n");
2030 return -ENODEV;
2033 return pci_register_driver(&starfire_driver);
2037 static void __exit starfire_cleanup (void)
2039 pci_unregister_driver (&starfire_driver);
2043 module_init(starfire_init);
2044 module_exit(starfire_cleanup);
2048 * Local variables:
2049 * c-basic-offset: 8
2050 * tab-width: 8
2051 * End: