iwlwifi: rename generic iwlagn functions that had a HW specific name
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / arm / at91_ether.c
blob442938d5038020dfd334100b7c3faf73e1f72c02
1 /*
2 * Ethernet driver for the Atmel AT91RM9200 (Thunder)
4 * Copyright (C) 2003 SAN People (Pty) Ltd
6 * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
7 * Initial version by Rick Bronson 01/11/2003
9 * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker
10 * (Polaroid Corporation)
12 * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru>
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/mii.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/skbuff.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/ethtool.h>
28 #include <linux/platform_device.h>
29 #include <linux/clk.h>
31 #include <asm/io.h>
32 #include <asm/uaccess.h>
33 #include <asm/mach-types.h>
35 #include <mach/at91rm9200_emac.h>
36 #include <mach/gpio.h>
37 #include <mach/board.h>
39 #include "at91_ether.h"
41 #define DRV_NAME "at91_ether"
42 #define DRV_VERSION "1.0"
44 #define LINK_POLL_INTERVAL (HZ)
46 /* ..................................................................... */
49 * Read from a EMAC register.
51 static inline unsigned long at91_emac_read(unsigned int reg)
53 void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC;
55 return __raw_readl(emac_base + reg);
59 * Write to a EMAC register.
61 static inline void at91_emac_write(unsigned int reg, unsigned long value)
63 void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC;
65 __raw_writel(value, emac_base + reg);
68 /* ........................... PHY INTERFACE ........................... */
71 * Enable the MDIO bit in MAC control register
72 * When not called from an interrupt-handler, access to the PHY must be
73 * protected by a spinlock.
75 static void enable_mdi(void)
77 unsigned long ctl;
79 ctl = at91_emac_read(AT91_EMAC_CTL);
80 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_MPE); /* enable management port */
84 * Disable the MDIO bit in the MAC control register
86 static void disable_mdi(void)
88 unsigned long ctl;
90 ctl = at91_emac_read(AT91_EMAC_CTL);
91 at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE); /* disable management port */
95 * Wait until the PHY operation is complete.
97 static inline void at91_phy_wait(void) {
98 unsigned long timeout = jiffies + 2;
100 while (!(at91_emac_read(AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) {
101 if (time_after(jiffies, timeout)) {
102 printk("at91_ether: MIO timeout\n");
103 break;
105 cpu_relax();
110 * Write value to the a PHY register
111 * Note: MDI interface is assumed to already have been enabled.
113 static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value)
115 at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W
116 | ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA));
118 /* Wait until IDLE bit in Network Status register is cleared */
119 at91_phy_wait();
123 * Read value stored in a PHY register.
124 * Note: MDI interface is assumed to already have been enabled.
126 static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value)
128 at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R
129 | ((phy_addr & 0x1f) << 23) | (address << 18));
131 /* Wait until IDLE bit in Network Status register is cleared */
132 at91_phy_wait();
134 *value = at91_emac_read(AT91_EMAC_MAN) & AT91_EMAC_DATA;
137 /* ........................... PHY MANAGEMENT .......................... */
140 * Access the PHY to determine the current link speed and mode, and update the
141 * MAC accordingly.
142 * If no link or auto-negotiation is busy, then no changes are made.
144 static void update_linkspeed(struct net_device *dev, int silent)
146 struct at91_private *lp = netdev_priv(dev);
147 unsigned int bmsr, bmcr, lpa, mac_cfg;
148 unsigned int speed, duplex;
150 if (!mii_link_ok(&lp->mii)) { /* no link */
151 netif_carrier_off(dev);
152 if (!silent)
153 printk(KERN_INFO "%s: Link down.\n", dev->name);
154 return;
157 /* Link up, or auto-negotiation still in progress */
158 read_phy(lp->phy_address, MII_BMSR, &bmsr);
159 read_phy(lp->phy_address, MII_BMCR, &bmcr);
160 if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */
161 if (!(bmsr & BMSR_ANEGCOMPLETE))
162 return; /* Do nothing - another interrupt generated when negotiation complete */
164 read_phy(lp->phy_address, MII_LPA, &lpa);
165 if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100;
166 else speed = SPEED_10;
167 if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL;
168 else duplex = DUPLEX_HALF;
169 } else {
170 speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
171 duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
174 /* Update the MAC */
175 mac_cfg = at91_emac_read(AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD);
176 if (speed == SPEED_100) {
177 if (duplex == DUPLEX_FULL) /* 100 Full Duplex */
178 mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD;
179 else /* 100 Half Duplex */
180 mac_cfg |= AT91_EMAC_SPD;
181 } else {
182 if (duplex == DUPLEX_FULL) /* 10 Full Duplex */
183 mac_cfg |= AT91_EMAC_FD;
184 else {} /* 10 Half Duplex */
186 at91_emac_write(AT91_EMAC_CFG, mac_cfg);
188 if (!silent)
189 printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
190 netif_carrier_on(dev);
194 * Handle interrupts from the PHY
196 static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id)
198 struct net_device *dev = (struct net_device *) dev_id;
199 struct at91_private *lp = netdev_priv(dev);
200 unsigned int phy;
203 * This hander is triggered on both edges, but the PHY chips expect
204 * level-triggering. We therefore have to check if the PHY actually has
205 * an IRQ pending.
207 enable_mdi();
208 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
209 read_phy(lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */
210 if (!(phy & (1 << 0)))
211 goto done;
213 else if (lp->phy_type == MII_LXT971A_ID) {
214 read_phy(lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */
215 if (!(phy & (1 << 2)))
216 goto done;
218 else if (lp->phy_type == MII_BCM5221_ID) {
219 read_phy(lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */
220 if (!(phy & (1 << 0)))
221 goto done;
223 else if (lp->phy_type == MII_KS8721_ID) {
224 read_phy(lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */
225 if (!(phy & ((1 << 2) | 1)))
226 goto done;
228 else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */
229 read_phy(lp->phy_address, MII_T78Q21INT_REG, &phy);
230 if (!(phy & ((1 << 2) | 1)))
231 goto done;
233 else if (lp->phy_type == MII_DP83848_ID) {
234 read_phy(lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */
235 if (!(phy & (1 << 7)))
236 goto done;
239 update_linkspeed(dev, 0);
241 done:
242 disable_mdi();
244 return IRQ_HANDLED;
248 * Initialize and enable the PHY interrupt for link-state changes
250 static void enable_phyirq(struct net_device *dev)
252 struct at91_private *lp = netdev_priv(dev);
253 unsigned int dsintr, irq_number;
254 int status;
256 irq_number = lp->board_data.phy_irq_pin;
257 if (!irq_number) {
259 * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L),
260 * or board does not have it connected.
262 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
263 return;
266 status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev);
267 if (status) {
268 printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status);
269 return;
272 spin_lock_irq(&lp->lock);
273 enable_mdi();
275 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
276 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
277 dsintr = dsintr & ~0xf00; /* clear bits 8..11 */
278 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
280 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
281 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
282 dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */
283 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
285 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
286 dsintr = (1 << 15) | ( 1 << 14);
287 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
289 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
290 dsintr = (1 << 10) | ( 1 << 8);
291 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
293 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
294 read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
295 dsintr = dsintr | 0x500; /* set bits 8, 10 */
296 write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
298 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
299 read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
300 dsintr = dsintr | 0x3c; /* set bits 2..5 */
301 write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
302 read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
303 dsintr = dsintr | 0x3; /* set bits 0,1 */
304 write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
307 disable_mdi();
308 spin_unlock_irq(&lp->lock);
312 * Disable the PHY interrupt
314 static void disable_phyirq(struct net_device *dev)
316 struct at91_private *lp = netdev_priv(dev);
317 unsigned int dsintr;
318 unsigned int irq_number;
320 irq_number = lp->board_data.phy_irq_pin;
321 if (!irq_number) {
322 del_timer_sync(&lp->check_timer);
323 return;
326 spin_lock_irq(&lp->lock);
327 enable_mdi();
329 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
330 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
331 dsintr = dsintr | 0xf00; /* set bits 8..11 */
332 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
334 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
335 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
336 dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */
337 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
339 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
340 read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr);
341 dsintr = ~(1 << 14);
342 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
344 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
345 read_phy(lp->phy_address, MII_TPISTATUS, &dsintr);
346 dsintr = ~((1 << 10) | (1 << 8));
347 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
349 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
350 read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
351 dsintr = dsintr & ~0x500; /* clear bits 8, 10 */
352 write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
354 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
355 read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
356 dsintr = dsintr & ~0x3; /* clear bits 0, 1 */
357 write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
358 read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
359 dsintr = dsintr & ~0x3c; /* clear bits 2..5 */
360 write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
363 disable_mdi();
364 spin_unlock_irq(&lp->lock);
366 free_irq(irq_number, dev); /* Free interrupt handler */
370 * Perform a software reset of the PHY.
372 #if 0
373 static void reset_phy(struct net_device *dev)
375 struct at91_private *lp = netdev_priv(dev);
376 unsigned int bmcr;
378 spin_lock_irq(&lp->lock);
379 enable_mdi();
381 /* Perform PHY reset */
382 write_phy(lp->phy_address, MII_BMCR, BMCR_RESET);
384 /* Wait until PHY reset is complete */
385 do {
386 read_phy(lp->phy_address, MII_BMCR, &bmcr);
387 } while (!(bmcr & BMCR_RESET));
389 disable_mdi();
390 spin_unlock_irq(&lp->lock);
392 #endif
394 static void at91ether_check_link(unsigned long dev_id)
396 struct net_device *dev = (struct net_device *) dev_id;
397 struct at91_private *lp = netdev_priv(dev);
399 enable_mdi();
400 update_linkspeed(dev, 1);
401 disable_mdi();
403 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
406 /* ......................... ADDRESS MANAGEMENT ........................ */
409 * NOTE: Your bootloader must always set the MAC address correctly before
410 * booting into Linux.
412 * - It must always set the MAC address after reset, even if it doesn't
413 * happen to access the Ethernet while it's booting. Some versions of
414 * U-Boot on the AT91RM9200-DK do not do this.
416 * - Likewise it must store the addresses in the correct byte order.
417 * MicroMonitor (uMon) on the CSB337 does this incorrectly (and
418 * continues to do so, for bug-compatibility).
421 static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo)
423 char addr[6];
425 if (machine_is_csb337()) {
426 addr[5] = (lo & 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */
427 addr[4] = (lo & 0xff00) >> 8;
428 addr[3] = (lo & 0xff0000) >> 16;
429 addr[2] = (lo & 0xff000000) >> 24;
430 addr[1] = (hi & 0xff);
431 addr[0] = (hi & 0xff00) >> 8;
433 else {
434 addr[0] = (lo & 0xff);
435 addr[1] = (lo & 0xff00) >> 8;
436 addr[2] = (lo & 0xff0000) >> 16;
437 addr[3] = (lo & 0xff000000) >> 24;
438 addr[4] = (hi & 0xff);
439 addr[5] = (hi & 0xff00) >> 8;
442 if (is_valid_ether_addr(addr)) {
443 memcpy(dev->dev_addr, &addr, 6);
444 return 1;
446 return 0;
450 * Set the ethernet MAC address in dev->dev_addr
452 static void __init get_mac_address(struct net_device *dev)
454 /* Check Specific-Address 1 */
455 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA1H), at91_emac_read(AT91_EMAC_SA1L)))
456 return;
457 /* Check Specific-Address 2 */
458 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA2H), at91_emac_read(AT91_EMAC_SA2L)))
459 return;
460 /* Check Specific-Address 3 */
461 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA3H), at91_emac_read(AT91_EMAC_SA3L)))
462 return;
463 /* Check Specific-Address 4 */
464 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA4H), at91_emac_read(AT91_EMAC_SA4L)))
465 return;
467 printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n");
471 * Program the hardware MAC address from dev->dev_addr.
473 static void update_mac_address(struct net_device *dev)
475 at91_emac_write(AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0]));
476 at91_emac_write(AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4]));
478 at91_emac_write(AT91_EMAC_SA2L, 0);
479 at91_emac_write(AT91_EMAC_SA2H, 0);
483 * Store the new hardware address in dev->dev_addr, and update the MAC.
485 static int set_mac_address(struct net_device *dev, void* addr)
487 struct sockaddr *address = addr;
489 if (!is_valid_ether_addr(address->sa_data))
490 return -EADDRNOTAVAIL;
492 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
493 update_mac_address(dev);
495 printk("%s: Setting MAC address to %pM\n", dev->name,
496 dev->dev_addr);
498 return 0;
501 static int inline hash_bit_value(int bitnr, __u8 *addr)
503 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
504 return 1;
505 return 0;
509 * The hash address register is 64 bits long and takes up two locations in the memory map.
510 * The least significant bits are stored in EMAC_HSL and the most significant
511 * bits in EMAC_HSH.
513 * The unicast hash enable and the multicast hash enable bits in the network configuration
514 * register enable the reception of hash matched frames. The destination address is
515 * reduced to a 6 bit index into the 64 bit hash register using the following hash function.
516 * The hash function is an exclusive or of every sixth bit of the destination address.
517 * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
518 * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
519 * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
520 * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
521 * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
522 * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
523 * da[0] represents the least significant bit of the first byte received, that is, the multicast/
524 * unicast indicator, and da[47] represents the most significant bit of the last byte
525 * received.
526 * If the hash index points to a bit that is set in the hash register then the frame will be
527 * matched according to whether the frame is multicast or unicast.
528 * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and
529 * the hash index points to a bit set in the hash register.
530 * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the
531 * hash index points to a bit set in the hash register.
532 * To receive all multicast frames, the hash register should be set with all ones and the
533 * multicast hash enable bit should be set in the network configuration register.
537 * Return the hash index value for the specified address.
539 static int hash_get_index(__u8 *addr)
541 int i, j, bitval;
542 int hash_index = 0;
544 for (j = 0; j < 6; j++) {
545 for (i = 0, bitval = 0; i < 8; i++)
546 bitval ^= hash_bit_value(i*6 + j, addr);
548 hash_index |= (bitval << j);
551 return hash_index;
555 * Add multicast addresses to the internal multicast-hash table.
557 static void at91ether_sethashtable(struct net_device *dev)
559 struct dev_mc_list *curr;
560 unsigned long mc_filter[2];
561 unsigned int i, bitnr;
563 mc_filter[0] = mc_filter[1] = 0;
565 curr = dev->mc_list;
566 for (i = 0; i < dev->mc_count; i++, curr = curr->next) {
567 if (!curr) break; /* unexpected end of list */
569 bitnr = hash_get_index(curr->dmi_addr);
570 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
573 at91_emac_write(AT91_EMAC_HSL, mc_filter[0]);
574 at91_emac_write(AT91_EMAC_HSH, mc_filter[1]);
578 * Enable/Disable promiscuous and multicast modes.
580 static void at91ether_set_rx_mode(struct net_device *dev)
582 unsigned long cfg;
584 cfg = at91_emac_read(AT91_EMAC_CFG);
586 if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */
587 cfg |= AT91_EMAC_CAF;
588 else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */
589 cfg &= ~AT91_EMAC_CAF;
591 if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */
592 at91_emac_write(AT91_EMAC_HSH, -1);
593 at91_emac_write(AT91_EMAC_HSL, -1);
594 cfg |= AT91_EMAC_MTI;
595 } else if (dev->mc_count > 0) { /* Enable specific multicasts */
596 at91ether_sethashtable(dev);
597 cfg |= AT91_EMAC_MTI;
598 } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */
599 at91_emac_write(AT91_EMAC_HSH, 0);
600 at91_emac_write(AT91_EMAC_HSL, 0);
601 cfg &= ~AT91_EMAC_MTI;
604 at91_emac_write(AT91_EMAC_CFG, cfg);
607 /* ......................... ETHTOOL SUPPORT ........................... */
609 static int mdio_read(struct net_device *dev, int phy_id, int location)
611 unsigned int value;
613 read_phy(phy_id, location, &value);
614 return value;
617 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
619 write_phy(phy_id, location, value);
622 static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
624 struct at91_private *lp = netdev_priv(dev);
625 int ret;
627 spin_lock_irq(&lp->lock);
628 enable_mdi();
630 ret = mii_ethtool_gset(&lp->mii, cmd);
632 disable_mdi();
633 spin_unlock_irq(&lp->lock);
635 if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */
636 cmd->supported = SUPPORTED_FIBRE;
637 cmd->port = PORT_FIBRE;
640 return ret;
643 static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
645 struct at91_private *lp = netdev_priv(dev);
646 int ret;
648 spin_lock_irq(&lp->lock);
649 enable_mdi();
651 ret = mii_ethtool_sset(&lp->mii, cmd);
653 disable_mdi();
654 spin_unlock_irq(&lp->lock);
656 return ret;
659 static int at91ether_nwayreset(struct net_device *dev)
661 struct at91_private *lp = netdev_priv(dev);
662 int ret;
664 spin_lock_irq(&lp->lock);
665 enable_mdi();
667 ret = mii_nway_restart(&lp->mii);
669 disable_mdi();
670 spin_unlock_irq(&lp->lock);
672 return ret;
675 static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
677 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
678 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
679 strlcpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info));
682 static const struct ethtool_ops at91ether_ethtool_ops = {
683 .get_settings = at91ether_get_settings,
684 .set_settings = at91ether_set_settings,
685 .get_drvinfo = at91ether_get_drvinfo,
686 .nway_reset = at91ether_nwayreset,
687 .get_link = ethtool_op_get_link,
690 static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
692 struct at91_private *lp = netdev_priv(dev);
693 int res;
695 if (!netif_running(dev))
696 return -EINVAL;
698 spin_lock_irq(&lp->lock);
699 enable_mdi();
700 res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL);
701 disable_mdi();
702 spin_unlock_irq(&lp->lock);
704 return res;
707 /* ................................ MAC ................................ */
710 * Initialize and start the Receiver and Transmit subsystems
712 static void at91ether_start(struct net_device *dev)
714 struct at91_private *lp = netdev_priv(dev);
715 struct recv_desc_bufs *dlist, *dlist_phys;
716 int i;
717 unsigned long ctl;
719 dlist = lp->dlist;
720 dlist_phys = lp->dlist_phys;
722 for (i = 0; i < MAX_RX_DESCR; i++) {
723 dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0];
724 dlist->descriptors[i].size = 0;
727 /* Set the Wrap bit on the last descriptor */
728 dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP;
730 /* Reset buffer index */
731 lp->rxBuffIndex = 0;
733 /* Program address of descriptor list in Rx Buffer Queue register */
734 at91_emac_write(AT91_EMAC_RBQP, (unsigned long) dlist_phys);
736 /* Enable Receive and Transmit */
737 ctl = at91_emac_read(AT91_EMAC_CTL);
738 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE);
742 * Open the ethernet interface
744 static int at91ether_open(struct net_device *dev)
746 struct at91_private *lp = netdev_priv(dev);
747 unsigned long ctl;
749 if (!is_valid_ether_addr(dev->dev_addr))
750 return -EADDRNOTAVAIL;
752 clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */
754 /* Clear internal statistics */
755 ctl = at91_emac_read(AT91_EMAC_CTL);
756 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_CSR);
758 /* Update the MAC address (incase user has changed it) */
759 update_mac_address(dev);
761 /* Enable PHY interrupt */
762 enable_phyirq(dev);
764 /* Enable MAC interrupts */
765 at91_emac_write(AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA
766 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
767 | AT91_EMAC_ROVR | AT91_EMAC_ABT);
769 /* Determine current link speed */
770 spin_lock_irq(&lp->lock);
771 enable_mdi();
772 update_linkspeed(dev, 0);
773 disable_mdi();
774 spin_unlock_irq(&lp->lock);
776 at91ether_start(dev);
777 netif_start_queue(dev);
778 return 0;
782 * Close the interface
784 static int at91ether_close(struct net_device *dev)
786 struct at91_private *lp = netdev_priv(dev);
787 unsigned long ctl;
789 /* Disable Receiver and Transmitter */
790 ctl = at91_emac_read(AT91_EMAC_CTL);
791 at91_emac_write(AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE));
793 /* Disable PHY interrupt */
794 disable_phyirq(dev);
796 /* Disable MAC interrupts */
797 at91_emac_write(AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA
798 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
799 | AT91_EMAC_ROVR | AT91_EMAC_ABT);
801 netif_stop_queue(dev);
803 clk_disable(lp->ether_clk); /* Disable Peripheral clock */
805 return 0;
809 * Transmit packet.
811 static int at91ether_tx(struct sk_buff *skb, struct net_device *dev)
813 struct at91_private *lp = netdev_priv(dev);
815 if (at91_emac_read(AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) {
816 netif_stop_queue(dev);
818 /* Store packet information (to free when Tx completed) */
819 lp->skb = skb;
820 lp->skb_length = skb->len;
821 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
822 dev->stats.tx_bytes += skb->len;
824 /* Set address of the data in the Transmit Address register */
825 at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr);
826 /* Set length of the packet in the Transmit Control register */
827 at91_emac_write(AT91_EMAC_TCR, skb->len);
829 dev->trans_start = jiffies;
830 } else {
831 printk(KERN_ERR "at91_ether.c: at91ether_tx() called, but device is busy!\n");
832 return 1; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb)
833 on this skb, he also reports -ENETDOWN and printk's, so either
834 we free and return(0) or don't free and return 1 */
837 return 0;
841 * Update the current statistics from the internal statistics registers.
843 static struct net_device_stats *at91ether_stats(struct net_device *dev)
845 int ale, lenerr, seqe, lcol, ecol;
847 if (netif_running(dev)) {
848 dev->stats.rx_packets += at91_emac_read(AT91_EMAC_OK); /* Good frames received */
849 ale = at91_emac_read(AT91_EMAC_ALE);
850 dev->stats.rx_frame_errors += ale; /* Alignment errors */
851 lenerr = at91_emac_read(AT91_EMAC_ELR) + at91_emac_read(AT91_EMAC_USF);
852 dev->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */
853 seqe = at91_emac_read(AT91_EMAC_SEQE);
854 dev->stats.rx_crc_errors += seqe; /* CRC error */
855 dev->stats.rx_fifo_errors += at91_emac_read(AT91_EMAC_DRFC); /* Receive buffer not available */
856 dev->stats.rx_errors += (ale + lenerr + seqe
857 + at91_emac_read(AT91_EMAC_CDE) + at91_emac_read(AT91_EMAC_RJB));
859 dev->stats.tx_packets += at91_emac_read(AT91_EMAC_FRA); /* Frames successfully transmitted */
860 dev->stats.tx_fifo_errors += at91_emac_read(AT91_EMAC_TUE); /* Transmit FIFO underruns */
861 dev->stats.tx_carrier_errors += at91_emac_read(AT91_EMAC_CSE); /* Carrier Sense errors */
862 dev->stats.tx_heartbeat_errors += at91_emac_read(AT91_EMAC_SQEE);/* Heartbeat error */
864 lcol = at91_emac_read(AT91_EMAC_LCOL);
865 ecol = at91_emac_read(AT91_EMAC_ECOL);
866 dev->stats.tx_window_errors += lcol; /* Late collisions */
867 dev->stats.tx_aborted_errors += ecol; /* 16 collisions */
869 dev->stats.collisions += (at91_emac_read(AT91_EMAC_SCOL) + at91_emac_read(AT91_EMAC_MCOL) + lcol + ecol);
871 return &dev->stats;
875 * Extract received frame from buffer descriptors and sent to upper layers.
876 * (Called from interrupt context)
878 static void at91ether_rx(struct net_device *dev)
880 struct at91_private *lp = netdev_priv(dev);
881 struct recv_desc_bufs *dlist;
882 unsigned char *p_recv;
883 struct sk_buff *skb;
884 unsigned int pktlen;
886 dlist = lp->dlist;
887 while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) {
888 p_recv = dlist->recv_buf[lp->rxBuffIndex];
889 pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */
890 skb = dev_alloc_skb(pktlen + 2);
891 if (skb != NULL) {
892 skb_reserve(skb, 2);
893 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
895 skb->protocol = eth_type_trans(skb, dev);
896 dev->stats.rx_bytes += pktlen;
897 netif_rx(skb);
899 else {
900 dev->stats.rx_dropped += 1;
901 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
904 if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST)
905 dev->stats.multicast++;
907 dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */
908 if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */
909 lp->rxBuffIndex = 0;
910 else
911 lp->rxBuffIndex++;
916 * MAC interrupt handler
918 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
920 struct net_device *dev = (struct net_device *) dev_id;
921 struct at91_private *lp = netdev_priv(dev);
922 unsigned long intstatus, ctl;
924 /* MAC Interrupt Status register indicates what interrupts are pending.
925 It is automatically cleared once read. */
926 intstatus = at91_emac_read(AT91_EMAC_ISR);
928 if (intstatus & AT91_EMAC_RCOM) /* Receive complete */
929 at91ether_rx(dev);
931 if (intstatus & AT91_EMAC_TCOM) { /* Transmit complete */
932 /* The TCOM bit is set even if the transmission failed. */
933 if (intstatus & (AT91_EMAC_TUND | AT91_EMAC_RTRY))
934 dev->stats.tx_errors += 1;
936 if (lp->skb) {
937 dev_kfree_skb_irq(lp->skb);
938 lp->skb = NULL;
939 dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE);
941 netif_wake_queue(dev);
944 /* Work-around for Errata #11 */
945 if (intstatus & AT91_EMAC_RBNA) {
946 ctl = at91_emac_read(AT91_EMAC_CTL);
947 at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE);
948 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE);
951 if (intstatus & AT91_EMAC_ROVR)
952 printk("%s: ROVR error\n", dev->name);
954 return IRQ_HANDLED;
957 #ifdef CONFIG_NET_POLL_CONTROLLER
958 static void at91ether_poll_controller(struct net_device *dev)
960 unsigned long flags;
962 local_irq_save(flags);
963 at91ether_interrupt(dev->irq, dev);
964 local_irq_restore(flags);
966 #endif
969 * Initialize the ethernet interface
971 static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_address,
972 struct platform_device *pdev, struct clk *ether_clk)
974 struct at91_eth_data *board_data = pdev->dev.platform_data;
975 struct net_device *dev;
976 struct at91_private *lp;
977 unsigned int val;
978 int res;
980 dev = alloc_etherdev(sizeof(struct at91_private));
981 if (!dev)
982 return -ENOMEM;
984 dev->base_addr = AT91_VA_BASE_EMAC;
985 dev->irq = AT91RM9200_ID_EMAC;
987 /* Install the interrupt handler */
988 if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) {
989 free_netdev(dev);
990 return -EBUSY;
993 /* Allocate memory for DMA Receive descriptors */
994 lp = netdev_priv(dev);
995 lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL);
996 if (lp->dlist == NULL) {
997 free_irq(dev->irq, dev);
998 free_netdev(dev);
999 return -ENOMEM;
1001 lp->board_data = *board_data;
1002 lp->ether_clk = ether_clk;
1003 platform_set_drvdata(pdev, dev);
1005 spin_lock_init(&lp->lock);
1007 ether_setup(dev);
1008 dev->open = at91ether_open;
1009 dev->stop = at91ether_close;
1010 dev->hard_start_xmit = at91ether_tx;
1011 dev->get_stats = at91ether_stats;
1012 dev->set_multicast_list = at91ether_set_rx_mode;
1013 dev->set_mac_address = set_mac_address;
1014 dev->ethtool_ops = &at91ether_ethtool_ops;
1015 dev->do_ioctl = at91ether_ioctl;
1016 #ifdef CONFIG_NET_POLL_CONTROLLER
1017 dev->poll_controller = at91ether_poll_controller;
1018 #endif
1020 SET_NETDEV_DEV(dev, &pdev->dev);
1022 get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */
1023 update_mac_address(dev); /* Program ethernet address into MAC */
1025 at91_emac_write(AT91_EMAC_CTL, 0);
1027 if (lp->board_data.is_rmii)
1028 at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII);
1029 else
1030 at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG);
1032 /* Perform PHY-specific initialization */
1033 spin_lock_irq(&lp->lock);
1034 enable_mdi();
1035 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
1036 read_phy(phy_address, MII_DSCR_REG, &val);
1037 if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */
1038 lp->phy_media = PORT_FIBRE;
1039 } else if (machine_is_csb337()) {
1040 /* mix link activity status into LED2 link state */
1041 write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22);
1042 } else if (machine_is_ecbat91())
1043 write_phy(phy_address, MII_LEDCTRL_REG, 0x156A);
1045 disable_mdi();
1046 spin_unlock_irq(&lp->lock);
1048 lp->mii.dev = dev; /* Support for ethtool */
1049 lp->mii.mdio_read = mdio_read;
1050 lp->mii.mdio_write = mdio_write;
1051 lp->mii.phy_id = phy_address;
1052 lp->mii.phy_id_mask = 0x1f;
1053 lp->mii.reg_num_mask = 0x1f;
1055 lp->phy_type = phy_type; /* Type of PHY connected */
1056 lp->phy_address = phy_address; /* MDI address of PHY */
1058 /* Register the network interface */
1059 res = register_netdev(dev);
1060 if (res) {
1061 free_irq(dev->irq, dev);
1062 free_netdev(dev);
1063 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
1064 return res;
1067 /* Determine current link speed */
1068 spin_lock_irq(&lp->lock);
1069 enable_mdi();
1070 update_linkspeed(dev, 0);
1071 disable_mdi();
1072 spin_unlock_irq(&lp->lock);
1073 netif_carrier_off(dev); /* will be enabled in open() */
1075 /* If board has no PHY IRQ, use a timer to poll the PHY */
1076 if (!lp->board_data.phy_irq_pin) {
1077 init_timer(&lp->check_timer);
1078 lp->check_timer.data = (unsigned long)dev;
1079 lp->check_timer.function = at91ether_check_link;
1080 } else if (lp->board_data.phy_irq_pin >= 32)
1081 gpio_request(lp->board_data.phy_irq_pin, "ethernet_phy");
1083 /* Display ethernet banner */
1084 printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%pM)\n",
1085 dev->name, (uint) dev->base_addr, dev->irq,
1086 at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-",
1087 at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex",
1088 dev->dev_addr);
1089 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID))
1090 printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)");
1091 else if (phy_type == MII_LXT971A_ID)
1092 printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name);
1093 else if (phy_type == MII_RTL8201_ID)
1094 printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name);
1095 else if (phy_type == MII_BCM5221_ID)
1096 printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name);
1097 else if (phy_type == MII_DP83847_ID)
1098 printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name);
1099 else if (phy_type == MII_DP83848_ID)
1100 printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name);
1101 else if (phy_type == MII_AC101L_ID)
1102 printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name);
1103 else if (phy_type == MII_KS8721_ID)
1104 printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name);
1105 else if (phy_type == MII_T78Q21x3_ID)
1106 printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name);
1107 else if (phy_type == MII_LAN83C185_ID)
1108 printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name);
1110 return 0;
1114 * Detect MAC and PHY and perform initialization
1116 static int __init at91ether_probe(struct platform_device *pdev)
1118 unsigned int phyid1, phyid2;
1119 int detected = -1;
1120 unsigned long phy_id;
1121 unsigned short phy_address = 0;
1122 struct clk *ether_clk;
1124 ether_clk = clk_get(&pdev->dev, "ether_clk");
1125 if (IS_ERR(ether_clk)) {
1126 printk(KERN_ERR "at91_ether: no clock defined\n");
1127 return -ENODEV;
1129 clk_enable(ether_clk); /* Enable Peripheral clock */
1131 while ((detected != 0) && (phy_address < 32)) {
1132 /* Read the PHY ID registers */
1133 enable_mdi();
1134 read_phy(phy_address, MII_PHYSID1, &phyid1);
1135 read_phy(phy_address, MII_PHYSID2, &phyid2);
1136 disable_mdi();
1138 phy_id = (phyid1 << 16) | (phyid2 & 0xfff0);
1139 switch (phy_id) {
1140 case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */
1141 case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */
1142 case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */
1143 case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
1144 case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
1145 case MII_DP83847_ID: /* National Semiconductor DP83847: */
1146 case MII_DP83848_ID: /* National Semiconductor DP83848: */
1147 case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
1148 case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
1149 case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */
1150 case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */
1151 detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk);
1152 break;
1155 phy_address++;
1158 clk_disable(ether_clk); /* Disable Peripheral clock */
1160 return detected;
1163 static int __devexit at91ether_remove(struct platform_device *pdev)
1165 struct net_device *dev = platform_get_drvdata(pdev);
1166 struct at91_private *lp = netdev_priv(dev);
1168 if (lp->board_data.phy_irq_pin >= 32)
1169 gpio_free(lp->board_data.phy_irq_pin);
1171 unregister_netdev(dev);
1172 free_irq(dev->irq, dev);
1173 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
1174 clk_put(lp->ether_clk);
1176 platform_set_drvdata(pdev, NULL);
1177 free_netdev(dev);
1178 return 0;
1181 #ifdef CONFIG_PM
1183 static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg)
1185 struct net_device *net_dev = platform_get_drvdata(pdev);
1186 struct at91_private *lp = netdev_priv(net_dev);
1187 int phy_irq = lp->board_data.phy_irq_pin;
1189 if (netif_running(net_dev)) {
1190 if (phy_irq)
1191 disable_irq(phy_irq);
1193 netif_stop_queue(net_dev);
1194 netif_device_detach(net_dev);
1196 clk_disable(lp->ether_clk);
1198 return 0;
1201 static int at91ether_resume(struct platform_device *pdev)
1203 struct net_device *net_dev = platform_get_drvdata(pdev);
1204 struct at91_private *lp = netdev_priv(net_dev);
1205 int phy_irq = lp->board_data.phy_irq_pin;
1207 if (netif_running(net_dev)) {
1208 clk_enable(lp->ether_clk);
1210 netif_device_attach(net_dev);
1211 netif_start_queue(net_dev);
1213 if (phy_irq)
1214 enable_irq(phy_irq);
1216 return 0;
1219 #else
1220 #define at91ether_suspend NULL
1221 #define at91ether_resume NULL
1222 #endif
1224 static struct platform_driver at91ether_driver = {
1225 .probe = at91ether_probe,
1226 .remove = __devexit_p(at91ether_remove),
1227 .suspend = at91ether_suspend,
1228 .resume = at91ether_resume,
1229 .driver = {
1230 .name = DRV_NAME,
1231 .owner = THIS_MODULE,
1235 static int __init at91ether_init(void)
1237 return platform_driver_register(&at91ether_driver);
1240 static void __exit at91ether_exit(void)
1242 platform_driver_unregister(&at91ether_driver);
1245 module_init(at91ether_init)
1246 module_exit(at91ether_exit)
1248 MODULE_LICENSE("GPL");
1249 MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver");
1250 MODULE_AUTHOR("Andrew Victor");
1251 MODULE_ALIAS("platform:" DRV_NAME);