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drivers/net/wireless/b43/main.c: Use printf extension %pV
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / b43 / main.c
blobfa4880366586a554bef9757b8677fded2477cd7f
1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 SDIO support
12 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
13
14 Some parts of the code in this file are derived from the ipw2200
15 driver Copyright(c) 2003 - 2004 Intel Corporation.
16
17 This program is free software; you can redistribute it and/or modify
18 it under the terms of the GNU General Public License as published by
19 the Free Software Foundation; either version 2 of the License, or
20 (at your option) any later version.
21
22 This program is distributed in the hope that it will be useful,
23 but WITHOUT ANY WARRANTY; without even the implied warranty of
24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 GNU General Public License for more details.
26
27 You should have received a copy of the GNU General Public License
28 along with this program; see the file COPYING. If not, write to
29 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
30 Boston, MA 02110-1301, USA.
31
32 */
33
34 #include <linux/delay.h>
35 #include <linux/init.h>
36 #include <linux/moduleparam.h>
37 #include <linux/if_arp.h>
38 #include <linux/etherdevice.h>
39 #include <linux/firmware.h>
40 #include <linux/wireless.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
43 #include <linux/io.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/slab.h>
46 #include <asm/unaligned.h>
47
48 #include "b43.h"
49 #include "main.h"
50 #include "debugfs.h"
51 #include "phy_common.h"
52 #include "phy_g.h"
53 #include "phy_n.h"
54 #include "dma.h"
55 #include "pio.h"
56 #include "sysfs.h"
57 #include "xmit.h"
58 #include "lo.h"
59 #include "pcmcia.h"
60 #include "sdio.h"
61 #include <linux/mmc/sdio_func.h>
62
63 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64 MODULE_AUTHOR("Martin Langer");
65 MODULE_AUTHOR("Stefano Brivio");
66 MODULE_AUTHOR("Michael Buesch");
67 MODULE_AUTHOR("Gábor Stefanik");
68 MODULE_LICENSE("GPL");
69
70 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
71 MODULE_FIRMWARE("b43/ucode11.fw");
72 MODULE_FIRMWARE("b43/ucode13.fw");
73 MODULE_FIRMWARE("b43/ucode14.fw");
74 MODULE_FIRMWARE("b43/ucode15.fw");
75 MODULE_FIRMWARE("b43/ucode5.fw");
76 MODULE_FIRMWARE("b43/ucode9.fw");
77
78 static int modparam_bad_frames_preempt;
79 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
80 MODULE_PARM_DESC(bad_frames_preempt,
81 "enable(1) / disable(0) Bad Frames Preemption");
82
83 static char modparam_fwpostfix[16];
84 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
85 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
86
87 static int modparam_hwpctl;
88 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
89 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
90
91 static int modparam_nohwcrypt;
92 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
93 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
94
95 static int modparam_hwtkip;
96 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
97 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
98
99 static int modparam_qos = 1;
100 module_param_named(qos, modparam_qos, int, 0444);
101 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
102
103 static int modparam_btcoex = 1;
104 module_param_named(btcoex, modparam_btcoex, int, 0444);
105 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
106
107 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
108 module_param_named(verbose, b43_modparam_verbose, int, 0644);
109 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
110
111 static int b43_modparam_pio = B43_PIO_DEFAULT;
112 module_param_named(pio, b43_modparam_pio, int, 0644);
113 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
114
115 static const struct ssb_device_id b43_ssb_tbl[] = {
116 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
117 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
118 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
119 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
120 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
121 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
122 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
123 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
124 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
125 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
126 SSB_DEVTABLE_END
127 };
128
129 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
130
131 /* Channel and ratetables are shared for all devices.
132 * They can't be const, because ieee80211 puts some precalculated
133 * data in there. This data is the same for all devices, so we don't
134 * get concurrency issues */
135 #define RATETAB_ENT(_rateid, _flags) \
136 { \
137 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
138 .hw_value = (_rateid), \
139 .flags = (_flags), \
140 }
141
142 /*
143 * NOTE: When changing this, sync with xmit.c's
144 * b43_plcp_get_bitrate_idx_* functions!
145 */
146 static struct ieee80211_rate __b43_ratetable[] = {
147 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
148 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
149 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
150 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
151 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
152 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
153 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
154 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
155 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
156 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
157 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
158 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
159 };
160
161 #define b43_a_ratetable (__b43_ratetable + 4)
162 #define b43_a_ratetable_size 8
163 #define b43_b_ratetable (__b43_ratetable + 0)
164 #define b43_b_ratetable_size 4
165 #define b43_g_ratetable (__b43_ratetable + 0)
166 #define b43_g_ratetable_size 12
167
168 #define CHAN4G(_channel, _freq, _flags) { \
169 .band = IEEE80211_BAND_2GHZ, \
170 .center_freq = (_freq), \
171 .hw_value = (_channel), \
172 .flags = (_flags), \
173 .max_antenna_gain = 0, \
174 .max_power = 30, \
175 }
176 static struct ieee80211_channel b43_2ghz_chantable[] = {
177 CHAN4G(1, 2412, 0),
178 CHAN4G(2, 2417, 0),
179 CHAN4G(3, 2422, 0),
180 CHAN4G(4, 2427, 0),
181 CHAN4G(5, 2432, 0),
182 CHAN4G(6, 2437, 0),
183 CHAN4G(7, 2442, 0),
184 CHAN4G(8, 2447, 0),
185 CHAN4G(9, 2452, 0),
186 CHAN4G(10, 2457, 0),
187 CHAN4G(11, 2462, 0),
188 CHAN4G(12, 2467, 0),
189 CHAN4G(13, 2472, 0),
190 CHAN4G(14, 2484, 0),
191 };
192 #undef CHAN4G
193
194 #define CHAN5G(_channel, _flags) { \
195 .band = IEEE80211_BAND_5GHZ, \
196 .center_freq = 5000 + (5 * (_channel)), \
197 .hw_value = (_channel), \
198 .flags = (_flags), \
199 .max_antenna_gain = 0, \
200 .max_power = 30, \
201 }
202 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
203 CHAN5G(32, 0), CHAN5G(34, 0),
204 CHAN5G(36, 0), CHAN5G(38, 0),
205 CHAN5G(40, 0), CHAN5G(42, 0),
206 CHAN5G(44, 0), CHAN5G(46, 0),
207 CHAN5G(48, 0), CHAN5G(50, 0),
208 CHAN5G(52, 0), CHAN5G(54, 0),
209 CHAN5G(56, 0), CHAN5G(58, 0),
210 CHAN5G(60, 0), CHAN5G(62, 0),
211 CHAN5G(64, 0), CHAN5G(66, 0),
212 CHAN5G(68, 0), CHAN5G(70, 0),
213 CHAN5G(72, 0), CHAN5G(74, 0),
214 CHAN5G(76, 0), CHAN5G(78, 0),
215 CHAN5G(80, 0), CHAN5G(82, 0),
216 CHAN5G(84, 0), CHAN5G(86, 0),
217 CHAN5G(88, 0), CHAN5G(90, 0),
218 CHAN5G(92, 0), CHAN5G(94, 0),
219 CHAN5G(96, 0), CHAN5G(98, 0),
220 CHAN5G(100, 0), CHAN5G(102, 0),
221 CHAN5G(104, 0), CHAN5G(106, 0),
222 CHAN5G(108, 0), CHAN5G(110, 0),
223 CHAN5G(112, 0), CHAN5G(114, 0),
224 CHAN5G(116, 0), CHAN5G(118, 0),
225 CHAN5G(120, 0), CHAN5G(122, 0),
226 CHAN5G(124, 0), CHAN5G(126, 0),
227 CHAN5G(128, 0), CHAN5G(130, 0),
228 CHAN5G(132, 0), CHAN5G(134, 0),
229 CHAN5G(136, 0), CHAN5G(138, 0),
230 CHAN5G(140, 0), CHAN5G(142, 0),
231 CHAN5G(144, 0), CHAN5G(145, 0),
232 CHAN5G(146, 0), CHAN5G(147, 0),
233 CHAN5G(148, 0), CHAN5G(149, 0),
234 CHAN5G(150, 0), CHAN5G(151, 0),
235 CHAN5G(152, 0), CHAN5G(153, 0),
236 CHAN5G(154, 0), CHAN5G(155, 0),
237 CHAN5G(156, 0), CHAN5G(157, 0),
238 CHAN5G(158, 0), CHAN5G(159, 0),
239 CHAN5G(160, 0), CHAN5G(161, 0),
240 CHAN5G(162, 0), CHAN5G(163, 0),
241 CHAN5G(164, 0), CHAN5G(165, 0),
242 CHAN5G(166, 0), CHAN5G(168, 0),
243 CHAN5G(170, 0), CHAN5G(172, 0),
244 CHAN5G(174, 0), CHAN5G(176, 0),
245 CHAN5G(178, 0), CHAN5G(180, 0),
246 CHAN5G(182, 0), CHAN5G(184, 0),
247 CHAN5G(186, 0), CHAN5G(188, 0),
248 CHAN5G(190, 0), CHAN5G(192, 0),
249 CHAN5G(194, 0), CHAN5G(196, 0),
250 CHAN5G(198, 0), CHAN5G(200, 0),
251 CHAN5G(202, 0), CHAN5G(204, 0),
252 CHAN5G(206, 0), CHAN5G(208, 0),
253 CHAN5G(210, 0), CHAN5G(212, 0),
254 CHAN5G(214, 0), CHAN5G(216, 0),
255 CHAN5G(218, 0), CHAN5G(220, 0),
256 CHAN5G(222, 0), CHAN5G(224, 0),
257 CHAN5G(226, 0), CHAN5G(228, 0),
258 };
259
260 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
261 CHAN5G(34, 0), CHAN5G(36, 0),
262 CHAN5G(38, 0), CHAN5G(40, 0),
263 CHAN5G(42, 0), CHAN5G(44, 0),
264 CHAN5G(46, 0), CHAN5G(48, 0),
265 CHAN5G(52, 0), CHAN5G(56, 0),
266 CHAN5G(60, 0), CHAN5G(64, 0),
267 CHAN5G(100, 0), CHAN5G(104, 0),
268 CHAN5G(108, 0), CHAN5G(112, 0),
269 CHAN5G(116, 0), CHAN5G(120, 0),
270 CHAN5G(124, 0), CHAN5G(128, 0),
271 CHAN5G(132, 0), CHAN5G(136, 0),
272 CHAN5G(140, 0), CHAN5G(149, 0),
273 CHAN5G(153, 0), CHAN5G(157, 0),
274 CHAN5G(161, 0), CHAN5G(165, 0),
275 CHAN5G(184, 0), CHAN5G(188, 0),
276 CHAN5G(192, 0), CHAN5G(196, 0),
277 CHAN5G(200, 0), CHAN5G(204, 0),
278 CHAN5G(208, 0), CHAN5G(212, 0),
279 CHAN5G(216, 0),
280 };
281 #undef CHAN5G
282
283 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
284 .band = IEEE80211_BAND_5GHZ,
285 .channels = b43_5ghz_nphy_chantable,
286 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
287 .bitrates = b43_a_ratetable,
288 .n_bitrates = b43_a_ratetable_size,
289 };
290
291 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
292 .band = IEEE80211_BAND_5GHZ,
293 .channels = b43_5ghz_aphy_chantable,
294 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
295 .bitrates = b43_a_ratetable,
296 .n_bitrates = b43_a_ratetable_size,
297 };
298
299 static struct ieee80211_supported_band b43_band_2GHz = {
300 .band = IEEE80211_BAND_2GHZ,
301 .channels = b43_2ghz_chantable,
302 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
303 .bitrates = b43_g_ratetable,
304 .n_bitrates = b43_g_ratetable_size,
305 };
306
307 static void b43_wireless_core_exit(struct b43_wldev *dev);
308 static int b43_wireless_core_init(struct b43_wldev *dev);
309 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
310 static int b43_wireless_core_start(struct b43_wldev *dev);
311
312 static int b43_ratelimit(struct b43_wl *wl)
313 {
314 if (!wl || !wl->current_dev)
315 return 1;
316 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
317 return 1;
318 /* We are up and running.
319 * Ratelimit the messages to avoid DoS over the net. */
320 return net_ratelimit();
321 }
322
323 void b43info(struct b43_wl *wl, const char *fmt, ...)
324 {
325 struct va_format vaf;
326 va_list args;
327
328 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
329 return;
330 if (!b43_ratelimit(wl))
331 return;
332
333 va_start(args, fmt);
334
335 vaf.fmt = fmt;
336 vaf.va = &args;
337
338 printk(KERN_INFO "b43-%s: %pV",
339 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
340
341 va_end(args);
342 }
343
344 void b43err(struct b43_wl *wl, const char *fmt, ...)
345 {
346 struct va_format vaf;
347 va_list args;
348
349 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
350 return;
351 if (!b43_ratelimit(wl))
352 return;
353
354 va_start(args, fmt);
355
356 vaf.fmt = fmt;
357 vaf.va = &args;
358
359 printk(KERN_ERR "b43-%s ERROR: %pV",
360 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
361
362 va_end(args);
363 }
364
365 void b43warn(struct b43_wl *wl, const char *fmt, ...)
366 {
367 struct va_format vaf;
368 va_list args;
369
370 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
371 return;
372 if (!b43_ratelimit(wl))
373 return;
374
375 va_start(args, fmt);
376
377 vaf.fmt = fmt;
378 vaf.va = &args;
379
380 printk(KERN_WARNING "b43-%s warning: %pV",
381 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
382
383 va_end(args);
384 }
385
386 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
387 {
388 struct va_format vaf;
389 va_list args;
390
391 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
392 return;
393
394 va_start(args, fmt);
395
396 vaf.fmt = fmt;
397 vaf.va = &args;
398
399 printk(KERN_DEBUG "b43-%s debug: %pV",
400 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
401
402 va_end(args);
403 }
404
405 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
406 {
407 u32 macctl;
408
409 B43_WARN_ON(offset % 4 != 0);
410
411 macctl = b43_read32(dev, B43_MMIO_MACCTL);
412 if (macctl & B43_MACCTL_BE)
413 val = swab32(val);
414
415 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
416 mmiowb();
417 b43_write32(dev, B43_MMIO_RAM_DATA, val);
418 }
419
420 static inline void b43_shm_control_word(struct b43_wldev *dev,
421 u16 routing, u16 offset)
422 {
423 u32 control;
424
425 /* "offset" is the WORD offset. */
426 control = routing;
427 control <<= 16;
428 control |= offset;
429 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
430 }
431
432 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
433 {
434 u32 ret;
435
436 if (routing == B43_SHM_SHARED) {
437 B43_WARN_ON(offset & 0x0001);
438 if (offset & 0x0003) {
439 /* Unaligned access */
440 b43_shm_control_word(dev, routing, offset >> 2);
441 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
442 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
443 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
444
445 goto out;
446 }
447 offset >>= 2;
448 }
449 b43_shm_control_word(dev, routing, offset);
450 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
451 out:
452 return ret;
453 }
454
455 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
456 {
457 u16 ret;
458
459 if (routing == B43_SHM_SHARED) {
460 B43_WARN_ON(offset & 0x0001);
461 if (offset & 0x0003) {
462 /* Unaligned access */
463 b43_shm_control_word(dev, routing, offset >> 2);
464 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
465
466 goto out;
467 }
468 offset >>= 2;
469 }
470 b43_shm_control_word(dev, routing, offset);
471 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
472 out:
473 return ret;
474 }
475
476 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
477 {
478 if (routing == B43_SHM_SHARED) {
479 B43_WARN_ON(offset & 0x0001);
480 if (offset & 0x0003) {
481 /* Unaligned access */
482 b43_shm_control_word(dev, routing, offset >> 2);
483 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
484 value & 0xFFFF);
485 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
486 b43_write16(dev, B43_MMIO_SHM_DATA,
487 (value >> 16) & 0xFFFF);
488 return;
489 }
490 offset >>= 2;
491 }
492 b43_shm_control_word(dev, routing, offset);
493 b43_write32(dev, B43_MMIO_SHM_DATA, value);
494 }
495
496 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
497 {
498 if (routing == B43_SHM_SHARED) {
499 B43_WARN_ON(offset & 0x0001);
500 if (offset & 0x0003) {
501 /* Unaligned access */
502 b43_shm_control_word(dev, routing, offset >> 2);
503 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
504 return;
505 }
506 offset >>= 2;
507 }
508 b43_shm_control_word(dev, routing, offset);
509 b43_write16(dev, B43_MMIO_SHM_DATA, value);
510 }
511
512 /* Read HostFlags */
513 u64 b43_hf_read(struct b43_wldev *dev)
514 {
515 u64 ret;
516
517 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
518 ret <<= 16;
519 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
520 ret <<= 16;
521 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
522
523 return ret;
524 }
525
526 /* Write HostFlags */
527 void b43_hf_write(struct b43_wldev *dev, u64 value)
528 {
529 u16 lo, mi, hi;
530
531 lo = (value & 0x00000000FFFFULL);
532 mi = (value & 0x0000FFFF0000ULL) >> 16;
533 hi = (value & 0xFFFF00000000ULL) >> 32;
534 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
535 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
536 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
537 }
538
539 /* Read the firmware capabilities bitmask (Opensource firmware only) */
540 static u16 b43_fwcapa_read(struct b43_wldev *dev)
541 {
542 B43_WARN_ON(!dev->fw.opensource);
543 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
544 }
545
546 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
547 {
548 u32 low, high;
549
550 B43_WARN_ON(dev->dev->id.revision < 3);
551
552 /* The hardware guarantees us an atomic read, if we
553 * read the low register first. */
554 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
555 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
556
557 *tsf = high;
558 *tsf <<= 32;
559 *tsf |= low;
560 }
561
562 static void b43_time_lock(struct b43_wldev *dev)
563 {
564 u32 macctl;
565
566 macctl = b43_read32(dev, B43_MMIO_MACCTL);
567 macctl |= B43_MACCTL_TBTTHOLD;
568 b43_write32(dev, B43_MMIO_MACCTL, macctl);
569 /* Commit the write */
570 b43_read32(dev, B43_MMIO_MACCTL);
571 }
572
573 static void b43_time_unlock(struct b43_wldev *dev)
574 {
575 u32 macctl;
576
577 macctl = b43_read32(dev, B43_MMIO_MACCTL);
578 macctl &= ~B43_MACCTL_TBTTHOLD;
579 b43_write32(dev, B43_MMIO_MACCTL, macctl);
580 /* Commit the write */
581 b43_read32(dev, B43_MMIO_MACCTL);
582 }
583
584 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
585 {
586 u32 low, high;
587
588 B43_WARN_ON(dev->dev->id.revision < 3);
589
590 low = tsf;
591 high = (tsf >> 32);
592 /* The hardware guarantees us an atomic write, if we
593 * write the low register first. */
594 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
595 mmiowb();
596 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
597 mmiowb();
598 }
599
600 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
601 {
602 b43_time_lock(dev);
603 b43_tsf_write_locked(dev, tsf);
604 b43_time_unlock(dev);
605 }
606
607 static
608 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
609 {
610 static const u8 zero_addr[ETH_ALEN] = { 0 };
611 u16 data;
612
613 if (!mac)
614 mac = zero_addr;
615
616 offset |= 0x0020;
617 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
618
619 data = mac[0];
620 data |= mac[1] << 8;
621 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
622 data = mac[2];
623 data |= mac[3] << 8;
624 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
625 data = mac[4];
626 data |= mac[5] << 8;
627 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
628 }
629
630 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
631 {
632 const u8 *mac;
633 const u8 *bssid;
634 u8 mac_bssid[ETH_ALEN * 2];
635 int i;
636 u32 tmp;
637
638 bssid = dev->wl->bssid;
639 mac = dev->wl->mac_addr;
640
641 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
642
643 memcpy(mac_bssid, mac, ETH_ALEN);
644 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
645
646 /* Write our MAC address and BSSID to template ram */
647 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
648 tmp = (u32) (mac_bssid[i + 0]);
649 tmp |= (u32) (mac_bssid[i + 1]) << 8;
650 tmp |= (u32) (mac_bssid[i + 2]) << 16;
651 tmp |= (u32) (mac_bssid[i + 3]) << 24;
652 b43_ram_write(dev, 0x20 + i, tmp);
653 }
654 }
655
656 static void b43_upload_card_macaddress(struct b43_wldev *dev)
657 {
658 b43_write_mac_bssid_templates(dev);
659 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
660 }
661
662 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
663 {
664 /* slot_time is in usec. */
665 /* This test used to exit for all but a G PHY. */
666 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
667 return;
668 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
669 /* Shared memory location 0x0010 is the slot time and should be
670 * set to slot_time; however, this register is initially 0 and changing
671 * the value adversely affects the transmit rate for BCM4311
672 * devices. Until this behavior is unterstood, delete this step
673 *
674 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
675 */
676 }
677
678 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
679 {
680 b43_set_slot_time(dev, 9);
681 }
682
683 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
684 {
685 b43_set_slot_time(dev, 20);
686 }
687
688 /* DummyTransmission function, as documented on
689 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
690 */
691 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
692 {
693 struct b43_phy *phy = &dev->phy;
694 unsigned int i, max_loop;
695 u16 value;
696 u32 buffer[5] = {
697 0x00000000,
698 0x00D40000,
699 0x00000000,
700 0x01000000,
701 0x00000000,
702 };
703
704 if (ofdm) {
705 max_loop = 0x1E;
706 buffer[0] = 0x000201CC;
707 } else {
708 max_loop = 0xFA;
709 buffer[0] = 0x000B846E;
710 }
711
712 for (i = 0; i < 5; i++)
713 b43_ram_write(dev, i * 4, buffer[i]);
714
715 b43_write16(dev, 0x0568, 0x0000);
716 if (dev->dev->id.revision < 11)
717 b43_write16(dev, 0x07C0, 0x0000);
718 else
719 b43_write16(dev, 0x07C0, 0x0100);
720 value = (ofdm ? 0x41 : 0x40);
721 b43_write16(dev, 0x050C, value);
722 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
723 b43_write16(dev, 0x0514, 0x1A02);
724 b43_write16(dev, 0x0508, 0x0000);
725 b43_write16(dev, 0x050A, 0x0000);
726 b43_write16(dev, 0x054C, 0x0000);
727 b43_write16(dev, 0x056A, 0x0014);
728 b43_write16(dev, 0x0568, 0x0826);
729 b43_write16(dev, 0x0500, 0x0000);
730 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
731 //SPEC TODO
732 }
733
734 switch (phy->type) {
735 case B43_PHYTYPE_N:
736 b43_write16(dev, 0x0502, 0x00D0);
737 break;
738 case B43_PHYTYPE_LP:
739 b43_write16(dev, 0x0502, 0x0050);
740 break;
741 default:
742 b43_write16(dev, 0x0502, 0x0030);
743 }
744
745 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
746 b43_radio_write16(dev, 0x0051, 0x0017);
747 for (i = 0x00; i < max_loop; i++) {
748 value = b43_read16(dev, 0x050E);
749 if (value & 0x0080)
750 break;
751 udelay(10);
752 }
753 for (i = 0x00; i < 0x0A; i++) {
754 value = b43_read16(dev, 0x050E);
755 if (value & 0x0400)
756 break;
757 udelay(10);
758 }
759 for (i = 0x00; i < 0x19; i++) {
760 value = b43_read16(dev, 0x0690);
761 if (!(value & 0x0100))
762 break;
763 udelay(10);
764 }
765 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
766 b43_radio_write16(dev, 0x0051, 0x0037);
767 }
768
769 static void key_write(struct b43_wldev *dev,
770 u8 index, u8 algorithm, const u8 *key)
771 {
772 unsigned int i;
773 u32 offset;
774 u16 value;
775 u16 kidx;
776
777 /* Key index/algo block */
778 kidx = b43_kidx_to_fw(dev, index);
779 value = ((kidx << 4) | algorithm);
780 b43_shm_write16(dev, B43_SHM_SHARED,
781 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
782
783 /* Write the key to the Key Table Pointer offset */
784 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
785 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
786 value = key[i];
787 value |= (u16) (key[i + 1]) << 8;
788 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
789 }
790 }
791
792 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
793 {
794 u32 addrtmp[2] = { 0, 0, };
795 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
796
797 if (b43_new_kidx_api(dev))
798 pairwise_keys_start = B43_NR_GROUP_KEYS;
799
800 B43_WARN_ON(index < pairwise_keys_start);
801 /* We have four default TX keys and possibly four default RX keys.
802 * Physical mac 0 is mapped to physical key 4 or 8, depending
803 * on the firmware version.
804 * So we must adjust the index here.
805 */
806 index -= pairwise_keys_start;
807 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
808
809 if (addr) {
810 addrtmp[0] = addr[0];
811 addrtmp[0] |= ((u32) (addr[1]) << 8);
812 addrtmp[0] |= ((u32) (addr[2]) << 16);
813 addrtmp[0] |= ((u32) (addr[3]) << 24);
814 addrtmp[1] = addr[4];
815 addrtmp[1] |= ((u32) (addr[5]) << 8);
816 }
817
818 /* Receive match transmitter address (RCMTA) mechanism */
819 b43_shm_write32(dev, B43_SHM_RCMTA,
820 (index * 2) + 0, addrtmp[0]);
821 b43_shm_write16(dev, B43_SHM_RCMTA,
822 (index * 2) + 1, addrtmp[1]);
823 }
824
825 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
826 * When a packet is received, the iv32 is checked.
827 * - if it doesn't the packet is returned without modification (and software
828 * decryption can be done). That's what happen when iv16 wrap.
829 * - if it does, the rc4 key is computed, and decryption is tried.
830 * Either it will success and B43_RX_MAC_DEC is returned,
831 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
832 * and the packet is not usable (it got modified by the ucode).
833 * So in order to never have B43_RX_MAC_DECERR, we should provide
834 * a iv32 and phase1key that match. Because we drop packets in case of
835 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
836 * packets will be lost without higher layer knowing (ie no resync possible
837 * until next wrap).
838 *
839 * NOTE : this should support 50 key like RCMTA because
840 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
841 */
842 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
843 u16 *phase1key)
844 {
845 unsigned int i;
846 u32 offset;
847 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
848
849 if (!modparam_hwtkip)
850 return;
851
852 if (b43_new_kidx_api(dev))
853 pairwise_keys_start = B43_NR_GROUP_KEYS;
854
855 B43_WARN_ON(index < pairwise_keys_start);
856 /* We have four default TX keys and possibly four default RX keys.
857 * Physical mac 0 is mapped to physical key 4 or 8, depending
858 * on the firmware version.
859 * So we must adjust the index here.
860 */
861 index -= pairwise_keys_start;
862 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
863
864 if (b43_debug(dev, B43_DBG_KEYS)) {
865 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
866 index, iv32);
867 }
868 /* Write the key to the RX tkip shared mem */
869 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
870 for (i = 0; i < 10; i += 2) {
871 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
872 phase1key ? phase1key[i / 2] : 0);
873 }
874 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
875 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
876 }
877
878 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
879 struct ieee80211_vif *vif,
880 struct ieee80211_key_conf *keyconf,
881 struct ieee80211_sta *sta,
882 u32 iv32, u16 *phase1key)
883 {
884 struct b43_wl *wl = hw_to_b43_wl(hw);
885 struct b43_wldev *dev;
886 int index = keyconf->hw_key_idx;
887
888 if (B43_WARN_ON(!modparam_hwtkip))
889 return;
890
891 /* This is only called from the RX path through mac80211, where
892 * our mutex is already locked. */
893 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
894 dev = wl->current_dev;
895 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
896
897 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
898
899 rx_tkip_phase1_write(dev, index, iv32, phase1key);
900 /* only pairwise TKIP keys are supported right now */
901 if (WARN_ON(!sta))
902 return;
903 keymac_write(dev, index, sta->addr);
904 }
905
906 static void do_key_write(struct b43_wldev *dev,
907 u8 index, u8 algorithm,
908 const u8 *key, size_t key_len, const u8 *mac_addr)
909 {
910 u8 buf[B43_SEC_KEYSIZE] = { 0, };
911 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
912
913 if (b43_new_kidx_api(dev))
914 pairwise_keys_start = B43_NR_GROUP_KEYS;
915
916 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
917 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
918
919 if (index >= pairwise_keys_start)
920 keymac_write(dev, index, NULL); /* First zero out mac. */
921 if (algorithm == B43_SEC_ALGO_TKIP) {
922 /*
923 * We should provide an initial iv32, phase1key pair.
924 * We could start with iv32=0 and compute the corresponding
925 * phase1key, but this means calling ieee80211_get_tkip_key
926 * with a fake skb (or export other tkip function).
927 * Because we are lazy we hope iv32 won't start with
928 * 0xffffffff and let's b43_op_update_tkip_key provide a
929 * correct pair.
930 */
931 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
932 } else if (index >= pairwise_keys_start) /* clear it */
933 rx_tkip_phase1_write(dev, index, 0, NULL);
934 if (key)
935 memcpy(buf, key, key_len);
936 key_write(dev, index, algorithm, buf);
937 if (index >= pairwise_keys_start)
938 keymac_write(dev, index, mac_addr);
939
940 dev->key[index].algorithm = algorithm;
941 }
942
943 static int b43_key_write(struct b43_wldev *dev,
944 int index, u8 algorithm,
945 const u8 *key, size_t key_len,
946 const u8 *mac_addr,
947 struct ieee80211_key_conf *keyconf)
948 {
949 int i;
950 int pairwise_keys_start;
951
952 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
953 * - Temporal Encryption Key (128 bits)
954 * - Temporal Authenticator Tx MIC Key (64 bits)
955 * - Temporal Authenticator Rx MIC Key (64 bits)
956 *
957 * Hardware only store TEK
958 */
959 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
960 key_len = 16;
961 if (key_len > B43_SEC_KEYSIZE)
962 return -EINVAL;
963 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
964 /* Check that we don't already have this key. */
965 B43_WARN_ON(dev->key[i].keyconf == keyconf);
966 }
967 if (index < 0) {
968 /* Pairwise key. Get an empty slot for the key. */
969 if (b43_new_kidx_api(dev))
970 pairwise_keys_start = B43_NR_GROUP_KEYS;
971 else
972 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
973 for (i = pairwise_keys_start;
974 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
975 i++) {
976 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
977 if (!dev->key[i].keyconf) {
978 /* found empty */
979 index = i;
980 break;
981 }
982 }
983 if (index < 0) {
984 b43warn(dev->wl, "Out of hardware key memory\n");
985 return -ENOSPC;
986 }
987 } else
988 B43_WARN_ON(index > 3);
989
990 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
991 if ((index <= 3) && !b43_new_kidx_api(dev)) {
992 /* Default RX key */
993 B43_WARN_ON(mac_addr);
994 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
995 }
996 keyconf->hw_key_idx = index;
997 dev->key[index].keyconf = keyconf;
998
999 return 0;
1000 }
1001
1002 static int b43_key_clear(struct b43_wldev *dev, int index)
1003 {
1004 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1005 return -EINVAL;
1006 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1007 NULL, B43_SEC_KEYSIZE, NULL);
1008 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1009 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1010 NULL, B43_SEC_KEYSIZE, NULL);
1011 }
1012 dev->key[index].keyconf = NULL;
1013
1014 return 0;
1015 }
1016
1017 static void b43_clear_keys(struct b43_wldev *dev)
1018 {
1019 int i, count;
1020
1021 if (b43_new_kidx_api(dev))
1022 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1023 else
1024 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1025 for (i = 0; i < count; i++)
1026 b43_key_clear(dev, i);
1027 }
1028
1029 static void b43_dump_keymemory(struct b43_wldev *dev)
1030 {
1031 unsigned int i, index, count, offset, pairwise_keys_start;
1032 u8 mac[ETH_ALEN];
1033 u16 algo;
1034 u32 rcmta0;
1035 u16 rcmta1;
1036 u64 hf;
1037 struct b43_key *key;
1038
1039 if (!b43_debug(dev, B43_DBG_KEYS))
1040 return;
1041
1042 hf = b43_hf_read(dev);
1043 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1044 !!(hf & B43_HF_USEDEFKEYS));
1045 if (b43_new_kidx_api(dev)) {
1046 pairwise_keys_start = B43_NR_GROUP_KEYS;
1047 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1048 } else {
1049 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1050 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1051 }
1052 for (index = 0; index < count; index++) {
1053 key = &(dev->key[index]);
1054 printk(KERN_DEBUG "Key slot %02u: %s",
1055 index, (key->keyconf == NULL) ? " " : "*");
1056 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1057 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1058 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1059 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1060 }
1061
1062 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1063 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1064 printk(" Algo: %04X/%02X", algo, key->algorithm);
1065
1066 if (index >= pairwise_keys_start) {
1067 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1068 printk(" TKIP: ");
1069 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1070 for (i = 0; i < 14; i += 2) {
1071 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1072 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1073 }
1074 }
1075 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1076 ((index - pairwise_keys_start) * 2) + 0);
1077 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1078 ((index - pairwise_keys_start) * 2) + 1);
1079 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1080 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1081 printk(" MAC: %pM", mac);
1082 } else
1083 printk(" DEFAULT KEY");
1084 printk("\n");
1085 }
1086 }
1087
1088 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1089 {
1090 u32 macctl;
1091 u16 ucstat;
1092 bool hwps;
1093 bool awake;
1094 int i;
1095
1096 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1097 (ps_flags & B43_PS_DISABLED));
1098 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1099
1100 if (ps_flags & B43_PS_ENABLED) {
1101 hwps = 1;
1102 } else if (ps_flags & B43_PS_DISABLED) {
1103 hwps = 0;
1104 } else {
1105 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1106 // and thus is not an AP and we are associated, set bit 25
1107 }
1108 if (ps_flags & B43_PS_AWAKE) {
1109 awake = 1;
1110 } else if (ps_flags & B43_PS_ASLEEP) {
1111 awake = 0;
1112 } else {
1113 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1114 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1115 // successful, set bit26
1116 }
1117
1118 /* FIXME: For now we force awake-on and hwps-off */
1119 hwps = 0;
1120 awake = 1;
1121
1122 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1123 if (hwps)
1124 macctl |= B43_MACCTL_HWPS;
1125 else
1126 macctl &= ~B43_MACCTL_HWPS;
1127 if (awake)
1128 macctl |= B43_MACCTL_AWAKE;
1129 else
1130 macctl &= ~B43_MACCTL_AWAKE;
1131 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1132 /* Commit write */
1133 b43_read32(dev, B43_MMIO_MACCTL);
1134 if (awake && dev->dev->id.revision >= 5) {
1135 /* Wait for the microcode to wake up. */
1136 for (i = 0; i < 100; i++) {
1137 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1138 B43_SHM_SH_UCODESTAT);
1139 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1140 break;
1141 udelay(10);
1142 }
1143 }
1144 }
1145
1146 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1147 {
1148 u32 tmslow;
1149 u32 macctl;
1150
1151 flags |= B43_TMSLOW_PHYCLKEN;
1152 flags |= B43_TMSLOW_PHYRESET;
1153 ssb_device_enable(dev->dev, flags);
1154 msleep(2); /* Wait for the PLL to turn on. */
1155
1156 /* Now take the PHY out of Reset again */
1157 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1158 tmslow |= SSB_TMSLOW_FGC;
1159 tmslow &= ~B43_TMSLOW_PHYRESET;
1160 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1161 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1162 msleep(1);
1163 tmslow &= ~SSB_TMSLOW_FGC;
1164 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1165 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1166 msleep(1);
1167
1168 /* Turn Analog ON, but only if we already know the PHY-type.
1169 * This protects against very early setup where we don't know the
1170 * PHY-type, yet. wireless_core_reset will be called once again later,
1171 * when we know the PHY-type. */
1172 if (dev->phy.ops)
1173 dev->phy.ops->switch_analog(dev, 1);
1174
1175 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1176 macctl &= ~B43_MACCTL_GMODE;
1177 if (flags & B43_TMSLOW_GMODE)
1178 macctl |= B43_MACCTL_GMODE;
1179 macctl |= B43_MACCTL_IHR_ENABLED;
1180 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1181 }
1182
1183 static void handle_irq_transmit_status(struct b43_wldev *dev)
1184 {
1185 u32 v0, v1;
1186 u16 tmp;
1187 struct b43_txstatus stat;
1188
1189 while (1) {
1190 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1191 if (!(v0 & 0x00000001))
1192 break;
1193 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1194
1195 stat.cookie = (v0 >> 16);
1196 stat.seq = (v1 & 0x0000FFFF);
1197 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1198 tmp = (v0 & 0x0000FFFF);
1199 stat.frame_count = ((tmp & 0xF000) >> 12);
1200 stat.rts_count = ((tmp & 0x0F00) >> 8);
1201 stat.supp_reason = ((tmp & 0x001C) >> 2);
1202 stat.pm_indicated = !!(tmp & 0x0080);
1203 stat.intermediate = !!(tmp & 0x0040);
1204 stat.for_ampdu = !!(tmp & 0x0020);
1205 stat.acked = !!(tmp & 0x0002);
1206
1207 b43_handle_txstatus(dev, &stat);
1208 }
1209 }
1210
1211 static void drain_txstatus_queue(struct b43_wldev *dev)
1212 {
1213 u32 dummy;
1214
1215 if (dev->dev->id.revision < 5)
1216 return;
1217 /* Read all entries from the microcode TXstatus FIFO
1218 * and throw them away.
1219 */
1220 while (1) {
1221 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1222 if (!(dummy & 0x00000001))
1223 break;
1224 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1225 }
1226 }
1227
1228 static u32 b43_jssi_read(struct b43_wldev *dev)
1229 {
1230 u32 val = 0;
1231
1232 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1233 val <<= 16;
1234 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1235
1236 return val;
1237 }
1238
1239 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1240 {
1241 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1242 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1243 }
1244
1245 static void b43_generate_noise_sample(struct b43_wldev *dev)
1246 {
1247 b43_jssi_write(dev, 0x7F7F7F7F);
1248 b43_write32(dev, B43_MMIO_MACCMD,
1249 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1250 }
1251
1252 static void b43_calculate_link_quality(struct b43_wldev *dev)
1253 {
1254 /* Top half of Link Quality calculation. */
1255
1256 if (dev->phy.type != B43_PHYTYPE_G)
1257 return;
1258 if (dev->noisecalc.calculation_running)
1259 return;
1260 dev->noisecalc.calculation_running = 1;
1261 dev->noisecalc.nr_samples = 0;
1262
1263 b43_generate_noise_sample(dev);
1264 }
1265
1266 static void handle_irq_noise(struct b43_wldev *dev)
1267 {
1268 struct b43_phy_g *phy = dev->phy.g;
1269 u16 tmp;
1270 u8 noise[4];
1271 u8 i, j;
1272 s32 average;
1273
1274 /* Bottom half of Link Quality calculation. */
1275
1276 if (dev->phy.type != B43_PHYTYPE_G)
1277 return;
1278
1279 /* Possible race condition: It might be possible that the user
1280 * changed to a different channel in the meantime since we
1281 * started the calculation. We ignore that fact, since it's
1282 * not really that much of a problem. The background noise is
1283 * an estimation only anyway. Slightly wrong results will get damped
1284 * by the averaging of the 8 sample rounds. Additionally the
1285 * value is shortlived. So it will be replaced by the next noise
1286 * calculation round soon. */
1287
1288 B43_WARN_ON(!dev->noisecalc.calculation_running);
1289 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1290 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1291 noise[2] == 0x7F || noise[3] == 0x7F)
1292 goto generate_new;
1293
1294 /* Get the noise samples. */
1295 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1296 i = dev->noisecalc.nr_samples;
1297 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1298 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1299 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1300 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1301 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1302 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1303 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1304 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1305 dev->noisecalc.nr_samples++;
1306 if (dev->noisecalc.nr_samples == 8) {
1307 /* Calculate the Link Quality by the noise samples. */
1308 average = 0;
1309 for (i = 0; i < 8; i++) {
1310 for (j = 0; j < 4; j++)
1311 average += dev->noisecalc.samples[i][j];
1312 }
1313 average /= (8 * 4);
1314 average *= 125;
1315 average += 64;
1316 average /= 128;
1317 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1318 tmp = (tmp / 128) & 0x1F;
1319 if (tmp >= 8)
1320 average += 2;
1321 else
1322 average -= 25;
1323 if (tmp == 8)
1324 average -= 72;
1325 else
1326 average -= 48;
1327
1328 dev->stats.link_noise = average;
1329 dev->noisecalc.calculation_running = 0;
1330 return;
1331 }
1332 generate_new:
1333 b43_generate_noise_sample(dev);
1334 }
1335
1336 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1337 {
1338 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1339 ///TODO: PS TBTT
1340 } else {
1341 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1342 b43_power_saving_ctl_bits(dev, 0);
1343 }
1344 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1345 dev->dfq_valid = 1;
1346 }
1347
1348 static void handle_irq_atim_end(struct b43_wldev *dev)
1349 {
1350 if (dev->dfq_valid) {
1351 b43_write32(dev, B43_MMIO_MACCMD,
1352 b43_read32(dev, B43_MMIO_MACCMD)
1353 | B43_MACCMD_DFQ_VALID);
1354 dev->dfq_valid = 0;
1355 }
1356 }
1357
1358 static void handle_irq_pmq(struct b43_wldev *dev)
1359 {
1360 u32 tmp;
1361
1362 //TODO: AP mode.
1363
1364 while (1) {
1365 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1366 if (!(tmp & 0x00000008))
1367 break;
1368 }
1369 /* 16bit write is odd, but correct. */
1370 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1371 }
1372
1373 static void b43_write_template_common(struct b43_wldev *dev,
1374 const u8 *data, u16 size,
1375 u16 ram_offset,
1376 u16 shm_size_offset, u8 rate)
1377 {
1378 u32 i, tmp;
1379 struct b43_plcp_hdr4 plcp;
1380
1381 plcp.data = 0;
1382 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1383 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1384 ram_offset += sizeof(u32);
1385 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1386 * So leave the first two bytes of the next write blank.
1387 */
1388 tmp = (u32) (data[0]) << 16;
1389 tmp |= (u32) (data[1]) << 24;
1390 b43_ram_write(dev, ram_offset, tmp);
1391 ram_offset += sizeof(u32);
1392 for (i = 2; i < size; i += sizeof(u32)) {
1393 tmp = (u32) (data[i + 0]);
1394 if (i + 1 < size)
1395 tmp |= (u32) (data[i + 1]) << 8;
1396 if (i + 2 < size)
1397 tmp |= (u32) (data[i + 2]) << 16;
1398 if (i + 3 < size)
1399 tmp |= (u32) (data[i + 3]) << 24;
1400 b43_ram_write(dev, ram_offset + i - 2, tmp);
1401 }
1402 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1403 size + sizeof(struct b43_plcp_hdr6));
1404 }
1405
1406 /* Check if the use of the antenna that ieee80211 told us to
1407 * use is possible. This will fall back to DEFAULT.
1408 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1409 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1410 u8 antenna_nr)
1411 {
1412 u8 antenna_mask;
1413
1414 if (antenna_nr == 0) {
1415 /* Zero means "use default antenna". That's always OK. */
1416 return 0;
1417 }
1418
1419 /* Get the mask of available antennas. */
1420 if (dev->phy.gmode)
1421 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1422 else
1423 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1424
1425 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1426 /* This antenna is not available. Fall back to default. */
1427 return 0;
1428 }
1429
1430 return antenna_nr;
1431 }
1432
1433 /* Convert a b43 antenna number value to the PHY TX control value. */
1434 static u16 b43_antenna_to_phyctl(int antenna)
1435 {
1436 switch (antenna) {
1437 case B43_ANTENNA0:
1438 return B43_TXH_PHY_ANT0;
1439 case B43_ANTENNA1:
1440 return B43_TXH_PHY_ANT1;
1441 case B43_ANTENNA2:
1442 return B43_TXH_PHY_ANT2;
1443 case B43_ANTENNA3:
1444 return B43_TXH_PHY_ANT3;
1445 case B43_ANTENNA_AUTO0:
1446 case B43_ANTENNA_AUTO1:
1447 return B43_TXH_PHY_ANT01AUTO;
1448 }
1449 B43_WARN_ON(1);
1450 return 0;
1451 }
1452
1453 static void b43_write_beacon_template(struct b43_wldev *dev,
1454 u16 ram_offset,
1455 u16 shm_size_offset)
1456 {
1457 unsigned int i, len, variable_len;
1458 const struct ieee80211_mgmt *bcn;
1459 const u8 *ie;
1460 bool tim_found = 0;
1461 unsigned int rate;
1462 u16 ctl;
1463 int antenna;
1464 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1465
1466 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1467 len = min((size_t) dev->wl->current_beacon->len,
1468 0x200 - sizeof(struct b43_plcp_hdr6));
1469 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1470
1471 b43_write_template_common(dev, (const u8 *)bcn,
1472 len, ram_offset, shm_size_offset, rate);
1473
1474 /* Write the PHY TX control parameters. */
1475 antenna = B43_ANTENNA_DEFAULT;
1476 antenna = b43_antenna_to_phyctl(antenna);
1477 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1478 /* We can't send beacons with short preamble. Would get PHY errors. */
1479 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1480 ctl &= ~B43_TXH_PHY_ANT;
1481 ctl &= ~B43_TXH_PHY_ENC;
1482 ctl |= antenna;
1483 if (b43_is_cck_rate(rate))
1484 ctl |= B43_TXH_PHY_ENC_CCK;
1485 else
1486 ctl |= B43_TXH_PHY_ENC_OFDM;
1487 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1488
1489 /* Find the position of the TIM and the DTIM_period value
1490 * and write them to SHM. */
1491 ie = bcn->u.beacon.variable;
1492 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1493 for (i = 0; i < variable_len - 2; ) {
1494 uint8_t ie_id, ie_len;
1495
1496 ie_id = ie[i];
1497 ie_len = ie[i + 1];
1498 if (ie_id == 5) {
1499 u16 tim_position;
1500 u16 dtim_period;
1501 /* This is the TIM Information Element */
1502
1503 /* Check whether the ie_len is in the beacon data range. */
1504 if (variable_len < ie_len + 2 + i)
1505 break;
1506 /* A valid TIM is at least 4 bytes long. */
1507 if (ie_len < 4)
1508 break;
1509 tim_found = 1;
1510
1511 tim_position = sizeof(struct b43_plcp_hdr6);
1512 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1513 tim_position += i;
1514
1515 dtim_period = ie[i + 3];
1516
1517 b43_shm_write16(dev, B43_SHM_SHARED,
1518 B43_SHM_SH_TIMBPOS, tim_position);
1519 b43_shm_write16(dev, B43_SHM_SHARED,
1520 B43_SHM_SH_DTIMPER, dtim_period);
1521 break;
1522 }
1523 i += ie_len + 2;
1524 }
1525 if (!tim_found) {
1526 /*
1527 * If ucode wants to modify TIM do it behind the beacon, this
1528 * will happen, for example, when doing mesh networking.
1529 */
1530 b43_shm_write16(dev, B43_SHM_SHARED,
1531 B43_SHM_SH_TIMBPOS,
1532 len + sizeof(struct b43_plcp_hdr6));
1533 b43_shm_write16(dev, B43_SHM_SHARED,
1534 B43_SHM_SH_DTIMPER, 0);
1535 }
1536 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1537 }
1538
1539 static void b43_upload_beacon0(struct b43_wldev *dev)
1540 {
1541 struct b43_wl *wl = dev->wl;
1542
1543 if (wl->beacon0_uploaded)
1544 return;
1545 b43_write_beacon_template(dev, 0x68, 0x18);
1546 wl->beacon0_uploaded = 1;
1547 }
1548
1549 static void b43_upload_beacon1(struct b43_wldev *dev)
1550 {
1551 struct b43_wl *wl = dev->wl;
1552
1553 if (wl->beacon1_uploaded)
1554 return;
1555 b43_write_beacon_template(dev, 0x468, 0x1A);
1556 wl->beacon1_uploaded = 1;
1557 }
1558
1559 static void handle_irq_beacon(struct b43_wldev *dev)
1560 {
1561 struct b43_wl *wl = dev->wl;
1562 u32 cmd, beacon0_valid, beacon1_valid;
1563
1564 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1565 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
1566 return;
1567
1568 /* This is the bottom half of the asynchronous beacon update. */
1569
1570 /* Ignore interrupt in the future. */
1571 dev->irq_mask &= ~B43_IRQ_BEACON;
1572
1573 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1574 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1575 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1576
1577 /* Schedule interrupt manually, if busy. */
1578 if (beacon0_valid && beacon1_valid) {
1579 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1580 dev->irq_mask |= B43_IRQ_BEACON;
1581 return;
1582 }
1583
1584 if (unlikely(wl->beacon_templates_virgin)) {
1585 /* We never uploaded a beacon before.
1586 * Upload both templates now, but only mark one valid. */
1587 wl->beacon_templates_virgin = 0;
1588 b43_upload_beacon0(dev);
1589 b43_upload_beacon1(dev);
1590 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1591 cmd |= B43_MACCMD_BEACON0_VALID;
1592 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1593 } else {
1594 if (!beacon0_valid) {
1595 b43_upload_beacon0(dev);
1596 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1597 cmd |= B43_MACCMD_BEACON0_VALID;
1598 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1599 } else if (!beacon1_valid) {
1600 b43_upload_beacon1(dev);
1601 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1602 cmd |= B43_MACCMD_BEACON1_VALID;
1603 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1604 }
1605 }
1606 }
1607
1608 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1609 {
1610 u32 old_irq_mask = dev->irq_mask;
1611
1612 /* update beacon right away or defer to irq */
1613 handle_irq_beacon(dev);
1614 if (old_irq_mask != dev->irq_mask) {
1615 /* The handler updated the IRQ mask. */
1616 B43_WARN_ON(!dev->irq_mask);
1617 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1618 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1619 } else {
1620 /* Device interrupts are currently disabled. That means
1621 * we just ran the hardirq handler and scheduled the
1622 * IRQ thread. The thread will write the IRQ mask when
1623 * it finished, so there's nothing to do here. Writing
1624 * the mask _here_ would incorrectly re-enable IRQs. */
1625 }
1626 }
1627 }
1628
1629 static void b43_beacon_update_trigger_work(struct work_struct *work)
1630 {
1631 struct b43_wl *wl = container_of(work, struct b43_wl,
1632 beacon_update_trigger);
1633 struct b43_wldev *dev;
1634
1635 mutex_lock(&wl->mutex);
1636 dev = wl->current_dev;
1637 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1638 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
1639 /* wl->mutex is enough. */
1640 b43_do_beacon_update_trigger_work(dev);
1641 mmiowb();
1642 } else {
1643 spin_lock_irq(&wl->hardirq_lock);
1644 b43_do_beacon_update_trigger_work(dev);
1645 mmiowb();
1646 spin_unlock_irq(&wl->hardirq_lock);
1647 }
1648 }
1649 mutex_unlock(&wl->mutex);
1650 }
1651
1652 /* Asynchronously update the packet templates in template RAM.
1653 * Locking: Requires wl->mutex to be locked. */
1654 static void b43_update_templates(struct b43_wl *wl)
1655 {
1656 struct sk_buff *beacon;
1657
1658 /* This is the top half of the ansynchronous beacon update.
1659 * The bottom half is the beacon IRQ.
1660 * Beacon update must be asynchronous to avoid sending an
1661 * invalid beacon. This can happen for example, if the firmware
1662 * transmits a beacon while we are updating it. */
1663
1664 /* We could modify the existing beacon and set the aid bit in
1665 * the TIM field, but that would probably require resizing and
1666 * moving of data within the beacon template.
1667 * Simply request a new beacon and let mac80211 do the hard work. */
1668 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1669 if (unlikely(!beacon))
1670 return;
1671
1672 if (wl->current_beacon)
1673 dev_kfree_skb_any(wl->current_beacon);
1674 wl->current_beacon = beacon;
1675 wl->beacon0_uploaded = 0;
1676 wl->beacon1_uploaded = 0;
1677 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1678 }
1679
1680 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1681 {
1682 b43_time_lock(dev);
1683 if (dev->dev->id.revision >= 3) {
1684 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1685 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1686 } else {
1687 b43_write16(dev, 0x606, (beacon_int >> 6));
1688 b43_write16(dev, 0x610, beacon_int);
1689 }
1690 b43_time_unlock(dev);
1691 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1692 }
1693
1694 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1695 {
1696 u16 reason;
1697
1698 /* Read the register that contains the reason code for the panic. */
1699 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1700 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1701
1702 switch (reason) {
1703 default:
1704 b43dbg(dev->wl, "The panic reason is unknown.\n");
1705 /* fallthrough */
1706 case B43_FWPANIC_DIE:
1707 /* Do not restart the controller or firmware.
1708 * The device is nonfunctional from now on.
1709 * Restarting would result in this panic to trigger again,
1710 * so we avoid that recursion. */
1711 break;
1712 case B43_FWPANIC_RESTART:
1713 b43_controller_restart(dev, "Microcode panic");
1714 break;
1715 }
1716 }
1717
1718 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1719 {
1720 unsigned int i, cnt;
1721 u16 reason, marker_id, marker_line;
1722 __le16 *buf;
1723
1724 /* The proprietary firmware doesn't have this IRQ. */
1725 if (!dev->fw.opensource)
1726 return;
1727
1728 /* Read the register that contains the reason code for this IRQ. */
1729 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1730
1731 switch (reason) {
1732 case B43_DEBUGIRQ_PANIC:
1733 b43_handle_firmware_panic(dev);
1734 break;
1735 case B43_DEBUGIRQ_DUMP_SHM:
1736 if (!B43_DEBUG)
1737 break; /* Only with driver debugging enabled. */
1738 buf = kmalloc(4096, GFP_ATOMIC);
1739 if (!buf) {
1740 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1741 goto out;
1742 }
1743 for (i = 0; i < 4096; i += 2) {
1744 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1745 buf[i / 2] = cpu_to_le16(tmp);
1746 }
1747 b43info(dev->wl, "Shared memory dump:\n");
1748 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1749 16, 2, buf, 4096, 1);
1750 kfree(buf);
1751 break;
1752 case B43_DEBUGIRQ_DUMP_REGS:
1753 if (!B43_DEBUG)
1754 break; /* Only with driver debugging enabled. */
1755 b43info(dev->wl, "Microcode register dump:\n");
1756 for (i = 0, cnt = 0; i < 64; i++) {
1757 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1758 if (cnt == 0)
1759 printk(KERN_INFO);
1760 printk("r%02u: 0x%04X ", i, tmp);
1761 cnt++;
1762 if (cnt == 6) {
1763 printk("\n");
1764 cnt = 0;
1765 }
1766 }
1767 printk("\n");
1768 break;
1769 case B43_DEBUGIRQ_MARKER:
1770 if (!B43_DEBUG)
1771 break; /* Only with driver debugging enabled. */
1772 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1773 B43_MARKER_ID_REG);
1774 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1775 B43_MARKER_LINE_REG);
1776 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1777 "at line number %u\n",
1778 marker_id, marker_line);
1779 break;
1780 default:
1781 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1782 reason);
1783 }
1784 out:
1785 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1786 b43_shm_write16(dev, B43_SHM_SCRATCH,
1787 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1788 }
1789
1790 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1791 {
1792 u32 reason;
1793 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1794 u32 merged_dma_reason = 0;
1795 int i;
1796
1797 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1798 return;
1799
1800 reason = dev->irq_reason;
1801 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1802 dma_reason[i] = dev->dma_reason[i];
1803 merged_dma_reason |= dma_reason[i];
1804 }
1805
1806 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1807 b43err(dev->wl, "MAC transmission error\n");
1808
1809 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1810 b43err(dev->wl, "PHY transmission error\n");
1811 rmb();
1812 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1813 atomic_set(&dev->phy.txerr_cnt,
1814 B43_PHY_TX_BADNESS_LIMIT);
1815 b43err(dev->wl, "Too many PHY TX errors, "
1816 "restarting the controller\n");
1817 b43_controller_restart(dev, "PHY TX errors");
1818 }
1819 }
1820
1821 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1822 B43_DMAIRQ_NONFATALMASK))) {
1823 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1824 b43err(dev->wl, "Fatal DMA error: "
1825 "0x%08X, 0x%08X, 0x%08X, "
1826 "0x%08X, 0x%08X, 0x%08X\n",
1827 dma_reason[0], dma_reason[1],
1828 dma_reason[2], dma_reason[3],
1829 dma_reason[4], dma_reason[5]);
1830 b43err(dev->wl, "This device does not support DMA "
1831 "on your system. It will now be switched to PIO.\n");
1832 /* Fall back to PIO transfers if we get fatal DMA errors! */
1833 dev->use_pio = 1;
1834 b43_controller_restart(dev, "DMA error");
1835 return;
1836 }
1837 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1838 b43err(dev->wl, "DMA error: "
1839 "0x%08X, 0x%08X, 0x%08X, "
1840 "0x%08X, 0x%08X, 0x%08X\n",
1841 dma_reason[0], dma_reason[1],
1842 dma_reason[2], dma_reason[3],
1843 dma_reason[4], dma_reason[5]);
1844 }
1845 }
1846
1847 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1848 handle_irq_ucode_debug(dev);
1849 if (reason & B43_IRQ_TBTT_INDI)
1850 handle_irq_tbtt_indication(dev);
1851 if (reason & B43_IRQ_ATIM_END)
1852 handle_irq_atim_end(dev);
1853 if (reason & B43_IRQ_BEACON)
1854 handle_irq_beacon(dev);
1855 if (reason & B43_IRQ_PMQ)
1856 handle_irq_pmq(dev);
1857 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1858 ;/* TODO */
1859 if (reason & B43_IRQ_NOISESAMPLE_OK)
1860 handle_irq_noise(dev);
1861
1862 /* Check the DMA reason registers for received data. */
1863 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1864 if (b43_using_pio_transfers(dev))
1865 b43_pio_rx(dev->pio.rx_queue);
1866 else
1867 b43_dma_rx(dev->dma.rx_ring);
1868 }
1869 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1870 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1871 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1872 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1873 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1874
1875 if (reason & B43_IRQ_TX_OK)
1876 handle_irq_transmit_status(dev);
1877
1878 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1879 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1880
1881 #if B43_DEBUG
1882 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1883 dev->irq_count++;
1884 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1885 if (reason & (1 << i))
1886 dev->irq_bit_count[i]++;
1887 }
1888 }
1889 #endif
1890 }
1891
1892 /* Interrupt thread handler. Handles device interrupts in thread context. */
1893 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1894 {
1895 struct b43_wldev *dev = dev_id;
1896
1897 mutex_lock(&dev->wl->mutex);
1898 b43_do_interrupt_thread(dev);
1899 mmiowb();
1900 mutex_unlock(&dev->wl->mutex);
1901
1902 return IRQ_HANDLED;
1903 }
1904
1905 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1906 {
1907 u32 reason;
1908
1909 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1910 * On SDIO, this runs under wl->mutex. */
1911
1912 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1913 if (reason == 0xffffffff) /* shared IRQ */
1914 return IRQ_NONE;
1915 reason &= dev->irq_mask;
1916 if (!reason)
1917 return IRQ_HANDLED;
1918
1919 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1920 & 0x0001DC00;
1921 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1922 & 0x0000DC00;
1923 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1924 & 0x0000DC00;
1925 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1926 & 0x0001DC00;
1927 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1928 & 0x0000DC00;
1929 /* Unused ring
1930 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1931 & 0x0000DC00;
1932 */
1933
1934 /* ACK the interrupt. */
1935 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1936 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1937 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1938 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1939 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1940 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1941 /* Unused ring
1942 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1943 */
1944
1945 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
1946 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
1947 /* Save the reason bitmasks for the IRQ thread handler. */
1948 dev->irq_reason = reason;
1949
1950 return IRQ_WAKE_THREAD;
1951 }
1952
1953 /* Interrupt handler top-half. This runs with interrupts disabled. */
1954 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1955 {
1956 struct b43_wldev *dev = dev_id;
1957 irqreturn_t ret;
1958
1959 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
1960 return IRQ_NONE;
1961
1962 spin_lock(&dev->wl->hardirq_lock);
1963 ret = b43_do_interrupt(dev);
1964 mmiowb();
1965 spin_unlock(&dev->wl->hardirq_lock);
1966
1967 return ret;
1968 }
1969
1970 /* SDIO interrupt handler. This runs in process context. */
1971 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
1972 {
1973 struct b43_wl *wl = dev->wl;
1974 irqreturn_t ret;
1975
1976 mutex_lock(&wl->mutex);
1977
1978 ret = b43_do_interrupt(dev);
1979 if (ret == IRQ_WAKE_THREAD)
1980 b43_do_interrupt_thread(dev);
1981
1982 mutex_unlock(&wl->mutex);
1983 }
1984
1985 void b43_do_release_fw(struct b43_firmware_file *fw)
1986 {
1987 release_firmware(fw->data);
1988 fw->data = NULL;
1989 fw->filename = NULL;
1990 }
1991
1992 static void b43_release_firmware(struct b43_wldev *dev)
1993 {
1994 b43_do_release_fw(&dev->fw.ucode);
1995 b43_do_release_fw(&dev->fw.pcm);
1996 b43_do_release_fw(&dev->fw.initvals);
1997 b43_do_release_fw(&dev->fw.initvals_band);
1998 }
1999
2000 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2001 {
2002 const char text[] =
2003 "You must go to " \
2004 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2005 "and download the correct firmware for this driver version. " \
2006 "Please carefully read all instructions on this website.\n";
2007
2008 if (error)
2009 b43err(wl, text);
2010 else
2011 b43warn(wl, text);
2012 }
2013
2014 int b43_do_request_fw(struct b43_request_fw_context *ctx,
2015 const char *name,
2016 struct b43_firmware_file *fw)
2017 {
2018 const struct firmware *blob;
2019 struct b43_fw_header *hdr;
2020 u32 size;
2021 int err;
2022
2023 if (!name) {
2024 /* Don't fetch anything. Free possibly cached firmware. */
2025 /* FIXME: We should probably keep it anyway, to save some headache
2026 * on suspend/resume with multiband devices. */
2027 b43_do_release_fw(fw);
2028 return 0;
2029 }
2030 if (fw->filename) {
2031 if ((fw->type == ctx->req_type) &&
2032 (strcmp(fw->filename, name) == 0))
2033 return 0; /* Already have this fw. */
2034 /* Free the cached firmware first. */
2035 /* FIXME: We should probably do this later after we successfully
2036 * got the new fw. This could reduce headache with multiband devices.
2037 * We could also redesign this to cache the firmware for all possible
2038 * bands all the time. */
2039 b43_do_release_fw(fw);
2040 }
2041
2042 switch (ctx->req_type) {
2043 case B43_FWTYPE_PROPRIETARY:
2044 snprintf(ctx->fwname, sizeof(ctx->fwname),
2045 "b43%s/%s.fw",
2046 modparam_fwpostfix, name);
2047 break;
2048 case B43_FWTYPE_OPENSOURCE:
2049 snprintf(ctx->fwname, sizeof(ctx->fwname),
2050 "b43-open%s/%s.fw",
2051 modparam_fwpostfix, name);
2052 break;
2053 default:
2054 B43_WARN_ON(1);
2055 return -ENOSYS;
2056 }
2057 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2058 if (err == -ENOENT) {
2059 snprintf(ctx->errors[ctx->req_type],
2060 sizeof(ctx->errors[ctx->req_type]),
2061 "Firmware file \"%s\" not found\n", ctx->fwname);
2062 return err;
2063 } else if (err) {
2064 snprintf(ctx->errors[ctx->req_type],
2065 sizeof(ctx->errors[ctx->req_type]),
2066 "Firmware file \"%s\" request failed (err=%d)\n",
2067 ctx->fwname, err);
2068 return err;
2069 }
2070 if (blob->size < sizeof(struct b43_fw_header))
2071 goto err_format;
2072 hdr = (struct b43_fw_header *)(blob->data);
2073 switch (hdr->type) {
2074 case B43_FW_TYPE_UCODE:
2075 case B43_FW_TYPE_PCM:
2076 size = be32_to_cpu(hdr->size);
2077 if (size != blob->size - sizeof(struct b43_fw_header))
2078 goto err_format;
2079 /* fallthrough */
2080 case B43_FW_TYPE_IV:
2081 if (hdr->ver != 1)
2082 goto err_format;
2083 break;
2084 default:
2085 goto err_format;
2086 }
2087
2088 fw->data = blob;
2089 fw->filename = name;
2090 fw->type = ctx->req_type;
2091
2092 return 0;
2093
2094 err_format:
2095 snprintf(ctx->errors[ctx->req_type],
2096 sizeof(ctx->errors[ctx->req_type]),
2097 "Firmware file \"%s\" format error.\n", ctx->fwname);
2098 release_firmware(blob);
2099
2100 return -EPROTO;
2101 }
2102
2103 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2104 {
2105 struct b43_wldev *dev = ctx->dev;
2106 struct b43_firmware *fw = &ctx->dev->fw;
2107 const u8 rev = ctx->dev->dev->id.revision;
2108 const char *filename;
2109 u32 tmshigh;
2110 int err;
2111
2112 /* Get microcode */
2113 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
2114 if ((rev >= 5) && (rev <= 10))
2115 filename = "ucode5";
2116 else if ((rev >= 11) && (rev <= 12))
2117 filename = "ucode11";
2118 else if (rev == 13)
2119 filename = "ucode13";
2120 else if (rev == 14)
2121 filename = "ucode14";
2122 else if (rev >= 15)
2123 filename = "ucode15";
2124 else
2125 goto err_no_ucode;
2126 err = b43_do_request_fw(ctx, filename, &fw->ucode);
2127 if (err)
2128 goto err_load;
2129
2130 /* Get PCM code */
2131 if ((rev >= 5) && (rev <= 10))
2132 filename = "pcm5";
2133 else if (rev >= 11)
2134 filename = NULL;
2135 else
2136 goto err_no_pcm;
2137 fw->pcm_request_failed = 0;
2138 err = b43_do_request_fw(ctx, filename, &fw->pcm);
2139 if (err == -ENOENT) {
2140 /* We did not find a PCM file? Not fatal, but
2141 * core rev <= 10 must do without hwcrypto then. */
2142 fw->pcm_request_failed = 1;
2143 } else if (err)
2144 goto err_load;
2145
2146 /* Get initvals */
2147 switch (dev->phy.type) {
2148 case B43_PHYTYPE_A:
2149 if ((rev >= 5) && (rev <= 10)) {
2150 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2151 filename = "a0g1initvals5";
2152 else
2153 filename = "a0g0initvals5";
2154 } else
2155 goto err_no_initvals;
2156 break;
2157 case B43_PHYTYPE_G:
2158 if ((rev >= 5) && (rev <= 10))
2159 filename = "b0g0initvals5";
2160 else if (rev >= 13)
2161 filename = "b0g0initvals13";
2162 else
2163 goto err_no_initvals;
2164 break;
2165 case B43_PHYTYPE_N:
2166 if ((rev >= 11) && (rev <= 12))
2167 filename = "n0initvals11";
2168 else
2169 goto err_no_initvals;
2170 break;
2171 case B43_PHYTYPE_LP:
2172 if (rev == 13)
2173 filename = "lp0initvals13";
2174 else if (rev == 14)
2175 filename = "lp0initvals14";
2176 else if (rev >= 15)
2177 filename = "lp0initvals15";
2178 else
2179 goto err_no_initvals;
2180 break;
2181 default:
2182 goto err_no_initvals;
2183 }
2184 err = b43_do_request_fw(ctx, filename, &fw->initvals);
2185 if (err)
2186 goto err_load;
2187
2188 /* Get bandswitch initvals */
2189 switch (dev->phy.type) {
2190 case B43_PHYTYPE_A:
2191 if ((rev >= 5) && (rev <= 10)) {
2192 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2193 filename = "a0g1bsinitvals5";
2194 else
2195 filename = "a0g0bsinitvals5";
2196 } else if (rev >= 11)
2197 filename = NULL;
2198 else
2199 goto err_no_initvals;
2200 break;
2201 case B43_PHYTYPE_G:
2202 if ((rev >= 5) && (rev <= 10))
2203 filename = "b0g0bsinitvals5";
2204 else if (rev >= 11)
2205 filename = NULL;
2206 else
2207 goto err_no_initvals;
2208 break;
2209 case B43_PHYTYPE_N:
2210 if ((rev >= 11) && (rev <= 12))
2211 filename = "n0bsinitvals11";
2212 else
2213 goto err_no_initvals;
2214 break;
2215 case B43_PHYTYPE_LP:
2216 if (rev == 13)
2217 filename = "lp0bsinitvals13";
2218 else if (rev == 14)
2219 filename = "lp0bsinitvals14";
2220 else if (rev >= 15)
2221 filename = "lp0bsinitvals15";
2222 else
2223 goto err_no_initvals;
2224 break;
2225 default:
2226 goto err_no_initvals;
2227 }
2228 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2229 if (err)
2230 goto err_load;
2231
2232 return 0;
2233
2234 err_no_ucode:
2235 err = ctx->fatal_failure = -EOPNOTSUPP;
2236 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2237 "is required for your device (wl-core rev %u)\n", rev);
2238 goto error;
2239
2240 err_no_pcm:
2241 err = ctx->fatal_failure = -EOPNOTSUPP;
2242 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2243 "is required for your device (wl-core rev %u)\n", rev);
2244 goto error;
2245
2246 err_no_initvals:
2247 err = ctx->fatal_failure = -EOPNOTSUPP;
2248 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2249 "is required for your device (wl-core rev %u)\n", rev);
2250 goto error;
2251
2252 err_load:
2253 /* We failed to load this firmware image. The error message
2254 * already is in ctx->errors. Return and let our caller decide
2255 * what to do. */
2256 goto error;
2257
2258 error:
2259 b43_release_firmware(dev);
2260 return err;
2261 }
2262
2263 static int b43_request_firmware(struct b43_wldev *dev)
2264 {
2265 struct b43_request_fw_context *ctx;
2266 unsigned int i;
2267 int err;
2268 const char *errmsg;
2269
2270 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2271 if (!ctx)
2272 return -ENOMEM;
2273 ctx->dev = dev;
2274
2275 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2276 err = b43_try_request_fw(ctx);
2277 if (!err)
2278 goto out; /* Successfully loaded it. */
2279 err = ctx->fatal_failure;
2280 if (err)
2281 goto out;
2282
2283 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2284 err = b43_try_request_fw(ctx);
2285 if (!err)
2286 goto out; /* Successfully loaded it. */
2287 err = ctx->fatal_failure;
2288 if (err)
2289 goto out;
2290
2291 /* Could not find a usable firmware. Print the errors. */
2292 for (i = 0; i < B43_NR_FWTYPES; i++) {
2293 errmsg = ctx->errors[i];
2294 if (strlen(errmsg))
2295 b43err(dev->wl, errmsg);
2296 }
2297 b43_print_fw_helptext(dev->wl, 1);
2298 err = -ENOENT;
2299
2300 out:
2301 kfree(ctx);
2302 return err;
2303 }
2304
2305 static int b43_upload_microcode(struct b43_wldev *dev)
2306 {
2307 struct wiphy *wiphy = dev->wl->hw->wiphy;
2308 const size_t hdr_len = sizeof(struct b43_fw_header);
2309 const __be32 *data;
2310 unsigned int i, len;
2311 u16 fwrev, fwpatch, fwdate, fwtime;
2312 u32 tmp, macctl;
2313 int err = 0;
2314
2315 /* Jump the microcode PSM to offset 0 */
2316 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2317 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2318 macctl |= B43_MACCTL_PSM_JMP0;
2319 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2320 /* Zero out all microcode PSM registers and shared memory. */
2321 for (i = 0; i < 64; i++)
2322 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2323 for (i = 0; i < 4096; i += 2)
2324 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2325
2326 /* Upload Microcode. */
2327 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2328 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2329 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2330 for (i = 0; i < len; i++) {
2331 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2332 udelay(10);
2333 }
2334
2335 if (dev->fw.pcm.data) {
2336 /* Upload PCM data. */
2337 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2338 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2339 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2340 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2341 /* No need for autoinc bit in SHM_HW */
2342 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2343 for (i = 0; i < len; i++) {
2344 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2345 udelay(10);
2346 }
2347 }
2348
2349 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2350
2351 /* Start the microcode PSM */
2352 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2353 macctl &= ~B43_MACCTL_PSM_JMP0;
2354 macctl |= B43_MACCTL_PSM_RUN;
2355 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2356
2357 /* Wait for the microcode to load and respond */
2358 i = 0;
2359 while (1) {
2360 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2361 if (tmp == B43_IRQ_MAC_SUSPENDED)
2362 break;
2363 i++;
2364 if (i >= 20) {
2365 b43err(dev->wl, "Microcode not responding\n");
2366 b43_print_fw_helptext(dev->wl, 1);
2367 err = -ENODEV;
2368 goto error;
2369 }
2370 msleep(50);
2371 }
2372 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2373
2374 /* Get and check the revisions. */
2375 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2376 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2377 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2378 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2379
2380 if (fwrev <= 0x128) {
2381 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2382 "binary drivers older than version 4.x is unsupported. "
2383 "You must upgrade your firmware files.\n");
2384 b43_print_fw_helptext(dev->wl, 1);
2385 err = -EOPNOTSUPP;
2386 goto error;
2387 }
2388 dev->fw.rev = fwrev;
2389 dev->fw.patch = fwpatch;
2390 dev->fw.opensource = (fwdate == 0xFFFF);
2391
2392 /* Default to use-all-queues. */
2393 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2394 dev->qos_enabled = !!modparam_qos;
2395 /* Default to firmware/hardware crypto acceleration. */
2396 dev->hwcrypto_enabled = 1;
2397
2398 if (dev->fw.opensource) {
2399 u16 fwcapa;
2400
2401 /* Patchlevel info is encoded in the "time" field. */
2402 dev->fw.patch = fwtime;
2403 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2404 dev->fw.rev, dev->fw.patch);
2405
2406 fwcapa = b43_fwcapa_read(dev);
2407 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2408 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2409 /* Disable hardware crypto and fall back to software crypto. */
2410 dev->hwcrypto_enabled = 0;
2411 }
2412 if (!(fwcapa & B43_FWCAPA_QOS)) {
2413 b43info(dev->wl, "QoS not supported by firmware\n");
2414 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2415 * ieee80211_unregister to make sure the networking core can
2416 * properly free possible resources. */
2417 dev->wl->hw->queues = 1;
2418 dev->qos_enabled = 0;
2419 }
2420 } else {
2421 b43info(dev->wl, "Loading firmware version %u.%u "
2422 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2423 fwrev, fwpatch,
2424 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2425 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2426 if (dev->fw.pcm_request_failed) {
2427 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2428 "Hardware accelerated cryptography is disabled.\n");
2429 b43_print_fw_helptext(dev->wl, 0);
2430 }
2431 }
2432
2433 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2434 dev->fw.rev, dev->fw.patch);
2435 wiphy->hw_version = dev->dev->id.coreid;
2436
2437 if (b43_is_old_txhdr_format(dev)) {
2438 /* We're over the deadline, but we keep support for old fw
2439 * until it turns out to be in major conflict with something new. */
2440 b43warn(dev->wl, "You are using an old firmware image. "
2441 "Support for old firmware will be removed soon "
2442 "(official deadline was July 2008).\n");
2443 b43_print_fw_helptext(dev->wl, 0);
2444 }
2445
2446 return 0;
2447
2448 error:
2449 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2450 macctl &= ~B43_MACCTL_PSM_RUN;
2451 macctl |= B43_MACCTL_PSM_JMP0;
2452 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2453
2454 return err;
2455 }
2456
2457 static int b43_write_initvals(struct b43_wldev *dev,
2458 const struct b43_iv *ivals,
2459 size_t count,
2460 size_t array_size)
2461 {
2462 const struct b43_iv *iv;
2463 u16 offset;
2464 size_t i;
2465 bool bit32;
2466
2467 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2468 iv = ivals;
2469 for (i = 0; i < count; i++) {
2470 if (array_size < sizeof(iv->offset_size))
2471 goto err_format;
2472 array_size -= sizeof(iv->offset_size);
2473 offset = be16_to_cpu(iv->offset_size);
2474 bit32 = !!(offset & B43_IV_32BIT);
2475 offset &= B43_IV_OFFSET_MASK;
2476 if (offset >= 0x1000)
2477 goto err_format;
2478 if (bit32) {
2479 u32 value;
2480
2481 if (array_size < sizeof(iv->data.d32))
2482 goto err_format;
2483 array_size -= sizeof(iv->data.d32);
2484
2485 value = get_unaligned_be32(&iv->data.d32);
2486 b43_write32(dev, offset, value);
2487
2488 iv = (const struct b43_iv *)((const uint8_t *)iv +
2489 sizeof(__be16) +
2490 sizeof(__be32));
2491 } else {
2492 u16 value;
2493
2494 if (array_size < sizeof(iv->data.d16))
2495 goto err_format;
2496 array_size -= sizeof(iv->data.d16);
2497
2498 value = be16_to_cpu(iv->data.d16);
2499 b43_write16(dev, offset, value);
2500
2501 iv = (const struct b43_iv *)((const uint8_t *)iv +
2502 sizeof(__be16) +
2503 sizeof(__be16));
2504 }
2505 }
2506 if (array_size)
2507 goto err_format;
2508
2509 return 0;
2510
2511 err_format:
2512 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2513 b43_print_fw_helptext(dev->wl, 1);
2514
2515 return -EPROTO;
2516 }
2517
2518 static int b43_upload_initvals(struct b43_wldev *dev)
2519 {
2520 const size_t hdr_len = sizeof(struct b43_fw_header);
2521 const struct b43_fw_header *hdr;
2522 struct b43_firmware *fw = &dev->fw;
2523 const struct b43_iv *ivals;
2524 size_t count;
2525 int err;
2526
2527 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2528 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2529 count = be32_to_cpu(hdr->size);
2530 err = b43_write_initvals(dev, ivals, count,
2531 fw->initvals.data->size - hdr_len);
2532 if (err)
2533 goto out;
2534 if (fw->initvals_band.data) {
2535 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2536 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2537 count = be32_to_cpu(hdr->size);
2538 err = b43_write_initvals(dev, ivals, count,
2539 fw->initvals_band.data->size - hdr_len);
2540 if (err)
2541 goto out;
2542 }
2543 out:
2544
2545 return err;
2546 }
2547
2548 /* Initialize the GPIOs
2549 * http://bcm-specs.sipsolutions.net/GPIO
2550 */
2551 static int b43_gpio_init(struct b43_wldev *dev)
2552 {
2553 struct ssb_bus *bus = dev->dev->bus;
2554 struct ssb_device *gpiodev, *pcidev = NULL;
2555 u32 mask, set;
2556
2557 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2558 & ~B43_MACCTL_GPOUTSMSK);
2559
2560 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2561 | 0x000F);
2562
2563 mask = 0x0000001F;
2564 set = 0x0000000F;
2565 if (dev->dev->bus->chip_id == 0x4301) {
2566 mask |= 0x0060;
2567 set |= 0x0060;
2568 }
2569 if (0 /* FIXME: conditional unknown */ ) {
2570 b43_write16(dev, B43_MMIO_GPIO_MASK,
2571 b43_read16(dev, B43_MMIO_GPIO_MASK)
2572 | 0x0100);
2573 mask |= 0x0180;
2574 set |= 0x0180;
2575 }
2576 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2577 b43_write16(dev, B43_MMIO_GPIO_MASK,
2578 b43_read16(dev, B43_MMIO_GPIO_MASK)
2579 | 0x0200);
2580 mask |= 0x0200;
2581 set |= 0x0200;
2582 }
2583 if (dev->dev->id.revision >= 2)
2584 mask |= 0x0010; /* FIXME: This is redundant. */
2585
2586 #ifdef CONFIG_SSB_DRIVER_PCICORE
2587 pcidev = bus->pcicore.dev;
2588 #endif
2589 gpiodev = bus->chipco.dev ? : pcidev;
2590 if (!gpiodev)
2591 return 0;
2592 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2593 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2594 & mask) | set);
2595
2596 return 0;
2597 }
2598
2599 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2600 static void b43_gpio_cleanup(struct b43_wldev *dev)
2601 {
2602 struct ssb_bus *bus = dev->dev->bus;
2603 struct ssb_device *gpiodev, *pcidev = NULL;
2604
2605 #ifdef CONFIG_SSB_DRIVER_PCICORE
2606 pcidev = bus->pcicore.dev;
2607 #endif
2608 gpiodev = bus->chipco.dev ? : pcidev;
2609 if (!gpiodev)
2610 return;
2611 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2612 }
2613
2614 /* http://bcm-specs.sipsolutions.net/EnableMac */
2615 void b43_mac_enable(struct b43_wldev *dev)
2616 {
2617 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2618 u16 fwstate;
2619
2620 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2621 B43_SHM_SH_UCODESTAT);
2622 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2623 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2624 b43err(dev->wl, "b43_mac_enable(): The firmware "
2625 "should be suspended, but current state is %u\n",
2626 fwstate);
2627 }
2628 }
2629
2630 dev->mac_suspended--;
2631 B43_WARN_ON(dev->mac_suspended < 0);
2632 if (dev->mac_suspended == 0) {
2633 b43_write32(dev, B43_MMIO_MACCTL,
2634 b43_read32(dev, B43_MMIO_MACCTL)
2635 | B43_MACCTL_ENABLED);
2636 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2637 B43_IRQ_MAC_SUSPENDED);
2638 /* Commit writes */
2639 b43_read32(dev, B43_MMIO_MACCTL);
2640 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2641 b43_power_saving_ctl_bits(dev, 0);
2642 }
2643 }
2644
2645 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2646 void b43_mac_suspend(struct b43_wldev *dev)
2647 {
2648 int i;
2649 u32 tmp;
2650
2651 might_sleep();
2652 B43_WARN_ON(dev->mac_suspended < 0);
2653
2654 if (dev->mac_suspended == 0) {
2655 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2656 b43_write32(dev, B43_MMIO_MACCTL,
2657 b43_read32(dev, B43_MMIO_MACCTL)
2658 & ~B43_MACCTL_ENABLED);
2659 /* force pci to flush the write */
2660 b43_read32(dev, B43_MMIO_MACCTL);
2661 for (i = 35; i; i--) {
2662 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2663 if (tmp & B43_IRQ_MAC_SUSPENDED)
2664 goto out;
2665 udelay(10);
2666 }
2667 /* Hm, it seems this will take some time. Use msleep(). */
2668 for (i = 40; i; i--) {
2669 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2670 if (tmp & B43_IRQ_MAC_SUSPENDED)
2671 goto out;
2672 msleep(1);
2673 }
2674 b43err(dev->wl, "MAC suspend failed\n");
2675 }
2676 out:
2677 dev->mac_suspended++;
2678 }
2679
2680 static void b43_adjust_opmode(struct b43_wldev *dev)
2681 {
2682 struct b43_wl *wl = dev->wl;
2683 u32 ctl;
2684 u16 cfp_pretbtt;
2685
2686 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2687 /* Reset status to STA infrastructure mode. */
2688 ctl &= ~B43_MACCTL_AP;
2689 ctl &= ~B43_MACCTL_KEEP_CTL;
2690 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2691 ctl &= ~B43_MACCTL_KEEP_BAD;
2692 ctl &= ~B43_MACCTL_PROMISC;
2693 ctl &= ~B43_MACCTL_BEACPROMISC;
2694 ctl |= B43_MACCTL_INFRA;
2695
2696 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2697 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2698 ctl |= B43_MACCTL_AP;
2699 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2700 ctl &= ~B43_MACCTL_INFRA;
2701
2702 if (wl->filter_flags & FIF_CONTROL)
2703 ctl |= B43_MACCTL_KEEP_CTL;
2704 if (wl->filter_flags & FIF_FCSFAIL)
2705 ctl |= B43_MACCTL_KEEP_BAD;
2706 if (wl->filter_flags & FIF_PLCPFAIL)
2707 ctl |= B43_MACCTL_KEEP_BADPLCP;
2708 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2709 ctl |= B43_MACCTL_PROMISC;
2710 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2711 ctl |= B43_MACCTL_BEACPROMISC;
2712
2713 /* Workaround: On old hardware the HW-MAC-address-filter
2714 * doesn't work properly, so always run promisc in filter
2715 * it in software. */
2716 if (dev->dev->id.revision <= 4)
2717 ctl |= B43_MACCTL_PROMISC;
2718
2719 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2720
2721 cfp_pretbtt = 2;
2722 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2723 if (dev->dev->bus->chip_id == 0x4306 &&
2724 dev->dev->bus->chip_rev == 3)
2725 cfp_pretbtt = 100;
2726 else
2727 cfp_pretbtt = 50;
2728 }
2729 b43_write16(dev, 0x612, cfp_pretbtt);
2730
2731 /* FIXME: We don't currently implement the PMQ mechanism,
2732 * so always disable it. If we want to implement PMQ,
2733 * we need to enable it here (clear DISCPMQ) in AP mode.
2734 */
2735 if (0 /* ctl & B43_MACCTL_AP */) {
2736 b43_write32(dev, B43_MMIO_MACCTL,
2737 b43_read32(dev, B43_MMIO_MACCTL)
2738 & ~B43_MACCTL_DISCPMQ);
2739 } else {
2740 b43_write32(dev, B43_MMIO_MACCTL,
2741 b43_read32(dev, B43_MMIO_MACCTL)
2742 | B43_MACCTL_DISCPMQ);
2743 }
2744 }
2745
2746 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2747 {
2748 u16 offset;
2749
2750 if (is_ofdm) {
2751 offset = 0x480;
2752 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2753 } else {
2754 offset = 0x4C0;
2755 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2756 }
2757 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2758 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2759 }
2760
2761 static void b43_rate_memory_init(struct b43_wldev *dev)
2762 {
2763 switch (dev->phy.type) {
2764 case B43_PHYTYPE_A:
2765 case B43_PHYTYPE_G:
2766 case B43_PHYTYPE_N:
2767 case B43_PHYTYPE_LP:
2768 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2769 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2770 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2771 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2772 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2773 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2774 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2775 if (dev->phy.type == B43_PHYTYPE_A)
2776 break;
2777 /* fallthrough */
2778 case B43_PHYTYPE_B:
2779 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2780 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2781 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2782 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2783 break;
2784 default:
2785 B43_WARN_ON(1);
2786 }
2787 }
2788
2789 /* Set the default values for the PHY TX Control Words. */
2790 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2791 {
2792 u16 ctl = 0;
2793
2794 ctl |= B43_TXH_PHY_ENC_CCK;
2795 ctl |= B43_TXH_PHY_ANT01AUTO;
2796 ctl |= B43_TXH_PHY_TXPWR;
2797
2798 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2799 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2800 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2801 }
2802
2803 /* Set the TX-Antenna for management frames sent by firmware. */
2804 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2805 {
2806 u16 ant;
2807 u16 tmp;
2808
2809 ant = b43_antenna_to_phyctl(antenna);
2810
2811 /* For ACK/CTS */
2812 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2813 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2814 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2815 /* For Probe Resposes */
2816 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2817 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2818 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2819 }
2820
2821 /* This is the opposite of b43_chip_init() */
2822 static void b43_chip_exit(struct b43_wldev *dev)
2823 {
2824 b43_phy_exit(dev);
2825 b43_gpio_cleanup(dev);
2826 /* firmware is released later */
2827 }
2828
2829 /* Initialize the chip
2830 * http://bcm-specs.sipsolutions.net/ChipInit
2831 */
2832 static int b43_chip_init(struct b43_wldev *dev)
2833 {
2834 struct b43_phy *phy = &dev->phy;
2835 int err;
2836 u32 value32, macctl;
2837 u16 value16;
2838
2839 /* Initialize the MAC control */
2840 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2841 if (dev->phy.gmode)
2842 macctl |= B43_MACCTL_GMODE;
2843 macctl |= B43_MACCTL_INFRA;
2844 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2845
2846 err = b43_request_firmware(dev);
2847 if (err)
2848 goto out;
2849 err = b43_upload_microcode(dev);
2850 if (err)
2851 goto out; /* firmware is released later */
2852
2853 err = b43_gpio_init(dev);
2854 if (err)
2855 goto out; /* firmware is released later */
2856
2857 err = b43_upload_initvals(dev);
2858 if (err)
2859 goto err_gpio_clean;
2860
2861 /* Turn the Analog on and initialize the PHY. */
2862 phy->ops->switch_analog(dev, 1);
2863 err = b43_phy_init(dev);
2864 if (err)
2865 goto err_gpio_clean;
2866
2867 /* Disable Interference Mitigation. */
2868 if (phy->ops->interf_mitigation)
2869 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
2870
2871 /* Select the antennae */
2872 if (phy->ops->set_rx_antenna)
2873 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2874 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2875
2876 if (phy->type == B43_PHYTYPE_B) {
2877 value16 = b43_read16(dev, 0x005E);
2878 value16 |= 0x0004;
2879 b43_write16(dev, 0x005E, value16);
2880 }
2881 b43_write32(dev, 0x0100, 0x01000000);
2882 if (dev->dev->id.revision < 5)
2883 b43_write32(dev, 0x010C, 0x01000000);
2884
2885 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2886 & ~B43_MACCTL_INFRA);
2887 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2888 | B43_MACCTL_INFRA);
2889
2890 /* Probe Response Timeout value */
2891 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2892 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2893
2894 /* Initially set the wireless operation mode. */
2895 b43_adjust_opmode(dev);
2896
2897 if (dev->dev->id.revision < 3) {
2898 b43_write16(dev, 0x060E, 0x0000);
2899 b43_write16(dev, 0x0610, 0x8000);
2900 b43_write16(dev, 0x0604, 0x0000);
2901 b43_write16(dev, 0x0606, 0x0200);
2902 } else {
2903 b43_write32(dev, 0x0188, 0x80000000);
2904 b43_write32(dev, 0x018C, 0x02000000);
2905 }
2906 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2907 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2908 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2909 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2910 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2911 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2912 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2913
2914 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2915 value32 |= 0x00100000;
2916 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2917
2918 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2919 dev->dev->bus->chipco.fast_pwrup_delay);
2920
2921 err = 0;
2922 b43dbg(dev->wl, "Chip initialized\n");
2923 out:
2924 return err;
2925
2926 err_gpio_clean:
2927 b43_gpio_cleanup(dev);
2928 return err;
2929 }
2930
2931 static void b43_periodic_every60sec(struct b43_wldev *dev)
2932 {
2933 const struct b43_phy_operations *ops = dev->phy.ops;
2934
2935 if (ops->pwork_60sec)
2936 ops->pwork_60sec(dev);
2937
2938 /* Force check the TX power emission now. */
2939 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
2940 }
2941
2942 static void b43_periodic_every30sec(struct b43_wldev *dev)
2943 {
2944 /* Update device statistics. */
2945 b43_calculate_link_quality(dev);
2946 }
2947
2948 static void b43_periodic_every15sec(struct b43_wldev *dev)
2949 {
2950 struct b43_phy *phy = &dev->phy;
2951 u16 wdr;
2952
2953 if (dev->fw.opensource) {
2954 /* Check if the firmware is still alive.
2955 * It will reset the watchdog counter to 0 in its idle loop. */
2956 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2957 if (unlikely(wdr)) {
2958 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2959 b43_controller_restart(dev, "Firmware watchdog");
2960 return;
2961 } else {
2962 b43_shm_write16(dev, B43_SHM_SCRATCH,
2963 B43_WATCHDOG_REG, 1);
2964 }
2965 }
2966
2967 if (phy->ops->pwork_15sec)
2968 phy->ops->pwork_15sec(dev);
2969
2970 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2971 wmb();
2972
2973 #if B43_DEBUG
2974 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
2975 unsigned int i;
2976
2977 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
2978 dev->irq_count / 15,
2979 dev->tx_count / 15,
2980 dev->rx_count / 15);
2981 dev->irq_count = 0;
2982 dev->tx_count = 0;
2983 dev->rx_count = 0;
2984 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
2985 if (dev->irq_bit_count[i]) {
2986 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
2987 dev->irq_bit_count[i] / 15, i, (1 << i));
2988 dev->irq_bit_count[i] = 0;
2989 }
2990 }
2991 }
2992 #endif
2993 }
2994
2995 static void do_periodic_work(struct b43_wldev *dev)
2996 {
2997 unsigned int state;
2998
2999 state = dev->periodic_state;
3000 if (state % 4 == 0)
3001 b43_periodic_every60sec(dev);
3002 if (state % 2 == 0)
3003 b43_periodic_every30sec(dev);
3004 b43_periodic_every15sec(dev);
3005 }
3006
3007 /* Periodic work locking policy:
3008 * The whole periodic work handler is protected by
3009 * wl->mutex. If another lock is needed somewhere in the
3010 * pwork callchain, it's acquired in-place, where it's needed.
3011 */
3012 static void b43_periodic_work_handler(struct work_struct *work)
3013 {
3014 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3015 periodic_work.work);
3016 struct b43_wl *wl = dev->wl;
3017 unsigned long delay;
3018
3019 mutex_lock(&wl->mutex);
3020
3021 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3022 goto out;
3023 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3024 goto out_requeue;
3025
3026 do_periodic_work(dev);
3027
3028 dev->periodic_state++;
3029 out_requeue:
3030 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3031 delay = msecs_to_jiffies(50);
3032 else
3033 delay = round_jiffies_relative(HZ * 15);
3034 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3035 out:
3036 mutex_unlock(&wl->mutex);
3037 }
3038
3039 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3040 {
3041 struct delayed_work *work = &dev->periodic_work;
3042
3043 dev->periodic_state = 0;
3044 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3045 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3046 }
3047
3048 /* Check if communication with the device works correctly. */
3049 static int b43_validate_chipaccess(struct b43_wldev *dev)
3050 {
3051 u32 v, backup0, backup4;
3052
3053 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3054 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3055
3056 /* Check for read/write and endianness problems. */
3057 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3058 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3059 goto error;
3060 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3061 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3062 goto error;
3063
3064 /* Check if unaligned 32bit SHM_SHARED access works properly.
3065 * However, don't bail out on failure, because it's noncritical. */
3066 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3067 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3068 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3069 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3070 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3071 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3072 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3073 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3074 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3075 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3076 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3077 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3078
3079 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3080 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3081
3082 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
3083 /* The 32bit register shadows the two 16bit registers
3084 * with update sideeffects. Validate this. */
3085 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3086 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3087 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3088 goto error;
3089 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3090 goto error;
3091 }
3092 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3093
3094 v = b43_read32(dev, B43_MMIO_MACCTL);
3095 v |= B43_MACCTL_GMODE;
3096 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3097 goto error;
3098
3099 return 0;
3100 error:
3101 b43err(dev->wl, "Failed to validate the chipaccess\n");
3102 return -ENODEV;
3103 }
3104
3105 static void b43_security_init(struct b43_wldev *dev)
3106 {
3107 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3108 /* KTP is a word address, but we address SHM bytewise.
3109 * So multiply by two.
3110 */
3111 dev->ktp *= 2;
3112 /* Number of RCMTA address slots */
3113 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3114 /* Clear the key memory. */
3115 b43_clear_keys(dev);
3116 }
3117
3118 #ifdef CONFIG_B43_HWRNG
3119 static int b43_rng_read(struct hwrng *rng, u32 *data)
3120 {
3121 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3122 struct b43_wldev *dev;
3123 int count = -ENODEV;
3124
3125 mutex_lock(&wl->mutex);
3126 dev = wl->current_dev;
3127 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3128 *data = b43_read16(dev, B43_MMIO_RNG);
3129 count = sizeof(u16);
3130 }
3131 mutex_unlock(&wl->mutex);
3132
3133 return count;
3134 }
3135 #endif /* CONFIG_B43_HWRNG */
3136
3137 static void b43_rng_exit(struct b43_wl *wl)
3138 {
3139 #ifdef CONFIG_B43_HWRNG
3140 if (wl->rng_initialized)
3141 hwrng_unregister(&wl->rng);
3142 #endif /* CONFIG_B43_HWRNG */
3143 }
3144
3145 static int b43_rng_init(struct b43_wl *wl)
3146 {
3147 int err = 0;
3148
3149 #ifdef CONFIG_B43_HWRNG
3150 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3151 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3152 wl->rng.name = wl->rng_name;
3153 wl->rng.data_read = b43_rng_read;
3154 wl->rng.priv = (unsigned long)wl;
3155 wl->rng_initialized = 1;
3156 err = hwrng_register(&wl->rng);
3157 if (err) {
3158 wl->rng_initialized = 0;
3159 b43err(wl, "Failed to register the random "
3160 "number generator (%d)\n", err);
3161 }
3162 #endif /* CONFIG_B43_HWRNG */
3163
3164 return err;
3165 }
3166
3167 static void b43_tx_work(struct work_struct *work)
3168 {
3169 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3170 struct b43_wldev *dev;
3171 struct sk_buff *skb;
3172 int err = 0;
3173
3174 mutex_lock(&wl->mutex);
3175 dev = wl->current_dev;
3176 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3177 mutex_unlock(&wl->mutex);
3178 return;
3179 }
3180
3181 while (skb_queue_len(&wl->tx_queue)) {
3182 skb = skb_dequeue(&wl->tx_queue);
3183
3184 if (b43_using_pio_transfers(dev))
3185 err = b43_pio_tx(dev, skb);
3186 else
3187 err = b43_dma_tx(dev, skb);
3188 if (unlikely(err))
3189 dev_kfree_skb(skb); /* Drop it */
3190 }
3191
3192 #if B43_DEBUG
3193 dev->tx_count++;
3194 #endif
3195 mutex_unlock(&wl->mutex);
3196 }
3197
3198 static int b43_op_tx(struct ieee80211_hw *hw,
3199 struct sk_buff *skb)
3200 {
3201 struct b43_wl *wl = hw_to_b43_wl(hw);
3202
3203 if (unlikely(skb->len < 2 + 2 + 6)) {
3204 /* Too short, this can't be a valid frame. */
3205 dev_kfree_skb_any(skb);
3206 return NETDEV_TX_OK;
3207 }
3208 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3209
3210 skb_queue_tail(&wl->tx_queue, skb);
3211 ieee80211_queue_work(wl->hw, &wl->tx_work);
3212
3213 return NETDEV_TX_OK;
3214 }
3215
3216 static void b43_qos_params_upload(struct b43_wldev *dev,
3217 const struct ieee80211_tx_queue_params *p,
3218 u16 shm_offset)
3219 {
3220 u16 params[B43_NR_QOSPARAMS];
3221 int bslots, tmp;
3222 unsigned int i;
3223
3224 if (!dev->qos_enabled)
3225 return;
3226
3227 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3228
3229 memset(&params, 0, sizeof(params));
3230
3231 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3232 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3233 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3234 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3235 params[B43_QOSPARAM_AIFS] = p->aifs;
3236 params[B43_QOSPARAM_BSLOTS] = bslots;
3237 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3238
3239 for (i = 0; i < ARRAY_SIZE(params); i++) {
3240 if (i == B43_QOSPARAM_STATUS) {
3241 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3242 shm_offset + (i * 2));
3243 /* Mark the parameters as updated. */
3244 tmp |= 0x100;
3245 b43_shm_write16(dev, B43_SHM_SHARED,
3246 shm_offset + (i * 2),
3247 tmp);
3248 } else {
3249 b43_shm_write16(dev, B43_SHM_SHARED,
3250 shm_offset + (i * 2),
3251 params[i]);
3252 }
3253 }
3254 }
3255
3256 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3257 static const u16 b43_qos_shm_offsets[] = {
3258 /* [mac80211-queue-nr] = SHM_OFFSET, */
3259 [0] = B43_QOS_VOICE,
3260 [1] = B43_QOS_VIDEO,
3261 [2] = B43_QOS_BESTEFFORT,
3262 [3] = B43_QOS_BACKGROUND,
3263 };
3264
3265 /* Update all QOS parameters in hardware. */
3266 static void b43_qos_upload_all(struct b43_wldev *dev)
3267 {
3268 struct b43_wl *wl = dev->wl;
3269 struct b43_qos_params *params;
3270 unsigned int i;
3271
3272 if (!dev->qos_enabled)
3273 return;
3274
3275 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3276 ARRAY_SIZE(wl->qos_params));
3277
3278 b43_mac_suspend(dev);
3279 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3280 params = &(wl->qos_params[i]);
3281 b43_qos_params_upload(dev, &(params->p),
3282 b43_qos_shm_offsets[i]);
3283 }
3284 b43_mac_enable(dev);
3285 }
3286
3287 static void b43_qos_clear(struct b43_wl *wl)
3288 {
3289 struct b43_qos_params *params;
3290 unsigned int i;
3291
3292 /* Initialize QoS parameters to sane defaults. */
3293
3294 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3295 ARRAY_SIZE(wl->qos_params));
3296
3297 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3298 params = &(wl->qos_params[i]);
3299
3300 switch (b43_qos_shm_offsets[i]) {
3301 case B43_QOS_VOICE:
3302 params->p.txop = 0;
3303 params->p.aifs = 2;
3304 params->p.cw_min = 0x0001;
3305 params->p.cw_max = 0x0001;
3306 break;
3307 case B43_QOS_VIDEO:
3308 params->p.txop = 0;
3309 params->p.aifs = 2;
3310 params->p.cw_min = 0x0001;
3311 params->p.cw_max = 0x0001;
3312 break;
3313 case B43_QOS_BESTEFFORT:
3314 params->p.txop = 0;
3315 params->p.aifs = 3;
3316 params->p.cw_min = 0x0001;
3317 params->p.cw_max = 0x03FF;
3318 break;
3319 case B43_QOS_BACKGROUND:
3320 params->p.txop = 0;
3321 params->p.aifs = 7;
3322 params->p.cw_min = 0x0001;
3323 params->p.cw_max = 0x03FF;
3324 break;
3325 default:
3326 B43_WARN_ON(1);
3327 }
3328 }
3329 }
3330
3331 /* Initialize the core's QOS capabilities */
3332 static void b43_qos_init(struct b43_wldev *dev)
3333 {
3334 if (!dev->qos_enabled) {
3335 /* Disable QOS support. */
3336 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3337 b43_write16(dev, B43_MMIO_IFSCTL,
3338 b43_read16(dev, B43_MMIO_IFSCTL)
3339 & ~B43_MMIO_IFSCTL_USE_EDCF);
3340 b43dbg(dev->wl, "QoS disabled\n");
3341 return;
3342 }
3343
3344 /* Upload the current QOS parameters. */
3345 b43_qos_upload_all(dev);
3346
3347 /* Enable QOS support. */
3348 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3349 b43_write16(dev, B43_MMIO_IFSCTL,
3350 b43_read16(dev, B43_MMIO_IFSCTL)
3351 | B43_MMIO_IFSCTL_USE_EDCF);
3352 b43dbg(dev->wl, "QoS enabled\n");
3353 }
3354
3355 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3356 const struct ieee80211_tx_queue_params *params)
3357 {
3358 struct b43_wl *wl = hw_to_b43_wl(hw);
3359 struct b43_wldev *dev;
3360 unsigned int queue = (unsigned int)_queue;
3361 int err = -ENODEV;
3362
3363 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3364 /* Queue not available or don't support setting
3365 * params on this queue. Return success to not
3366 * confuse mac80211. */
3367 return 0;
3368 }
3369 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3370 ARRAY_SIZE(wl->qos_params));
3371
3372 mutex_lock(&wl->mutex);
3373 dev = wl->current_dev;
3374 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3375 goto out_unlock;
3376
3377 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3378 b43_mac_suspend(dev);
3379 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3380 b43_qos_shm_offsets[queue]);
3381 b43_mac_enable(dev);
3382 err = 0;
3383
3384 out_unlock:
3385 mutex_unlock(&wl->mutex);
3386
3387 return err;
3388 }
3389
3390 static int b43_op_get_stats(struct ieee80211_hw *hw,
3391 struct ieee80211_low_level_stats *stats)
3392 {
3393 struct b43_wl *wl = hw_to_b43_wl(hw);
3394
3395 mutex_lock(&wl->mutex);
3396 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3397 mutex_unlock(&wl->mutex);
3398
3399 return 0;
3400 }
3401
3402 static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3403 {
3404 struct b43_wl *wl = hw_to_b43_wl(hw);
3405 struct b43_wldev *dev;
3406 u64 tsf;
3407
3408 mutex_lock(&wl->mutex);
3409 dev = wl->current_dev;
3410
3411 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3412 b43_tsf_read(dev, &tsf);
3413 else
3414 tsf = 0;
3415
3416 mutex_unlock(&wl->mutex);
3417
3418 return tsf;
3419 }
3420
3421 static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3422 {
3423 struct b43_wl *wl = hw_to_b43_wl(hw);
3424 struct b43_wldev *dev;
3425
3426 mutex_lock(&wl->mutex);
3427 dev = wl->current_dev;
3428
3429 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3430 b43_tsf_write(dev, tsf);
3431
3432 mutex_unlock(&wl->mutex);
3433 }
3434
3435 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3436 {
3437 struct ssb_device *sdev = dev->dev;
3438 u32 tmslow;
3439
3440 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3441 tmslow &= ~B43_TMSLOW_GMODE;
3442 tmslow |= B43_TMSLOW_PHYRESET;
3443 tmslow |= SSB_TMSLOW_FGC;
3444 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3445 msleep(1);
3446
3447 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3448 tmslow &= ~SSB_TMSLOW_FGC;
3449 tmslow |= B43_TMSLOW_PHYRESET;
3450 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3451 msleep(1);
3452 }
3453
3454 static const char *band_to_string(enum ieee80211_band band)
3455 {
3456 switch (band) {
3457 case IEEE80211_BAND_5GHZ:
3458 return "5";
3459 case IEEE80211_BAND_2GHZ:
3460 return "2.4";
3461 default:
3462 break;
3463 }
3464 B43_WARN_ON(1);
3465 return "";
3466 }
3467
3468 /* Expects wl->mutex locked */
3469 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3470 {
3471 struct b43_wldev *up_dev = NULL;
3472 struct b43_wldev *down_dev;
3473 struct b43_wldev *d;
3474 int err;
3475 bool uninitialized_var(gmode);
3476 int prev_status;
3477
3478 /* Find a device and PHY which supports the band. */
3479 list_for_each_entry(d, &wl->devlist, list) {
3480 switch (chan->band) {
3481 case IEEE80211_BAND_5GHZ:
3482 if (d->phy.supports_5ghz) {
3483 up_dev = d;
3484 gmode = 0;
3485 }
3486 break;
3487 case IEEE80211_BAND_2GHZ:
3488 if (d->phy.supports_2ghz) {
3489 up_dev = d;
3490 gmode = 1;
3491 }
3492 break;
3493 default:
3494 B43_WARN_ON(1);
3495 return -EINVAL;
3496 }
3497 if (up_dev)
3498 break;
3499 }
3500 if (!up_dev) {
3501 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3502 band_to_string(chan->band));
3503 return -ENODEV;
3504 }
3505 if ((up_dev == wl->current_dev) &&
3506 (!!wl->current_dev->phy.gmode == !!gmode)) {
3507 /* This device is already running. */
3508 return 0;
3509 }
3510 b43dbg(wl, "Switching to %s-GHz band\n",
3511 band_to_string(chan->band));
3512 down_dev = wl->current_dev;
3513
3514 prev_status = b43_status(down_dev);
3515 /* Shutdown the currently running core. */
3516 if (prev_status >= B43_STAT_STARTED)
3517 down_dev = b43_wireless_core_stop(down_dev);
3518 if (prev_status >= B43_STAT_INITIALIZED)
3519 b43_wireless_core_exit(down_dev);
3520
3521 if (down_dev != up_dev) {
3522 /* We switch to a different core, so we put PHY into
3523 * RESET on the old core. */
3524 b43_put_phy_into_reset(down_dev);
3525 }
3526
3527 /* Now start the new core. */
3528 up_dev->phy.gmode = gmode;
3529 if (prev_status >= B43_STAT_INITIALIZED) {
3530 err = b43_wireless_core_init(up_dev);
3531 if (err) {
3532 b43err(wl, "Fatal: Could not initialize device for "
3533 "selected %s-GHz band\n",
3534 band_to_string(chan->band));
3535 goto init_failure;
3536 }
3537 }
3538 if (prev_status >= B43_STAT_STARTED) {
3539 err = b43_wireless_core_start(up_dev);
3540 if (err) {
3541 b43err(wl, "Fatal: Coult not start device for "
3542 "selected %s-GHz band\n",
3543 band_to_string(chan->band));
3544 b43_wireless_core_exit(up_dev);
3545 goto init_failure;
3546 }
3547 }
3548 B43_WARN_ON(b43_status(up_dev) != prev_status);
3549
3550 wl->current_dev = up_dev;
3551
3552 return 0;
3553 init_failure:
3554 /* Whoops, failed to init the new core. No core is operating now. */
3555 wl->current_dev = NULL;
3556 return err;
3557 }
3558
3559 /* Write the short and long frame retry limit values. */
3560 static void b43_set_retry_limits(struct b43_wldev *dev,
3561 unsigned int short_retry,
3562 unsigned int long_retry)
3563 {
3564 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3565 * the chip-internal counter. */
3566 short_retry = min(short_retry, (unsigned int)0xF);
3567 long_retry = min(long_retry, (unsigned int)0xF);
3568
3569 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3570 short_retry);
3571 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3572 long_retry);
3573 }
3574
3575 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3576 {
3577 struct b43_wl *wl = hw_to_b43_wl(hw);
3578 struct b43_wldev *dev;
3579 struct b43_phy *phy;
3580 struct ieee80211_conf *conf = &hw->conf;
3581 int antenna;
3582 int err = 0;
3583
3584 mutex_lock(&wl->mutex);
3585
3586 /* Switch the band (if necessary). This might change the active core. */
3587 err = b43_switch_band(wl, conf->channel);
3588 if (err)
3589 goto out_unlock_mutex;
3590 dev = wl->current_dev;
3591 phy = &dev->phy;
3592
3593 if (conf_is_ht(conf))
3594 phy->is_40mhz =
3595 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3596 else
3597 phy->is_40mhz = false;
3598
3599 b43_mac_suspend(dev);
3600
3601 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3602 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3603 conf->long_frame_max_tx_count);
3604 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3605 if (!changed)
3606 goto out_mac_enable;
3607
3608 /* Switch to the requested channel.
3609 * The firmware takes care of races with the TX handler. */
3610 if (conf->channel->hw_value != phy->channel)
3611 b43_switch_channel(dev, conf->channel->hw_value);
3612
3613 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3614
3615 /* Adjust the desired TX power level. */
3616 if (conf->power_level != 0) {
3617 if (conf->power_level != phy->desired_txpower) {
3618 phy->desired_txpower = conf->power_level;
3619 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3620 B43_TXPWR_IGNORE_TSSI);
3621 }
3622 }
3623
3624 /* Antennas for RX and management frame TX. */
3625 antenna = B43_ANTENNA_DEFAULT;
3626 b43_mgmtframe_txantenna(dev, antenna);
3627 antenna = B43_ANTENNA_DEFAULT;
3628 if (phy->ops->set_rx_antenna)
3629 phy->ops->set_rx_antenna(dev, antenna);
3630
3631 if (wl->radio_enabled != phy->radio_on) {
3632 if (wl->radio_enabled) {
3633 b43_software_rfkill(dev, false);
3634 b43info(dev->wl, "Radio turned on by software\n");
3635 if (!dev->radio_hw_enable) {
3636 b43info(dev->wl, "The hardware RF-kill button "
3637 "still turns the radio physically off. "
3638 "Press the button to turn it on.\n");
3639 }
3640 } else {
3641 b43_software_rfkill(dev, true);
3642 b43info(dev->wl, "Radio turned off by software\n");
3643 }
3644 }
3645
3646 out_mac_enable:
3647 b43_mac_enable(dev);
3648 out_unlock_mutex:
3649 mutex_unlock(&wl->mutex);
3650
3651 return err;
3652 }
3653
3654 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3655 {
3656 struct ieee80211_supported_band *sband =
3657 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3658 struct ieee80211_rate *rate;
3659 int i;
3660 u16 basic, direct, offset, basic_offset, rateptr;
3661
3662 for (i = 0; i < sband->n_bitrates; i++) {
3663 rate = &sband->bitrates[i];
3664
3665 if (b43_is_cck_rate(rate->hw_value)) {
3666 direct = B43_SHM_SH_CCKDIRECT;
3667 basic = B43_SHM_SH_CCKBASIC;
3668 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3669 offset &= 0xF;
3670 } else {
3671 direct = B43_SHM_SH_OFDMDIRECT;
3672 basic = B43_SHM_SH_OFDMBASIC;
3673 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3674 offset &= 0xF;
3675 }
3676
3677 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3678
3679 if (b43_is_cck_rate(rate->hw_value)) {
3680 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3681 basic_offset &= 0xF;
3682 } else {
3683 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3684 basic_offset &= 0xF;
3685 }
3686
3687 /*
3688 * Get the pointer that we need to point to
3689 * from the direct map
3690 */
3691 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3692 direct + 2 * basic_offset);
3693 /* and write it to the basic map */
3694 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3695 rateptr);
3696 }
3697 }
3698
3699 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3700 struct ieee80211_vif *vif,
3701 struct ieee80211_bss_conf *conf,
3702 u32 changed)
3703 {
3704 struct b43_wl *wl = hw_to_b43_wl(hw);
3705 struct b43_wldev *dev;
3706
3707 mutex_lock(&wl->mutex);
3708
3709 dev = wl->current_dev;
3710 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3711 goto out_unlock_mutex;
3712
3713 B43_WARN_ON(wl->vif != vif);
3714
3715 if (changed & BSS_CHANGED_BSSID) {
3716 if (conf->bssid)
3717 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3718 else
3719 memset(wl->bssid, 0, ETH_ALEN);
3720 }
3721
3722 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3723 if (changed & BSS_CHANGED_BEACON &&
3724 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3725 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3726 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3727 b43_update_templates(wl);
3728
3729 if (changed & BSS_CHANGED_BSSID)
3730 b43_write_mac_bssid_templates(dev);
3731 }
3732
3733 b43_mac_suspend(dev);
3734
3735 /* Update templates for AP/mesh mode. */
3736 if (changed & BSS_CHANGED_BEACON_INT &&
3737 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3738 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3739 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3740 b43_set_beacon_int(dev, conf->beacon_int);
3741
3742 if (changed & BSS_CHANGED_BASIC_RATES)
3743 b43_update_basic_rates(dev, conf->basic_rates);
3744
3745 if (changed & BSS_CHANGED_ERP_SLOT) {
3746 if (conf->use_short_slot)
3747 b43_short_slot_timing_enable(dev);
3748 else
3749 b43_short_slot_timing_disable(dev);
3750 }
3751
3752 b43_mac_enable(dev);
3753 out_unlock_mutex:
3754 mutex_unlock(&wl->mutex);
3755 }
3756
3757 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3758 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3759 struct ieee80211_key_conf *key)
3760 {
3761 struct b43_wl *wl = hw_to_b43_wl(hw);
3762 struct b43_wldev *dev;
3763 u8 algorithm;
3764 u8 index;
3765 int err;
3766 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3767
3768 if (modparam_nohwcrypt)
3769 return -ENOSPC; /* User disabled HW-crypto */
3770
3771 mutex_lock(&wl->mutex);
3772
3773 dev = wl->current_dev;
3774 err = -ENODEV;
3775 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3776 goto out_unlock;
3777
3778 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
3779 /* We don't have firmware for the crypto engine.
3780 * Must use software-crypto. */
3781 err = -EOPNOTSUPP;
3782 goto out_unlock;
3783 }
3784
3785 err = -EINVAL;
3786 switch (key->cipher) {
3787 case WLAN_CIPHER_SUITE_WEP40:
3788 algorithm = B43_SEC_ALGO_WEP40;
3789 break;
3790 case WLAN_CIPHER_SUITE_WEP104:
3791 algorithm = B43_SEC_ALGO_WEP104;
3792 break;
3793 case WLAN_CIPHER_SUITE_TKIP:
3794 algorithm = B43_SEC_ALGO_TKIP;
3795 break;
3796 case WLAN_CIPHER_SUITE_CCMP:
3797 algorithm = B43_SEC_ALGO_AES;
3798 break;
3799 default:
3800 B43_WARN_ON(1);
3801 goto out_unlock;
3802 }
3803 index = (u8) (key->keyidx);
3804 if (index > 3)
3805 goto out_unlock;
3806
3807 switch (cmd) {
3808 case SET_KEY:
3809 if (algorithm == B43_SEC_ALGO_TKIP &&
3810 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
3811 !modparam_hwtkip)) {
3812 /* We support only pairwise key */
3813 err = -EOPNOTSUPP;
3814 goto out_unlock;
3815 }
3816
3817 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
3818 if (WARN_ON(!sta)) {
3819 err = -EOPNOTSUPP;
3820 goto out_unlock;
3821 }
3822 /* Pairwise key with an assigned MAC address. */
3823 err = b43_key_write(dev, -1, algorithm,
3824 key->key, key->keylen,
3825 sta->addr, key);
3826 } else {
3827 /* Group key */
3828 err = b43_key_write(dev, index, algorithm,
3829 key->key, key->keylen, NULL, key);
3830 }
3831 if (err)
3832 goto out_unlock;
3833
3834 if (algorithm == B43_SEC_ALGO_WEP40 ||
3835 algorithm == B43_SEC_ALGO_WEP104) {
3836 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3837 } else {
3838 b43_hf_write(dev,
3839 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3840 }
3841 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3842 if (algorithm == B43_SEC_ALGO_TKIP)
3843 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3844 break;
3845 case DISABLE_KEY: {
3846 err = b43_key_clear(dev, key->hw_key_idx);
3847 if (err)
3848 goto out_unlock;
3849 break;
3850 }
3851 default:
3852 B43_WARN_ON(1);
3853 }
3854
3855 out_unlock:
3856 if (!err) {
3857 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3858 "mac: %pM\n",
3859 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3860 sta ? sta->addr : bcast_addr);
3861 b43_dump_keymemory(dev);
3862 }
3863 mutex_unlock(&wl->mutex);
3864
3865 return err;
3866 }
3867
3868 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3869 unsigned int changed, unsigned int *fflags,
3870 u64 multicast)
3871 {
3872 struct b43_wl *wl = hw_to_b43_wl(hw);
3873 struct b43_wldev *dev;
3874
3875 mutex_lock(&wl->mutex);
3876 dev = wl->current_dev;
3877 if (!dev) {
3878 *fflags = 0;
3879 goto out_unlock;
3880 }
3881
3882 *fflags &= FIF_PROMISC_IN_BSS |
3883 FIF_ALLMULTI |
3884 FIF_FCSFAIL |
3885 FIF_PLCPFAIL |
3886 FIF_CONTROL |
3887 FIF_OTHER_BSS |
3888 FIF_BCN_PRBRESP_PROMISC;
3889
3890 changed &= FIF_PROMISC_IN_BSS |
3891 FIF_ALLMULTI |
3892 FIF_FCSFAIL |
3893 FIF_PLCPFAIL |
3894 FIF_CONTROL |
3895 FIF_OTHER_BSS |
3896 FIF_BCN_PRBRESP_PROMISC;
3897
3898 wl->filter_flags = *fflags;
3899
3900 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3901 b43_adjust_opmode(dev);
3902
3903 out_unlock:
3904 mutex_unlock(&wl->mutex);
3905 }
3906
3907 /* Locking: wl->mutex
3908 * Returns the current dev. This might be different from the passed in dev,
3909 * because the core might be gone away while we unlocked the mutex. */
3910 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
3911 {
3912 struct b43_wl *wl = dev->wl;
3913 struct b43_wldev *orig_dev;
3914 u32 mask;
3915
3916 redo:
3917 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3918 return dev;
3919
3920 /* Cancel work. Unlock to avoid deadlocks. */
3921 mutex_unlock(&wl->mutex);
3922 cancel_delayed_work_sync(&dev->periodic_work);
3923 cancel_work_sync(&wl->tx_work);
3924 mutex_lock(&wl->mutex);
3925 dev = wl->current_dev;
3926 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
3927 /* Whoops, aliens ate up the device while we were unlocked. */
3928 return dev;
3929 }
3930
3931 /* Disable interrupts on the device. */
3932 b43_set_status(dev, B43_STAT_INITIALIZED);
3933 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3934 /* wl->mutex is locked. That is enough. */
3935 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3936 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3937 } else {
3938 spin_lock_irq(&wl->hardirq_lock);
3939 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3940 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3941 spin_unlock_irq(&wl->hardirq_lock);
3942 }
3943 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
3944 orig_dev = dev;
3945 mutex_unlock(&wl->mutex);
3946 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3947 b43_sdio_free_irq(dev);
3948 } else {
3949 synchronize_irq(dev->dev->irq);
3950 free_irq(dev->dev->irq, dev);
3951 }
3952 mutex_lock(&wl->mutex);
3953 dev = wl->current_dev;
3954 if (!dev)
3955 return dev;
3956 if (dev != orig_dev) {
3957 if (b43_status(dev) >= B43_STAT_STARTED)
3958 goto redo;
3959 return dev;
3960 }
3961 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
3962 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
3963
3964 /* Drain the TX queue */
3965 while (skb_queue_len(&wl->tx_queue))
3966 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
3967
3968 b43_mac_suspend(dev);
3969 b43_leds_exit(dev);
3970 b43dbg(wl, "Wireless interface stopped\n");
3971
3972 return dev;
3973 }
3974
3975 /* Locking: wl->mutex */
3976 static int b43_wireless_core_start(struct b43_wldev *dev)
3977 {
3978 int err;
3979
3980 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3981
3982 drain_txstatus_queue(dev);
3983 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3984 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
3985 if (err) {
3986 b43err(dev->wl, "Cannot request SDIO IRQ\n");
3987 goto out;
3988 }
3989 } else {
3990 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3991 b43_interrupt_thread_handler,
3992 IRQF_SHARED, KBUILD_MODNAME, dev);
3993 if (err) {
3994 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3995 goto out;
3996 }
3997 }
3998
3999 /* We are ready to run. */
4000 ieee80211_wake_queues(dev->wl->hw);
4001 b43_set_status(dev, B43_STAT_STARTED);
4002
4003 /* Start data flow (TX/RX). */
4004 b43_mac_enable(dev);
4005 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4006
4007 /* Start maintainance work */
4008 b43_periodic_tasks_setup(dev);
4009
4010 b43_leds_init(dev);
4011
4012 b43dbg(dev->wl, "Wireless interface started\n");
4013 out:
4014 return err;
4015 }
4016
4017 /* Get PHY and RADIO versioning numbers */
4018 static int b43_phy_versioning(struct b43_wldev *dev)
4019 {
4020 struct b43_phy *phy = &dev->phy;
4021 u32 tmp;
4022 u8 analog_type;
4023 u8 phy_type;
4024 u8 phy_rev;
4025 u16 radio_manuf;
4026 u16 radio_ver;
4027 u16 radio_rev;
4028 int unsupported = 0;
4029
4030 /* Get PHY versioning */
4031 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4032 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4033 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4034 phy_rev = (tmp & B43_PHYVER_VERSION);
4035 switch (phy_type) {
4036 case B43_PHYTYPE_A:
4037 if (phy_rev >= 4)
4038 unsupported = 1;
4039 break;
4040 case B43_PHYTYPE_B:
4041 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4042 && phy_rev != 7)
4043 unsupported = 1;
4044 break;
4045 case B43_PHYTYPE_G:
4046 if (phy_rev > 9)
4047 unsupported = 1;
4048 break;
4049 #ifdef CONFIG_B43_NPHY
4050 case B43_PHYTYPE_N:
4051 if (phy_rev > 4)
4052 unsupported = 1;
4053 break;
4054 #endif
4055 #ifdef CONFIG_B43_PHY_LP
4056 case B43_PHYTYPE_LP:
4057 if (phy_rev > 2)
4058 unsupported = 1;
4059 break;
4060 #endif
4061 default:
4062 unsupported = 1;
4063 };
4064 if (unsupported) {
4065 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4066 "(Analog %u, Type %u, Revision %u)\n",
4067 analog_type, phy_type, phy_rev);
4068 return -EOPNOTSUPP;
4069 }
4070 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4071 analog_type, phy_type, phy_rev);
4072
4073 /* Get RADIO versioning */
4074 if (dev->dev->bus->chip_id == 0x4317) {
4075 if (dev->dev->bus->chip_rev == 0)
4076 tmp = 0x3205017F;
4077 else if (dev->dev->bus->chip_rev == 1)
4078 tmp = 0x4205017F;
4079 else
4080 tmp = 0x5205017F;
4081 } else {
4082 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
4083 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4084 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
4085 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
4086 }
4087 radio_manuf = (tmp & 0x00000FFF);
4088 radio_ver = (tmp & 0x0FFFF000) >> 12;
4089 radio_rev = (tmp & 0xF0000000) >> 28;
4090 if (radio_manuf != 0x17F /* Broadcom */)
4091 unsupported = 1;
4092 switch (phy_type) {
4093 case B43_PHYTYPE_A:
4094 if (radio_ver != 0x2060)
4095 unsupported = 1;
4096 if (radio_rev != 1)
4097 unsupported = 1;
4098 if (radio_manuf != 0x17F)
4099 unsupported = 1;
4100 break;
4101 case B43_PHYTYPE_B:
4102 if ((radio_ver & 0xFFF0) != 0x2050)
4103 unsupported = 1;
4104 break;
4105 case B43_PHYTYPE_G:
4106 if (radio_ver != 0x2050)
4107 unsupported = 1;
4108 break;
4109 case B43_PHYTYPE_N:
4110 if (radio_ver != 0x2055 && radio_ver != 0x2056)
4111 unsupported = 1;
4112 break;
4113 case B43_PHYTYPE_LP:
4114 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4115 unsupported = 1;
4116 break;
4117 default:
4118 B43_WARN_ON(1);
4119 }
4120 if (unsupported) {
4121 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4122 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4123 radio_manuf, radio_ver, radio_rev);
4124 return -EOPNOTSUPP;
4125 }
4126 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4127 radio_manuf, radio_ver, radio_rev);
4128
4129 phy->radio_manuf = radio_manuf;
4130 phy->radio_ver = radio_ver;
4131 phy->radio_rev = radio_rev;
4132
4133 phy->analog = analog_type;
4134 phy->type = phy_type;
4135 phy->rev = phy_rev;
4136
4137 return 0;
4138 }
4139
4140 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4141 struct b43_phy *phy)
4142 {
4143 phy->hardware_power_control = !!modparam_hwpctl;
4144 phy->next_txpwr_check_time = jiffies;
4145 /* PHY TX errors counter. */
4146 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4147
4148 #if B43_DEBUG
4149 phy->phy_locked = 0;
4150 phy->radio_locked = 0;
4151 #endif
4152 }
4153
4154 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4155 {
4156 dev->dfq_valid = 0;
4157
4158 /* Assume the radio is enabled. If it's not enabled, the state will
4159 * immediately get fixed on the first periodic work run. */
4160 dev->radio_hw_enable = 1;
4161
4162 /* Stats */
4163 memset(&dev->stats, 0, sizeof(dev->stats));
4164
4165 setup_struct_phy_for_init(dev, &dev->phy);
4166
4167 /* IRQ related flags */
4168 dev->irq_reason = 0;
4169 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4170 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4171 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4172 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4173
4174 dev->mac_suspended = 1;
4175
4176 /* Noise calculation context */
4177 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4178 }
4179
4180 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4181 {
4182 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
4183 u64 hf;
4184
4185 if (!modparam_btcoex)
4186 return;
4187 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4188 return;
4189 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4190 return;
4191
4192 hf = b43_hf_read(dev);
4193 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4194 hf |= B43_HF_BTCOEXALT;
4195 else
4196 hf |= B43_HF_BTCOEX;
4197 b43_hf_write(dev, hf);
4198 }
4199
4200 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4201 {
4202 if (!modparam_btcoex)
4203 return;
4204 //TODO
4205 }
4206
4207 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4208 {
4209 #ifdef CONFIG_SSB_DRIVER_PCICORE
4210 struct ssb_bus *bus = dev->dev->bus;
4211 u32 tmp;
4212
4213 if (bus->pcicore.dev &&
4214 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
4215 bus->pcicore.dev->id.revision <= 5) {
4216 /* IMCFGLO timeouts workaround. */
4217 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
4218 switch (bus->bustype) {
4219 case SSB_BUSTYPE_PCI:
4220 case SSB_BUSTYPE_PCMCIA:
4221 tmp &= ~SSB_IMCFGLO_REQTO;
4222 tmp &= ~SSB_IMCFGLO_SERTO;
4223 tmp |= 0x32;
4224 break;
4225 case SSB_BUSTYPE_SSB:
4226 tmp &= ~SSB_IMCFGLO_REQTO;
4227 tmp &= ~SSB_IMCFGLO_SERTO;
4228 tmp |= 0x53;
4229 break;
4230 default:
4231 break;
4232 }
4233 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
4234 }
4235 #endif /* CONFIG_SSB_DRIVER_PCICORE */
4236 }
4237
4238 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4239 {
4240 u16 pu_delay;
4241
4242 /* The time value is in microseconds. */
4243 if (dev->phy.type == B43_PHYTYPE_A)
4244 pu_delay = 3700;
4245 else
4246 pu_delay = 1050;
4247 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4248 pu_delay = 500;
4249 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4250 pu_delay = max(pu_delay, (u16)2400);
4251
4252 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4253 }
4254
4255 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4256 static void b43_set_pretbtt(struct b43_wldev *dev)
4257 {
4258 u16 pretbtt;
4259
4260 /* The time value is in microseconds. */
4261 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4262 pretbtt = 2;
4263 } else {
4264 if (dev->phy.type == B43_PHYTYPE_A)
4265 pretbtt = 120;
4266 else
4267 pretbtt = 250;
4268 }
4269 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4270 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4271 }
4272
4273 /* Shutdown a wireless core */
4274 /* Locking: wl->mutex */
4275 static void b43_wireless_core_exit(struct b43_wldev *dev)
4276 {
4277 u32 macctl;
4278
4279 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4280 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4281 return;
4282
4283 /* Unregister HW RNG driver */
4284 b43_rng_exit(dev->wl);
4285
4286 b43_set_status(dev, B43_STAT_UNINIT);
4287
4288 /* Stop the microcode PSM. */
4289 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4290 macctl &= ~B43_MACCTL_PSM_RUN;
4291 macctl |= B43_MACCTL_PSM_JMP0;
4292 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4293
4294 b43_dma_free(dev);
4295 b43_pio_free(dev);
4296 b43_chip_exit(dev);
4297 dev->phy.ops->switch_analog(dev, 0);
4298 if (dev->wl->current_beacon) {
4299 dev_kfree_skb_any(dev->wl->current_beacon);
4300 dev->wl->current_beacon = NULL;
4301 }
4302
4303 ssb_device_disable(dev->dev, 0);
4304 ssb_bus_may_powerdown(dev->dev->bus);
4305 }
4306
4307 /* Initialize a wireless core */
4308 static int b43_wireless_core_init(struct b43_wldev *dev)
4309 {
4310 struct ssb_bus *bus = dev->dev->bus;
4311 struct ssb_sprom *sprom = &bus->sprom;
4312 struct b43_phy *phy = &dev->phy;
4313 int err;
4314 u64 hf;
4315 u32 tmp;
4316
4317 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4318
4319 err = ssb_bus_powerup(bus, 0);
4320 if (err)
4321 goto out;
4322 if (!ssb_device_is_enabled(dev->dev)) {
4323 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4324 b43_wireless_core_reset(dev, tmp);
4325 }
4326
4327 /* Reset all data structures. */
4328 setup_struct_wldev_for_init(dev);
4329 phy->ops->prepare_structs(dev);
4330
4331 /* Enable IRQ routing to this device. */
4332 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4333
4334 b43_imcfglo_timeouts_workaround(dev);
4335 b43_bluetooth_coext_disable(dev);
4336 if (phy->ops->prepare_hardware) {
4337 err = phy->ops->prepare_hardware(dev);
4338 if (err)
4339 goto err_busdown;
4340 }
4341 err = b43_chip_init(dev);
4342 if (err)
4343 goto err_busdown;
4344 b43_shm_write16(dev, B43_SHM_SHARED,
4345 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4346 hf = b43_hf_read(dev);
4347 if (phy->type == B43_PHYTYPE_G) {
4348 hf |= B43_HF_SYMW;
4349 if (phy->rev == 1)
4350 hf |= B43_HF_GDCW;
4351 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4352 hf |= B43_HF_OFDMPABOOST;
4353 }
4354 if (phy->radio_ver == 0x2050) {
4355 if (phy->radio_rev == 6)
4356 hf |= B43_HF_4318TSSI;
4357 if (phy->radio_rev < 6)
4358 hf |= B43_HF_VCORECALC;
4359 }
4360 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4361 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4362 #ifdef CONFIG_SSB_DRIVER_PCICORE
4363 if ((bus->bustype == SSB_BUSTYPE_PCI) &&
4364 (bus->pcicore.dev->id.revision <= 10))
4365 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4366 #endif
4367 hf &= ~B43_HF_SKCFPUP;
4368 b43_hf_write(dev, hf);
4369
4370 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4371 B43_DEFAULT_LONG_RETRY_LIMIT);
4372 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4373 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4374
4375 /* Disable sending probe responses from firmware.
4376 * Setting the MaxTime to one usec will always trigger
4377 * a timeout, so we never send any probe resp.
4378 * A timeout of zero is infinite. */
4379 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4380
4381 b43_rate_memory_init(dev);
4382 b43_set_phytxctl_defaults(dev);
4383
4384 /* Minimum Contention Window */
4385 if (phy->type == B43_PHYTYPE_B)
4386 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4387 else
4388 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4389 /* Maximum Contention Window */
4390 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4391
4392 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) ||
4393 (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) ||
4394 dev->use_pio) {
4395 dev->__using_pio_transfers = 1;
4396 err = b43_pio_init(dev);
4397 } else {
4398 dev->__using_pio_transfers = 0;
4399 err = b43_dma_init(dev);
4400 }
4401 if (err)
4402 goto err_chip_exit;
4403 b43_qos_init(dev);
4404 b43_set_synth_pu_delay(dev, 1);
4405 b43_bluetooth_coext_enable(dev);
4406
4407 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4408 b43_upload_card_macaddress(dev);
4409 b43_security_init(dev);
4410
4411 ieee80211_wake_queues(dev->wl->hw);
4412
4413 b43_set_status(dev, B43_STAT_INITIALIZED);
4414
4415 /* Register HW RNG driver */
4416 b43_rng_init(dev->wl);
4417
4418 out:
4419 return err;
4420
4421 err_chip_exit:
4422 b43_chip_exit(dev);
4423 err_busdown:
4424 ssb_bus_may_powerdown(bus);
4425 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4426 return err;
4427 }
4428
4429 static int b43_op_add_interface(struct ieee80211_hw *hw,
4430 struct ieee80211_vif *vif)
4431 {
4432 struct b43_wl *wl = hw_to_b43_wl(hw);
4433 struct b43_wldev *dev;
4434 int err = -EOPNOTSUPP;
4435
4436 /* TODO: allow WDS/AP devices to coexist */
4437
4438 if (vif->type != NL80211_IFTYPE_AP &&
4439 vif->type != NL80211_IFTYPE_MESH_POINT &&
4440 vif->type != NL80211_IFTYPE_STATION &&
4441 vif->type != NL80211_IFTYPE_WDS &&
4442 vif->type != NL80211_IFTYPE_ADHOC)
4443 return -EOPNOTSUPP;
4444
4445 mutex_lock(&wl->mutex);
4446 if (wl->operating)
4447 goto out_mutex_unlock;
4448
4449 b43dbg(wl, "Adding Interface type %d\n", vif->type);
4450
4451 dev = wl->current_dev;
4452 wl->operating = 1;
4453 wl->vif = vif;
4454 wl->if_type = vif->type;
4455 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4456
4457 b43_adjust_opmode(dev);
4458 b43_set_pretbtt(dev);
4459 b43_set_synth_pu_delay(dev, 0);
4460 b43_upload_card_macaddress(dev);
4461
4462 err = 0;
4463 out_mutex_unlock:
4464 mutex_unlock(&wl->mutex);
4465
4466 return err;
4467 }
4468
4469 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4470 struct ieee80211_vif *vif)
4471 {
4472 struct b43_wl *wl = hw_to_b43_wl(hw);
4473 struct b43_wldev *dev = wl->current_dev;
4474
4475 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4476
4477 mutex_lock(&wl->mutex);
4478
4479 B43_WARN_ON(!wl->operating);
4480 B43_WARN_ON(wl->vif != vif);
4481 wl->vif = NULL;
4482
4483 wl->operating = 0;
4484
4485 b43_adjust_opmode(dev);
4486 memset(wl->mac_addr, 0, ETH_ALEN);
4487 b43_upload_card_macaddress(dev);
4488
4489 mutex_unlock(&wl->mutex);
4490 }
4491
4492 static int b43_op_start(struct ieee80211_hw *hw)
4493 {
4494 struct b43_wl *wl = hw_to_b43_wl(hw);
4495 struct b43_wldev *dev = wl->current_dev;
4496 int did_init = 0;
4497 int err = 0;
4498
4499 /* Kill all old instance specific information to make sure
4500 * the card won't use it in the short timeframe between start
4501 * and mac80211 reconfiguring it. */
4502 memset(wl->bssid, 0, ETH_ALEN);
4503 memset(wl->mac_addr, 0, ETH_ALEN);
4504 wl->filter_flags = 0;
4505 wl->radiotap_enabled = 0;
4506 b43_qos_clear(wl);
4507 wl->beacon0_uploaded = 0;
4508 wl->beacon1_uploaded = 0;
4509 wl->beacon_templates_virgin = 1;
4510 wl->radio_enabled = 1;
4511
4512 mutex_lock(&wl->mutex);
4513
4514 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4515 err = b43_wireless_core_init(dev);
4516 if (err)
4517 goto out_mutex_unlock;
4518 did_init = 1;
4519 }
4520
4521 if (b43_status(dev) < B43_STAT_STARTED) {
4522 err = b43_wireless_core_start(dev);
4523 if (err) {
4524 if (did_init)
4525 b43_wireless_core_exit(dev);
4526 goto out_mutex_unlock;
4527 }
4528 }
4529
4530 /* XXX: only do if device doesn't support rfkill irq */
4531 wiphy_rfkill_start_polling(hw->wiphy);
4532
4533 out_mutex_unlock:
4534 mutex_unlock(&wl->mutex);
4535
4536 return err;
4537 }
4538
4539 static void b43_op_stop(struct ieee80211_hw *hw)
4540 {
4541 struct b43_wl *wl = hw_to_b43_wl(hw);
4542 struct b43_wldev *dev = wl->current_dev;
4543
4544 cancel_work_sync(&(wl->beacon_update_trigger));
4545
4546 mutex_lock(&wl->mutex);
4547 if (b43_status(dev) >= B43_STAT_STARTED) {
4548 dev = b43_wireless_core_stop(dev);
4549 if (!dev)
4550 goto out_unlock;
4551 }
4552 b43_wireless_core_exit(dev);
4553 wl->radio_enabled = 0;
4554
4555 out_unlock:
4556 mutex_unlock(&wl->mutex);
4557
4558 cancel_work_sync(&(wl->txpower_adjust_work));
4559 }
4560
4561 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4562 struct ieee80211_sta *sta, bool set)
4563 {
4564 struct b43_wl *wl = hw_to_b43_wl(hw);
4565
4566 /* FIXME: add locking */
4567 b43_update_templates(wl);
4568
4569 return 0;
4570 }
4571
4572 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4573 struct ieee80211_vif *vif,
4574 enum sta_notify_cmd notify_cmd,
4575 struct ieee80211_sta *sta)
4576 {
4577 struct b43_wl *wl = hw_to_b43_wl(hw);
4578
4579 B43_WARN_ON(!vif || wl->vif != vif);
4580 }
4581
4582 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4583 {
4584 struct b43_wl *wl = hw_to_b43_wl(hw);
4585 struct b43_wldev *dev;
4586
4587 mutex_lock(&wl->mutex);
4588 dev = wl->current_dev;
4589 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4590 /* Disable CFP update during scan on other channels. */
4591 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4592 }
4593 mutex_unlock(&wl->mutex);
4594 }
4595
4596 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4597 {
4598 struct b43_wl *wl = hw_to_b43_wl(hw);
4599 struct b43_wldev *dev;
4600
4601 mutex_lock(&wl->mutex);
4602 dev = wl->current_dev;
4603 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4604 /* Re-enable CFP update. */
4605 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4606 }
4607 mutex_unlock(&wl->mutex);
4608 }
4609
4610 static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4611 struct survey_info *survey)
4612 {
4613 struct b43_wl *wl = hw_to_b43_wl(hw);
4614 struct b43_wldev *dev = wl->current_dev;
4615 struct ieee80211_conf *conf = &hw->conf;
4616
4617 if (idx != 0)
4618 return -ENOENT;
4619
4620 survey->channel = conf->channel;
4621 survey->filled = SURVEY_INFO_NOISE_DBM;
4622 survey->noise = dev->stats.link_noise;
4623
4624 return 0;
4625 }
4626
4627 static const struct ieee80211_ops b43_hw_ops = {
4628 .tx = b43_op_tx,
4629 .conf_tx = b43_op_conf_tx,
4630 .add_interface = b43_op_add_interface,
4631 .remove_interface = b43_op_remove_interface,
4632 .config = b43_op_config,
4633 .bss_info_changed = b43_op_bss_info_changed,
4634 .configure_filter = b43_op_configure_filter,
4635 .set_key = b43_op_set_key,
4636 .update_tkip_key = b43_op_update_tkip_key,
4637 .get_stats = b43_op_get_stats,
4638 .get_tsf = b43_op_get_tsf,
4639 .set_tsf = b43_op_set_tsf,
4640 .start = b43_op_start,
4641 .stop = b43_op_stop,
4642 .set_tim = b43_op_beacon_set_tim,
4643 .sta_notify = b43_op_sta_notify,
4644 .sw_scan_start = b43_op_sw_scan_start_notifier,
4645 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
4646 .get_survey = b43_op_get_survey,
4647 .rfkill_poll = b43_rfkill_poll,
4648 };
4649
4650 /* Hard-reset the chip. Do not call this directly.
4651 * Use b43_controller_restart()
4652 */
4653 static void b43_chip_reset(struct work_struct *work)
4654 {
4655 struct b43_wldev *dev =
4656 container_of(work, struct b43_wldev, restart_work);
4657 struct b43_wl *wl = dev->wl;
4658 int err = 0;
4659 int prev_status;
4660
4661 mutex_lock(&wl->mutex);
4662
4663 prev_status = b43_status(dev);
4664 /* Bring the device down... */
4665 if (prev_status >= B43_STAT_STARTED) {
4666 dev = b43_wireless_core_stop(dev);
4667 if (!dev) {
4668 err = -ENODEV;
4669 goto out;
4670 }
4671 }
4672 if (prev_status >= B43_STAT_INITIALIZED)
4673 b43_wireless_core_exit(dev);
4674
4675 /* ...and up again. */
4676 if (prev_status >= B43_STAT_INITIALIZED) {
4677 err = b43_wireless_core_init(dev);
4678 if (err)
4679 goto out;
4680 }
4681 if (prev_status >= B43_STAT_STARTED) {
4682 err = b43_wireless_core_start(dev);
4683 if (err) {
4684 b43_wireless_core_exit(dev);
4685 goto out;
4686 }
4687 }
4688 out:
4689 if (err)
4690 wl->current_dev = NULL; /* Failed to init the dev. */
4691 mutex_unlock(&wl->mutex);
4692 if (err)
4693 b43err(wl, "Controller restart FAILED\n");
4694 else
4695 b43info(wl, "Controller restarted\n");
4696 }
4697
4698 static int b43_setup_bands(struct b43_wldev *dev,
4699 bool have_2ghz_phy, bool have_5ghz_phy)
4700 {
4701 struct ieee80211_hw *hw = dev->wl->hw;
4702
4703 if (have_2ghz_phy)
4704 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4705 if (dev->phy.type == B43_PHYTYPE_N) {
4706 if (have_5ghz_phy)
4707 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4708 } else {
4709 if (have_5ghz_phy)
4710 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4711 }
4712
4713 dev->phy.supports_2ghz = have_2ghz_phy;
4714 dev->phy.supports_5ghz = have_5ghz_phy;
4715
4716 return 0;
4717 }
4718
4719 static void b43_wireless_core_detach(struct b43_wldev *dev)
4720 {
4721 /* We release firmware that late to not be required to re-request
4722 * is all the time when we reinit the core. */
4723 b43_release_firmware(dev);
4724 b43_phy_free(dev);
4725 }
4726
4727 static int b43_wireless_core_attach(struct b43_wldev *dev)
4728 {
4729 struct b43_wl *wl = dev->wl;
4730 struct ssb_bus *bus = dev->dev->bus;
4731 struct pci_dev *pdev = (bus->bustype == SSB_BUSTYPE_PCI) ? bus->host_pci : NULL;
4732 int err;
4733 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4734 u32 tmp;
4735
4736 /* Do NOT do any device initialization here.
4737 * Do it in wireless_core_init() instead.
4738 * This function is for gathering basic information about the HW, only.
4739 * Also some structs may be set up here. But most likely you want to have
4740 * that in core_init(), too.
4741 */
4742
4743 err = ssb_bus_powerup(bus, 0);
4744 if (err) {
4745 b43err(wl, "Bus powerup failed\n");
4746 goto out;
4747 }
4748 /* Get the PHY type. */
4749 if (dev->dev->id.revision >= 5) {
4750 u32 tmshigh;
4751
4752 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4753 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4754 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4755 } else
4756 B43_WARN_ON(1);
4757
4758 dev->phy.gmode = have_2ghz_phy;
4759 dev->phy.radio_on = 1;
4760 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4761 b43_wireless_core_reset(dev, tmp);
4762
4763 err = b43_phy_versioning(dev);
4764 if (err)
4765 goto err_powerdown;
4766 /* Check if this device supports multiband. */
4767 if (!pdev ||
4768 (pdev->device != 0x4312 &&
4769 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4770 /* No multiband support. */
4771 have_2ghz_phy = 0;
4772 have_5ghz_phy = 0;
4773 switch (dev->phy.type) {
4774 case B43_PHYTYPE_A:
4775 have_5ghz_phy = 1;
4776 break;
4777 case B43_PHYTYPE_LP: //FIXME not always!
4778 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
4779 have_5ghz_phy = 1;
4780 #endif
4781 case B43_PHYTYPE_G:
4782 case B43_PHYTYPE_N:
4783 have_2ghz_phy = 1;
4784 break;
4785 default:
4786 B43_WARN_ON(1);
4787 }
4788 }
4789 if (dev->phy.type == B43_PHYTYPE_A) {
4790 /* FIXME */
4791 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4792 err = -EOPNOTSUPP;
4793 goto err_powerdown;
4794 }
4795 if (1 /* disable A-PHY */) {
4796 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4797 if (dev->phy.type != B43_PHYTYPE_N &&
4798 dev->phy.type != B43_PHYTYPE_LP) {
4799 have_2ghz_phy = 1;
4800 have_5ghz_phy = 0;
4801 }
4802 }
4803
4804 err = b43_phy_allocate(dev);
4805 if (err)
4806 goto err_powerdown;
4807
4808 dev->phy.gmode = have_2ghz_phy;
4809 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4810 b43_wireless_core_reset(dev, tmp);
4811
4812 err = b43_validate_chipaccess(dev);
4813 if (err)
4814 goto err_phy_free;
4815 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4816 if (err)
4817 goto err_phy_free;
4818
4819 /* Now set some default "current_dev" */
4820 if (!wl->current_dev)
4821 wl->current_dev = dev;
4822 INIT_WORK(&dev->restart_work, b43_chip_reset);
4823
4824 dev->phy.ops->switch_analog(dev, 0);
4825 ssb_device_disable(dev->dev, 0);
4826 ssb_bus_may_powerdown(bus);
4827
4828 out:
4829 return err;
4830
4831 err_phy_free:
4832 b43_phy_free(dev);
4833 err_powerdown:
4834 ssb_bus_may_powerdown(bus);
4835 return err;
4836 }
4837
4838 static void b43_one_core_detach(struct ssb_device *dev)
4839 {
4840 struct b43_wldev *wldev;
4841 struct b43_wl *wl;
4842
4843 /* Do not cancel ieee80211-workqueue based work here.
4844 * See comment in b43_remove(). */
4845
4846 wldev = ssb_get_drvdata(dev);
4847 wl = wldev->wl;
4848 b43_debugfs_remove_device(wldev);
4849 b43_wireless_core_detach(wldev);
4850 list_del(&wldev->list);
4851 wl->nr_devs--;
4852 ssb_set_drvdata(dev, NULL);
4853 kfree(wldev);
4854 }
4855
4856 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4857 {
4858 struct b43_wldev *wldev;
4859 struct pci_dev *pdev;
4860 int err = -ENOMEM;
4861
4862 if (!list_empty(&wl->devlist)) {
4863 /* We are not the first core on this chip. */
4864 pdev = (dev->bus->bustype == SSB_BUSTYPE_PCI) ? dev->bus->host_pci : NULL;
4865 /* Only special chips support more than one wireless
4866 * core, although some of the other chips have more than
4867 * one wireless core as well. Check for this and
4868 * bail out early.
4869 */
4870 if (!pdev ||
4871 ((pdev->device != 0x4321) &&
4872 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4873 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4874 return -ENODEV;
4875 }
4876 }
4877
4878 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4879 if (!wldev)
4880 goto out;
4881
4882 wldev->use_pio = b43_modparam_pio;
4883 wldev->dev = dev;
4884 wldev->wl = wl;
4885 b43_set_status(wldev, B43_STAT_UNINIT);
4886 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4887 INIT_LIST_HEAD(&wldev->list);
4888
4889 err = b43_wireless_core_attach(wldev);
4890 if (err)
4891 goto err_kfree_wldev;
4892
4893 list_add(&wldev->list, &wl->devlist);
4894 wl->nr_devs++;
4895 ssb_set_drvdata(dev, wldev);
4896 b43_debugfs_add_device(wldev);
4897
4898 out:
4899 return err;
4900
4901 err_kfree_wldev:
4902 kfree(wldev);
4903 return err;
4904 }
4905
4906 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4907 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4908 (pdev->device == _device) && \
4909 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4910 (pdev->subsystem_device == _subdevice) )
4911
4912 static void b43_sprom_fixup(struct ssb_bus *bus)
4913 {
4914 struct pci_dev *pdev;
4915
4916 /* boardflags workarounds */
4917 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4918 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4919 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4920 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4921 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4922 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4923 if (bus->bustype == SSB_BUSTYPE_PCI) {
4924 pdev = bus->host_pci;
4925 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4926 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
4927 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
4928 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4929 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
4930 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4931 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
4932 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4933 }
4934 }
4935
4936 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4937 {
4938 struct ieee80211_hw *hw = wl->hw;
4939
4940 ssb_set_devtypedata(dev, NULL);
4941 ieee80211_free_hw(hw);
4942 }
4943
4944 static int b43_wireless_init(struct ssb_device *dev)
4945 {
4946 struct ssb_sprom *sprom = &dev->bus->sprom;
4947 struct ieee80211_hw *hw;
4948 struct b43_wl *wl;
4949 int err = -ENOMEM;
4950
4951 b43_sprom_fixup(dev->bus);
4952
4953 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4954 if (!hw) {
4955 b43err(NULL, "Could not allocate ieee80211 device\n");
4956 goto out;
4957 }
4958 wl = hw_to_b43_wl(hw);
4959
4960 /* fill hw info */
4961 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
4962 IEEE80211_HW_SIGNAL_DBM;
4963
4964 hw->wiphy->interface_modes =
4965 BIT(NL80211_IFTYPE_AP) |
4966 BIT(NL80211_IFTYPE_MESH_POINT) |
4967 BIT(NL80211_IFTYPE_STATION) |
4968 BIT(NL80211_IFTYPE_WDS) |
4969 BIT(NL80211_IFTYPE_ADHOC);
4970
4971 hw->queues = modparam_qos ? 4 : 1;
4972 wl->mac80211_initially_registered_queues = hw->queues;
4973 hw->max_rates = 2;
4974 SET_IEEE80211_DEV(hw, dev->dev);
4975 if (is_valid_ether_addr(sprom->et1mac))
4976 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4977 else
4978 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4979
4980 /* Initialize struct b43_wl */
4981 wl->hw = hw;
4982 mutex_init(&wl->mutex);
4983 spin_lock_init(&wl->hardirq_lock);
4984 INIT_LIST_HEAD(&wl->devlist);
4985 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4986 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
4987 INIT_WORK(&wl->tx_work, b43_tx_work);
4988 skb_queue_head_init(&wl->tx_queue);
4989
4990 ssb_set_devtypedata(dev, wl);
4991 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
4992 dev->bus->chip_id, dev->id.revision);
4993 err = 0;
4994 out:
4995 return err;
4996 }
4997
4998 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4999 {
5000 struct b43_wl *wl;
5001 int err;
5002 int first = 0;
5003
5004 wl = ssb_get_devtypedata(dev);
5005 if (!wl) {
5006 /* Probing the first core. Must setup common struct b43_wl */
5007 first = 1;
5008 err = b43_wireless_init(dev);
5009 if (err)
5010 goto out;
5011 wl = ssb_get_devtypedata(dev);
5012 B43_WARN_ON(!wl);
5013 }
5014 err = b43_one_core_attach(dev, wl);
5015 if (err)
5016 goto err_wireless_exit;
5017
5018 if (first) {
5019 err = ieee80211_register_hw(wl->hw);
5020 if (err)
5021 goto err_one_core_detach;
5022 b43_leds_register(wl->current_dev);
5023 }
5024
5025 out:
5026 return err;
5027
5028 err_one_core_detach:
5029 b43_one_core_detach(dev);
5030 err_wireless_exit:
5031 if (first)
5032 b43_wireless_exit(dev, wl);
5033 return err;
5034 }
5035
5036 static void b43_remove(struct ssb_device *dev)
5037 {
5038 struct b43_wl *wl = ssb_get_devtypedata(dev);
5039 struct b43_wldev *wldev = ssb_get_drvdata(dev);
5040
5041 /* We must cancel any work here before unregistering from ieee80211,
5042 * as the ieee80211 unreg will destroy the workqueue. */
5043 cancel_work_sync(&wldev->restart_work);
5044
5045 B43_WARN_ON(!wl);
5046 if (wl->current_dev == wldev) {
5047 /* Restore the queues count before unregistering, because firmware detect
5048 * might have modified it. Restoring is important, so the networking
5049 * stack can properly free resources. */
5050 wl->hw->queues = wl->mac80211_initially_registered_queues;
5051 b43_leds_stop(wldev);
5052 ieee80211_unregister_hw(wl->hw);
5053 }
5054
5055 b43_one_core_detach(dev);
5056
5057 if (list_empty(&wl->devlist)) {
5058 b43_leds_unregister(wl);
5059 /* Last core on the chip unregistered.
5060 * We can destroy common struct b43_wl.
5061 */
5062 b43_wireless_exit(dev, wl);
5063 }
5064 }
5065
5066 /* Perform a hardware reset. This can be called from any context. */
5067 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5068 {
5069 /* Must avoid requeueing, if we are in shutdown. */
5070 if (b43_status(dev) < B43_STAT_INITIALIZED)
5071 return;
5072 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5073 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5074 }
5075
5076 static struct ssb_driver b43_ssb_driver = {
5077 .name = KBUILD_MODNAME,
5078 .id_table = b43_ssb_tbl,
5079 .probe = b43_probe,
5080 .remove = b43_remove,
5081 };
5082
5083 static void b43_print_driverinfo(void)
5084 {
5085 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5086 *feat_leds = "", *feat_sdio = "";
5087
5088 #ifdef CONFIG_B43_PCI_AUTOSELECT
5089 feat_pci = "P";
5090 #endif
5091 #ifdef CONFIG_B43_PCMCIA
5092 feat_pcmcia = "M";
5093 #endif
5094 #ifdef CONFIG_B43_NPHY
5095 feat_nphy = "N";
5096 #endif
5097 #ifdef CONFIG_B43_LEDS
5098 feat_leds = "L";
5099 #endif
5100 #ifdef CONFIG_B43_SDIO
5101 feat_sdio = "S";
5102 #endif
5103 printk(KERN_INFO "Broadcom 43xx driver loaded "
5104 "[ Features: %s%s%s%s%s, Firmware-ID: "
5105 B43_SUPPORTED_FIRMWARE_ID " ]\n",
5106 feat_pci, feat_pcmcia, feat_nphy,
5107 feat_leds, feat_sdio);
5108 }
5109
5110 static int __init b43_init(void)
5111 {
5112 int err;
5113
5114 b43_debugfs_init();
5115 err = b43_pcmcia_init();
5116 if (err)
5117 goto err_dfs_exit;
5118 err = b43_sdio_init();
5119 if (err)
5120 goto err_pcmcia_exit;
5121 err = ssb_driver_register(&b43_ssb_driver);
5122 if (err)
5123 goto err_sdio_exit;
5124 b43_print_driverinfo();
5125
5126 return err;
5127
5128 err_sdio_exit:
5129 b43_sdio_exit();
5130 err_pcmcia_exit:
5131 b43_pcmcia_exit();
5132 err_dfs_exit:
5133 b43_debugfs_exit();
5134 return err;
5135 }
5136
5137 static void __exit b43_exit(void)
5138 {
5139 ssb_driver_unregister(&b43_ssb_driver);
5140 b43_sdio_exit();
5141 b43_pcmcia_exit();
5142 b43_debugfs_exit();
5143 }
5144
5145 module_init(b43_init)
5146 module_exit(b43_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree