drivers/net/bnx2x/bnx2x_cmn.h

   1 /* bnx2x_cmn.h: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2010 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17 #ifndef BNX2X_CMN_H
  18 #define BNX2X_CMN_H
  19
  20 #include <linux/types.h>
  21 #include <linux/netdevice.h>
  22
  23
  24 #include "bnx2x.h"
  25
  26 extern int num_queues;
  27
  28 /*********************** Interfaces ****************************
  29  *  Functions that need to be implemented by each driver version
  30  */
  31
  32 /**
  33  * Initialize link parameters structure variables.
  34  *
  35  * @param bp
  36  * @param load_mode
  37  *
  38  * @return u8
  39  */
  40 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
  41
  42 /**
  43  * Configure hw according to link parameters structure.
  44  *
  45  * @param bp
  46  */
  47 void bnx2x_link_set(struct bnx2x *bp);
  48
  49 /**
  50  * Query link status
  51  *
  52  * @param bp
  53  * @param is_serdes
  54  *
  55  * @return 0 - link is UP
  56  */
  57 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
  58
  59 /**
  60  * Handles link status change
  61  *
  62  * @param bp
  63  */
  64 void bnx2x__link_status_update(struct bnx2x *bp);
  65
  66 /**
  67  * Report link status to upper layer
  68  *
  69  * @param bp
  70  *
  71  * @return int
  72  */
  73 void bnx2x_link_report(struct bnx2x *bp);
  74
  75 /**
  76  * MSI-X slowpath interrupt handler
  77  *
  78  * @param irq
  79  * @param dev_instance
  80  *
  81  * @return irqreturn_t
  82  */
  83 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
  84
  85 /**
  86  * non MSI-X interrupt handler
  87  *
  88  * @param irq
  89  * @param dev_instance
  90  *
  91  * @return irqreturn_t
  92  */
  93 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
  94 #ifdef BCM_CNIC
  95
  96 /**
  97  * Send command to cnic driver
  98  *
  99  * @param bp
 100  * @param cmd
 101  */
 102 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
 103
 104 /**
 105  * Provides cnic information for proper interrupt handling
 106  *
 107  * @param bp
 108  */
 109 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
 110 #endif
 111
 112 /**
 113  * Enable HW interrupts.
 114  *
 115  * @param bp
 116  */
 117 void bnx2x_int_enable(struct bnx2x *bp);
 118
 119 /**
 120  * Disable HW interrupts.
 121  *
 122  * @param bp
 123  */
 124 void bnx2x_int_disable(struct bnx2x *bp);
 125
 126 /**
 127  * Disable interrupts. This function ensures that there are no
 128  * ISRs or SP DPCs (sp_task) are running after it returns.
 129  *
 130  * @param bp
 131  * @param disable_hw if true, disable HW interrupts.
 132  */
 133 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
 134
 135 /**
 136  * Loads device firmware
 137  *
 138  * @param bp
 139  *
 140  * @return int
 141  */
 142 int bnx2x_init_firmware(struct bnx2x *bp);
 143
 144 /**
 145  * Init HW blocks according to current initialization stage:
 146  * COMMON, PORT or FUNCTION.
 147  *
 148  * @param bp
 149  * @param load_code: COMMON, PORT or FUNCTION
 150  *
 151  * @return int
 152  */
 153 int bnx2x_init_hw(struct bnx2x *bp, u32 load_code);
 154
 155 /**
 156  * Init driver internals:
 157  *  - rings
 158  *  - status blocks
 159  *  - etc.
 160  *
 161  * @param bp
 162  * @param load_code COMMON, PORT or FUNCTION
 163  */
 164 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code);
 165
 166 /**
 167  * Allocate driver's memory.
 168  *
 169  * @param bp
 170  *
 171  * @return int
 172  */
 173 int bnx2x_alloc_mem(struct bnx2x *bp);
 174
 175 /**
 176  * Release driver's memory.
 177  *
 178  * @param bp
 179  */
 180 void bnx2x_free_mem(struct bnx2x *bp);
 181
 182 /**
 183  * Setup eth Client.
 184  *
 185  * @param bp
 186  * @param fp
 187  * @param is_leading
 188  *
 189  * @return int
 190  */
 191 int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
 192                        int is_leading);
 193
 194 /**
 195  * Bring down an eth client.
 196  *
 197  * @param bp
 198  * @param p
 199  *
 200  * @return int
 201  */
 202 int bnx2x_stop_fw_client(struct bnx2x *bp,
 203                          struct bnx2x_client_ramrod_params *p);
 204
 205 /**
 206  * Set number of queues according to mode
 207  *
 208  * @param bp
 209  *
 210  */
 211 void bnx2x_set_num_queues(struct bnx2x *bp);
 212
 213 /**
 214  * Cleanup chip internals:
 215  * - Cleanup MAC configuration.
 216  * - Close clients.
 217  * - etc.
 218  *
 219  * @param bp
 220  * @param unload_mode
 221  */
 222 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode);
 223
 224 /**
 225  * Acquire HW lock.
 226  *
 227  * @param bp
 228  * @param resource Resource bit which was locked
 229  *
 230  * @return int
 231  */
 232 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
 233
 234 /**
 235  * Release HW lock.
 236  *
 237  * @param bp driver handle
 238  * @param resource Resource bit which was locked
 239  *
 240  * @return int
 241  */
 242 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
 243
 244 /**
 245  * Configure eth MAC address in the HW according to the value in
 246  * netdev->dev_addr.
 247  *
 248  * @param bp driver handle
 249  * @param set
 250  */
 251 void bnx2x_set_eth_mac(struct bnx2x *bp, int set);
 252
 253 #ifdef BCM_CNIC
 254 /**
 255  * Set iSCSI MAC(s) at the next enties in the CAM after the ETH
 256  * MAC(s). The function will wait until the ramrod completion
 257  * returns.
 258  *
 259  * @param bp driver handle
 260  * @param set set or clear the CAM entry
 261  *
 262  * @return 0 if cussess, -ENODEV if ramrod doesn't return.
 263  */
 264 int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set);
 265 #endif
 266
 267 /**
 268  * Initialize status block in FW and HW
 269  *
 270  * @param bp driver handle
 271  * @param dma_addr_t mapping
 272  * @param int sb_id
 273  * @param int vfid
 274  * @param u8 vf_valid
 275  * @param int fw_sb_id
 276  * @param int igu_sb_id
 277  */
 278 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
 279                           u8 vf_valid, int fw_sb_id, int igu_sb_id);
 280
 281 /**
 282  * Set MAC filtering configurations.
 283  *
 284  * @remarks called with netif_tx_lock from dev_mcast.c
 285  *
 286  * @param dev net_device
 287  */
 288 void bnx2x_set_rx_mode(struct net_device *dev);
 289
 290 /**
 291  * Configure MAC filtering rules in a FW.
 292  *
 293  * @param bp driver handle
 294  */
 295 void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
 296
 297 /* Parity errors related */
 298 void bnx2x_inc_load_cnt(struct bnx2x *bp);
 299 u32 bnx2x_dec_load_cnt(struct bnx2x *bp);
 300 bool bnx2x_chk_parity_attn(struct bnx2x *bp);
 301 bool bnx2x_reset_is_done(struct bnx2x *bp);
 302 void bnx2x_disable_close_the_gate(struct bnx2x *bp);
 303
 304 /**
 305  * Perform statistics handling according to event
 306  *
 307  * @param bp driver handle
 308  * @param event bnx2x_stats_event
 309  */
 310 void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
 311
 312 /**
 313  * Handle ramrods completion
 314  *
 315  * @param fp fastpath handle for the event
 316  * @param rr_cqe eth_rx_cqe
 317  */
 318 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
 319
 320 /**
 321  * Init/halt function before/after sending
 322  * CLIENT_SETUP/CFC_DEL for the first/last client.
 323  *
 324  * @param bp
 325  *
 326  * @return int
 327  */
 328 int bnx2x_func_start(struct bnx2x *bp);
 329 int bnx2x_func_stop(struct bnx2x *bp);
 330
 331 /**
 332  * Prepare ILT configurations according to current driver
 333  * parameters.
 334  *
 335  * @param bp
 336  */
 337 void bnx2x_ilt_set_info(struct bnx2x *bp);
 338
 339 /**
 340  * Set power state to the requested value. Currently only D0 and
 341  * D3hot are supported.
 342  *
 343  * @param bp
 344  * @param state D0 or D3hot
 345  *
 346  * @return int
 347  */
 348 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
 349
 350 /* dev_close main block */
 351 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode);
 352
 353 /* dev_open main block */
 354 int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
 355
 356 /* hard_xmit callback */
 357 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
 358
 359 int bnx2x_change_mac_addr(struct net_device *dev, void *p);
 360
 361 /* NAPI poll Rx part */
 362 int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget);
 363
 364 /* NAPI poll Tx part */
 365 int bnx2x_tx_int(struct bnx2x_fastpath *fp);
 366
 367 /* suspend/resume callbacks */
 368 int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
 369 int bnx2x_resume(struct pci_dev *pdev);
 370
 371 /* Release IRQ vectors */
 372 void bnx2x_free_irq(struct bnx2x *bp);
 373
 374 void bnx2x_init_rx_rings(struct bnx2x *bp);
 375 void bnx2x_free_skbs(struct bnx2x *bp);
 376 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
 377 void bnx2x_netif_start(struct bnx2x *bp);
 378
 379 /**
 380  * Fill msix_table, request vectors, update num_queues according
 381  * to number of available vectors
 382  *
 383  * @param bp
 384  *
 385  * @return int
 386  */
 387 int bnx2x_enable_msix(struct bnx2x *bp);
 388
 389 /**
 390  * Request msi mode from OS, updated internals accordingly
 391  *
 392  * @param bp
 393  *
 394  * @return int
 395  */
 396 int bnx2x_enable_msi(struct bnx2x *bp);
 397
 398 /**
 399  * Request IRQ vectors from OS.
 400  *
 401  * @param bp
 402  *
 403  * @return int
 404  */
 405 int bnx2x_setup_irqs(struct bnx2x *bp);
 406 /**
 407  * NAPI callback
 408  *
 409  * @param napi
 410  * @param budget
 411  *
 412  * @return int
 413  */
 414 int bnx2x_poll(struct napi_struct *napi, int budget);
 415
 416 /**
 417  * Allocate/release memories outsize main driver structure
 418  *
 419  * @param bp
 420  *
 421  * @return int
 422  */
 423 int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp);
 424 void bnx2x_free_mem_bp(struct bnx2x *bp);
 425
 426 /**
 427  * Change mtu netdev callback
 428  *
 429  * @param dev
 430  * @param new_mtu
 431  *
 432  * @return int
 433  */
 434 int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
 435
 436 /**
 437  * tx timeout netdev callback
 438  *
 439  * @param dev
 440  * @param new_mtu
 441  *
 442  * @return int
 443  */
 444 void bnx2x_tx_timeout(struct net_device *dev);
 445
 446 #ifdef BCM_VLAN
 447 /**
 448  * vlan rx register netdev callback
 449  *
 450  * @param dev
 451  * @param new_mtu
 452  *
 453  * @return int
 454  */
 455 void bnx2x_vlan_rx_register(struct net_device *dev,
 456                                    struct vlan_group *vlgrp);
 457
 458 #endif
 459
 460 static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
 461 {
 462         barrier(); /* status block is written to by the chip */
 463         fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
 464 }
 465
 466 static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
 467                                         struct bnx2x_fastpath *fp,
 468                                         u16 bd_prod, u16 rx_comp_prod,
 469                                         u16 rx_sge_prod)
 470 {
 471         struct ustorm_eth_rx_producers rx_prods = {0};
 472         int i;
 473
 474         /* Update producers */
 475         rx_prods.bd_prod = bd_prod;
 476         rx_prods.cqe_prod = rx_comp_prod;
 477         rx_prods.sge_prod = rx_sge_prod;
 478
 479         /*
 480          * Make sure that the BD and SGE data is updated before updating the
 481          * producers since FW might read the BD/SGE right after the producer
 482          * is updated.
 483          * This is only applicable for weak-ordered memory model archs such
 484          * as IA-64. The following barrier is also mandatory since FW will
 485          * assumes BDs must have buffers.
 486          */
 487         wmb();
 488
 489         for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
 490                 REG_WR(bp,
 491                        BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset + i*4,
 492                        ((u32 *)&rx_prods)[i]);
 493
 494         mmiowb(); /* keep prod updates ordered */
 495
 496         DP(NETIF_MSG_RX_STATUS,
 497            "queue[%d]:  wrote  bd_prod %u  cqe_prod %u  sge_prod %u\n",
 498            fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
 499 }
 500
 501 static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
 502                                         u8 segment, u16 index, u8 op,
 503                                         u8 update, u32 igu_addr)
 504 {
 505         struct igu_regular cmd_data = {0};
 506
 507         cmd_data.sb_id_and_flags =
 508                         ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
 509                          (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
 510                          (update << IGU_REGULAR_BUPDATE_SHIFT) |
 511                          (op << IGU_REGULAR_ENABLE_INT_SHIFT));
 512
 513         DP(NETIF_MSG_HW, "write 0x%08x to IGU addr 0x%x\n",
 514            cmd_data.sb_id_and_flags, igu_addr);
 515         REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
 516
 517         /* Make sure that ACK is written */
 518         mmiowb();
 519         barrier();
 520 }
 521
 522 static inline void bnx2x_igu_clear_sb_gen(struct bnx2x *bp,
 523                                           u8 idu_sb_id, bool is_Pf)
 524 {
 525         u32 data, ctl, cnt = 100;
 526         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
 527         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
 528         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
 529         u32 sb_bit =  1 << (idu_sb_id%32);
 530         u32 func_encode = BP_FUNC(bp) |
 531                         ((is_Pf == true ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT);
 532         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
 533
 534         /* Not supported in BC mode */
 535         if (CHIP_INT_MODE_IS_BC(bp))
 536                 return;
 537
 538         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
 539                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
 540                 IGU_REGULAR_CLEANUP_SET                         |
 541                 IGU_REGULAR_BCLEANUP;
 542
 543         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
 544               func_encode << IGU_CTRL_REG_FID_SHIFT             |
 545               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
 546
 547         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
 548                          data, igu_addr_data);
 549         REG_WR(bp, igu_addr_data, data);
 550         mmiowb();
 551         barrier();
 552         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
 553                           ctl, igu_addr_ctl);
 554         REG_WR(bp, igu_addr_ctl, ctl);
 555         mmiowb();
 556         barrier();
 557
 558         /* wait for clean up to finish */
 559         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
 560                 msleep(20);
 561
 562
 563         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
 564                 DP(NETIF_MSG_HW, "Unable to finish IGU cleanup: "
 565                           "idu_sb_id %d offset %d bit %d (cnt %d)\n",
 566                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
 567         }
 568 }
 569
 570 static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
 571                                    u8 storm, u16 index, u8 op, u8 update)
 572 {
 573         u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
 574                        COMMAND_REG_INT_ACK);
 575         struct igu_ack_register igu_ack;
 576
 577         igu_ack.status_block_index = index;
 578         igu_ack.sb_id_and_flags =
 579                         ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
 580                          (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
 581                          (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
 582                          (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
 583
 584         DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
 585            (*(u32 *)&igu_ack), hc_addr);
 586         REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
 587
 588         /* Make sure that ACK is written */
 589         mmiowb();
 590         barrier();
 591 }
 592
 593 static inline void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
 594                       u16 index, u8 op, u8 update)
 595 {
 596         u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
 597
 598         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
 599                              igu_addr);
 600 }
 601
 602 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
 603                                 u16 index, u8 op, u8 update)
 604 {
 605         if (bp->common.int_block == INT_BLOCK_HC)
 606                 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
 607         else {
 608                 u8 segment;
 609
 610                 if (CHIP_INT_MODE_IS_BC(bp))
 611                         segment = storm;
 612                 else if (igu_sb_id != bp->igu_dsb_id)
 613                         segment = IGU_SEG_ACCESS_DEF;
 614                 else if (storm == ATTENTION_ID)
 615                         segment = IGU_SEG_ACCESS_ATTN;
 616                 else
 617                         segment = IGU_SEG_ACCESS_DEF;
 618                 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
 619         }
 620 }
 621
 622 static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
 623 {
 624         u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
 625                        COMMAND_REG_SIMD_MASK);
 626         u32 result = REG_RD(bp, hc_addr);
 627
 628         DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
 629            result, hc_addr);
 630
 631         barrier();
 632         return result;
 633 }
 634
 635 static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
 636 {
 637         u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
 638         u32 result = REG_RD(bp, igu_addr);
 639
 640         DP(NETIF_MSG_HW, "read 0x%08x from IGU addr 0x%x\n",
 641            result, igu_addr);
 642
 643         barrier();
 644         return result;
 645 }
 646
 647 static inline u16 bnx2x_ack_int(struct bnx2x *bp)
 648 {
 649         barrier();
 650         if (bp->common.int_block == INT_BLOCK_HC)
 651                 return bnx2x_hc_ack_int(bp);
 652         else
 653                 return bnx2x_igu_ack_int(bp);
 654 }
 655
 656 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp)
 657 {
 658         /* Tell compiler that consumer and producer can change */
 659         barrier();
 660         return fp->tx_pkt_prod != fp->tx_pkt_cons;
 661 }
 662
 663 static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
 664 {
 665         s16 used;
 666         u16 prod;
 667         u16 cons;
 668
 669         prod = fp->tx_bd_prod;
 670         cons = fp->tx_bd_cons;
 671
 672         /* NUM_TX_RINGS = number of "next-page" entries
 673            It will be used as a threshold */
 674         used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
 675
 676 #ifdef BNX2X_STOP_ON_ERROR
 677         WARN_ON(used < 0);
 678         WARN_ON(used > fp->bp->tx_ring_size);
 679         WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
 680 #endif
 681
 682         return (s16)(fp->bp->tx_ring_size) - used;
 683 }
 684
 685 static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
 686 {
 687         u16 hw_cons;
 688
 689         /* Tell compiler that status block fields can change */
 690         barrier();
 691         hw_cons = le16_to_cpu(*fp->tx_cons_sb);
 692         return hw_cons != fp->tx_pkt_cons;
 693 }
 694
 695 static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
 696 {
 697         u16 rx_cons_sb;
 698
 699         /* Tell compiler that status block fields can change */
 700         barrier();
 701         rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
 702         if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
 703                 rx_cons_sb++;
 704         return (fp->rx_comp_cons != rx_cons_sb);
 705 }
 706
 707 /**
 708  * disables tx from stack point of view
 709  *
 710  * @param bp
 711  */
 712 static inline void bnx2x_tx_disable(struct bnx2x *bp)
 713 {
 714         netif_tx_disable(bp->dev);
 715         netif_carrier_off(bp->dev);
 716 }
 717
 718 static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
 719                                      struct bnx2x_fastpath *fp, u16 index)
 720 {
 721         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
 722         struct page *page = sw_buf->page;
 723         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
 724
 725         /* Skip "next page" elements */
 726         if (!page)
 727                 return;
 728
 729         dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
 730                        SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
 731         __free_pages(page, PAGES_PER_SGE_SHIFT);
 732
 733         sw_buf->page = NULL;
 734         sge->addr_hi = 0;
 735         sge->addr_lo = 0;
 736 }
 737
 738 static inline void bnx2x_add_all_napi(struct bnx2x *bp)
 739 {
 740         int i;
 741
 742         /* Add NAPI objects */
 743         for_each_queue(bp, i)
 744                 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
 745                                bnx2x_poll, BNX2X_NAPI_WEIGHT);
 746 }
 747
 748 static inline void bnx2x_del_all_napi(struct bnx2x *bp)
 749 {
 750         int i;
 751
 752         for_each_queue(bp, i)
 753                 netif_napi_del(&bnx2x_fp(bp, i, napi));
 754 }
 755
 756 static inline void bnx2x_disable_msi(struct bnx2x *bp)
 757 {
 758         if (bp->flags & USING_MSIX_FLAG) {
 759                 pci_disable_msix(bp->pdev);
 760                 bp->flags &= ~USING_MSIX_FLAG;
 761         } else if (bp->flags & USING_MSI_FLAG) {
 762                 pci_disable_msi(bp->pdev);
 763                 bp->flags &= ~USING_MSI_FLAG;
 764         }
 765 }
 766
 767 static inline int bnx2x_calc_num_queues(struct bnx2x *bp)
 768 {
 769         return  num_queues ?
 770                  min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) :
 771                  min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp));
 772 }
 773
 774 static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
 775 {
 776         int i, j;
 777
 778         for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
 779                 int idx = RX_SGE_CNT * i - 1;
 780
 781                 for (j = 0; j < 2; j++) {
 782                         SGE_MASK_CLEAR_BIT(fp, idx);
 783                         idx--;
 784                 }
 785         }
 786 }
 787
 788 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
 789 {
 790         /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
 791         memset(fp->sge_mask, 0xff,
 792                (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
 793
 794         /* Clear the two last indices in the page to 1:
 795            these are the indices that correspond to the "next" element,
 796            hence will never be indicated and should be removed from
 797            the calculations. */
 798         bnx2x_clear_sge_mask_next_elems(fp);
 799 }
 800
 801 static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
 802                                      struct bnx2x_fastpath *fp, u16 index)
 803 {
 804         struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
 805         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
 806         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
 807         dma_addr_t mapping;
 808
 809         if (unlikely(page == NULL))
 810                 return -ENOMEM;
 811
 812         mapping = dma_map_page(&bp->pdev->dev, page, 0,
 813                                SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
 814         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
 815                 __free_pages(page, PAGES_PER_SGE_SHIFT);
 816                 return -ENOMEM;
 817         }
 818
 819         sw_buf->page = page;
 820         dma_unmap_addr_set(sw_buf, mapping, mapping);
 821
 822         sge->addr_hi = cpu_to_le32(U64_HI(mapping));
 823         sge->addr_lo = cpu_to_le32(U64_LO(mapping));
 824
 825         return 0;
 826 }
 827
 828 static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
 829                                      struct bnx2x_fastpath *fp, u16 index)
 830 {
 831         struct sk_buff *skb;
 832         struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
 833         struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
 834         dma_addr_t mapping;
 835
 836         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
 837         if (unlikely(skb == NULL))
 838                 return -ENOMEM;
 839
 840         mapping = dma_map_single(&bp->pdev->dev, skb->data, bp->rx_buf_size,
 841                                  DMA_FROM_DEVICE);
 842         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
 843                 dev_kfree_skb(skb);
 844                 return -ENOMEM;
 845         }
 846
 847         rx_buf->skb = skb;
 848         dma_unmap_addr_set(rx_buf, mapping, mapping);
 849
 850         rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
 851         rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
 852
 853         return 0;
 854 }
 855
 856 /* note that we are not allocating a new skb,
 857  * we are just moving one from cons to prod
 858  * we are not creating a new mapping,
 859  * so there is no need to check for dma_mapping_error().
 860  */
 861 static inline void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
 862                                       u16 cons, u16 prod)
 863 {
 864         struct bnx2x *bp = fp->bp;
 865         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
 866         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
 867         struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
 868         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
 869
 870         dma_sync_single_for_device(&bp->pdev->dev,
 871                                    dma_unmap_addr(cons_rx_buf, mapping),
 872                                    RX_COPY_THRESH, DMA_FROM_DEVICE);
 873
 874         prod_rx_buf->skb = cons_rx_buf->skb;
 875         dma_unmap_addr_set(prod_rx_buf, mapping,
 876                            dma_unmap_addr(cons_rx_buf, mapping));
 877         *prod_bd = *cons_bd;
 878 }
 879
 880 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
 881                                            struct bnx2x_fastpath *fp, int last)
 882 {
 883         int i;
 884
 885         for (i = 0; i < last; i++)
 886                 bnx2x_free_rx_sge(bp, fp, i);
 887 }
 888
 889 static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
 890                                        struct bnx2x_fastpath *fp, int last)
 891 {
 892         int i;
 893
 894         for (i = 0; i < last; i++) {
 895                 struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
 896                 struct sk_buff *skb = rx_buf->skb;
 897
 898                 if (skb == NULL) {
 899                         DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
 900                         continue;
 901                 }
 902
 903                 if (fp->tpa_state[i] == BNX2X_TPA_START)
 904                         dma_unmap_single(&bp->pdev->dev,
 905                                          dma_unmap_addr(rx_buf, mapping),
 906                                          bp->rx_buf_size, DMA_FROM_DEVICE);
 907
 908                 dev_kfree_skb(skb);
 909                 rx_buf->skb = NULL;
 910         }
 911 }
 912
 913
 914 static inline void bnx2x_init_tx_rings(struct bnx2x *bp)
 915 {
 916         int i, j;
 917
 918         for_each_queue(bp, j) {
 919                 struct bnx2x_fastpath *fp = &bp->fp[j];
 920
 921                 for (i = 1; i <= NUM_TX_RINGS; i++) {
 922                         struct eth_tx_next_bd *tx_next_bd =
 923                                 &fp->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
 924
 925                         tx_next_bd->addr_hi =
 926                                 cpu_to_le32(U64_HI(fp->tx_desc_mapping +
 927                                             BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
 928                         tx_next_bd->addr_lo =
 929                                 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
 930                                             BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
 931                 }
 932
 933                 SET_FLAG(fp->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
 934                 fp->tx_db.data.zero_fill1 = 0;
 935                 fp->tx_db.data.prod = 0;
 936
 937                 fp->tx_pkt_prod = 0;
 938                 fp->tx_pkt_cons = 0;
 939                 fp->tx_bd_prod = 0;
 940                 fp->tx_bd_cons = 0;
 941                 fp->tx_pkt = 0;
 942         }
 943 }
 944
 945 static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
 946 {
 947         int i;
 948
 949         for (i = 1; i <= NUM_RX_RINGS; i++) {
 950                 struct eth_rx_bd *rx_bd;
 951
 952                 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
 953                 rx_bd->addr_hi =
 954                         cpu_to_le32(U64_HI(fp->rx_desc_mapping +
 955                                     BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
 956                 rx_bd->addr_lo =
 957                         cpu_to_le32(U64_LO(fp->rx_desc_mapping +
 958                                     BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
 959         }
 960 }
 961
 962 static inline void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
 963 {
 964         int i;
 965
 966         for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
 967                 struct eth_rx_sge *sge;
 968
 969                 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
 970                 sge->addr_hi =
 971                         cpu_to_le32(U64_HI(fp->rx_sge_mapping +
 972                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
 973
 974                 sge->addr_lo =
 975                         cpu_to_le32(U64_LO(fp->rx_sge_mapping +
 976                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
 977         }
 978 }
 979
 980 static inline void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp)
 981 {
 982         int i;
 983         for (i = 1; i <= NUM_RCQ_RINGS; i++) {
 984                 struct eth_rx_cqe_next_page *nextpg;
 985
 986                 nextpg = (struct eth_rx_cqe_next_page *)
 987                         &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
 988                 nextpg->addr_hi =
 989                         cpu_to_le32(U64_HI(fp->rx_comp_mapping +
 990                                    BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
 991                 nextpg->addr_lo =
 992                         cpu_to_le32(U64_LO(fp->rx_comp_mapping +
 993                                    BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
 994         }
 995 }
 996
 997
 998
 999 static inline void __storm_memset_struct(struct bnx2x *bp,
1000                                          u32 addr, size_t size, u32 *data)
1001 {
1002         int i;
1003         for (i = 0; i < size/4; i++)
1004                 REG_WR(bp, addr + (i * 4), data[i]);
1005 }
1006
1007 static inline void storm_memset_mac_filters(struct bnx2x *bp,
1008                         struct tstorm_eth_mac_filter_config *mac_filters,
1009                         u16 abs_fid)
1010 {
1011         size_t size = sizeof(struct tstorm_eth_mac_filter_config);
1012
1013         u32 addr = BAR_TSTRORM_INTMEM +
1014                         TSTORM_MAC_FILTER_CONFIG_OFFSET(abs_fid);
1015
1016         __storm_memset_struct(bp, addr, size, (u32 *)mac_filters);
1017 }
1018
1019 static inline void storm_memset_cmng(struct bnx2x *bp,
1020                                 struct cmng_struct_per_port *cmng,
1021                                 u8 port)
1022 {
1023         size_t size = sizeof(struct cmng_struct_per_port);
1024
1025         u32 addr = BAR_XSTRORM_INTMEM +
1026                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
1027
1028         __storm_memset_struct(bp, addr, size, (u32 *)cmng);
1029 }
1030
1031 /* HW Lock for shared dual port PHYs */
1032 void bnx2x_acquire_phy_lock(struct bnx2x *bp);
1033 void bnx2x_release_phy_lock(struct bnx2x *bp);
1034
1035 #define BNX2X_FW_IP_HDR_ALIGN_PAD       2 /* FW places hdr with this padding */
1036
1037 #endif /* BNX2X_CMN_H */