drivers/media/dvb/frontends/dibx000_common.h

   1 #ifndef DIBX000_COMMON_H
   2 #define DIBX000_COMMON_H
   3
   4 enum dibx000_i2c_interface {
   5         DIBX000_I2C_INTERFACE_TUNER = 0,
   6         DIBX000_I2C_INTERFACE_GPIO_1_2 = 1,
   7         DIBX000_I2C_INTERFACE_GPIO_3_4 = 2,
   8         DIBX000_I2C_INTERFACE_GPIO_6_7 = 3
   9 };
  10
  11 struct dibx000_i2c_master {
  12 #define DIB3000MC 1
  13 #define DIB7000   2
  14 #define DIB7000P  11
  15 #define DIB7000MC 12
  16 #define DIB8000   13
  17         u16 device_rev;
  18
  19         enum dibx000_i2c_interface selected_interface;
  20
  21 /*      struct i2c_adapter  tuner_i2c_adap; */
  22         struct i2c_adapter gated_tuner_i2c_adap;
  23         struct i2c_adapter master_i2c_adap_gpio12;
  24         struct i2c_adapter master_i2c_adap_gpio34;
  25         struct i2c_adapter master_i2c_adap_gpio67;
  26
  27         struct i2c_adapter *i2c_adap;
  28         u8 i2c_addr;
  29
  30         u16 base_reg;
  31
  32         /* for the I2C transfer */
  33         struct i2c_msg msg[34];
  34         u8 i2c_write_buffer[8];
  35         u8 i2c_read_buffer[2];
  36 };
  37
  38 extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst,
  39                                         u16 device_rev, struct i2c_adapter *i2c_adap,
  40                                         u8 i2c_addr);
  41 extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master
  42                                                         *mst,
  43                                                         enum dibx000_i2c_interface
  44                                                         intf, int gating);
  45 extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst);
  46 extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst);
  47 extern int dibx000_i2c_set_speed(struct i2c_adapter *i2c_adap, u16 speed);
  48
  49 extern u32 systime(void);
  50
  51 #define BAND_LBAND 0x01
  52 #define BAND_UHF   0x02
  53 #define BAND_VHF   0x04
  54 #define BAND_SBAND 0x08
  55 #define BAND_FM    0x10
  56 #define BAND_CBAND 0x20
  57
  58 #define BAND_OF_FREQUENCY(freq_kHz) ((freq_kHz) <= 170000 ? BAND_CBAND : \
  59                                                                         (freq_kHz) <= 115000 ? BAND_FM : \
  60                                                                         (freq_kHz) <= 250000 ? BAND_VHF : \
  61                                                                         (freq_kHz) <= 863000 ? BAND_UHF : \
  62                                                                         (freq_kHz) <= 2000000 ? BAND_LBAND : BAND_SBAND )
  63
  64 struct dibx000_agc_config {
  65         /* defines the capabilities of this AGC-setting - using the BAND_-defines */
  66         u8 band_caps;
  67
  68         u16 setup;
  69
  70         u16 inv_gain;
  71         u16 time_stabiliz;
  72
  73         u8 alpha_level;
  74         u16 thlock;
  75
  76         u8 wbd_inv;
  77         u16 wbd_ref;
  78         u8 wbd_sel;
  79         u8 wbd_alpha;
  80
  81         u16 agc1_max;
  82         u16 agc1_min;
  83         u16 agc2_max;
  84         u16 agc2_min;
  85
  86         u8 agc1_pt1;
  87         u8 agc1_pt2;
  88         u8 agc1_pt3;
  89
  90         u8 agc1_slope1;
  91         u8 agc1_slope2;
  92
  93         u8 agc2_pt1;
  94         u8 agc2_pt2;
  95
  96         u8 agc2_slope1;
  97         u8 agc2_slope2;
  98
  99         u8 alpha_mant;
 100         u8 alpha_exp;
 101
 102         u8 beta_mant;
 103         u8 beta_exp;
 104
 105         u8 perform_agc_softsplit;
 106
 107         struct {
 108                 u16 min;
 109                 u16 max;
 110                 u16 min_thres;
 111                 u16 max_thres;
 112         } split;
 113 };
 114
 115 struct dibx000_bandwidth_config {
 116         u32 internal;
 117         u32 sampling;
 118
 119         u8 pll_prediv;
 120         u8 pll_ratio;
 121         u8 pll_range;
 122         u8 pll_reset;
 123         u8 pll_bypass;
 124
 125         u8 enable_refdiv;
 126         u8 bypclk_div;
 127         u8 IO_CLK_en_core;
 128         u8 ADClkSrc;
 129         u8 modulo;
 130
 131         u16 sad_cfg;
 132
 133         u32 ifreq;
 134         u32 timf;
 135
 136         u32 xtal_hz;
 137 };
 138
 139 enum dibx000_adc_states {
 140         DIBX000_SLOW_ADC_ON = 0,
 141         DIBX000_SLOW_ADC_OFF,
 142         DIBX000_ADC_ON,
 143         DIBX000_ADC_OFF,
 144         DIBX000_VBG_ENABLE,
 145         DIBX000_VBG_DISABLE,
 146 };
 147
 148 #define BANDWIDTH_TO_KHZ(v) ((v) == BANDWIDTH_8_MHZ  ? 8000 : \
 149                                 (v) == BANDWIDTH_7_MHZ  ? 7000 : \
 150                                 (v) == BANDWIDTH_6_MHZ  ? 6000 : 8000)
 151
 152 #define BANDWIDTH_TO_INDEX(v) ( \
 153         (v) == 8000 ? BANDWIDTH_8_MHZ : \
 154                 (v) == 7000 ? BANDWIDTH_7_MHZ : \
 155                 (v) == 6000 ? BANDWIDTH_6_MHZ : BANDWIDTH_8_MHZ )
 156
 157 /* Chip output mode. */
 158 #define OUTMODE_HIGH_Z              0
 159 #define OUTMODE_MPEG2_PAR_GATED_CLK 1
 160 #define OUTMODE_MPEG2_PAR_CONT_CLK  2
 161 #define OUTMODE_MPEG2_SERIAL        7
 162 #define OUTMODE_DIVERSITY           4
 163 #define OUTMODE_MPEG2_FIFO          5
 164 #define OUTMODE_ANALOG_ADC          6
 165
 166 #define INPUT_MODE_OFF                0x11
 167 #define INPUT_MODE_DIVERSITY          0x12
 168 #define INPUT_MODE_MPEG               0x13
 169
 170 enum frontend_tune_state {
 171         CT_TUNER_START = 10,
 172         CT_TUNER_STEP_0,
 173         CT_TUNER_STEP_1,
 174         CT_TUNER_STEP_2,
 175         CT_TUNER_STEP_3,
 176         CT_TUNER_STEP_4,
 177         CT_TUNER_STEP_5,
 178         CT_TUNER_STEP_6,
 179         CT_TUNER_STEP_7,
 180         CT_TUNER_STOP,
 181
 182         CT_AGC_START = 20,
 183         CT_AGC_STEP_0,
 184         CT_AGC_STEP_1,
 185         CT_AGC_STEP_2,
 186         CT_AGC_STEP_3,
 187         CT_AGC_STEP_4,
 188         CT_AGC_STOP,
 189
 190         CT_DEMOD_START = 30,
 191         CT_DEMOD_STEP_1,
 192         CT_DEMOD_STEP_2,
 193         CT_DEMOD_STEP_3,
 194         CT_DEMOD_STEP_4,
 195         CT_DEMOD_STEP_5,
 196         CT_DEMOD_STEP_6,
 197         CT_DEMOD_STEP_7,
 198         CT_DEMOD_STEP_8,
 199         CT_DEMOD_STEP_9,
 200         CT_DEMOD_STEP_10,
 201         CT_DEMOD_SEARCH_NEXT = 41,
 202         CT_DEMOD_STEP_LOCKED,
 203         CT_DEMOD_STOP,
 204
 205         CT_DONE = 100,
 206         CT_SHUTDOWN,
 207
 208 };
 209
 210 struct dvb_frontend_parametersContext {
 211 #define CHANNEL_STATUS_PARAMETERS_UNKNOWN   0x01
 212 #define CHANNEL_STATUS_PARAMETERS_SET       0x02
 213         u8 status;
 214         u32 tune_time_estimation[2];
 215         s32 tps_available;
 216         u16 tps[9];
 217 };
 218
 219 #define FE_STATUS_TUNE_FAILED          0
 220 #define FE_STATUS_TUNE_TIMED_OUT      -1
 221 #define FE_STATUS_TUNE_TIME_TOO_SHORT -2
 222 #define FE_STATUS_TUNE_PENDING        -3
 223 #define FE_STATUS_STD_SUCCESS         -4
 224 #define FE_STATUS_FFT_SUCCESS         -5
 225 #define FE_STATUS_DEMOD_SUCCESS       -6
 226 #define FE_STATUS_LOCKED              -7
 227 #define FE_STATUS_DATA_LOCKED         -8
 228
 229 #define FE_CALLBACK_TIME_NEVER 0xffffffff
 230
 231 #define ABS(x) ((x < 0) ? (-x) : (x))
 232
 233 #define DATA_BUS_ACCESS_MODE_8BIT                 0x01
 234 #define DATA_BUS_ACCESS_MODE_16BIT                0x02
 235 #define DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT 0x10
 236
 237 struct dibGPIOFunction {
 238 #define BOARD_GPIO_COMPONENT_BUS_ADAPTER 1
 239 #define BOARD_GPIO_COMPONENT_DEMOD       2
 240         u8 component;
 241
 242 #define BOARD_GPIO_FUNCTION_BOARD_ON      1
 243 #define BOARD_GPIO_FUNCTION_BOARD_OFF     2
 244 #define BOARD_GPIO_FUNCTION_COMPONENT_ON  3
 245 #define BOARD_GPIO_FUNCTION_COMPONENT_OFF 4
 246 #define BOARD_GPIO_FUNCTION_SUBBAND_PWM   5
 247 #define BOARD_GPIO_FUNCTION_SUBBAND_GPIO   6
 248         u8 function;
 249
 250 /* mask, direction and value are used specify which GPIO to change GPIO0
 251  * is LSB and possible GPIO31 is MSB.  The same bit-position as in the
 252  * mask is used for the direction and the value. Direction == 1 is OUT,
 253  * 0 == IN. For direction "OUT" value is either 1 or 0, for direction IN
 254  * value has no meaning.
 255  *
 256  * In case of BOARD_GPIO_FUNCTION_PWM mask is giving the GPIO to be
 257  * used to do the PWM. Direction gives the PWModulator to be used.
 258  * Value gives the PWM value in device-dependent scale.
 259  */
 260         u32 mask;
 261         u32 direction;
 262         u32 value;
 263 };
 264
 265 #define MAX_NB_SUBBANDS   8
 266 struct dibSubbandSelection {
 267         u8  size; /* Actual number of subbands. */
 268         struct {
 269                 u16 f_mhz;
 270                 struct dibGPIOFunction gpio;
 271         } subband[MAX_NB_SUBBANDS];
 272 };
 273
 274 #define DEMOD_TIMF_SET    0x00
 275 #define DEMOD_TIMF_GET    0x01
 276 #define DEMOD_TIMF_UPDATE 0x02
 277
 278 #endif