2 * pata_efar.c - EFAR PIIX clone controller driver
4 * (C) 2005 Red Hat <alan@redhat.com>
6 * Some parts based on ata_piix.c by Jeff Garzik and others.
8 * The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later
9 * Intel ICH controllers the EFAR widened the UDMA mode register bits
10 * and doesn't require the funky clock selection.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 #include <linux/init.h>
17 #include <linux/blkdev.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <scsi/scsi_host.h>
21 #include <linux/libata.h>
22 #include <linux/ata.h>
24 #define DRV_NAME "pata_efar"
25 #define DRV_VERSION "0.4.4"
28 * efar_pre_reset - Enable bits
31 * Perform cable detection for the EFAR ATA interface. This is
32 * different to the PIIX arrangement
35 static int efar_pre_reset(struct ata_port
*ap
)
37 static const struct pci_bits efar_enable_bits
[] = {
38 { 0x41U
, 1U, 0x80UL
, 0x80UL
}, /* port 0 */
39 { 0x43U
, 1U, 0x80UL
, 0x80UL
}, /* port 1 */
41 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
43 if (!pci_test_config_bits(pdev
, &efar_enable_bits
[ap
->port_no
]))
46 return ata_std_prereset(ap
);
50 * efar_probe_reset - Probe specified port on PATA host controller
54 * None (inherited from caller).
57 static void efar_error_handler(struct ata_port
*ap
)
59 ata_bmdma_drive_eh(ap
, efar_pre_reset
, ata_std_softreset
, NULL
, ata_std_postreset
);
63 * efar_cable_detect - check for 40/80 pin
66 * Perform cable detection for the EFAR ATA interface. This is
67 * different to the PIIX arrangement
70 static int efar_cable_detect(struct ata_port
*ap
)
72 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
75 pci_read_config_byte(pdev
, 0x47, &tmp
);
76 if (tmp
& (2 >> ap
->port_no
))
77 return ATA_CBL_PATA40
;
78 return ATA_CBL_PATA80
;
82 * efar_set_piomode - Initialize host controller PATA PIO timings
83 * @ap: Port whose timings we are configuring
86 * Set PIO mode for device, in host controller PCI config space.
89 * None (inherited from caller).
92 static void efar_set_piomode (struct ata_port
*ap
, struct ata_device
*adev
)
94 unsigned int pio
= adev
->pio_mode
- XFER_PIO_0
;
95 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
96 unsigned int idetm_port
= ap
->port_no
? 0x42 : 0x40;
101 * See Intel Document 298600-004 for the timing programing rules
102 * for PIIX/ICH. The EFAR is a clone so very similar
105 static const /* ISP RTC */
106 u8 timings
[][2] = { { 0, 0 },
113 control
|= 1; /* TIME1 enable */
114 if (ata_pio_need_iordy(adev
)) /* PIO 3/4 require IORDY */
115 control
|= 2; /* IE enable */
116 /* Intel specifies that the PPE functionality is for disk only */
117 if (adev
->class == ATA_DEV_ATA
)
118 control
|= 4; /* PPE enable */
120 pci_read_config_word(dev
, idetm_port
, &idetm_data
);
122 /* Enable PPE, IE and TIME as appropriate */
124 if (adev
->devno
== 0) {
125 idetm_data
&= 0xCCF0;
126 idetm_data
|= control
;
127 idetm_data
|= (timings
[pio
][0] << 12) |
128 (timings
[pio
][1] << 8);
130 int shift
= 4 * ap
->port_no
;
133 idetm_data
&= 0xCC0F;
134 idetm_data
|= (control
<< 4);
136 /* Slave timing in seperate register */
137 pci_read_config_byte(dev
, 0x44, &slave_data
);
138 slave_data
&= 0x0F << shift
;
139 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1]) << shift
;
140 pci_write_config_byte(dev
, 0x44, slave_data
);
143 idetm_data
|= 0x4000; /* Ensure SITRE is enabled */
144 pci_write_config_word(dev
, idetm_port
, idetm_data
);
148 * efar_set_dmamode - Initialize host controller PATA DMA timings
149 * @ap: Port whose timings we are configuring
150 * @adev: Device to program
152 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
155 * None (inherited from caller).
158 static void efar_set_dmamode (struct ata_port
*ap
, struct ata_device
*adev
)
160 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
161 u8 master_port
= ap
->port_no
? 0x42 : 0x40;
163 u8 speed
= adev
->dma_mode
;
164 int devid
= adev
->devno
+ 2 * ap
->port_no
;
167 static const /* ISP RTC */
168 u8 timings
[][2] = { { 0, 0 },
174 pci_read_config_word(dev
, master_port
, &master_data
);
175 pci_read_config_byte(dev
, 0x48, &udma_enable
);
177 if (speed
>= XFER_UDMA_0
) {
178 unsigned int udma
= adev
->dma_mode
- XFER_UDMA_0
;
181 udma_enable
|= (1 << devid
);
183 /* Load the UDMA mode number */
184 pci_read_config_word(dev
, 0x4A, &udma_timing
);
185 udma_timing
&= ~(7 << (4 * devid
));
186 udma_timing
|= udma
<< (4 * devid
);
187 pci_write_config_word(dev
, 0x4A, udma_timing
);
190 * MWDMA is driven by the PIO timings. We must also enable
191 * IORDY unconditionally along with TIME1. PPE has already
192 * been set when the PIO timing was set.
194 unsigned int mwdma
= adev
->dma_mode
- XFER_MW_DMA_0
;
195 unsigned int control
;
197 const unsigned int needed_pio
[3] = {
198 XFER_PIO_0
, XFER_PIO_3
, XFER_PIO_4
200 int pio
= needed_pio
[mwdma
] - XFER_PIO_0
;
202 control
= 3; /* IORDY|TIME1 */
204 /* If the drive MWDMA is faster than it can do PIO then
205 we must force PIO into PIO0 */
207 if (adev
->pio_mode
< needed_pio
[mwdma
])
208 /* Enable DMA timing only */
209 control
|= 8; /* PIO cycles in PIO0 */
211 if (adev
->devno
) { /* Slave */
212 master_data
&= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
213 master_data
|= control
<< 4;
214 pci_read_config_byte(dev
, 0x44, &slave_data
);
215 slave_data
&= (0x0F + 0xE1 * ap
->port_no
);
216 /* Load the matching timing */
217 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1]) << (ap
->port_no
? 4 : 0);
218 pci_write_config_byte(dev
, 0x44, slave_data
);
219 } else { /* Master */
220 master_data
&= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
221 and master timing bits */
222 master_data
|= control
;
224 (timings
[pio
][0] << 12) |
225 (timings
[pio
][1] << 8);
227 udma_enable
&= ~(1 << devid
);
228 pci_write_config_word(dev
, master_port
, master_data
);
230 pci_write_config_byte(dev
, 0x48, udma_enable
);
233 static struct scsi_host_template efar_sht
= {
234 .module
= THIS_MODULE
,
236 .ioctl
= ata_scsi_ioctl
,
237 .queuecommand
= ata_scsi_queuecmd
,
238 .can_queue
= ATA_DEF_QUEUE
,
239 .this_id
= ATA_SHT_THIS_ID
,
240 .sg_tablesize
= LIBATA_MAX_PRD
,
241 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
242 .emulated
= ATA_SHT_EMULATED
,
243 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
244 .proc_name
= DRV_NAME
,
245 .dma_boundary
= ATA_DMA_BOUNDARY
,
246 .slave_configure
= ata_scsi_slave_config
,
247 .slave_destroy
= ata_scsi_slave_destroy
,
248 .bios_param
= ata_std_bios_param
,
250 .resume
= ata_scsi_device_resume
,
251 .suspend
= ata_scsi_device_suspend
,
255 static const struct ata_port_operations efar_ops
= {
256 .port_disable
= ata_port_disable
,
257 .set_piomode
= efar_set_piomode
,
258 .set_dmamode
= efar_set_dmamode
,
259 .mode_filter
= ata_pci_default_filter
,
261 .tf_load
= ata_tf_load
,
262 .tf_read
= ata_tf_read
,
263 .check_status
= ata_check_status
,
264 .exec_command
= ata_exec_command
,
265 .dev_select
= ata_std_dev_select
,
267 .freeze
= ata_bmdma_freeze
,
268 .thaw
= ata_bmdma_thaw
,
269 .error_handler
= efar_error_handler
,
270 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
271 .cable_detect
= efar_cable_detect
,
273 .bmdma_setup
= ata_bmdma_setup
,
274 .bmdma_start
= ata_bmdma_start
,
275 .bmdma_stop
= ata_bmdma_stop
,
276 .bmdma_status
= ata_bmdma_status
,
277 .qc_prep
= ata_qc_prep
,
278 .qc_issue
= ata_qc_issue_prot
,
279 .data_xfer
= ata_data_xfer
,
281 .irq_handler
= ata_interrupt
,
282 .irq_clear
= ata_bmdma_irq_clear
,
283 .irq_on
= ata_irq_on
,
284 .irq_ack
= ata_irq_ack
,
286 .port_start
= ata_port_start
,
291 * efar_init_one - Register EFAR ATA PCI device with kernel services
292 * @pdev: PCI device to register
293 * @ent: Entry in efar_pci_tbl matching with @pdev
295 * Called from kernel PCI layer.
298 * Inherited from PCI layer (may sleep).
301 * Zero on success, or -ERRNO value.
304 static int efar_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
306 static int printed_version
;
307 static struct ata_port_info info
= {
309 .flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_SRST
,
310 .pio_mask
= 0x1f, /* pio0-4 */
311 .mwdma_mask
= 0x07, /* mwdma1-2 */
312 .udma_mask
= 0x0f, /* UDMA 66 */
313 .port_ops
= &efar_ops
,
315 static struct ata_port_info
*port_info
[2] = { &info
, &info
};
317 if (!printed_version
++)
318 dev_printk(KERN_DEBUG
, &pdev
->dev
,
319 "version " DRV_VERSION
"\n");
321 return ata_pci_init_one(pdev
, port_info
, 2);
324 static const struct pci_device_id efar_pci_tbl
[] = {
325 { PCI_VDEVICE(EFAR
, 0x9130), },
327 { } /* terminate list */
330 static struct pci_driver efar_pci_driver
= {
332 .id_table
= efar_pci_tbl
,
333 .probe
= efar_init_one
,
334 .remove
= ata_pci_remove_one
,
336 .suspend
= ata_pci_device_suspend
,
337 .resume
= ata_pci_device_resume
,
341 static int __init
efar_init(void)
343 return pci_register_driver(&efar_pci_driver
);
346 static void __exit
efar_exit(void)
348 pci_unregister_driver(&efar_pci_driver
);
351 module_init(efar_init
);
352 module_exit(efar_exit
);
354 MODULE_AUTHOR("Alan Cox");
355 MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones");
356 MODULE_LICENSE("GPL");
357 MODULE_DEVICE_TABLE(pci
, efar_pci_tbl
);
358 MODULE_VERSION(DRV_VERSION
);