?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[ARM] 5605/1: Fix ep93xx gpio.c headers
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / mach-realview / core.c
blob9ea9c05093cd47afed1d6798d5a2eeb9d9333f43
1 /*
2 * linux/arch/arm/mach-realview/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/amba/bus.h>
27 #include <linux/amba/clcd.h>
28 #include <linux/clocksource.h>
29 #include <linux/clockchips.h>
30 #include <linux/io.h>
31 #include <linux/smsc911x.h>
32 #include <linux/ata_platform.h>
33
34 #include <asm/clkdev.h>
35 #include <asm/system.h>
36 #include <mach/hardware.h>
37 #include <asm/irq.h>
38 #include <asm/leds.h>
39 #include <asm/mach-types.h>
40 #include <asm/hardware/arm_timer.h>
41 #include <asm/hardware/icst307.h>
42
43 #include <asm/mach/arch.h>
44 #include <asm/mach/flash.h>
45 #include <asm/mach/irq.h>
46 #include <asm/mach/map.h>
47 #include <asm/mach/mmc.h>
48
49 #include <asm/hardware/gic.h>
50
51 #include <mach/platform.h>
52 #include <mach/irqs.h>
53
54 #include "core.h"
55 #include "clock.h"
56
57 #define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
58
59 /* used by entry-macro.S and platsmp.c */
60 void __iomem *gic_cpu_base_addr;
61
62 /*
63 * This is the RealView sched_clock implementation. This has
64 * a resolution of 41.7ns, and a maximum value of about 179s.
65 */
66 unsigned long long sched_clock(void)
67 {
68 unsigned long long v;
69
70 v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
71 do_div(v, 3);
72
73 return v;
74 }
75
76
77 #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
78
79 static int realview_flash_init(void)
80 {
81 u32 val;
82
83 val = __raw_readl(REALVIEW_FLASHCTRL);
84 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
85 __raw_writel(val, REALVIEW_FLASHCTRL);
86
87 return 0;
88 }
89
90 static void realview_flash_exit(void)
91 {
92 u32 val;
93
94 val = __raw_readl(REALVIEW_FLASHCTRL);
95 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
96 __raw_writel(val, REALVIEW_FLASHCTRL);
97 }
98
99 static void realview_flash_set_vpp(int on)
100 {
101 u32 val;
102
103 val = __raw_readl(REALVIEW_FLASHCTRL);
104 if (on)
105 val |= REALVIEW_FLASHPROG_FLVPPEN;
106 else
107 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
108 __raw_writel(val, REALVIEW_FLASHCTRL);
109 }
110
111 static struct flash_platform_data realview_flash_data = {
112 .map_name = "cfi_probe",
113 .width = 4,
114 .init = realview_flash_init,
115 .exit = realview_flash_exit,
116 .set_vpp = realview_flash_set_vpp,
117 };
118
119 struct platform_device realview_flash_device = {
120 .name = "armflash",
121 .id = 0,
122 .dev = {
123 .platform_data = &realview_flash_data,
124 },
125 };
126
127 int realview_flash_register(struct resource *res, u32 num)
128 {
129 realview_flash_device.resource = res;
130 realview_flash_device.num_resources = num;
131 return platform_device_register(&realview_flash_device);
132 }
133
134 static struct smsc911x_platform_config smsc911x_config = {
135 .flags = SMSC911X_USE_32BIT,
136 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
137 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
138 .phy_interface = PHY_INTERFACE_MODE_MII,
139 };
140
141 static struct platform_device realview_eth_device = {
142 .name = "smsc911x",
143 .id = 0,
144 .num_resources = 2,
145 };
146
147 int realview_eth_register(const char *name, struct resource *res)
148 {
149 if (name)
150 realview_eth_device.name = name;
151 realview_eth_device.resource = res;
152 if (strcmp(realview_eth_device.name, "smsc911x") == 0)
153 realview_eth_device.dev.platform_data = &smsc911x_config;
154
155 return platform_device_register(&realview_eth_device);
156 }
157
158 struct platform_device realview_usb_device = {
159 .name = "isp1760",
160 .num_resources = 2,
161 };
162
163 int realview_usb_register(struct resource *res)
164 {
165 realview_usb_device.resource = res;
166 return platform_device_register(&realview_usb_device);
167 }
168
169 static struct pata_platform_info pata_platform_data = {
170 .ioport_shift = 1,
171 };
172
173 static struct resource pata_resources[] = {
174 [0] = {
175 .start = REALVIEW_CF_BASE,
176 .end = REALVIEW_CF_BASE + 0xff,
177 .flags = IORESOURCE_MEM,
178 },
179 [1] = {
180 .start = REALVIEW_CF_BASE + 0x100,
181 .end = REALVIEW_CF_BASE + SZ_4K - 1,
182 .flags = IORESOURCE_MEM,
183 },
184 };
185
186 struct platform_device realview_cf_device = {
187 .name = "pata_platform",
188 .id = -1,
189 .num_resources = ARRAY_SIZE(pata_resources),
190 .resource = pata_resources,
191 .dev = {
192 .platform_data = &pata_platform_data,
193 },
194 };
195
196 static struct resource realview_i2c_resource = {
197 .start = REALVIEW_I2C_BASE,
198 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
199 .flags = IORESOURCE_MEM,
200 };
201
202 struct platform_device realview_i2c_device = {
203 .name = "versatile-i2c",
204 .id = 0,
205 .num_resources = 1,
206 .resource = &realview_i2c_resource,
207 };
208
209 static struct i2c_board_info realview_i2c_board_info[] = {
210 {
211 I2C_BOARD_INFO("rtc-ds1307", 0xd0 >> 1),
212 .type = "ds1338",
213 },
214 };
215
216 static int __init realview_i2c_init(void)
217 {
218 return i2c_register_board_info(0, realview_i2c_board_info,
219 ARRAY_SIZE(realview_i2c_board_info));
220 }
221 arch_initcall(realview_i2c_init);
222
223 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
224
225 static unsigned int realview_mmc_status(struct device *dev)
226 {
227 struct amba_device *adev = container_of(dev, struct amba_device, dev);
228 u32 mask;
229
230 if (adev->res.start == REALVIEW_MMCI0_BASE)
231 mask = 1;
232 else
233 mask = 2;
234
235 return readl(REALVIEW_SYSMCI) & mask;
236 }
237
238 struct mmc_platform_data realview_mmc0_plat_data = {
239 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
240 .status = realview_mmc_status,
241 };
242
243 struct mmc_platform_data realview_mmc1_plat_data = {
244 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
245 .status = realview_mmc_status,
246 };
247
248 /*
249 * Clock handling
250 */
251 static const struct icst307_params realview_oscvco_params = {
252 .ref = 24000,
253 .vco_max = 200000,
254 .vd_min = 4 + 8,
255 .vd_max = 511 + 8,
256 .rd_min = 1 + 2,
257 .rd_max = 127 + 2,
258 };
259
260 static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
261 {
262 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
263 void __iomem *sys_osc;
264 u32 val;
265
266 if (machine_is_realview_pb1176())
267 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
268 else
269 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
270
271 val = readl(sys_osc) & ~0x7ffff;
272 val |= vco.v | (vco.r << 9) | (vco.s << 16);
273
274 writel(0xa05f, sys_lock);
275 writel(val, sys_osc);
276 writel(0, sys_lock);
277 }
278
279 static struct clk oscvco_clk = {
280 .params = &realview_oscvco_params,
281 .setvco = realview_oscvco_set,
282 };
283
284 /*
285 * These are fixed clocks.
286 */
287 static struct clk ref24_clk = {
288 .rate = 24000000,
289 };
290
291 static struct clk_lookup lookups[] = {
292 { /* UART0 */
293 .dev_id = "dev:f1",
294 .clk = &ref24_clk,
295 }, { /* UART1 */
296 .dev_id = "dev:f2",
297 .clk = &ref24_clk,
298 }, { /* UART2 */
299 .dev_id = "dev:f3",
300 .clk = &ref24_clk,
301 }, { /* UART3 */
302 .dev_id = "fpga:09",
303 .clk = &ref24_clk,
304 }, { /* KMI0 */
305 .dev_id = "fpga:06",
306 .clk = &ref24_clk,
307 }, { /* KMI1 */
308 .dev_id = "fpga:07",
309 .clk = &ref24_clk,
310 }, { /* MMC0 */
311 .dev_id = "fpga:05",
312 .clk = &ref24_clk,
313 }, { /* EB:CLCD */
314 .dev_id = "dev:20",
315 .clk = &oscvco_clk,
316 }, { /* PB:CLCD */
317 .dev_id = "issp:20",
318 .clk = &oscvco_clk,
319 }
320 };
321
322 static int __init clk_init(void)
323 {
324 int i;
325
326 for (i = 0; i < ARRAY_SIZE(lookups); i++)
327 clkdev_add(&lookups[i]);
328 return 0;
329 }
330 arch_initcall(clk_init);
331
332 /*
333 * CLCD support.
334 */
335 #define SYS_CLCD_NLCDIOON (1 << 2)
336 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
337 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
338 #define SYS_CLCD_ID_MASK (0x1f << 8)
339 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
340 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
341 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
342 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
343 #define SYS_CLCD_ID_VGA (0x1f << 8)
344
345 static struct clcd_panel vga = {
346 .mode = {
347 .name = "VGA",
348 .refresh = 60,
349 .xres = 640,
350 .yres = 480,
351 .pixclock = 39721,
352 .left_margin = 40,
353 .right_margin = 24,
354 .upper_margin = 32,
355 .lower_margin = 11,
356 .hsync_len = 96,
357 .vsync_len = 2,
358 .sync = 0,
359 .vmode = FB_VMODE_NONINTERLACED,
360 },
361 .width = -1,
362 .height = -1,
363 .tim2 = TIM2_BCD | TIM2_IPC,
364 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
365 .bpp = 16,
366 };
367
368 static struct clcd_panel xvga = {
369 .mode = {
370 .name = "XVGA",
371 .refresh = 60,
372 .xres = 1024,
373 .yres = 768,
374 .pixclock = 15748,
375 .left_margin = 152,
376 .right_margin = 48,
377 .upper_margin = 23,
378 .lower_margin = 3,
379 .hsync_len = 104,
380 .vsync_len = 4,
381 .sync = 0,
382 .vmode = FB_VMODE_NONINTERLACED,
383 },
384 .width = -1,
385 .height = -1,
386 .tim2 = TIM2_BCD | TIM2_IPC,
387 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
388 .bpp = 16,
389 };
390
391 static struct clcd_panel sanyo_3_8_in = {
392 .mode = {
393 .name = "Sanyo QVGA",
394 .refresh = 116,
395 .xres = 320,
396 .yres = 240,
397 .pixclock = 100000,
398 .left_margin = 6,
399 .right_margin = 6,
400 .upper_margin = 5,
401 .lower_margin = 5,
402 .hsync_len = 6,
403 .vsync_len = 6,
404 .sync = 0,
405 .vmode = FB_VMODE_NONINTERLACED,
406 },
407 .width = -1,
408 .height = -1,
409 .tim2 = TIM2_BCD,
410 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
411 .bpp = 16,
412 };
413
414 static struct clcd_panel sanyo_2_5_in = {
415 .mode = {
416 .name = "Sanyo QVGA Portrait",
417 .refresh = 116,
418 .xres = 240,
419 .yres = 320,
420 .pixclock = 100000,
421 .left_margin = 20,
422 .right_margin = 10,
423 .upper_margin = 2,
424 .lower_margin = 2,
425 .hsync_len = 10,
426 .vsync_len = 2,
427 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
428 .vmode = FB_VMODE_NONINTERLACED,
429 },
430 .width = -1,
431 .height = -1,
432 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
433 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
434 .bpp = 16,
435 };
436
437 static struct clcd_panel epson_2_2_in = {
438 .mode = {
439 .name = "Epson QCIF",
440 .refresh = 390,
441 .xres = 176,
442 .yres = 220,
443 .pixclock = 62500,
444 .left_margin = 3,
445 .right_margin = 2,
446 .upper_margin = 1,
447 .lower_margin = 0,
448 .hsync_len = 3,
449 .vsync_len = 2,
450 .sync = 0,
451 .vmode = FB_VMODE_NONINTERLACED,
452 },
453 .width = -1,
454 .height = -1,
455 .tim2 = TIM2_BCD | TIM2_IPC,
456 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
457 .bpp = 16,
458 };
459
460 /*
461 * Detect which LCD panel is connected, and return the appropriate
462 * clcd_panel structure. Note: we do not have any information on
463 * the required timings for the 8.4in panel, so we presently assume
464 * VGA timings.
465 */
466 static struct clcd_panel *realview_clcd_panel(void)
467 {
468 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
469 struct clcd_panel *vga_panel;
470 struct clcd_panel *panel;
471 u32 val;
472
473 if (machine_is_realview_eb())
474 vga_panel = &vga;
475 else
476 vga_panel = &xvga;
477
478 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
479 if (val == SYS_CLCD_ID_SANYO_3_8)
480 panel = &sanyo_3_8_in;
481 else if (val == SYS_CLCD_ID_SANYO_2_5)
482 panel = &sanyo_2_5_in;
483 else if (val == SYS_CLCD_ID_EPSON_2_2)
484 panel = &epson_2_2_in;
485 else if (val == SYS_CLCD_ID_VGA)
486 panel = vga_panel;
487 else {
488 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
489 val);
490 panel = vga_panel;
491 }
492
493 return panel;
494 }
495
496 /*
497 * Disable all display connectors on the interface module.
498 */
499 static void realview_clcd_disable(struct clcd_fb *fb)
500 {
501 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
502 u32 val;
503
504 val = readl(sys_clcd);
505 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
506 writel(val, sys_clcd);
507 }
508
509 /*
510 * Enable the relevant connector on the interface module.
511 */
512 static void realview_clcd_enable(struct clcd_fb *fb)
513 {
514 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
515 u32 val;
516
517 /*
518 * Enable the PSUs
519 */
520 val = readl(sys_clcd);
521 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
522 writel(val, sys_clcd);
523 }
524
525 static int realview_clcd_setup(struct clcd_fb *fb)
526 {
527 unsigned long framesize;
528 dma_addr_t dma;
529
530 if (machine_is_realview_eb())
531 /* VGA, 16bpp */
532 framesize = 640 * 480 * 2;
533 else
534 /* XVGA, 16bpp */
535 framesize = 1024 * 768 * 2;
536
537 fb->panel = realview_clcd_panel();
538
539 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
540 &dma, GFP_KERNEL);
541 if (!fb->fb.screen_base) {
542 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
543 return -ENOMEM;
544 }
545
546 fb->fb.fix.smem_start = dma;
547 fb->fb.fix.smem_len = framesize;
548
549 return 0;
550 }
551
552 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
553 {
554 return dma_mmap_writecombine(&fb->dev->dev, vma,
555 fb->fb.screen_base,
556 fb->fb.fix.smem_start,
557 fb->fb.fix.smem_len);
558 }
559
560 static void realview_clcd_remove(struct clcd_fb *fb)
561 {
562 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
563 fb->fb.screen_base, fb->fb.fix.smem_start);
564 }
565
566 struct clcd_board clcd_plat_data = {
567 .name = "RealView",
568 .check = clcdfb_check,
569 .decode = clcdfb_decode,
570 .disable = realview_clcd_disable,
571 .enable = realview_clcd_enable,
572 .setup = realview_clcd_setup,
573 .mmap = realview_clcd_mmap,
574 .remove = realview_clcd_remove,
575 };
576
577 #ifdef CONFIG_LEDS
578 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
579
580 void realview_leds_event(led_event_t ledevt)
581 {
582 unsigned long flags;
583 u32 val;
584 u32 led = 1 << smp_processor_id();
585
586 local_irq_save(flags);
587 val = readl(VA_LEDS_BASE);
588
589 switch (ledevt) {
590 case led_idle_start:
591 val = val & ~led;
592 break;
593
594 case led_idle_end:
595 val = val | led;
596 break;
597
598 case led_timer:
599 val = val ^ REALVIEW_SYS_LED7;
600 break;
601
602 case led_halted:
603 val = 0;
604 break;
605
606 default:
607 break;
608 }
609
610 writel(val, VA_LEDS_BASE);
611 local_irq_restore(flags);
612 }
613 #endif /* CONFIG_LEDS */
614
615 /*
616 * Where is the timer (VA)?
617 */
618 void __iomem *timer0_va_base;
619 void __iomem *timer1_va_base;
620 void __iomem *timer2_va_base;
621 void __iomem *timer3_va_base;
622
623 /*
624 * How long is the timer interval?
625 */
626 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
627 #if TIMER_INTERVAL >= 0x100000
628 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
629 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
630 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
631 #elif TIMER_INTERVAL >= 0x10000
632 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
633 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
634 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
635 #else
636 #define TIMER_RELOAD (TIMER_INTERVAL)
637 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
638 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
639 #endif
640
641 static void timer_set_mode(enum clock_event_mode mode,
642 struct clock_event_device *clk)
643 {
644 unsigned long ctrl;
645
646 switch(mode) {
647 case CLOCK_EVT_MODE_PERIODIC:
648 writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
649
650 ctrl = TIMER_CTRL_PERIODIC;
651 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
652 break;
653 case CLOCK_EVT_MODE_ONESHOT:
654 /* period set, and timer enabled in 'next_event' hook */
655 ctrl = TIMER_CTRL_ONESHOT;
656 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
657 break;
658 case CLOCK_EVT_MODE_UNUSED:
659 case CLOCK_EVT_MODE_SHUTDOWN:
660 default:
661 ctrl = 0;
662 }
663
664 writel(ctrl, timer0_va_base + TIMER_CTRL);
665 }
666
667 static int timer_set_next_event(unsigned long evt,
668 struct clock_event_device *unused)
669 {
670 unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
671
672 writel(evt, timer0_va_base + TIMER_LOAD);
673 writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
674
675 return 0;
676 }
677
678 static struct clock_event_device timer0_clockevent = {
679 .name = "timer0",
680 .shift = 32,
681 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
682 .set_mode = timer_set_mode,
683 .set_next_event = timer_set_next_event,
684 .rating = 300,
685 .cpumask = cpu_all_mask,
686 };
687
688 static void __init realview_clockevents_init(unsigned int timer_irq)
689 {
690 timer0_clockevent.irq = timer_irq;
691 timer0_clockevent.mult =
692 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
693 timer0_clockevent.max_delta_ns =
694 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
695 timer0_clockevent.min_delta_ns =
696 clockevent_delta2ns(0xf, &timer0_clockevent);
697
698 clockevents_register_device(&timer0_clockevent);
699 }
700
701 /*
702 * IRQ handler for the timer
703 */
704 static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
705 {
706 struct clock_event_device *evt = &timer0_clockevent;
707
708 /* clear the interrupt */
709 writel(1, timer0_va_base + TIMER_INTCLR);
710
711 evt->event_handler(evt);
712
713 return IRQ_HANDLED;
714 }
715
716 static struct irqaction realview_timer_irq = {
717 .name = "RealView Timer Tick",
718 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
719 .handler = realview_timer_interrupt,
720 };
721
722 static cycle_t realview_get_cycles(struct clocksource *cs)
723 {
724 return ~readl(timer3_va_base + TIMER_VALUE);
725 }
726
727 static struct clocksource clocksource_realview = {
728 .name = "timer3",
729 .rating = 200,
730 .read = realview_get_cycles,
731 .mask = CLOCKSOURCE_MASK(32),
732 .shift = 20,
733 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
734 };
735
736 static void __init realview_clocksource_init(void)
737 {
738 /* setup timer 0 as free-running clocksource */
739 writel(0, timer3_va_base + TIMER_CTRL);
740 writel(0xffffffff, timer3_va_base + TIMER_LOAD);
741 writel(0xffffffff, timer3_va_base + TIMER_VALUE);
742 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
743 timer3_va_base + TIMER_CTRL);
744
745 clocksource_realview.mult =
746 clocksource_khz2mult(1000, clocksource_realview.shift);
747 clocksource_register(&clocksource_realview);
748 }
749
750 /*
751 * Set up the clock source and clock events devices
752 */
753 void __init realview_timer_init(unsigned int timer_irq)
754 {
755 u32 val;
756
757 /*
758 * set clock frequency:
759 * REALVIEW_REFCLK is 32KHz
760 * REALVIEW_TIMCLK is 1MHz
761 */
762 val = readl(__io_address(REALVIEW_SCTL_BASE));
763 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
764 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
765 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
766 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
767 __io_address(REALVIEW_SCTL_BASE));
768
769 /*
770 * Initialise to a known state (all timers off)
771 */
772 writel(0, timer0_va_base + TIMER_CTRL);
773 writel(0, timer1_va_base + TIMER_CTRL);
774 writel(0, timer2_va_base + TIMER_CTRL);
775 writel(0, timer3_va_base + TIMER_CTRL);
776
777 /*
778 * Make irqs happen for the system timer
779 */
780 setup_irq(timer_irq, &realview_timer_irq);
781
782 realview_clocksource_init();
783 realview_clockevents_init(timer_irq);
784 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree