drivers/usb/host/r8a66597.h

   1 /*
   2  * R8A66597 HCD (Host Controller Driver)
   3  *
   4  * Copyright (C) 2006-2007 Renesas Solutions Corp.
   5  * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
   6  * Portions Copyright (C) 2004-2005 David Brownell
   7  * Portions Copyright (C) 1999 Roman Weissgaerber
   8  *
   9  * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; version 2 of the License.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  23  *
  24  */
  25
  26 #ifndef __R8A66597_H__
  27 #define __R8A66597_H__
  28
  29 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) && defined(CONFIG_HAVE_CLK)
  30 #include <linux/clk.h>
  31 #endif
  32
  33 #define SYSCFG0         0x00
  34 #define SYSCFG1         0x02
  35 #define SYSSTS0         0x04
  36 #define SYSSTS1         0x06
  37 #define DVSTCTR0        0x08
  38 #define DVSTCTR1        0x0A
  39 #define TESTMODE        0x0C
  40 #define PINCFG          0x0E
  41 #define DMA0CFG         0x10
  42 #define DMA1CFG         0x12
  43 #define CFIFO           0x14
  44 #define D0FIFO          0x18
  45 #define D1FIFO          0x1C
  46 #define CFIFOSEL        0x20
  47 #define CFIFOCTR        0x22
  48 #define CFIFOSIE        0x24
  49 #define D0FIFOSEL       0x28
  50 #define D0FIFOCTR       0x2A
  51 #define D1FIFOSEL       0x2C
  52 #define D1FIFOCTR       0x2E
  53 #define INTENB0         0x30
  54 #define INTENB1         0x32
  55 #define INTENB2         0x34
  56 #define BRDYENB         0x36
  57 #define NRDYENB         0x38
  58 #define BEMPENB         0x3A
  59 #define SOFCFG          0x3C
  60 #define INTSTS0         0x40
  61 #define INTSTS1         0x42
  62 #define INTSTS2         0x44
  63 #define BRDYSTS         0x46
  64 #define NRDYSTS         0x48
  65 #define BEMPSTS         0x4A
  66 #define FRMNUM          0x4C
  67 #define UFRMNUM         0x4E
  68 #define USBADDR         0x50
  69 #define USBREQ          0x54
  70 #define USBVAL          0x56
  71 #define USBINDX         0x58
  72 #define USBLENG         0x5A
  73 #define DCPCFG          0x5C
  74 #define DCPMAXP         0x5E
  75 #define DCPCTR          0x60
  76 #define PIPESEL         0x64
  77 #define PIPECFG         0x68
  78 #define PIPEBUF         0x6A
  79 #define PIPEMAXP        0x6C
  80 #define PIPEPERI        0x6E
  81 #define PIPE1CTR        0x70
  82 #define PIPE2CTR        0x72
  83 #define PIPE3CTR        0x74
  84 #define PIPE4CTR        0x76
  85 #define PIPE5CTR        0x78
  86 #define PIPE6CTR        0x7A
  87 #define PIPE7CTR        0x7C
  88 #define PIPE8CTR        0x7E
  89 #define PIPE9CTR        0x80
  90 #define PIPE1TRE        0x90
  91 #define PIPE1TRN        0x92
  92 #define PIPE2TRE        0x94
  93 #define PIPE2TRN        0x96
  94 #define PIPE3TRE        0x98
  95 #define PIPE3TRN        0x9A
  96 #define PIPE4TRE        0x9C
  97 #define PIPE4TRN        0x9E
  98 #define PIPE5TRE        0xA0
  99 #define PIPE5TRN        0xA2
 100 #define DEVADD0         0xD0
 101 #define DEVADD1         0xD2
 102 #define DEVADD2         0xD4
 103 #define DEVADD3         0xD6
 104 #define DEVADD4         0xD8
 105 #define DEVADD5         0xDA
 106 #define DEVADD6         0xDC
 107 #define DEVADD7         0xDE
 108 #define DEVADD8         0xE0
 109 #define DEVADD9         0xE2
 110 #define DEVADDA         0xE4
 111
 112 /* System Configuration Control Register */
 113 #define XTAL            0xC000  /* b15-14: Crystal selection */
 114 #define   XTAL48         0x8000   /* 48MHz */
 115 #define   XTAL24         0x4000   /* 24MHz */
 116 #define   XTAL12         0x0000   /* 12MHz */
 117 #define XCKE            0x2000  /* b13: External clock enable */
 118 #define PLLC            0x0800  /* b11: PLL control */
 119 #define SCKE            0x0400  /* b10: USB clock enable */
 120 #define PCSDIS          0x0200  /* b9: not CS wakeup */
 121 #define LPSME           0x0100  /* b8: Low power sleep mode */
 122 #define HSE             0x0080  /* b7: Hi-speed enable */
 123 #define DCFM            0x0040  /* b6: Controller function select  */
 124 #define DRPD            0x0020  /* b5: D+/- pull down control */
 125 #define DPRPU           0x0010  /* b4: D+ pull up control */
 126 #define USBE            0x0001  /* b0: USB module operation enable */
 127
 128 /* System Configuration Status Register */
 129 #define OVCBIT          0x8000  /* b15-14: Over-current bit */
 130 #define OVCMON          0xC000  /* b15-14: Over-current monitor */
 131 #define SOFEA           0x0020  /* b5: SOF monitor */
 132 #define IDMON           0x0004  /* b3: ID-pin monitor */
 133 #define LNST            0x0003  /* b1-0: D+, D- line status */
 134 #define   SE1            0x0003   /* SE1 */
 135 #define   FS_KSTS        0x0002   /* Full-Speed K State */
 136 #define   FS_JSTS        0x0001   /* Full-Speed J State */
 137 #define   LS_JSTS        0x0002   /* Low-Speed J State */
 138 #define   LS_KSTS        0x0001   /* Low-Speed K State */
 139 #define   SE0            0x0000   /* SE0 */
 140
 141 /* Device State Control Register */
 142 #define EXTLP0          0x0400  /* b10: External port */
 143 #define VBOUT           0x0200  /* b9: VBUS output */
 144 #define WKUP            0x0100  /* b8: Remote wakeup */
 145 #define RWUPE           0x0080  /* b7: Remote wakeup sense */
 146 #define USBRST          0x0040  /* b6: USB reset enable */
 147 #define RESUME          0x0020  /* b5: Resume enable */
 148 #define UACT            0x0010  /* b4: USB bus enable */
 149 #define RHST            0x0007  /* b1-0: Reset handshake status */
 150 #define   HSPROC         0x0004   /* HS handshake is processing */
 151 #define   HSMODE         0x0003   /* Hi-Speed mode */
 152 #define   FSMODE         0x0002   /* Full-Speed mode */
 153 #define   LSMODE         0x0001   /* Low-Speed mode */
 154 #define   UNDECID        0x0000   /* Undecided */
 155
 156 /* Test Mode Register */
 157 #define UTST                    0x000F  /* b3-0: Test select */
 158 #define   H_TST_PACKET           0x000C   /* HOST TEST Packet */
 159 #define   H_TST_SE0_NAK          0x000B   /* HOST TEST SE0 NAK */
 160 #define   H_TST_K                0x000A   /* HOST TEST K */
 161 #define   H_TST_J                0x0009   /* HOST TEST J */
 162 #define   H_TST_NORMAL           0x0000   /* HOST Normal Mode */
 163 #define   P_TST_PACKET           0x0004   /* PERI TEST Packet */
 164 #define   P_TST_SE0_NAK          0x0003   /* PERI TEST SE0 NAK */
 165 #define   P_TST_K                0x0002   /* PERI TEST K */
 166 #define   P_TST_J                0x0001   /* PERI TEST J */
 167 #define   P_TST_NORMAL           0x0000   /* PERI Normal Mode */
 168
 169 /* Data Pin Configuration Register */
 170 #define LDRV                    0x8000  /* b15: Drive Current Adjust */
 171 #define   VIF1                    0x0000                /* VIF = 1.8V */
 172 #define   VIF3                    0x8000                /* VIF = 3.3V */
 173 #define INTA                    0x0001  /* b1: USB INT-pin active */
 174
 175 /* DMAx Pin Configuration Register */
 176 #define DREQA                   0x4000  /* b14: Dreq active select */
 177 #define BURST                   0x2000  /* b13: Burst mode */
 178 #define DACKA                   0x0400  /* b10: Dack active select */
 179 #define DFORM                   0x0380  /* b9-7: DMA mode select */
 180 #define   CPU_ADR_RD_WR          0x0000   /* Address + RD/WR mode (CPU bus) */
 181 #define   CPU_DACK_RD_WR         0x0100   /* DACK + RD/WR mode (CPU bus) */
 182 #define   CPU_DACK_ONLY          0x0180   /* DACK only mode (CPU bus) */
 183 #define   SPLIT_DACK_ONLY        0x0200   /* DACK only mode (SPLIT bus) */
 184 #define DENDA                   0x0040  /* b6: Dend active select */
 185 #define PKTM                    0x0020  /* b5: Packet mode */
 186 #define DENDE                   0x0010  /* b4: Dend enable */
 187 #define OBUS                    0x0004  /* b2: OUTbus mode */
 188
 189 /* CFIFO/DxFIFO Port Select Register */
 190 #define RCNT            0x8000  /* b15: Read count mode */
 191 #define REW             0x4000  /* b14: Buffer rewind */
 192 #define DCLRM           0x2000  /* b13: DMA buffer clear mode */
 193 #define DREQE           0x1000  /* b12: DREQ output enable */
 194 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
 195 #define MBW             0x0800
 196 #else
 197 #define MBW             0x0400  /* b10: Maximum bit width for FIFO access */
 198 #endif
 199 #define   MBW_8          0x0000   /*  8bit */
 200 #define   MBW_16         0x0400   /* 16bit */
 201 #define BIGEND          0x0100  /* b8: Big endian mode */
 202 #define   BYTE_LITTLE    0x0000         /* little dendian */
 203 #define   BYTE_BIG       0x0100         /* big endifan */
 204 #define ISEL            0x0020  /* b5: DCP FIFO port direction select */
 205 #define CURPIPE         0x000F  /* b2-0: PIPE select */
 206
 207 /* CFIFO/DxFIFO Port Control Register */
 208 #define BVAL            0x8000  /* b15: Buffer valid flag */
 209 #define BCLR            0x4000  /* b14: Buffer clear */
 210 #define FRDY            0x2000  /* b13: FIFO ready */
 211 #define DTLN            0x0FFF  /* b11-0: FIFO received data length */
 212
 213 /* Interrupt Enable Register 0 */
 214 #define VBSE    0x8000  /* b15: VBUS interrupt */
 215 #define RSME    0x4000  /* b14: Resume interrupt */
 216 #define SOFE    0x2000  /* b13: Frame update interrupt */
 217 #define DVSE    0x1000  /* b12: Device state transition interrupt */
 218 #define CTRE    0x0800  /* b11: Control transfer stage transition interrupt */
 219 #define BEMPE   0x0400  /* b10: Buffer empty interrupt */
 220 #define NRDYE   0x0200  /* b9: Buffer not ready interrupt */
 221 #define BRDYE   0x0100  /* b8: Buffer ready interrupt */
 222
 223 /* Interrupt Enable Register 1 */
 224 #define OVRCRE          0x8000  /* b15: Over-current interrupt */
 225 #define BCHGE           0x4000  /* b14: USB us chenge interrupt */
 226 #define DTCHE           0x1000  /* b12: Detach sense interrupt */
 227 #define ATTCHE          0x0800  /* b11: Attach sense interrupt */
 228 #define EOFERRE         0x0040  /* b6: EOF error interrupt */
 229 #define SIGNE           0x0020  /* b5: SETUP IGNORE interrupt */
 230 #define SACKE           0x0010  /* b4: SETUP ACK interrupt */
 231
 232 /* BRDY Interrupt Enable/Status Register */
 233 #define BRDY9           0x0200  /* b9: PIPE9 */
 234 #define BRDY8           0x0100  /* b8: PIPE8 */
 235 #define BRDY7           0x0080  /* b7: PIPE7 */
 236 #define BRDY6           0x0040  /* b6: PIPE6 */
 237 #define BRDY5           0x0020  /* b5: PIPE5 */
 238 #define BRDY4           0x0010  /* b4: PIPE4 */
 239 #define BRDY3           0x0008  /* b3: PIPE3 */
 240 #define BRDY2           0x0004  /* b2: PIPE2 */
 241 #define BRDY1           0x0002  /* b1: PIPE1 */
 242 #define BRDY0           0x0001  /* b1: PIPE0 */
 243
 244 /* NRDY Interrupt Enable/Status Register */
 245 #define NRDY9           0x0200  /* b9: PIPE9 */
 246 #define NRDY8           0x0100  /* b8: PIPE8 */
 247 #define NRDY7           0x0080  /* b7: PIPE7 */
 248 #define NRDY6           0x0040  /* b6: PIPE6 */
 249 #define NRDY5           0x0020  /* b5: PIPE5 */
 250 #define NRDY4           0x0010  /* b4: PIPE4 */
 251 #define NRDY3           0x0008  /* b3: PIPE3 */
 252 #define NRDY2           0x0004  /* b2: PIPE2 */
 253 #define NRDY1           0x0002  /* b1: PIPE1 */
 254 #define NRDY0           0x0001  /* b1: PIPE0 */
 255
 256 /* BEMP Interrupt Enable/Status Register */
 257 #define BEMP9           0x0200  /* b9: PIPE9 */
 258 #define BEMP8           0x0100  /* b8: PIPE8 */
 259 #define BEMP7           0x0080  /* b7: PIPE7 */
 260 #define BEMP6           0x0040  /* b6: PIPE6 */
 261 #define BEMP5           0x0020  /* b5: PIPE5 */
 262 #define BEMP4           0x0010  /* b4: PIPE4 */
 263 #define BEMP3           0x0008  /* b3: PIPE3 */
 264 #define BEMP2           0x0004  /* b2: PIPE2 */
 265 #define BEMP1           0x0002  /* b1: PIPE1 */
 266 #define BEMP0           0x0001  /* b0: PIPE0 */
 267
 268 /* SOF Pin Configuration Register */
 269 #define TRNENSEL        0x0100  /* b8: Select transaction enable period */
 270 #define BRDYM           0x0040  /* b6: BRDY clear timing */
 271 #define INTL            0x0020  /* b5: Interrupt sense select */
 272 #define EDGESTS         0x0010  /* b4:  */
 273 #define SOFMODE         0x000C  /* b3-2: SOF pin select */
 274 #define   SOF_125US      0x0008   /* SOF OUT 125us Frame Signal */
 275 #define   SOF_1MS        0x0004   /* SOF OUT 1ms Frame Signal */
 276 #define   SOF_DISABLE    0x0000   /* SOF OUT Disable */
 277
 278 /* Interrupt Status Register 0 */
 279 #define VBINT   0x8000  /* b15: VBUS interrupt */
 280 #define RESM    0x4000  /* b14: Resume interrupt */
 281 #define SOFR    0x2000  /* b13: SOF frame update interrupt */
 282 #define DVST    0x1000  /* b12: Device state transition interrupt */
 283 #define CTRT    0x0800  /* b11: Control transfer stage transition interrupt */
 284 #define BEMP    0x0400  /* b10: Buffer empty interrupt */
 285 #define NRDY    0x0200  /* b9: Buffer not ready interrupt */
 286 #define BRDY    0x0100  /* b8: Buffer ready interrupt */
 287 #define VBSTS   0x0080  /* b7: VBUS input port */
 288 #define DVSQ    0x0070  /* b6-4: Device state */
 289 #define   DS_SPD_CNFG    0x0070   /* Suspend Configured */
 290 #define   DS_SPD_ADDR    0x0060   /* Suspend Address */
 291 #define   DS_SPD_DFLT    0x0050   /* Suspend Default */
 292 #define   DS_SPD_POWR    0x0040   /* Suspend Powered */
 293 #define   DS_SUSP        0x0040   /* Suspend */
 294 #define   DS_CNFG        0x0030   /* Configured */
 295 #define   DS_ADDS        0x0020   /* Address */
 296 #define   DS_DFLT        0x0010   /* Default */
 297 #define   DS_POWR        0x0000   /* Powered */
 298 #define DVSQS           0x0030  /* b5-4: Device state */
 299 #define VALID           0x0008  /* b3: Setup packet detected flag */
 300 #define CTSQ            0x0007  /* b2-0: Control transfer stage */
 301 #define   CS_SQER        0x0006   /* Sequence error */
 302 #define   CS_WRND        0x0005   /* Control write nodata status stage */
 303 #define   CS_WRSS        0x0004   /* Control write status stage */
 304 #define   CS_WRDS        0x0003   /* Control write data stage */
 305 #define   CS_RDSS        0x0002   /* Control read status stage */
 306 #define   CS_RDDS        0x0001   /* Control read data stage */
 307 #define   CS_IDST        0x0000   /* Idle or setup stage */
 308
 309 /* Interrupt Status Register 1 */
 310 #define OVRCR           0x8000  /* b15: Over-current interrupt */
 311 #define BCHG            0x4000  /* b14: USB bus chenge interrupt */
 312 #define DTCH            0x1000  /* b12: Detach sense interrupt */
 313 #define ATTCH           0x0800  /* b11: Attach sense interrupt */
 314 #define EOFERR          0x0040  /* b6: EOF-error interrupt */
 315 #define SIGN            0x0020  /* b5: Setup ignore interrupt */
 316 #define SACK            0x0010  /* b4: Setup acknowledge interrupt */
 317
 318 /* Frame Number Register */
 319 #define OVRN            0x8000  /* b15: Overrun error */
 320 #define CRCE            0x4000  /* b14: Received data error */
 321 #define FRNM            0x07FF  /* b10-0: Frame number */
 322
 323 /* Micro Frame Number Register */
 324 #define UFRNM           0x0007  /* b2-0: Micro frame number */
 325
 326 /* Default Control Pipe Maxpacket Size Register */
 327 /* Pipe Maxpacket Size Register */
 328 #define DEVSEL  0xF000  /* b15-14: Device address select */
 329 #define MAXP    0x007F  /* b6-0: Maxpacket size of default control pipe */
 330
 331 /* Default Control Pipe Control Register */
 332 #define BSTS            0x8000  /* b15: Buffer status */
 333 #define SUREQ           0x4000  /* b14: Send USB request  */
 334 #define CSCLR           0x2000  /* b13: complete-split status clear */
 335 #define CSSTS           0x1000  /* b12: complete-split status */
 336 #define SUREQCLR        0x0800  /* b11: stop setup request */
 337 #define SQCLR           0x0100  /* b8: Sequence toggle bit clear */
 338 #define SQSET           0x0080  /* b7: Sequence toggle bit set */
 339 #define SQMON           0x0040  /* b6: Sequence toggle bit monitor */
 340 #define PBUSY           0x0020  /* b5: pipe busy */
 341 #define PINGE           0x0010  /* b4: ping enable */
 342 #define CCPL            0x0004  /* b2: Enable control transfer complete */
 343 #define PID             0x0003  /* b1-0: Response PID */
 344 #define   PID_STALL11    0x0003   /* STALL */
 345 #define   PID_STALL      0x0002   /* STALL */
 346 #define   PID_BUF        0x0001   /* BUF */
 347 #define   PID_NAK        0x0000   /* NAK */
 348
 349 /* Pipe Window Select Register */
 350 #define PIPENM          0x0007  /* b2-0: Pipe select */
 351
 352 /* Pipe Configuration Register */
 353 #define R8A66597_TYP    0xC000  /* b15-14: Transfer type */
 354 #define   R8A66597_ISO   0xC000           /* Isochronous */
 355 #define   R8A66597_INT   0x8000           /* Interrupt */
 356 #define   R8A66597_BULK  0x4000           /* Bulk */
 357 #define R8A66597_BFRE   0x0400  /* b10: Buffer ready interrupt mode select */
 358 #define R8A66597_DBLB   0x0200  /* b9: Double buffer mode select */
 359 #define R8A66597_CNTMD  0x0100  /* b8: Continuous transfer mode select */
 360 #define R8A66597_SHTNAK 0x0080  /* b7: Transfer end NAK */
 361 #define R8A66597_DIR    0x0010  /* b4: Transfer direction select */
 362 #define R8A66597_EPNUM  0x000F  /* b3-0: Eendpoint number select */
 363
 364 /* Pipe Buffer Configuration Register */
 365 #define BUFSIZE         0x7C00  /* b14-10: Pipe buffer size */
 366 #define BUFNMB          0x007F  /* b6-0: Pipe buffer number */
 367 #define PIPE0BUF        256
 368 #define PIPExBUF        64
 369
 370 /* Pipe Maxpacket Size Register */
 371 #define MXPS            0x07FF  /* b10-0: Maxpacket size */
 372
 373 /* Pipe Cycle Configuration Register */
 374 #define IFIS    0x1000  /* b12: Isochronous in-buffer flush mode select */
 375 #define IITV    0x0007  /* b2-0: Isochronous interval */
 376
 377 /* Pipex Control Register */
 378 #define BSTS    0x8000  /* b15: Buffer status */
 379 #define INBUFM  0x4000  /* b14: IN buffer monitor (Only for PIPE1 to 5) */
 380 #define CSCLR   0x2000  /* b13: complete-split status clear */
 381 #define CSSTS   0x1000  /* b12: complete-split status */
 382 #define ATREPM  0x0400  /* b10: Auto repeat mode */
 383 #define ACLRM   0x0200  /* b9: Out buffer auto clear mode */
 384 #define SQCLR   0x0100  /* b8: Sequence toggle bit clear */
 385 #define SQSET   0x0080  /* b7: Sequence toggle bit set */
 386 #define SQMON   0x0040  /* b6: Sequence toggle bit monitor */
 387 #define PBUSY   0x0020  /* b5: pipe busy */
 388 #define PID     0x0003  /* b1-0: Response PID */
 389
 390 /* PIPExTRE */
 391 #define TRENB           0x0200  /* b9: Transaction counter enable */
 392 #define TRCLR           0x0100  /* b8: Transaction counter clear */
 393
 394 /* PIPExTRN */
 395 #define TRNCNT          0xFFFF  /* b15-0: Transaction counter */
 396
 397 /* DEVADDx */
 398 #define UPPHUB          0x7800
 399 #define HUBPORT         0x0700
 400 #define USBSPD          0x00C0
 401 #define RTPORT          0x0001
 402
 403 #define R8A66597_MAX_NUM_PIPE           10
 404 #define R8A66597_BUF_BSIZE              8
 405 #define R8A66597_MAX_DEVICE             10
 406 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
 407 #define R8A66597_MAX_ROOT_HUB           1
 408 #else
 409 #define R8A66597_MAX_ROOT_HUB           2
 410 #endif
 411 #define R8A66597_MAX_SAMPLING           5
 412 #define R8A66597_RH_POLL_TIME           10
 413 #define R8A66597_MAX_DMA_CHANNEL        2
 414 #define R8A66597_PIPE_NO_DMA            R8A66597_MAX_DMA_CHANNEL
 415 #define check_bulk_or_isoc(pipenum)     ((pipenum >= 1 && pipenum <= 5))
 416 #define check_interrupt(pipenum)        ((pipenum >= 6 && pipenum <= 9))
 417 #define make_devsel(addr)               (addr << 12)
 418
 419 struct r8a66597_pipe_info {
 420         unsigned long timer_interval;
 421         u16 pipenum;
 422         u16 address;    /* R8A66597 HCD usb address */
 423         u16 epnum;
 424         u16 maxpacket;
 425         u16 type;
 426         u16 bufnum;
 427         u16 buf_bsize;
 428         u16 interval;
 429         u16 dir_in;
 430 };
 431
 432 struct r8a66597_pipe {
 433         struct r8a66597_pipe_info info;
 434
 435         unsigned long fifoaddr;
 436         unsigned long fifosel;
 437         unsigned long fifoctr;
 438         unsigned long pipectr;
 439         unsigned long pipetre;
 440         unsigned long pipetrn;
 441 };
 442
 443 struct r8a66597_td {
 444         struct r8a66597_pipe *pipe;
 445         struct urb *urb;
 446         struct list_head queue;
 447
 448         u16 type;
 449         u16 pipenum;
 450         int iso_cnt;
 451
 452         u16 address;            /* R8A66597's USB address */
 453         u16 maxpacket;
 454
 455         unsigned zero_packet:1;
 456         unsigned short_packet:1;
 457         unsigned set_address:1;
 458 };
 459
 460 struct r8a66597_device {
 461         u16     address;        /* R8A66597's USB address */
 462         u16     hub_port;
 463         u16     root_port;
 464
 465         unsigned short ep_in_toggle;
 466         unsigned short ep_out_toggle;
 467         unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
 468         unsigned char dma_map;
 469
 470         enum usb_device_state state;
 471
 472         struct usb_device *udev;
 473         int usb_address;
 474         struct list_head device_list;
 475 };
 476
 477 struct r8a66597_root_hub {
 478         u32 port;
 479         u16 old_syssts;
 480         int scount;
 481
 482         struct r8a66597_device  *dev;
 483 };
 484
 485 struct r8a66597 {
 486         spinlock_t lock;
 487         unsigned long reg;
 488 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) && defined(CONFIG_HAVE_CLK)
 489         struct clk *clk;
 490 #endif
 491         struct r8a66597_device          device0;
 492         struct r8a66597_root_hub        root_hub[R8A66597_MAX_ROOT_HUB];
 493         struct list_head                pipe_queue[R8A66597_MAX_NUM_PIPE];
 494
 495         struct timer_list rh_timer;
 496         struct timer_list td_timer[R8A66597_MAX_NUM_PIPE];
 497         struct timer_list interval_timer[R8A66597_MAX_NUM_PIPE];
 498
 499         unsigned short address_map;
 500         unsigned short timeout_map;
 501         unsigned short interval_map;
 502         unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
 503         unsigned char dma_map;
 504
 505         struct list_head child_device;
 506         unsigned long child_connect_map[4];
 507
 508         unsigned bus_suspended:1;
 509 };
 510
 511 static inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd)
 512 {
 513         return (struct r8a66597 *)(hcd->hcd_priv);
 514 }
 515
 516 static inline struct usb_hcd *r8a66597_to_hcd(struct r8a66597 *r8a66597)
 517 {
 518         return container_of((void *)r8a66597, struct usb_hcd, hcd_priv);
 519 }
 520
 521 static inline struct r8a66597_td *r8a66597_get_td(struct r8a66597 *r8a66597,
 522                                                   u16 pipenum)
 523 {
 524         if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum])))
 525                 return NULL;
 526
 527         return list_entry(r8a66597->pipe_queue[pipenum].next,
 528                           struct r8a66597_td, queue);
 529 }
 530
 531 static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
 532                                            u16 pipenum)
 533 {
 534         struct r8a66597_td *td;
 535
 536         td = r8a66597_get_td(r8a66597, pipenum);
 537         return (td ? td->urb : NULL);
 538 }
 539
 540 static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
 541 {
 542         return inw(r8a66597->reg + offset);
 543 }
 544
 545 static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
 546                                       unsigned long offset, u16 *buf,
 547                                       int len)
 548 {
 549 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
 550         unsigned long fifoaddr = r8a66597->reg + offset;
 551         unsigned long count;
 552
 553         count = len / 4;
 554         insl(fifoaddr, buf, count);
 555
 556         if (len & 0x00000003) {
 557                 unsigned long tmp = inl(fifoaddr);
 558                 memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03);
 559         }
 560 #else
 561         len = (len + 1) / 2;
 562         insw(r8a66597->reg + offset, buf, len);
 563 #endif
 564 }
 565
 566 static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
 567                                   unsigned long offset)
 568 {
 569         outw(val, r8a66597->reg + offset);
 570 }
 571
 572 static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
 573                                        unsigned long offset, u16 *buf,
 574                                        int len)
 575 {
 576         unsigned long fifoaddr = r8a66597->reg + offset;
 577 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
 578         unsigned long count;
 579         unsigned char *pb;
 580         int i;
 581
 582         count = len / 4;
 583         outsl(fifoaddr, buf, count);
 584
 585         if (len & 0x00000003) {
 586                 pb = (unsigned char *)buf + count * 4;
 587                 for (i = 0; i < (len & 0x00000003); i++) {
 588                         if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
 589                                 outb(pb[i], fifoaddr + i);
 590                         else
 591                                 outb(pb[i], fifoaddr + 3 - i);
 592                 }
 593         }
 594 #else
 595         int odd = len & 0x0001;
 596
 597         len = len / 2;
 598         outsw(fifoaddr, buf, len);
 599         if (unlikely(odd)) {
 600                 buf = &buf[len];
 601                 outb((unsigned char)*buf, fifoaddr);
 602         }
 603 #endif
 604 }
 605
 606 static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
 607                                  u16 val, u16 pat, unsigned long offset)
 608 {
 609         u16 tmp;
 610         tmp = r8a66597_read(r8a66597, offset);
 611         tmp = tmp & (~pat);
 612         tmp = tmp | val;
 613         r8a66597_write(r8a66597, tmp, offset);
 614 }
 615
 616 #define r8a66597_bclr(r8a66597, val, offset)    \
 617                         r8a66597_mdfy(r8a66597, 0, val, offset)
 618 #define r8a66597_bset(r8a66597, val, offset)    \
 619                         r8a66597_mdfy(r8a66597, val, 0, offset)
 620
 621 static inline unsigned long get_syscfg_reg(int port)
 622 {
 623         return port == 0 ? SYSCFG0 : SYSCFG1;
 624 }
 625
 626 static inline unsigned long get_syssts_reg(int port)
 627 {
 628         return port == 0 ? SYSSTS0 : SYSSTS1;
 629 }
 630
 631 static inline unsigned long get_dvstctr_reg(int port)
 632 {
 633         return port == 0 ? DVSTCTR0 : DVSTCTR1;
 634 }
 635
 636 static inline unsigned long get_dmacfg_reg(int port)
 637 {
 638         return port == 0 ? DMA0CFG : DMA1CFG;
 639 }
 640
 641 static inline unsigned long get_intenb_reg(int port)
 642 {
 643         return port == 0 ? INTENB1 : INTENB2;
 644 }
 645
 646 static inline unsigned long get_intsts_reg(int port)
 647 {
 648         return port == 0 ? INTSTS1 : INTSTS2;
 649 }
 650
 651 static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
 652 {
 653         unsigned long dvstctr_reg = get_dvstctr_reg(port);
 654
 655         return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
 656 }
 657
 658 static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
 659                                        int power)
 660 {
 661         unsigned long dvstctr_reg = get_dvstctr_reg(port);
 662
 663         if (power)
 664                 r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
 665         else
 666                 r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
 667 }
 668
 669 #define get_pipectr_addr(pipenum)       (PIPE1CTR + (pipenum - 1) * 2)
 670 #define get_pipetre_addr(pipenum)       (PIPE1TRE + (pipenum - 1) * 4)
 671 #define get_pipetrn_addr(pipenum)       (PIPE1TRN + (pipenum - 1) * 4)
 672 #define get_devadd_addr(address)        (DEVADD0 + address * 2)
 673
 674 #define enable_irq_ready(r8a66597, pipenum)     \
 675         enable_pipe_irq(r8a66597, pipenum, BRDYENB)
 676 #define disable_irq_ready(r8a66597, pipenum)    \
 677         disable_pipe_irq(r8a66597, pipenum, BRDYENB)
 678 #define enable_irq_empty(r8a66597, pipenum)     \
 679         enable_pipe_irq(r8a66597, pipenum, BEMPENB)
 680 #define disable_irq_empty(r8a66597, pipenum)    \
 681         disable_pipe_irq(r8a66597, pipenum, BEMPENB)
 682 #define enable_irq_nrdy(r8a66597, pipenum)      \
 683         enable_pipe_irq(r8a66597, pipenum, NRDYENB)
 684 #define disable_irq_nrdy(r8a66597, pipenum)     \
 685         disable_pipe_irq(r8a66597, pipenum, NRDYENB)
 686
 687 #endif  /* __R8A66597_H__ */
 688