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drm/radeon/kms: fix support for DDC on dp bridges
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / radeon_encoders.c
blob8e058f1f46d63935baa33ba584fd412b4925ac65
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 extern int atom_debug;
33
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
39 {
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
45 int count;
46
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
49 return index_mask;
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
52 return index_mask;
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
55 return index_mask;
56
57 count = -1;
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
60 count++;
61
62 if (clone_encoder == encoder)
63 continue;
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
65 continue;
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
67 continue;
68 else
69 index_mask |= (1 << count);
70 }
71 return index_mask;
72 }
73
74 void radeon_setup_encoder_clones(struct drm_device *dev)
75 {
76 struct drm_encoder *encoder;
77
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
80 }
81 }
82
83 uint32_t
84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
85 {
86 struct radeon_device *rdev = dev->dev_private;
87 uint32_t ret = 0;
88
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
95 switch (dac) {
96 case 1: /* dac a */
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
103 else
104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
105 break;
106 case 2: /* dac b */
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
109 else {
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
112 else*/
113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
114 }
115 break;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
119 else
120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
121 break;
122 }
123 break;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
127 else
128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
129 break;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
137 else
138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
139 break;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
148 else
149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
150 break;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
153 break;
154 }
155
156 return ret;
157 }
158
159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
160 {
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
174 return true;
175 default:
176 return false;
177 }
178 }
179
180 void
181 radeon_link_encoder_connector(struct drm_device *dev)
182 {
183 struct drm_connector *connector;
184 struct radeon_connector *radeon_connector;
185 struct drm_encoder *encoder;
186 struct radeon_encoder *radeon_encoder;
187
188 /* walk the list and link encoders to connectors */
189 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
190 radeon_connector = to_radeon_connector(connector);
191 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
192 radeon_encoder = to_radeon_encoder(encoder);
193 if (radeon_encoder->devices & radeon_connector->devices)
194 drm_mode_connector_attach_encoder(connector, encoder);
195 }
196 }
197 }
198
199 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
200 {
201 struct drm_device *dev = encoder->dev;
202 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
203 struct drm_connector *connector;
204
205 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
206 if (connector->encoder == encoder) {
207 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
208 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
209 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
210 radeon_encoder->active_device, radeon_encoder->devices,
211 radeon_connector->devices, encoder->encoder_type);
212 }
213 }
214 }
215
216 struct drm_connector *
217 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
218 {
219 struct drm_device *dev = encoder->dev;
220 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
221 struct drm_connector *connector;
222 struct radeon_connector *radeon_connector;
223
224 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
225 radeon_connector = to_radeon_connector(connector);
226 if (radeon_encoder->active_device & radeon_connector->devices)
227 return connector;
228 }
229 return NULL;
230 }
231
232 static struct drm_connector *
233 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
234 {
235 struct drm_device *dev = encoder->dev;
236 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
237 struct drm_connector *connector;
238 struct radeon_connector *radeon_connector;
239
240 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
241 radeon_connector = to_radeon_connector(connector);
242 if (radeon_encoder->devices & radeon_connector->devices)
243 return connector;
244 }
245 return NULL;
246 }
247
248 struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
249 {
250 struct drm_device *dev = encoder->dev;
251 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
252 struct drm_encoder *other_encoder;
253 struct radeon_encoder *other_radeon_encoder;
254
255 if (radeon_encoder->is_ext_encoder)
256 return NULL;
257
258 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
259 if (other_encoder == encoder)
260 continue;
261 other_radeon_encoder = to_radeon_encoder(other_encoder);
262 if (other_radeon_encoder->is_ext_encoder &&
263 (radeon_encoder->devices & other_radeon_encoder->devices))
264 return other_encoder;
265 }
266 return NULL;
267 }
268
269 bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder)
270 {
271 struct drm_encoder *other_encoder = radeon_atom_get_external_encoder(encoder);
272
273 if (other_encoder) {
274 struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder);
275
276 switch (radeon_encoder->encoder_id) {
277 case ENCODER_OBJECT_ID_TRAVIS:
278 case ENCODER_OBJECT_ID_NUTMEG:
279 return true;
280 default:
281 return false;
282 }
283 }
284
285 return false;
286 }
287
288 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
289 struct drm_display_mode *adjusted_mode)
290 {
291 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
292 struct drm_device *dev = encoder->dev;
293 struct radeon_device *rdev = dev->dev_private;
294 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
295 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
296 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
297 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
298 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
299 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
300 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
301
302 adjusted_mode->clock = native_mode->clock;
303 adjusted_mode->flags = native_mode->flags;
304
305 if (ASIC_IS_AVIVO(rdev)) {
306 adjusted_mode->hdisplay = native_mode->hdisplay;
307 adjusted_mode->vdisplay = native_mode->vdisplay;
308 }
309
310 adjusted_mode->htotal = native_mode->hdisplay + hblank;
311 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
312 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
313
314 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
315 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
316 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
317
318 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
319
320 if (ASIC_IS_AVIVO(rdev)) {
321 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
322 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
323 }
324
325 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
326 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
327 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
328
329 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
330 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
331 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
332
333 }
334
335 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
336 struct drm_display_mode *mode,
337 struct drm_display_mode *adjusted_mode)
338 {
339 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
340 struct drm_device *dev = encoder->dev;
341 struct radeon_device *rdev = dev->dev_private;
342
343 /* set the active encoder to connector routing */
344 radeon_encoder_set_active_device(encoder);
345 drm_mode_set_crtcinfo(adjusted_mode, 0);
346
347 /* hw bug */
348 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
349 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
350 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
351
352 /* get the native mode for LVDS */
353 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
354 radeon_panel_mode_fixup(encoder, adjusted_mode);
355
356 /* get the native mode for TV */
357 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
358 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
359 if (tv_dac) {
360 if (tv_dac->tv_std == TV_STD_NTSC ||
361 tv_dac->tv_std == TV_STD_NTSC_J ||
362 tv_dac->tv_std == TV_STD_PAL_M)
363 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
364 else
365 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
366 }
367 }
368
369 if (ASIC_IS_DCE3(rdev) &&
370 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
371 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
372 radeon_dp_set_link_config(connector, mode);
373 }
374
375 return true;
376 }
377
378 static void
379 atombios_dac_setup(struct drm_encoder *encoder, int action)
380 {
381 struct drm_device *dev = encoder->dev;
382 struct radeon_device *rdev = dev->dev_private;
383 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
384 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
385 int index = 0;
386 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
387
388 memset(&args, 0, sizeof(args));
389
390 switch (radeon_encoder->encoder_id) {
391 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
392 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
393 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
394 break;
395 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
396 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
397 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
398 break;
399 }
400
401 args.ucAction = action;
402
403 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
404 args.ucDacStandard = ATOM_DAC1_PS2;
405 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
406 args.ucDacStandard = ATOM_DAC1_CV;
407 else {
408 switch (dac_info->tv_std) {
409 case TV_STD_PAL:
410 case TV_STD_PAL_M:
411 case TV_STD_SCART_PAL:
412 case TV_STD_SECAM:
413 case TV_STD_PAL_CN:
414 args.ucDacStandard = ATOM_DAC1_PAL;
415 break;
416 case TV_STD_NTSC:
417 case TV_STD_NTSC_J:
418 case TV_STD_PAL_60:
419 default:
420 args.ucDacStandard = ATOM_DAC1_NTSC;
421 break;
422 }
423 }
424 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
425
426 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
427
428 }
429
430 static void
431 atombios_tv_setup(struct drm_encoder *encoder, int action)
432 {
433 struct drm_device *dev = encoder->dev;
434 struct radeon_device *rdev = dev->dev_private;
435 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
436 TV_ENCODER_CONTROL_PS_ALLOCATION args;
437 int index = 0;
438 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
439
440 memset(&args, 0, sizeof(args));
441
442 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
443
444 args.sTVEncoder.ucAction = action;
445
446 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
447 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
448 else {
449 switch (dac_info->tv_std) {
450 case TV_STD_NTSC:
451 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
452 break;
453 case TV_STD_PAL:
454 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
455 break;
456 case TV_STD_PAL_M:
457 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
458 break;
459 case TV_STD_PAL_60:
460 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
461 break;
462 case TV_STD_NTSC_J:
463 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
464 break;
465 case TV_STD_SCART_PAL:
466 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
467 break;
468 case TV_STD_SECAM:
469 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
470 break;
471 case TV_STD_PAL_CN:
472 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
473 break;
474 default:
475 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
476 break;
477 }
478 }
479
480 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
481
482 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
483
484 }
485
486 union dvo_encoder_control {
487 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
488 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
489 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
490 };
491
492 void
493 atombios_dvo_setup(struct drm_encoder *encoder, int action)
494 {
495 struct drm_device *dev = encoder->dev;
496 struct radeon_device *rdev = dev->dev_private;
497 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
498 union dvo_encoder_control args;
499 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
500
501 memset(&args, 0, sizeof(args));
502
503 if (ASIC_IS_DCE3(rdev)) {
504 /* DCE3+ */
505 args.dvo_v3.ucAction = action;
506 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
507 args.dvo_v3.ucDVOConfig = 0; /* XXX */
508 } else if (ASIC_IS_DCE2(rdev)) {
509 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
510 args.dvo.sDVOEncoder.ucAction = action;
511 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
512 /* DFP1, CRT1, TV1 depending on the type of port */
513 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
514
515 if (radeon_encoder->pixel_clock > 165000)
516 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
517 } else {
518 /* R4xx, R5xx */
519 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
520
521 if (radeon_encoder->pixel_clock > 165000)
522 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
523
524 /*if (pScrn->rgbBits == 8)*/
525 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
526 }
527
528 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
529 }
530
531 union lvds_encoder_control {
532 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
533 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
534 };
535
536 void
537 atombios_digital_setup(struct drm_encoder *encoder, int action)
538 {
539 struct drm_device *dev = encoder->dev;
540 struct radeon_device *rdev = dev->dev_private;
541 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
542 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
543 union lvds_encoder_control args;
544 int index = 0;
545 int hdmi_detected = 0;
546 uint8_t frev, crev;
547
548 if (!dig)
549 return;
550
551 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
552 hdmi_detected = 1;
553
554 memset(&args, 0, sizeof(args));
555
556 switch (radeon_encoder->encoder_id) {
557 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
558 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
559 break;
560 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
561 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
562 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
563 break;
564 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
565 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
566 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
567 else
568 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
569 break;
570 }
571
572 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
573 return;
574
575 switch (frev) {
576 case 1:
577 case 2:
578 switch (crev) {
579 case 1:
580 args.v1.ucMisc = 0;
581 args.v1.ucAction = action;
582 if (hdmi_detected)
583 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
584 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
585 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
586 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
587 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
588 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
589 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
590 } else {
591 if (dig->linkb)
592 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
593 if (radeon_encoder->pixel_clock > 165000)
594 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
595 /*if (pScrn->rgbBits == 8) */
596 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
597 }
598 break;
599 case 2:
600 case 3:
601 args.v2.ucMisc = 0;
602 args.v2.ucAction = action;
603 if (crev == 3) {
604 if (dig->coherent_mode)
605 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
606 }
607 if (hdmi_detected)
608 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
609 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
610 args.v2.ucTruncate = 0;
611 args.v2.ucSpatial = 0;
612 args.v2.ucTemporal = 0;
613 args.v2.ucFRC = 0;
614 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
615 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
616 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
617 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
618 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
619 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
620 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
621 }
622 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
623 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
624 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
625 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
626 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
627 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
628 }
629 } else {
630 if (dig->linkb)
631 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
632 if (radeon_encoder->pixel_clock > 165000)
633 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
634 }
635 break;
636 default:
637 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
638 break;
639 }
640 break;
641 default:
642 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
643 break;
644 }
645
646 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
647 }
648
649 int
650 atombios_get_encoder_mode(struct drm_encoder *encoder)
651 {
652 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
653 struct drm_device *dev = encoder->dev;
654 struct radeon_device *rdev = dev->dev_private;
655 struct drm_connector *connector;
656 struct radeon_connector *radeon_connector;
657 struct radeon_connector_atom_dig *dig_connector;
658
659 /* dp bridges are always DP */
660 if (radeon_encoder_is_dp_bridge(encoder))
661 return ATOM_ENCODER_MODE_DP;
662
663 /* DVO is always DVO */
664 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
665 return ATOM_ENCODER_MODE_DVO;
666
667 connector = radeon_get_connector_for_encoder(encoder);
668 /* if we don't have an active device yet, just use one of
669 * the connectors tied to the encoder.
670 */
671 if (!connector)
672 connector = radeon_get_connector_for_encoder_init(encoder);
673 radeon_connector = to_radeon_connector(connector);
674
675 switch (connector->connector_type) {
676 case DRM_MODE_CONNECTOR_DVII:
677 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
678 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
679 /* fix me */
680 if (ASIC_IS_DCE4(rdev))
681 return ATOM_ENCODER_MODE_DVI;
682 else
683 return ATOM_ENCODER_MODE_HDMI;
684 } else if (radeon_connector->use_digital)
685 return ATOM_ENCODER_MODE_DVI;
686 else
687 return ATOM_ENCODER_MODE_CRT;
688 break;
689 case DRM_MODE_CONNECTOR_DVID:
690 case DRM_MODE_CONNECTOR_HDMIA:
691 default:
692 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
693 /* fix me */
694 if (ASIC_IS_DCE4(rdev))
695 return ATOM_ENCODER_MODE_DVI;
696 else
697 return ATOM_ENCODER_MODE_HDMI;
698 } else
699 return ATOM_ENCODER_MODE_DVI;
700 break;
701 case DRM_MODE_CONNECTOR_LVDS:
702 return ATOM_ENCODER_MODE_LVDS;
703 break;
704 case DRM_MODE_CONNECTOR_DisplayPort:
705 dig_connector = radeon_connector->con_priv;
706 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
707 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
708 return ATOM_ENCODER_MODE_DP;
709 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
710 /* fix me */
711 if (ASIC_IS_DCE4(rdev))
712 return ATOM_ENCODER_MODE_DVI;
713 else
714 return ATOM_ENCODER_MODE_HDMI;
715 } else
716 return ATOM_ENCODER_MODE_DVI;
717 break;
718 case DRM_MODE_CONNECTOR_eDP:
719 return ATOM_ENCODER_MODE_DP;
720 case DRM_MODE_CONNECTOR_DVIA:
721 case DRM_MODE_CONNECTOR_VGA:
722 return ATOM_ENCODER_MODE_CRT;
723 break;
724 case DRM_MODE_CONNECTOR_Composite:
725 case DRM_MODE_CONNECTOR_SVIDEO:
726 case DRM_MODE_CONNECTOR_9PinDIN:
727 /* fix me */
728 return ATOM_ENCODER_MODE_TV;
729 /*return ATOM_ENCODER_MODE_CV;*/
730 break;
731 }
732 }
733
734 /*
735 * DIG Encoder/Transmitter Setup
736 *
737 * DCE 3.0/3.1
738 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
739 * Supports up to 3 digital outputs
740 * - 2 DIG encoder blocks.
741 * DIG1 can drive UNIPHY link A or link B
742 * DIG2 can drive UNIPHY link B or LVTMA
743 *
744 * DCE 3.2
745 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
746 * Supports up to 5 digital outputs
747 * - 2 DIG encoder blocks.
748 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
749 *
750 * DCE 4.0/5.0
751 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
752 * Supports up to 6 digital outputs
753 * - 6 DIG encoder blocks.
754 * - DIG to PHY mapping is hardcoded
755 * DIG1 drives UNIPHY0 link A, A+B
756 * DIG2 drives UNIPHY0 link B
757 * DIG3 drives UNIPHY1 link A, A+B
758 * DIG4 drives UNIPHY1 link B
759 * DIG5 drives UNIPHY2 link A, A+B
760 * DIG6 drives UNIPHY2 link B
761 *
762 * DCE 4.1
763 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
764 * Supports up to 6 digital outputs
765 * - 2 DIG encoder blocks.
766 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
767 *
768 * Routing
769 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
770 * Examples:
771 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
772 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
773 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
774 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
775 */
776
777 union dig_encoder_control {
778 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
779 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
780 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
781 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
782 };
783
784 void
785 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
786 {
787 struct drm_device *dev = encoder->dev;
788 struct radeon_device *rdev = dev->dev_private;
789 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
790 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
791 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
792 union dig_encoder_control args;
793 int index = 0;
794 uint8_t frev, crev;
795 int dp_clock = 0;
796 int dp_lane_count = 0;
797 int hpd_id = RADEON_HPD_NONE;
798 int bpc = 8;
799
800 if (connector) {
801 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
802 struct radeon_connector_atom_dig *dig_connector =
803 radeon_connector->con_priv;
804
805 dp_clock = dig_connector->dp_clock;
806 dp_lane_count = dig_connector->dp_lane_count;
807 hpd_id = radeon_connector->hpd.hpd;
808 bpc = connector->display_info.bpc;
809 }
810
811 /* no dig encoder assigned */
812 if (dig->dig_encoder == -1)
813 return;
814
815 memset(&args, 0, sizeof(args));
816
817 if (ASIC_IS_DCE4(rdev))
818 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
819 else {
820 if (dig->dig_encoder)
821 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
822 else
823 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
824 }
825
826 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
827 return;
828
829 args.v1.ucAction = action;
830 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
831 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
832 args.v3.ucPanelMode = panel_mode;
833 else
834 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
835
836 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
837 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
838 args.v1.ucLaneNum = dp_lane_count;
839 else if (radeon_encoder->pixel_clock > 165000)
840 args.v1.ucLaneNum = 8;
841 else
842 args.v1.ucLaneNum = 4;
843
844 if (ASIC_IS_DCE5(rdev)) {
845 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
846 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) {
847 if (dp_clock == 270000)
848 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
849 else if (dp_clock == 540000)
850 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
851 }
852 args.v4.acConfig.ucDigSel = dig->dig_encoder;
853 switch (bpc) {
854 case 0:
855 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
856 break;
857 case 6:
858 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
859 break;
860 case 8:
861 default:
862 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
863 break;
864 case 10:
865 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
866 break;
867 case 12:
868 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
869 break;
870 case 16:
871 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
872 break;
873 }
874 if (hpd_id == RADEON_HPD_NONE)
875 args.v4.ucHPD_ID = 0;
876 else
877 args.v4.ucHPD_ID = hpd_id + 1;
878 } else if (ASIC_IS_DCE4(rdev)) {
879 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
880 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
881 args.v3.acConfig.ucDigSel = dig->dig_encoder;
882 switch (bpc) {
883 case 0:
884 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
885 break;
886 case 6:
887 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
888 break;
889 case 8:
890 default:
891 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
892 break;
893 case 10:
894 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
895 break;
896 case 12:
897 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
898 break;
899 case 16:
900 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
901 break;
902 }
903 } else {
904 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
905 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
906 switch (radeon_encoder->encoder_id) {
907 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
908 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
909 break;
910 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
911 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
912 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
913 break;
914 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
915 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
916 break;
917 }
918 if (dig->linkb)
919 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
920 else
921 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
922 }
923
924 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
925
926 }
927
928 union dig_transmitter_control {
929 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
930 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
931 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
932 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
933 };
934
935 void
936 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
937 {
938 struct drm_device *dev = encoder->dev;
939 struct radeon_device *rdev = dev->dev_private;
940 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
941 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
942 struct drm_connector *connector;
943 union dig_transmitter_control args;
944 int index = 0;
945 uint8_t frev, crev;
946 bool is_dp = false;
947 int pll_id = 0;
948 int dp_clock = 0;
949 int dp_lane_count = 0;
950 int connector_object_id = 0;
951 int igp_lane_info = 0;
952 int dig_encoder = dig->dig_encoder;
953
954 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
955 connector = radeon_get_connector_for_encoder_init(encoder);
956 /* just needed to avoid bailing in the encoder check. the encoder
957 * isn't used for init
958 */
959 dig_encoder = 0;
960 } else
961 connector = radeon_get_connector_for_encoder(encoder);
962
963 if (connector) {
964 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
965 struct radeon_connector_atom_dig *dig_connector =
966 radeon_connector->con_priv;
967
968 dp_clock = dig_connector->dp_clock;
969 dp_lane_count = dig_connector->dp_lane_count;
970 connector_object_id =
971 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
972 igp_lane_info = dig_connector->igp_lane_info;
973 }
974
975 /* no dig encoder assigned */
976 if (dig_encoder == -1)
977 return;
978
979 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
980 is_dp = true;
981
982 memset(&args, 0, sizeof(args));
983
984 switch (radeon_encoder->encoder_id) {
985 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
986 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
987 break;
988 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
989 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
990 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
991 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
992 break;
993 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
994 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
995 break;
996 }
997
998 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
999 return;
1000
1001 args.v1.ucAction = action;
1002 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1003 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1004 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1005 args.v1.asMode.ucLaneSel = lane_num;
1006 args.v1.asMode.ucLaneSet = lane_set;
1007 } else {
1008 if (is_dp)
1009 args.v1.usPixelClock =
1010 cpu_to_le16(dp_clock / 10);
1011 else if (radeon_encoder->pixel_clock > 165000)
1012 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1013 else
1014 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1015 }
1016 if (ASIC_IS_DCE4(rdev)) {
1017 if (is_dp)
1018 args.v3.ucLaneNum = dp_lane_count;
1019 else if (radeon_encoder->pixel_clock > 165000)
1020 args.v3.ucLaneNum = 8;
1021 else
1022 args.v3.ucLaneNum = 4;
1023
1024 if (dig->linkb)
1025 args.v3.acConfig.ucLinkSel = 1;
1026 if (dig_encoder & 1)
1027 args.v3.acConfig.ucEncoderSel = 1;
1028
1029 /* Select the PLL for the PHY
1030 * DP PHY should be clocked from external src if there is
1031 * one.
1032 */
1033 if (encoder->crtc) {
1034 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1035 pll_id = radeon_crtc->pll_id;
1036 }
1037
1038 if (ASIC_IS_DCE5(rdev)) {
1039 /* On DCE5 DCPLL usually generates the DP ref clock */
1040 if (is_dp) {
1041 if (rdev->clock.dp_extclk)
1042 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1043 else
1044 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1045 } else
1046 args.v4.acConfig.ucRefClkSource = pll_id;
1047 } else {
1048 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1049 if (is_dp && rdev->clock.dp_extclk)
1050 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1051 else
1052 args.v3.acConfig.ucRefClkSource = pll_id;
1053 }
1054
1055 switch (radeon_encoder->encoder_id) {
1056 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1057 args.v3.acConfig.ucTransmitterSel = 0;
1058 break;
1059 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1060 args.v3.acConfig.ucTransmitterSel = 1;
1061 break;
1062 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1063 args.v3.acConfig.ucTransmitterSel = 2;
1064 break;
1065 }
1066
1067 if (is_dp)
1068 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1069 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1070 if (dig->coherent_mode)
1071 args.v3.acConfig.fCoherentMode = 1;
1072 if (radeon_encoder->pixel_clock > 165000)
1073 args.v3.acConfig.fDualLinkConnector = 1;
1074 }
1075 } else if (ASIC_IS_DCE32(rdev)) {
1076 args.v2.acConfig.ucEncoderSel = dig_encoder;
1077 if (dig->linkb)
1078 args.v2.acConfig.ucLinkSel = 1;
1079
1080 switch (radeon_encoder->encoder_id) {
1081 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1082 args.v2.acConfig.ucTransmitterSel = 0;
1083 break;
1084 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1085 args.v2.acConfig.ucTransmitterSel = 1;
1086 break;
1087 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1088 args.v2.acConfig.ucTransmitterSel = 2;
1089 break;
1090 }
1091
1092 if (is_dp)
1093 args.v2.acConfig.fCoherentMode = 1;
1094 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1095 if (dig->coherent_mode)
1096 args.v2.acConfig.fCoherentMode = 1;
1097 if (radeon_encoder->pixel_clock > 165000)
1098 args.v2.acConfig.fDualLinkConnector = 1;
1099 }
1100 } else {
1101 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1102
1103 if (dig_encoder)
1104 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1105 else
1106 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1107
1108 if ((rdev->flags & RADEON_IS_IGP) &&
1109 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1110 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
1111 if (igp_lane_info & 0x1)
1112 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1113 else if (igp_lane_info & 0x2)
1114 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1115 else if (igp_lane_info & 0x4)
1116 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1117 else if (igp_lane_info & 0x8)
1118 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1119 } else {
1120 if (igp_lane_info & 0x3)
1121 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1122 else if (igp_lane_info & 0xc)
1123 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1124 }
1125 }
1126
1127 if (dig->linkb)
1128 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1129 else
1130 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1131
1132 if (is_dp)
1133 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1134 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1135 if (dig->coherent_mode)
1136 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1137 if (radeon_encoder->pixel_clock > 165000)
1138 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1139 }
1140 }
1141
1142 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1143 }
1144
1145 bool
1146 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1147 {
1148 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1149 struct drm_device *dev = radeon_connector->base.dev;
1150 struct radeon_device *rdev = dev->dev_private;
1151 union dig_transmitter_control args;
1152 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1153 uint8_t frev, crev;
1154
1155 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1156 goto done;
1157
1158 if (!ASIC_IS_DCE4(rdev))
1159 goto done;
1160
1161 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1162 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1163 goto done;
1164
1165 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1166 goto done;
1167
1168 memset(&args, 0, sizeof(args));
1169
1170 args.v1.ucAction = action;
1171
1172 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1173
1174 /* wait for the panel to power up */
1175 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1176 int i;
1177
1178 for (i = 0; i < 300; i++) {
1179 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1180 return true;
1181 mdelay(1);
1182 }
1183 return false;
1184 }
1185 done:
1186 return true;
1187 }
1188
1189 union external_encoder_control {
1190 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1191 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1192 };
1193
1194 static void
1195 atombios_external_encoder_setup(struct drm_encoder *encoder,
1196 struct drm_encoder *ext_encoder,
1197 int action)
1198 {
1199 struct drm_device *dev = encoder->dev;
1200 struct radeon_device *rdev = dev->dev_private;
1201 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1202 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1203 union external_encoder_control args;
1204 struct drm_connector *connector;
1205 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1206 u8 frev, crev;
1207 int dp_clock = 0;
1208 int dp_lane_count = 0;
1209 int connector_object_id = 0;
1210 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1211 int bpc = 8;
1212
1213 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1214 connector = radeon_get_connector_for_encoder_init(encoder);
1215 else
1216 connector = radeon_get_connector_for_encoder(encoder);
1217
1218 if (connector) {
1219 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1220 struct radeon_connector_atom_dig *dig_connector =
1221 radeon_connector->con_priv;
1222
1223 dp_clock = dig_connector->dp_clock;
1224 dp_lane_count = dig_connector->dp_lane_count;
1225 connector_object_id =
1226 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1227 bpc = connector->display_info.bpc;
1228 }
1229
1230 memset(&args, 0, sizeof(args));
1231
1232 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1233 return;
1234
1235 switch (frev) {
1236 case 1:
1237 /* no params on frev 1 */
1238 break;
1239 case 2:
1240 switch (crev) {
1241 case 1:
1242 case 2:
1243 args.v1.sDigEncoder.ucAction = action;
1244 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1245 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1246
1247 if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1248 if (dp_clock == 270000)
1249 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1250 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1251 } else if (radeon_encoder->pixel_clock > 165000)
1252 args.v1.sDigEncoder.ucLaneNum = 8;
1253 else
1254 args.v1.sDigEncoder.ucLaneNum = 4;
1255 break;
1256 case 3:
1257 args.v3.sExtEncoder.ucAction = action;
1258 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1259 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1260 else
1261 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1262 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1263
1264 if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1265 if (dp_clock == 270000)
1266 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1267 else if (dp_clock == 540000)
1268 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1269 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1270 } else if (radeon_encoder->pixel_clock > 165000)
1271 args.v3.sExtEncoder.ucLaneNum = 8;
1272 else
1273 args.v3.sExtEncoder.ucLaneNum = 4;
1274 switch (ext_enum) {
1275 case GRAPH_OBJECT_ENUM_ID1:
1276 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1277 break;
1278 case GRAPH_OBJECT_ENUM_ID2:
1279 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1280 break;
1281 case GRAPH_OBJECT_ENUM_ID3:
1282 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1283 break;
1284 }
1285 switch (bpc) {
1286 case 0:
1287 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1288 break;
1289 case 6:
1290 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1291 break;
1292 case 8:
1293 default:
1294 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1295 break;
1296 case 10:
1297 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1298 break;
1299 case 12:
1300 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1301 break;
1302 case 16:
1303 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1304 break;
1305 }
1306 break;
1307 default:
1308 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1309 return;
1310 }
1311 break;
1312 default:
1313 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1314 return;
1315 }
1316 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1317 }
1318
1319 static void
1320 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1321 {
1322 struct drm_device *dev = encoder->dev;
1323 struct radeon_device *rdev = dev->dev_private;
1324 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1325 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1326 ENABLE_YUV_PS_ALLOCATION args;
1327 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1328 uint32_t temp, reg;
1329
1330 memset(&args, 0, sizeof(args));
1331
1332 if (rdev->family >= CHIP_R600)
1333 reg = R600_BIOS_3_SCRATCH;
1334 else
1335 reg = RADEON_BIOS_3_SCRATCH;
1336
1337 /* XXX: fix up scratch reg handling */
1338 temp = RREG32(reg);
1339 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1340 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1341 (radeon_crtc->crtc_id << 18)));
1342 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1343 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1344 else
1345 WREG32(reg, 0);
1346
1347 if (enable)
1348 args.ucEnable = ATOM_ENABLE;
1349 args.ucCRTC = radeon_crtc->crtc_id;
1350
1351 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1352
1353 WREG32(reg, temp);
1354 }
1355
1356 static void
1357 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1358 {
1359 struct drm_device *dev = encoder->dev;
1360 struct radeon_device *rdev = dev->dev_private;
1361 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1362 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1363 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1364 int index = 0;
1365 bool is_dig = false;
1366 bool is_dce5_dac = false;
1367 bool is_dce5_dvo = false;
1368
1369 memset(&args, 0, sizeof(args));
1370
1371 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1372 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1373 radeon_encoder->active_device);
1374 switch (radeon_encoder->encoder_id) {
1375 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1376 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1377 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1378 break;
1379 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1380 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1381 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1382 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1383 is_dig = true;
1384 break;
1385 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1386 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1387 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1388 break;
1389 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1390 if (ASIC_IS_DCE5(rdev))
1391 is_dce5_dvo = true;
1392 else if (ASIC_IS_DCE3(rdev))
1393 is_dig = true;
1394 else
1395 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1396 break;
1397 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1398 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1399 break;
1400 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1401 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1402 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1403 else
1404 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1405 break;
1406 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1407 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1408 if (ASIC_IS_DCE5(rdev))
1409 is_dce5_dac = true;
1410 else {
1411 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1412 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1413 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1414 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1415 else
1416 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1417 }
1418 break;
1419 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1420 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1421 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1422 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1423 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1424 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1425 else
1426 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1427 break;
1428 }
1429
1430 if (is_dig) {
1431 switch (mode) {
1432 case DRM_MODE_DPMS_ON:
1433 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1434 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1435 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1436
1437 if (connector &&
1438 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1439 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1440 struct radeon_connector_atom_dig *radeon_dig_connector =
1441 radeon_connector->con_priv;
1442 atombios_set_edp_panel_power(connector,
1443 ATOM_TRANSMITTER_ACTION_POWER_ON);
1444 radeon_dig_connector->edp_on = true;
1445 }
1446 if (ASIC_IS_DCE4(rdev))
1447 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1448 radeon_dp_link_train(encoder, connector);
1449 if (ASIC_IS_DCE4(rdev))
1450 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1451 }
1452 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1453 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1454 break;
1455 case DRM_MODE_DPMS_STANDBY:
1456 case DRM_MODE_DPMS_SUSPEND:
1457 case DRM_MODE_DPMS_OFF:
1458 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1459 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1460 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1461
1462 if (ASIC_IS_DCE4(rdev))
1463 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1464 if (connector &&
1465 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1466 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1467 struct radeon_connector_atom_dig *radeon_dig_connector =
1468 radeon_connector->con_priv;
1469 atombios_set_edp_panel_power(connector,
1470 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1471 radeon_dig_connector->edp_on = false;
1472 }
1473 }
1474 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1475 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1476 break;
1477 }
1478 } else if (is_dce5_dac) {
1479 switch (mode) {
1480 case DRM_MODE_DPMS_ON:
1481 atombios_dac_setup(encoder, ATOM_ENABLE);
1482 break;
1483 case DRM_MODE_DPMS_STANDBY:
1484 case DRM_MODE_DPMS_SUSPEND:
1485 case DRM_MODE_DPMS_OFF:
1486 atombios_dac_setup(encoder, ATOM_DISABLE);
1487 break;
1488 }
1489 } else if (is_dce5_dvo) {
1490 switch (mode) {
1491 case DRM_MODE_DPMS_ON:
1492 atombios_dvo_setup(encoder, ATOM_ENABLE);
1493 break;
1494 case DRM_MODE_DPMS_STANDBY:
1495 case DRM_MODE_DPMS_SUSPEND:
1496 case DRM_MODE_DPMS_OFF:
1497 atombios_dvo_setup(encoder, ATOM_DISABLE);
1498 break;
1499 }
1500 } else {
1501 switch (mode) {
1502 case DRM_MODE_DPMS_ON:
1503 args.ucAction = ATOM_ENABLE;
1504 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1505 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1506 args.ucAction = ATOM_LCD_BLON;
1507 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1508 }
1509 break;
1510 case DRM_MODE_DPMS_STANDBY:
1511 case DRM_MODE_DPMS_SUSPEND:
1512 case DRM_MODE_DPMS_OFF:
1513 args.ucAction = ATOM_DISABLE;
1514 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1515 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1516 args.ucAction = ATOM_LCD_BLOFF;
1517 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1518 }
1519 break;
1520 }
1521 }
1522
1523 if (ext_encoder) {
1524 int action;
1525
1526 switch (mode) {
1527 case DRM_MODE_DPMS_ON:
1528 default:
1529 if (ASIC_IS_DCE41(rdev))
1530 action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT;
1531 else
1532 action = ATOM_ENABLE;
1533 break;
1534 case DRM_MODE_DPMS_STANDBY:
1535 case DRM_MODE_DPMS_SUSPEND:
1536 case DRM_MODE_DPMS_OFF:
1537 if (ASIC_IS_DCE41(rdev))
1538 action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT;
1539 else
1540 action = ATOM_DISABLE;
1541 break;
1542 }
1543 atombios_external_encoder_setup(encoder, ext_encoder, action);
1544 }
1545
1546 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1547
1548 }
1549
1550 union crtc_source_param {
1551 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1552 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1553 };
1554
1555 static void
1556 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1557 {
1558 struct drm_device *dev = encoder->dev;
1559 struct radeon_device *rdev = dev->dev_private;
1560 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1561 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1562 union crtc_source_param args;
1563 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1564 uint8_t frev, crev;
1565 struct radeon_encoder_atom_dig *dig;
1566
1567 memset(&args, 0, sizeof(args));
1568
1569 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1570 return;
1571
1572 switch (frev) {
1573 case 1:
1574 switch (crev) {
1575 case 1:
1576 default:
1577 if (ASIC_IS_AVIVO(rdev))
1578 args.v1.ucCRTC = radeon_crtc->crtc_id;
1579 else {
1580 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1581 args.v1.ucCRTC = radeon_crtc->crtc_id;
1582 } else {
1583 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1584 }
1585 }
1586 switch (radeon_encoder->encoder_id) {
1587 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1588 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1589 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1590 break;
1591 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1592 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1593 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1594 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1595 else
1596 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1597 break;
1598 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1599 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1600 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1601 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1602 break;
1603 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1604 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1605 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1606 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1607 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1608 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1609 else
1610 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1611 break;
1612 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1613 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1614 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1615 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1616 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1617 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1618 else
1619 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1620 break;
1621 }
1622 break;
1623 case 2:
1624 args.v2.ucCRTC = radeon_crtc->crtc_id;
1625 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1626 switch (radeon_encoder->encoder_id) {
1627 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1628 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1629 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1630 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1631 dig = radeon_encoder->enc_priv;
1632 switch (dig->dig_encoder) {
1633 case 0:
1634 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1635 break;
1636 case 1:
1637 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1638 break;
1639 case 2:
1640 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1641 break;
1642 case 3:
1643 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1644 break;
1645 case 4:
1646 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1647 break;
1648 case 5:
1649 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1650 break;
1651 }
1652 break;
1653 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1654 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1655 break;
1656 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1657 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1658 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1659 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1660 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1661 else
1662 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1663 break;
1664 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1665 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1666 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1667 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1668 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1669 else
1670 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1671 break;
1672 }
1673 break;
1674 }
1675 break;
1676 default:
1677 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1678 return;
1679 }
1680
1681 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1682
1683 /* update scratch regs with new routing */
1684 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1685 }
1686
1687 static void
1688 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1689 struct drm_display_mode *mode)
1690 {
1691 struct drm_device *dev = encoder->dev;
1692 struct radeon_device *rdev = dev->dev_private;
1693 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1694 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1695
1696 /* Funky macbooks */
1697 if ((dev->pdev->device == 0x71C5) &&
1698 (dev->pdev->subsystem_vendor == 0x106b) &&
1699 (dev->pdev->subsystem_device == 0x0080)) {
1700 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1701 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1702
1703 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1704 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1705
1706 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1707 }
1708 }
1709
1710 /* set scaler clears this on some chips */
1711 if (ASIC_IS_AVIVO(rdev) &&
1712 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1713 if (ASIC_IS_DCE4(rdev)) {
1714 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1715 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1716 EVERGREEN_INTERLEAVE_EN);
1717 else
1718 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1719 } else {
1720 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1721 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1722 AVIVO_D1MODE_INTERLEAVE_EN);
1723 else
1724 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1725 }
1726 }
1727 }
1728
1729 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1730 {
1731 struct drm_device *dev = encoder->dev;
1732 struct radeon_device *rdev = dev->dev_private;
1733 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1734 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1735 struct drm_encoder *test_encoder;
1736 struct radeon_encoder_atom_dig *dig;
1737 uint32_t dig_enc_in_use = 0;
1738
1739 /* DCE4/5 */
1740 if (ASIC_IS_DCE4(rdev)) {
1741 dig = radeon_encoder->enc_priv;
1742 if (ASIC_IS_DCE41(rdev))
1743 return radeon_crtc->crtc_id;
1744 else {
1745 switch (radeon_encoder->encoder_id) {
1746 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1747 if (dig->linkb)
1748 return 1;
1749 else
1750 return 0;
1751 break;
1752 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1753 if (dig->linkb)
1754 return 3;
1755 else
1756 return 2;
1757 break;
1758 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1759 if (dig->linkb)
1760 return 5;
1761 else
1762 return 4;
1763 break;
1764 }
1765 }
1766 }
1767
1768 /* on DCE32 and encoder can driver any block so just crtc id */
1769 if (ASIC_IS_DCE32(rdev)) {
1770 return radeon_crtc->crtc_id;
1771 }
1772
1773 /* on DCE3 - LVTMA can only be driven by DIGB */
1774 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1775 struct radeon_encoder *radeon_test_encoder;
1776
1777 if (encoder == test_encoder)
1778 continue;
1779
1780 if (!radeon_encoder_is_digital(test_encoder))
1781 continue;
1782
1783 radeon_test_encoder = to_radeon_encoder(test_encoder);
1784 dig = radeon_test_encoder->enc_priv;
1785
1786 if (dig->dig_encoder >= 0)
1787 dig_enc_in_use |= (1 << dig->dig_encoder);
1788 }
1789
1790 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1791 if (dig_enc_in_use & 0x2)
1792 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1793 return 1;
1794 }
1795 if (!(dig_enc_in_use & 1))
1796 return 0;
1797 return 1;
1798 }
1799
1800 /* This only needs to be called once at startup */
1801 void
1802 radeon_atom_encoder_init(struct radeon_device *rdev)
1803 {
1804 struct drm_device *dev = rdev->ddev;
1805 struct drm_encoder *encoder;
1806
1807 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1808 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1809 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1810
1811 switch (radeon_encoder->encoder_id) {
1812 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1813 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1814 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1815 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1816 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1817 break;
1818 default:
1819 break;
1820 }
1821
1822 if (ext_encoder && ASIC_IS_DCE41(rdev))
1823 atombios_external_encoder_setup(encoder, ext_encoder,
1824 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1825 }
1826 }
1827
1828 static void
1829 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1830 struct drm_display_mode *mode,
1831 struct drm_display_mode *adjusted_mode)
1832 {
1833 struct drm_device *dev = encoder->dev;
1834 struct radeon_device *rdev = dev->dev_private;
1835 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1836 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1837
1838 radeon_encoder->pixel_clock = adjusted_mode->clock;
1839
1840 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1841 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1842 atombios_yuv_setup(encoder, true);
1843 else
1844 atombios_yuv_setup(encoder, false);
1845 }
1846
1847 switch (radeon_encoder->encoder_id) {
1848 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1849 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1850 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1851 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1852 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1853 break;
1854 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1855 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1856 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1857 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1858 if (ASIC_IS_DCE4(rdev)) {
1859 /* disable the transmitter */
1860 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1861 /* setup and enable the encoder */
1862 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1863
1864 /* enable the transmitter */
1865 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1866 } else {
1867 /* disable the encoder and transmitter */
1868 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1869 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1870
1871 /* setup and enable the encoder and transmitter */
1872 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1873 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1874 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1875 }
1876 break;
1877 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1878 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1879 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1880 atombios_dvo_setup(encoder, ATOM_ENABLE);
1881 break;
1882 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1883 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1884 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1885 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1886 atombios_dac_setup(encoder, ATOM_ENABLE);
1887 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1888 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1889 atombios_tv_setup(encoder, ATOM_ENABLE);
1890 else
1891 atombios_tv_setup(encoder, ATOM_DISABLE);
1892 }
1893 break;
1894 }
1895
1896 if (ext_encoder) {
1897 if (ASIC_IS_DCE41(rdev))
1898 atombios_external_encoder_setup(encoder, ext_encoder,
1899 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1900 else
1901 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1902 }
1903
1904 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1905
1906 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1907 r600_hdmi_enable(encoder);
1908 r600_hdmi_setmode(encoder, adjusted_mode);
1909 }
1910 }
1911
1912 static bool
1913 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1914 {
1915 struct drm_device *dev = encoder->dev;
1916 struct radeon_device *rdev = dev->dev_private;
1917 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1918 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1919
1920 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1921 ATOM_DEVICE_CV_SUPPORT |
1922 ATOM_DEVICE_CRT_SUPPORT)) {
1923 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1924 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1925 uint8_t frev, crev;
1926
1927 memset(&args, 0, sizeof(args));
1928
1929 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1930 return false;
1931
1932 args.sDacload.ucMisc = 0;
1933
1934 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1935 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1936 args.sDacload.ucDacType = ATOM_DAC_A;
1937 else
1938 args.sDacload.ucDacType = ATOM_DAC_B;
1939
1940 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1941 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1942 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1943 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1944 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1945 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1946 if (crev >= 3)
1947 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1948 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1949 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1950 if (crev >= 3)
1951 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1952 }
1953
1954 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1955
1956 return true;
1957 } else
1958 return false;
1959 }
1960
1961 static enum drm_connector_status
1962 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1963 {
1964 struct drm_device *dev = encoder->dev;
1965 struct radeon_device *rdev = dev->dev_private;
1966 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1967 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1968 uint32_t bios_0_scratch;
1969
1970 if (!atombios_dac_load_detect(encoder, connector)) {
1971 DRM_DEBUG_KMS("detect returned false \n");
1972 return connector_status_unknown;
1973 }
1974
1975 if (rdev->family >= CHIP_R600)
1976 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1977 else
1978 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1979
1980 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1981 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1982 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1983 return connector_status_connected;
1984 }
1985 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1986 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1987 return connector_status_connected;
1988 }
1989 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1990 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1991 return connector_status_connected;
1992 }
1993 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1994 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1995 return connector_status_connected; /* CTV */
1996 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1997 return connector_status_connected; /* STV */
1998 }
1999 return connector_status_disconnected;
2000 }
2001
2002 static enum drm_connector_status
2003 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2004 {
2005 struct drm_device *dev = encoder->dev;
2006 struct radeon_device *rdev = dev->dev_private;
2007 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2008 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2009 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
2010 u32 bios_0_scratch;
2011
2012 if (!ASIC_IS_DCE4(rdev))
2013 return connector_status_unknown;
2014
2015 if (!ext_encoder)
2016 return connector_status_unknown;
2017
2018 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2019 return connector_status_unknown;
2020
2021 /* load detect on the dp bridge */
2022 atombios_external_encoder_setup(encoder, ext_encoder,
2023 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2024
2025 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2026
2027 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2028 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2029 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2030 return connector_status_connected;
2031 }
2032 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2033 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2034 return connector_status_connected;
2035 }
2036 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2037 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2038 return connector_status_connected;
2039 }
2040 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2041 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2042 return connector_status_connected; /* CTV */
2043 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2044 return connector_status_connected; /* STV */
2045 }
2046 return connector_status_disconnected;
2047 }
2048
2049 void
2050 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2051 {
2052 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
2053
2054 if (ext_encoder)
2055 /* ddc_setup on the dp bridge */
2056 atombios_external_encoder_setup(encoder, ext_encoder,
2057 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2058
2059 }
2060
2061 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2062 {
2063 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2064 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2065
2066 if ((radeon_encoder->active_device &
2067 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2068 radeon_encoder_is_dp_bridge(encoder)) {
2069 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2070 if (dig)
2071 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2072 }
2073
2074 radeon_atom_output_lock(encoder, true);
2075 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2076
2077 if (connector) {
2078 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2079
2080 /* select the clock/data port if it uses a router */
2081 if (radeon_connector->router.cd_valid)
2082 radeon_router_select_cd_port(radeon_connector);
2083
2084 /* turn eDP panel on for mode set */
2085 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2086 atombios_set_edp_panel_power(connector,
2087 ATOM_TRANSMITTER_ACTION_POWER_ON);
2088 }
2089
2090 /* this is needed for the pll/ss setup to work correctly in some cases */
2091 atombios_set_encoder_crtc_source(encoder);
2092 }
2093
2094 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2095 {
2096 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2097 radeon_atom_output_lock(encoder, false);
2098 }
2099
2100 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2101 {
2102 struct drm_device *dev = encoder->dev;
2103 struct radeon_device *rdev = dev->dev_private;
2104 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2105 struct radeon_encoder_atom_dig *dig;
2106
2107 /* check for pre-DCE3 cards with shared encoders;
2108 * can't really use the links individually, so don't disable
2109 * the encoder if it's in use by another connector
2110 */
2111 if (!ASIC_IS_DCE3(rdev)) {
2112 struct drm_encoder *other_encoder;
2113 struct radeon_encoder *other_radeon_encoder;
2114
2115 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2116 other_radeon_encoder = to_radeon_encoder(other_encoder);
2117 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2118 drm_helper_encoder_in_use(other_encoder))
2119 goto disable_done;
2120 }
2121 }
2122
2123 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2124
2125 switch (radeon_encoder->encoder_id) {
2126 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2127 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2128 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2129 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2130 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2131 break;
2132 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2133 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2134 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2135 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2136 if (ASIC_IS_DCE4(rdev))
2137 /* disable the transmitter */
2138 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2139 else {
2140 /* disable the encoder and transmitter */
2141 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2142 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
2143 }
2144 break;
2145 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2146 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2147 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2148 atombios_dvo_setup(encoder, ATOM_DISABLE);
2149 break;
2150 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2151 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2152 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2153 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2154 atombios_dac_setup(encoder, ATOM_DISABLE);
2155 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2156 atombios_tv_setup(encoder, ATOM_DISABLE);
2157 break;
2158 }
2159
2160 disable_done:
2161 if (radeon_encoder_is_digital(encoder)) {
2162 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2163 r600_hdmi_disable(encoder);
2164 dig = radeon_encoder->enc_priv;
2165 dig->dig_encoder = -1;
2166 }
2167 radeon_encoder->active_device = 0;
2168 }
2169
2170 /* these are handled by the primary encoders */
2171 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2172 {
2173
2174 }
2175
2176 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2177 {
2178
2179 }
2180
2181 static void
2182 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2183 struct drm_display_mode *mode,
2184 struct drm_display_mode *adjusted_mode)
2185 {
2186
2187 }
2188
2189 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2190 {
2191
2192 }
2193
2194 static void
2195 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2196 {
2197
2198 }
2199
2200 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2201 struct drm_display_mode *mode,
2202 struct drm_display_mode *adjusted_mode)
2203 {
2204 return true;
2205 }
2206
2207 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2208 .dpms = radeon_atom_ext_dpms,
2209 .mode_fixup = radeon_atom_ext_mode_fixup,
2210 .prepare = radeon_atom_ext_prepare,
2211 .mode_set = radeon_atom_ext_mode_set,
2212 .commit = radeon_atom_ext_commit,
2213 .disable = radeon_atom_ext_disable,
2214 /* no detect for TMDS/LVDS yet */
2215 };
2216
2217 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2218 .dpms = radeon_atom_encoder_dpms,
2219 .mode_fixup = radeon_atom_mode_fixup,
2220 .prepare = radeon_atom_encoder_prepare,
2221 .mode_set = radeon_atom_encoder_mode_set,
2222 .commit = radeon_atom_encoder_commit,
2223 .disable = radeon_atom_encoder_disable,
2224 .detect = radeon_atom_dig_detect,
2225 };
2226
2227 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2228 .dpms = radeon_atom_encoder_dpms,
2229 .mode_fixup = radeon_atom_mode_fixup,
2230 .prepare = radeon_atom_encoder_prepare,
2231 .mode_set = radeon_atom_encoder_mode_set,
2232 .commit = radeon_atom_encoder_commit,
2233 .detect = radeon_atom_dac_detect,
2234 };
2235
2236 void radeon_enc_destroy(struct drm_encoder *encoder)
2237 {
2238 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2239 kfree(radeon_encoder->enc_priv);
2240 drm_encoder_cleanup(encoder);
2241 kfree(radeon_encoder);
2242 }
2243
2244 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2245 .destroy = radeon_enc_destroy,
2246 };
2247
2248 struct radeon_encoder_atom_dac *
2249 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2250 {
2251 struct drm_device *dev = radeon_encoder->base.dev;
2252 struct radeon_device *rdev = dev->dev_private;
2253 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2254
2255 if (!dac)
2256 return NULL;
2257
2258 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2259 return dac;
2260 }
2261
2262 struct radeon_encoder_atom_dig *
2263 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2264 {
2265 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2266 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2267
2268 if (!dig)
2269 return NULL;
2270
2271 /* coherent mode by default */
2272 dig->coherent_mode = true;
2273 dig->dig_encoder = -1;
2274
2275 if (encoder_enum == 2)
2276 dig->linkb = true;
2277 else
2278 dig->linkb = false;
2279
2280 return dig;
2281 }
2282
2283 void
2284 radeon_add_atom_encoder(struct drm_device *dev,
2285 uint32_t encoder_enum,
2286 uint32_t supported_device,
2287 u16 caps)
2288 {
2289 struct radeon_device *rdev = dev->dev_private;
2290 struct drm_encoder *encoder;
2291 struct radeon_encoder *radeon_encoder;
2292
2293 /* see if we already added it */
2294 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2295 radeon_encoder = to_radeon_encoder(encoder);
2296 if (radeon_encoder->encoder_enum == encoder_enum) {
2297 radeon_encoder->devices |= supported_device;
2298 return;
2299 }
2300
2301 }
2302
2303 /* add a new one */
2304 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2305 if (!radeon_encoder)
2306 return;
2307
2308 encoder = &radeon_encoder->base;
2309 switch (rdev->num_crtc) {
2310 case 1:
2311 encoder->possible_crtcs = 0x1;
2312 break;
2313 case 2:
2314 default:
2315 encoder->possible_crtcs = 0x3;
2316 break;
2317 case 6:
2318 encoder->possible_crtcs = 0x3f;
2319 break;
2320 }
2321
2322 radeon_encoder->enc_priv = NULL;
2323
2324 radeon_encoder->encoder_enum = encoder_enum;
2325 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2326 radeon_encoder->devices = supported_device;
2327 radeon_encoder->rmx_type = RMX_OFF;
2328 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2329 radeon_encoder->is_ext_encoder = false;
2330 radeon_encoder->caps = caps;
2331
2332 switch (radeon_encoder->encoder_id) {
2333 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2334 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2335 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2336 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2337 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2338 radeon_encoder->rmx_type = RMX_FULL;
2339 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2340 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2341 } else {
2342 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2343 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2344 }
2345 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2346 break;
2347 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2348 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2349 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2350 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2351 break;
2352 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2353 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2354 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2355 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2356 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2357 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2358 break;
2359 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2360 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2361 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2362 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2363 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2364 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2365 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2366 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2367 radeon_encoder->rmx_type = RMX_FULL;
2368 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2369 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2370 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2371 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2372 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2373 } else {
2374 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2375 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2376 }
2377 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2378 break;
2379 case ENCODER_OBJECT_ID_SI170B:
2380 case ENCODER_OBJECT_ID_CH7303:
2381 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2382 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2383 case ENCODER_OBJECT_ID_TITFP513:
2384 case ENCODER_OBJECT_ID_VT1623:
2385 case ENCODER_OBJECT_ID_HDMI_SI1930:
2386 case ENCODER_OBJECT_ID_TRAVIS:
2387 case ENCODER_OBJECT_ID_NUTMEG:
2388 /* these are handled by the primary encoders */
2389 radeon_encoder->is_ext_encoder = true;
2390 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2391 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2392 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2393 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2394 else
2395 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2396 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2397 break;
2398 }
2399 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree