drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25 #include "avivod.h"
  26
  27 #define RADEON_IDLE_LOOP_MS 100
  28 #define RADEON_RECLOCK_DELAY_MS 200
  29 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  30 #define RADEON_WAIT_IDLE_TIMEOUT 200
  31
  32 static void radeon_pm_idle_work_handler(struct work_struct *work);
  33 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  34
  35 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
  36 {
  37         struct radeon_bo *bo, *n;
  38
  39         if (list_empty(&rdev->gem.objects))
  40                 return;
  41
  42         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
  43                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
  44                         ttm_bo_unmap_virtual(&bo->tbo);
  45         }
  46
  47         if (rdev->gart.table.vram.robj)
  48                 ttm_bo_unmap_virtual(&rdev->gart.table.vram.robj->tbo);
  49
  50         if (rdev->stollen_vga_memory)
  51                 ttm_bo_unmap_virtual(&rdev->stollen_vga_memory->tbo);
  52
  53         if (rdev->r600_blit.shader_obj)
  54                 ttm_bo_unmap_virtual(&rdev->r600_blit.shader_obj->tbo);
  55 }
  56
  57 static void radeon_pm_set_clocks(struct radeon_device *rdev, int static_switch)
  58 {
  59         int i;
  60
  61         mutex_lock(&rdev->cp.mutex);
  62
  63         /* wait for GPU idle */
  64         rdev->pm.gui_idle = false;
  65         rdev->irq.gui_idle = true;
  66         radeon_irq_set(rdev);
  67         wait_event_interruptible_timeout(
  68                 rdev->irq.idle_queue, rdev->pm.gui_idle,
  69                 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
  70         rdev->irq.gui_idle = false;
  71         radeon_irq_set(rdev);
  72
  73         mutex_lock(&rdev->vram_mutex);
  74
  75         radeon_unmap_vram_bos(rdev);
  76
  77         if (!static_switch) {
  78                 for (i = 0; i < rdev->num_crtc; i++) {
  79                         if (rdev->pm.active_crtcs & (1 << i)) {
  80                                 rdev->pm.req_vblank |= (1 << i);
  81                                 drm_vblank_get(rdev->ddev, i);
  82                         }
  83                 }
  84         }
  85
  86         radeon_set_power_state(rdev, static_switch);
  87
  88         if (!static_switch) {
  89                 for (i = 0; i < rdev->num_crtc; i++) {
  90                         if (rdev->pm.req_vblank & (1 << i)) {
  91                                 rdev->pm.req_vblank &= ~(1 << i);
  92                                 drm_vblank_put(rdev->ddev, i);
  93                         }
  94                 }
  95         }
  96
  97         mutex_unlock(&rdev->vram_mutex);
  98
  99         /* update display watermarks based on new power state */
 100         radeon_update_bandwidth_info(rdev);
 101         if (rdev->pm.active_crtc_count)
 102                 radeon_bandwidth_update(rdev);
 103
 104         rdev->pm.planned_action = PM_ACTION_NONE;
 105
 106         mutex_unlock(&rdev->cp.mutex);
 107 }
 108
 109 static ssize_t radeon_get_power_state_static(struct device *dev,
 110                                              struct device_attribute *attr,
 111                                              char *buf)
 112 {
 113         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 114         struct radeon_device *rdev = ddev->dev_private;
 115
 116         return snprintf(buf, PAGE_SIZE, "%d.%d\n", rdev->pm.current_power_state_index,
 117                         rdev->pm.current_clock_mode_index);
 118 }
 119
 120 static ssize_t radeon_set_power_state_static(struct device *dev,
 121                                              struct device_attribute *attr,
 122                                              const char *buf,
 123                                              size_t count)
 124 {
 125         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 126         struct radeon_device *rdev = ddev->dev_private;
 127         int ps, cm;
 128
 129         if (sscanf(buf, "%u.%u", &ps, &cm) != 2) {
 130                 DRM_ERROR("Invalid power state!\n");
 131                 return count;
 132         }
 133
 134         mutex_lock(&rdev->pm.mutex);
 135         if ((ps >= 0) && (ps < rdev->pm.num_power_states) &&
 136             (cm >= 0) && (cm < rdev->pm.power_state[ps].num_clock_modes)) {
 137                 if ((rdev->pm.active_crtc_count > 1) &&
 138                     (rdev->pm.power_state[ps].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)) {
 139                         DRM_ERROR("Invalid power state for multi-head: %d.%d\n", ps, cm);
 140                 } else {
 141                         /* disable dynpm */
 142                         rdev->pm.state = PM_STATE_DISABLED;
 143                         rdev->pm.planned_action = PM_ACTION_NONE;
 144                         rdev->pm.requested_power_state_index = ps;
 145                         rdev->pm.requested_clock_mode_index = cm;
 146                         radeon_pm_set_clocks(rdev, true);
 147                 }
 148         } else
 149                 DRM_ERROR("Invalid power state: %d.%d\n\n", ps, cm);
 150         mutex_unlock(&rdev->pm.mutex);
 151
 152         return count;
 153 }
 154
 155 static ssize_t radeon_get_dynpm(struct device *dev,
 156                                 struct device_attribute *attr,
 157                                 char *buf)
 158 {
 159         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 160         struct radeon_device *rdev = ddev->dev_private;
 161
 162         return snprintf(buf, PAGE_SIZE, "%s\n",
 163                         (rdev->pm.state == PM_STATE_DISABLED) ? "disabled" : "enabled");
 164 }
 165
 166 static ssize_t radeon_set_dynpm(struct device *dev,
 167                                 struct device_attribute *attr,
 168                                 const char *buf,
 169                                 size_t count)
 170 {
 171         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 172         struct radeon_device *rdev = ddev->dev_private;
 173         int tmp = simple_strtoul(buf, NULL, 10);
 174
 175         if (tmp == 0) {
 176                 /* update power mode info */
 177                 radeon_pm_compute_clocks(rdev);
 178                 /* disable dynpm */
 179                 mutex_lock(&rdev->pm.mutex);
 180                 rdev->pm.state = PM_STATE_DISABLED;
 181                 rdev->pm.planned_action = PM_ACTION_NONE;
 182                 mutex_unlock(&rdev->pm.mutex);
 183                 DRM_INFO("radeon: dynamic power management disabled\n");
 184         } else if (tmp == 1) {
 185                 if (rdev->pm.num_power_states > 1) {
 186                         /* enable dynpm */
 187                         mutex_lock(&rdev->pm.mutex);
 188                         rdev->pm.state = PM_STATE_PAUSED;
 189                         rdev->pm.planned_action = PM_ACTION_DEFAULT;
 190                         radeon_get_power_state(rdev, rdev->pm.planned_action);
 191                         mutex_unlock(&rdev->pm.mutex);
 192                         /* update power mode info */
 193                         radeon_pm_compute_clocks(rdev);
 194                         DRM_INFO("radeon: dynamic power management enabled\n");
 195                 } else
 196                         DRM_ERROR("dynpm not valid on this system\n");
 197         } else
 198                 DRM_ERROR("Invalid setting: %d\n", tmp);
 199
 200         return count;
 201 }
 202
 203 static DEVICE_ATTR(power_state, S_IRUGO | S_IWUSR, radeon_get_power_state_static, radeon_set_power_state_static);
 204 static DEVICE_ATTR(dynpm, S_IRUGO | S_IWUSR, radeon_get_dynpm, radeon_set_dynpm);
 205
 206
 207 static const char *pm_state_names[4] = {
 208         "PM_STATE_DISABLED",
 209         "PM_STATE_MINIMUM",
 210         "PM_STATE_PAUSED",
 211         "PM_STATE_ACTIVE"
 212 };
 213
 214 static const char *pm_state_types[5] = {
 215         "",
 216         "Powersave",
 217         "Battery",
 218         "Balanced",
 219         "Performance",
 220 };
 221
 222 static void radeon_print_power_mode_info(struct radeon_device *rdev)
 223 {
 224         int i, j;
 225         bool is_default;
 226
 227         DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
 228         for (i = 0; i < rdev->pm.num_power_states; i++) {
 229                 if (rdev->pm.default_power_state_index == i)
 230                         is_default = true;
 231                 else
 232                         is_default = false;
 233                 DRM_INFO("State %d %s %s\n", i,
 234                          pm_state_types[rdev->pm.power_state[i].type],
 235                          is_default ? "(default)" : "");
 236                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 237                         DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].pcie_lanes);
 238                 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
 239                         DRM_INFO("\tSingle display only\n");
 240                 DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
 241                 for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
 242                         if (rdev->flags & RADEON_IS_IGP)
 243                                 DRM_INFO("\t\t%d engine: %d\n",
 244                                          j,
 245                                          rdev->pm.power_state[i].clock_info[j].sclk * 10);
 246                         else
 247                                 DRM_INFO("\t\t%d engine/memory: %d/%d\n",
 248                                          j,
 249                                          rdev->pm.power_state[i].clock_info[j].sclk * 10,
 250                                          rdev->pm.power_state[i].clock_info[j].mclk * 10);
 251                 }
 252         }
 253 }
 254
 255 void radeon_sync_with_vblank(struct radeon_device *rdev)
 256 {
 257         if (rdev->pm.active_crtcs) {
 258                 rdev->pm.vblank_sync = false;
 259                 wait_event_timeout(
 260                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 261                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 262         }
 263 }
 264
 265 int radeon_pm_init(struct radeon_device *rdev)
 266 {
 267         rdev->pm.state = PM_STATE_DISABLED;
 268         rdev->pm.planned_action = PM_ACTION_NONE;
 269         rdev->pm.can_upclock = true;
 270         rdev->pm.can_downclock = true;
 271
 272         if (rdev->bios) {
 273                 if (rdev->is_atom_bios)
 274                         radeon_atombios_get_power_modes(rdev);
 275                 else
 276                         radeon_combios_get_power_modes(rdev);
 277                 radeon_print_power_mode_info(rdev);
 278         }
 279
 280         if (radeon_debugfs_pm_init(rdev)) {
 281                 DRM_ERROR("Failed to register debugfs file for PM!\n");
 282         }
 283
 284         /* where's the best place to put this? */
 285         device_create_file(rdev->dev, &dev_attr_power_state);
 286         device_create_file(rdev->dev, &dev_attr_dynpm);
 287
 288         INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
 289
 290         if ((radeon_dynpm != -1 && radeon_dynpm) && (rdev->pm.num_power_states > 1)) {
 291                 rdev->pm.state = PM_STATE_PAUSED;
 292                 DRM_INFO("radeon: dynamic power management enabled\n");
 293         }
 294
 295         DRM_INFO("radeon: power management initialized\n");
 296
 297         return 0;
 298 }
 299
 300 void radeon_pm_fini(struct radeon_device *rdev)
 301 {
 302         if (rdev->pm.state != PM_STATE_DISABLED) {
 303                 /* cancel work */
 304                 cancel_delayed_work_sync(&rdev->pm.idle_work);
 305                 /* reset default clocks */
 306                 rdev->pm.state = PM_STATE_DISABLED;
 307                 rdev->pm.planned_action = PM_ACTION_DEFAULT;
 308                 radeon_pm_set_clocks(rdev, false);
 309         } else if ((rdev->pm.current_power_state_index !=
 310                     rdev->pm.default_power_state_index) ||
 311                    (rdev->pm.current_clock_mode_index != 0)) {
 312                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 313                 rdev->pm.requested_clock_mode_index = 0;
 314                 mutex_lock(&rdev->pm.mutex);
 315                 radeon_pm_set_clocks(rdev, true);
 316                 mutex_unlock(&rdev->pm.mutex);
 317         }
 318
 319         device_remove_file(rdev->dev, &dev_attr_power_state);
 320         device_remove_file(rdev->dev, &dev_attr_dynpm);
 321
 322         if (rdev->pm.i2c_bus)
 323                 radeon_i2c_destroy(rdev->pm.i2c_bus);
 324 }
 325
 326 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 327 {
 328         struct drm_device *ddev = rdev->ddev;
 329         struct drm_crtc *crtc;
 330         struct radeon_crtc *radeon_crtc;
 331
 332         if (rdev->pm.state == PM_STATE_DISABLED)
 333                 return;
 334
 335         mutex_lock(&rdev->pm.mutex);
 336
 337         rdev->pm.active_crtcs = 0;
 338         rdev->pm.active_crtc_count = 0;
 339         list_for_each_entry(crtc,
 340                 &ddev->mode_config.crtc_list, head) {
 341                 radeon_crtc = to_radeon_crtc(crtc);
 342                 if (radeon_crtc->enabled) {
 343                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 344                         rdev->pm.active_crtc_count++;
 345                 }
 346         }
 347
 348         if (rdev->pm.active_crtc_count > 1) {
 349                 if (rdev->pm.state == PM_STATE_ACTIVE) {
 350                         cancel_delayed_work(&rdev->pm.idle_work);
 351
 352                         rdev->pm.state = PM_STATE_PAUSED;
 353                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 354                         radeon_pm_set_clocks(rdev, false);
 355
 356                         DRM_DEBUG("radeon: dynamic power management deactivated\n");
 357                 }
 358         } else if (rdev->pm.active_crtc_count == 1) {
 359                 /* TODO: Increase clocks if needed for current mode */
 360
 361                 if (rdev->pm.state == PM_STATE_MINIMUM) {
 362                         rdev->pm.state = PM_STATE_ACTIVE;
 363                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 364                         radeon_pm_set_clocks(rdev, false);
 365
 366                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 367                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 368                 } else if (rdev->pm.state == PM_STATE_PAUSED) {
 369                         rdev->pm.state = PM_STATE_ACTIVE;
 370                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 371                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 372                         DRM_DEBUG("radeon: dynamic power management activated\n");
 373                 }
 374         } else { /* count == 0 */
 375                 if (rdev->pm.state != PM_STATE_MINIMUM) {
 376                         cancel_delayed_work(&rdev->pm.idle_work);
 377
 378                         rdev->pm.state = PM_STATE_MINIMUM;
 379                         rdev->pm.planned_action = PM_ACTION_MINIMUM;
 380                         radeon_pm_set_clocks(rdev, false);
 381                 }
 382         }
 383
 384         mutex_unlock(&rdev->pm.mutex);
 385 }
 386
 387 bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 388 {
 389         u32 stat_crtc = 0;
 390         bool in_vbl = true;
 391
 392         if (ASIC_IS_DCE4(rdev)) {
 393                 if (rdev->pm.active_crtcs & (1 << 0)) {
 394                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
 395                         if (!(stat_crtc & 1))
 396                                 in_vbl = false;
 397                 }
 398                 if (rdev->pm.active_crtcs & (1 << 1)) {
 399                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
 400                         if (!(stat_crtc & 1))
 401                                 in_vbl = false;
 402                 }
 403                 if (rdev->pm.active_crtcs & (1 << 2)) {
 404                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
 405                         if (!(stat_crtc & 1))
 406                                 in_vbl = false;
 407                 }
 408                 if (rdev->pm.active_crtcs & (1 << 3)) {
 409                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
 410                         if (!(stat_crtc & 1))
 411                                 in_vbl = false;
 412                 }
 413                 if (rdev->pm.active_crtcs & (1 << 4)) {
 414                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
 415                         if (!(stat_crtc & 1))
 416                                 in_vbl = false;
 417                 }
 418                 if (rdev->pm.active_crtcs & (1 << 5)) {
 419                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
 420                         if (!(stat_crtc & 1))
 421                                 in_vbl = false;
 422                 }
 423         } else if (ASIC_IS_AVIVO(rdev)) {
 424                 if (rdev->pm.active_crtcs & (1 << 0)) {
 425                         stat_crtc = RREG32(D1CRTC_STATUS);
 426                         if (!(stat_crtc & 1))
 427                                 in_vbl = false;
 428                 }
 429                 if (rdev->pm.active_crtcs & (1 << 1)) {
 430                         stat_crtc = RREG32(D2CRTC_STATUS);
 431                         if (!(stat_crtc & 1))
 432                                 in_vbl = false;
 433                 }
 434         } else {
 435                 if (rdev->pm.active_crtcs & (1 << 0)) {
 436                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
 437                         if (!(stat_crtc & 1))
 438                                 in_vbl = false;
 439                 }
 440                 if (rdev->pm.active_crtcs & (1 << 1)) {
 441                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
 442                         if (!(stat_crtc & 1))
 443                                 in_vbl = false;
 444                 }
 445         }
 446         if (in_vbl == false)
 447                 DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc,
 448                          finish ? "exit" : "entry");
 449         return in_vbl;
 450 }
 451
 452 static void radeon_pm_idle_work_handler(struct work_struct *work)
 453 {
 454         struct radeon_device *rdev;
 455         rdev = container_of(work, struct radeon_device,
 456                                 pm.idle_work.work);
 457
 458         mutex_lock(&rdev->pm.mutex);
 459         if (rdev->pm.state == PM_STATE_ACTIVE) {
 460                 unsigned long irq_flags;
 461                 int not_processed = 0;
 462
 463                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
 464                 if (!list_empty(&rdev->fence_drv.emited)) {
 465                         struct list_head *ptr;
 466                         list_for_each(ptr, &rdev->fence_drv.emited) {
 467                                 /* count up to 3, that's enought info */
 468                                 if (++not_processed >= 3)
 469                                         break;
 470                         }
 471                 }
 472                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
 473
 474                 if (not_processed >= 3) { /* should upclock */
 475                         if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
 476                                 rdev->pm.planned_action = PM_ACTION_NONE;
 477                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 478                                    rdev->pm.can_upclock) {
 479                                 rdev->pm.planned_action =
 480                                         PM_ACTION_UPCLOCK;
 481                                 rdev->pm.action_timeout = jiffies +
 482                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 483                         }
 484                 } else if (not_processed == 0) { /* should downclock */
 485                         if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
 486                                 rdev->pm.planned_action = PM_ACTION_NONE;
 487                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 488                                    rdev->pm.can_downclock) {
 489                                 rdev->pm.planned_action =
 490                                         PM_ACTION_DOWNCLOCK;
 491                                 rdev->pm.action_timeout = jiffies +
 492                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 493                         }
 494                 }
 495
 496                 if (rdev->pm.planned_action != PM_ACTION_NONE &&
 497                     jiffies > rdev->pm.action_timeout) {
 498                         radeon_pm_set_clocks(rdev, false);
 499                 }
 500         }
 501         mutex_unlock(&rdev->pm.mutex);
 502
 503         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 504                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 505 }
 506
 507 /*
 508  * Debugfs info
 509  */
 510 #if defined(CONFIG_DEBUG_FS)
 511
 512 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 513 {
 514         struct drm_info_node *node = (struct drm_info_node *) m->private;
 515         struct drm_device *dev = node->minor->dev;
 516         struct radeon_device *rdev = dev->dev_private;
 517
 518         seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
 519         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
 520         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 521         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
 522         if (rdev->asic->get_memory_clock)
 523                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 524         if (rdev->asic->get_pcie_lanes)
 525                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 526
 527         return 0;
 528 }
 529
 530 static struct drm_info_list radeon_pm_info_list[] = {
 531         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 532 };
 533 #endif
 534
 535 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 536 {
 537 #if defined(CONFIG_DEBUG_FS)
 538         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 539 #else
 540         return 0;
 541 #endif
 542 }