3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
20 #include <asm/errno.h>
26 static int pci_msi_enable
= 1;
30 #ifndef arch_msi_check_device
31 int arch_msi_check_device(struct pci_dev
*dev
, int nvec
, int type
)
37 #ifndef arch_setup_msi_irqs
38 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
40 struct msi_desc
*entry
;
44 * If an architecture wants to support multiple MSI, it needs to
45 * override arch_setup_msi_irqs()
47 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
50 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
51 ret
= arch_setup_msi_irq(dev
, entry
);
62 #ifndef arch_teardown_msi_irqs
63 void arch_teardown_msi_irqs(struct pci_dev
*dev
)
65 struct msi_desc
*entry
;
67 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
71 nvec
= 1 << entry
->msi_attrib
.multiple
;
72 for (i
= 0; i
< nvec
; i
++)
73 arch_teardown_msi_irq(entry
->irq
+ i
);
78 static void msi_set_enable(struct pci_dev
*dev
, int pos
, int enable
)
84 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
85 control
&= ~PCI_MSI_FLAGS_ENABLE
;
87 control
|= PCI_MSI_FLAGS_ENABLE
;
88 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
91 static void msix_set_enable(struct pci_dev
*dev
, int enable
)
96 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
98 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
99 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
101 control
|= PCI_MSIX_FLAGS_ENABLE
;
102 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
106 static inline __attribute_const__ u32
msi_mask(unsigned x
)
108 /* Don't shift by >= width of type */
111 return (1 << (1 << x
)) - 1;
114 static inline __attribute_const__ u32
msi_capable_mask(u16 control
)
116 return msi_mask((control
>> 1) & 7);
119 static inline __attribute_const__ u32
msi_enabled_mask(u16 control
)
121 return msi_mask((control
>> 4) & 7);
125 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
126 * mask all MSI interrupts by clearing the MSI enable bit does not work
127 * reliably as devices without an INTx disable bit will then generate a
128 * level IRQ which will never be cleared.
130 static u32
__msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
132 u32 mask_bits
= desc
->masked
;
134 if (!desc
->msi_attrib
.maskbit
)
139 pci_write_config_dword(desc
->dev
, desc
->mask_pos
, mask_bits
);
144 static void msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
146 desc
->masked
= __msi_mask_irq(desc
, mask
, flag
);
150 * This internal function does not flush PCI writes to the device.
151 * All users must ensure that they read from the device before either
152 * assuming that the device state is up to date, or returning out of this
153 * file. This saves a few milliseconds when initialising devices with lots
154 * of MSI-X interrupts.
156 static u32
__msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
158 u32 mask_bits
= desc
->masked
;
159 unsigned offset
= desc
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
+
160 PCI_MSIX_ENTRY_VECTOR_CTRL
;
163 writel(mask_bits
, desc
->mask_base
+ offset
);
168 static void msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
170 desc
->masked
= __msix_mask_irq(desc
, flag
);
173 static void msi_set_mask_bit(unsigned irq
, u32 flag
)
175 struct msi_desc
*desc
= get_irq_msi(irq
);
177 if (desc
->msi_attrib
.is_msix
) {
178 msix_mask_irq(desc
, flag
);
179 readl(desc
->mask_base
); /* Flush write to device */
181 unsigned offset
= irq
- desc
->dev
->irq
;
182 msi_mask_irq(desc
, 1 << offset
, flag
<< offset
);
186 void mask_msi_irq(unsigned int irq
)
188 msi_set_mask_bit(irq
, 1);
191 void unmask_msi_irq(unsigned int irq
)
193 msi_set_mask_bit(irq
, 0);
196 void read_msi_msg_desc(struct irq_desc
*desc
, struct msi_msg
*msg
)
198 struct msi_desc
*entry
= get_irq_desc_msi(desc
);
199 if (entry
->msi_attrib
.is_msix
) {
200 void __iomem
*base
= entry
->mask_base
+
201 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
203 msg
->address_lo
= readl(base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
204 msg
->address_hi
= readl(base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
205 msg
->data
= readl(base
+ PCI_MSIX_ENTRY_DATA
);
207 struct pci_dev
*dev
= entry
->dev
;
208 int pos
= entry
->msi_attrib
.pos
;
211 pci_read_config_dword(dev
, msi_lower_address_reg(pos
),
213 if (entry
->msi_attrib
.is_64
) {
214 pci_read_config_dword(dev
, msi_upper_address_reg(pos
),
216 pci_read_config_word(dev
, msi_data_reg(pos
, 1), &data
);
219 pci_read_config_word(dev
, msi_data_reg(pos
, 0), &data
);
225 void read_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
227 struct irq_desc
*desc
= irq_to_desc(irq
);
229 read_msi_msg_desc(desc
, msg
);
232 void write_msi_msg_desc(struct irq_desc
*desc
, struct msi_msg
*msg
)
234 struct msi_desc
*entry
= get_irq_desc_msi(desc
);
235 if (entry
->msi_attrib
.is_msix
) {
237 base
= entry
->mask_base
+
238 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
240 writel(msg
->address_lo
, base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
241 writel(msg
->address_hi
, base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
242 writel(msg
->data
, base
+ PCI_MSIX_ENTRY_DATA
);
244 struct pci_dev
*dev
= entry
->dev
;
245 int pos
= entry
->msi_attrib
.pos
;
248 pci_read_config_word(dev
, msi_control_reg(pos
), &msgctl
);
249 msgctl
&= ~PCI_MSI_FLAGS_QSIZE
;
250 msgctl
|= entry
->msi_attrib
.multiple
<< 4;
251 pci_write_config_word(dev
, msi_control_reg(pos
), msgctl
);
253 pci_write_config_dword(dev
, msi_lower_address_reg(pos
),
255 if (entry
->msi_attrib
.is_64
) {
256 pci_write_config_dword(dev
, msi_upper_address_reg(pos
),
258 pci_write_config_word(dev
, msi_data_reg(pos
, 1),
261 pci_write_config_word(dev
, msi_data_reg(pos
, 0),
268 void write_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
270 struct irq_desc
*desc
= irq_to_desc(irq
);
272 write_msi_msg_desc(desc
, msg
);
275 static void free_msi_irqs(struct pci_dev
*dev
)
277 struct msi_desc
*entry
, *tmp
;
279 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
283 nvec
= 1 << entry
->msi_attrib
.multiple
;
284 for (i
= 0; i
< nvec
; i
++)
285 BUG_ON(irq_has_action(entry
->irq
+ i
));
288 arch_teardown_msi_irqs(dev
);
290 list_for_each_entry_safe(entry
, tmp
, &dev
->msi_list
, list
) {
291 if (entry
->msi_attrib
.is_msix
) {
292 if (list_is_last(&entry
->list
, &dev
->msi_list
))
293 iounmap(entry
->mask_base
);
295 list_del(&entry
->list
);
300 static struct msi_desc
*alloc_msi_entry(struct pci_dev
*dev
)
302 struct msi_desc
*desc
= kzalloc(sizeof(*desc
), GFP_KERNEL
);
306 INIT_LIST_HEAD(&desc
->list
);
312 static void pci_intx_for_msi(struct pci_dev
*dev
, int enable
)
314 if (!(dev
->dev_flags
& PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
))
315 pci_intx(dev
, enable
);
318 static void __pci_restore_msi_state(struct pci_dev
*dev
)
322 struct msi_desc
*entry
;
324 if (!dev
->msi_enabled
)
327 entry
= get_irq_msi(dev
->irq
);
328 pos
= entry
->msi_attrib
.pos
;
330 pci_intx_for_msi(dev
, 0);
331 msi_set_enable(dev
, pos
, 0);
332 write_msi_msg(dev
->irq
, &entry
->msg
);
334 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
335 msi_mask_irq(entry
, msi_capable_mask(control
), entry
->masked
);
336 control
&= ~PCI_MSI_FLAGS_QSIZE
;
337 control
|= (entry
->msi_attrib
.multiple
<< 4) | PCI_MSI_FLAGS_ENABLE
;
338 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
341 static void __pci_restore_msix_state(struct pci_dev
*dev
)
344 struct msi_desc
*entry
;
347 if (!dev
->msix_enabled
)
349 BUG_ON(list_empty(&dev
->msi_list
));
350 entry
= list_first_entry(&dev
->msi_list
, struct msi_desc
, list
);
351 pos
= entry
->msi_attrib
.pos
;
352 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
354 /* route the table */
355 pci_intx_for_msi(dev
, 0);
356 control
|= PCI_MSIX_FLAGS_ENABLE
| PCI_MSIX_FLAGS_MASKALL
;
357 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
359 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
360 write_msi_msg(entry
->irq
, &entry
->msg
);
361 msix_mask_irq(entry
, entry
->masked
);
364 control
&= ~PCI_MSIX_FLAGS_MASKALL
;
365 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
368 void pci_restore_msi_state(struct pci_dev
*dev
)
370 __pci_restore_msi_state(dev
);
371 __pci_restore_msix_state(dev
);
373 EXPORT_SYMBOL_GPL(pci_restore_msi_state
);
376 * msi_capability_init - configure device's MSI capability structure
377 * @dev: pointer to the pci_dev data structure of MSI device function
378 * @nvec: number of interrupts to allocate
380 * Setup the MSI capability structure of the device with the requested
381 * number of interrupts. A return value of zero indicates the successful
382 * setup of an entry with the new MSI irq. A negative return value indicates
383 * an error, and a positive return value indicates the number of interrupts
384 * which could have been allocated.
386 static int msi_capability_init(struct pci_dev
*dev
, int nvec
)
388 struct msi_desc
*entry
;
393 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
394 msi_set_enable(dev
, pos
, 0); /* Disable MSI during set up */
396 pci_read_config_word(dev
, msi_control_reg(pos
), &control
);
397 /* MSI Entry Initialization */
398 entry
= alloc_msi_entry(dev
);
402 entry
->msi_attrib
.is_msix
= 0;
403 entry
->msi_attrib
.is_64
= is_64bit_address(control
);
404 entry
->msi_attrib
.entry_nr
= 0;
405 entry
->msi_attrib
.maskbit
= is_mask_bit_support(control
);
406 entry
->msi_attrib
.default_irq
= dev
->irq
; /* Save IOAPIC IRQ */
407 entry
->msi_attrib
.pos
= pos
;
409 entry
->mask_pos
= msi_mask_reg(pos
, entry
->msi_attrib
.is_64
);
410 /* All MSIs are unmasked by default, Mask them all */
411 if (entry
->msi_attrib
.maskbit
)
412 pci_read_config_dword(dev
, entry
->mask_pos
, &entry
->masked
);
413 mask
= msi_capable_mask(control
);
414 msi_mask_irq(entry
, mask
, mask
);
416 list_add_tail(&entry
->list
, &dev
->msi_list
);
418 /* Configure MSI capability structure */
419 ret
= arch_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSI
);
421 msi_mask_irq(entry
, mask
, ~mask
);
426 /* Set MSI enabled bits */
427 pci_intx_for_msi(dev
, 0);
428 msi_set_enable(dev
, pos
, 1);
429 dev
->msi_enabled
= 1;
431 dev
->irq
= entry
->irq
;
436 * msix_capability_init - configure device's MSI-X capability
437 * @dev: pointer to the pci_dev data structure of MSI-X device function
438 * @entries: pointer to an array of struct msix_entry entries
439 * @nvec: number of @entries
441 * Setup the MSI-X capability structure of device function with a
442 * single MSI-X irq. A return of zero indicates the successful setup of
443 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
445 static int msix_capability_init(struct pci_dev
*dev
,
446 struct msix_entry
*entries
, int nvec
)
448 struct msi_desc
*entry
;
449 int pos
, i
, j
, nr_entries
, ret
;
450 unsigned long phys_addr
;
456 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
457 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
459 /* Ensure MSI-X is disabled while it is set up */
460 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
461 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
463 /* Request & Map MSI-X table region */
464 nr_entries
= multi_msix_capable(control
);
466 pci_read_config_dword(dev
, msix_table_offset_reg(pos
), &table_offset
);
467 bir
= (u8
)(table_offset
& PCI_MSIX_FLAGS_BIRMASK
);
468 table_offset
&= ~PCI_MSIX_FLAGS_BIRMASK
;
469 phys_addr
= pci_resource_start (dev
, bir
) + table_offset
;
470 base
= ioremap_nocache(phys_addr
, nr_entries
* PCI_MSIX_ENTRY_SIZE
);
474 for (i
= 0; i
< nvec
; i
++) {
475 entry
= alloc_msi_entry(dev
);
481 /* No enough memory. Don't try again */
485 j
= entries
[i
].entry
;
486 entry
->msi_attrib
.is_msix
= 1;
487 entry
->msi_attrib
.is_64
= 1;
488 entry
->msi_attrib
.entry_nr
= j
;
489 entry
->msi_attrib
.default_irq
= dev
->irq
;
490 entry
->msi_attrib
.pos
= pos
;
491 entry
->mask_base
= base
;
493 list_add_tail(&entry
->list
, &dev
->msi_list
);
496 ret
= arch_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSIX
);
501 * Some devices require MSI-X to be enabled before we can touch the
502 * MSI-X registers. We need to mask all the vectors to prevent
503 * interrupts coming in before they're fully set up.
505 control
|= PCI_MSIX_FLAGS_MASKALL
| PCI_MSIX_FLAGS_ENABLE
;
506 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
509 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
510 entries
[i
].vector
= entry
->irq
;
511 set_irq_msi(entry
->irq
, entry
);
512 j
= entries
[i
].entry
;
513 entry
->masked
= readl(base
+ j
* PCI_MSIX_ENTRY_SIZE
+
514 PCI_MSIX_ENTRY_VECTOR_CTRL
);
515 msix_mask_irq(entry
, 1);
519 /* Set MSI-X enabled bits and unmask the function */
520 pci_intx_for_msi(dev
, 0);
521 dev
->msix_enabled
= 1;
523 control
&= ~PCI_MSIX_FLAGS_MASKALL
;
524 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
531 * If we had some success, report the number of irqs
532 * we succeeded in setting up.
536 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
550 * pci_msi_check_device - check whether MSI may be enabled on a device
551 * @dev: pointer to the pci_dev data structure of MSI device function
552 * @nvec: how many MSIs have been requested ?
553 * @type: are we checking for MSI or MSI-X ?
555 * Look at global flags, the device itself, and its parent busses
556 * to determine if MSI/-X are supported for the device. If MSI/-X is
557 * supported return 0, else return an error code.
559 static int pci_msi_check_device(struct pci_dev
* dev
, int nvec
, int type
)
564 /* MSI must be globally enabled and supported by the device */
565 if (!pci_msi_enable
|| !dev
|| dev
->no_msi
)
569 * You can't ask to have 0 or less MSIs configured.
571 * b) the list manipulation code assumes nvec >= 1.
576 /* Any bridge which does NOT route MSI transactions from it's
577 * secondary bus to it's primary bus must set NO_MSI flag on
578 * the secondary pci_bus.
579 * We expect only arch-specific PCI host bus controller driver
580 * or quirks for specific PCI bridges to be setting NO_MSI.
582 for (bus
= dev
->bus
; bus
; bus
= bus
->parent
)
583 if (bus
->bus_flags
& PCI_BUS_FLAGS_NO_MSI
)
586 ret
= arch_msi_check_device(dev
, nvec
, type
);
590 if (!pci_find_capability(dev
, type
))
597 * pci_enable_msi_block - configure device's MSI capability structure
598 * @dev: device to configure
599 * @nvec: number of interrupts to configure
601 * Allocate IRQs for a device with the MSI capability.
602 * This function returns a negative errno if an error occurs. If it
603 * is unable to allocate the number of interrupts requested, it returns
604 * the number of interrupts it might be able to allocate. If it successfully
605 * allocates at least the number of interrupts requested, it returns 0 and
606 * updates the @dev's irq member to the lowest new interrupt number; the
607 * other interrupt numbers allocated to this device are consecutive.
609 int pci_enable_msi_block(struct pci_dev
*dev
, unsigned int nvec
)
611 int status
, pos
, maxvec
;
614 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
617 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &msgctl
);
618 maxvec
= 1 << ((msgctl
& PCI_MSI_FLAGS_QMASK
) >> 1);
622 status
= pci_msi_check_device(dev
, nvec
, PCI_CAP_ID_MSI
);
626 WARN_ON(!!dev
->msi_enabled
);
628 /* Check whether driver already requested MSI-X irqs */
629 if (dev
->msix_enabled
) {
630 dev_info(&dev
->dev
, "can't enable MSI "
631 "(MSI-X already enabled)\n");
635 status
= msi_capability_init(dev
, nvec
);
638 EXPORT_SYMBOL(pci_enable_msi_block
);
640 void pci_msi_shutdown(struct pci_dev
*dev
)
642 struct msi_desc
*desc
;
647 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
650 BUG_ON(list_empty(&dev
->msi_list
));
651 desc
= list_first_entry(&dev
->msi_list
, struct msi_desc
, list
);
652 pos
= desc
->msi_attrib
.pos
;
654 msi_set_enable(dev
, pos
, 0);
655 pci_intx_for_msi(dev
, 1);
656 dev
->msi_enabled
= 0;
658 /* Return the device with MSI unmasked as initial states */
659 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &ctrl
);
660 mask
= msi_capable_mask(ctrl
);
661 /* Keep cached state to be restored */
662 __msi_mask_irq(desc
, mask
, ~mask
);
664 /* Restore dev->irq to its default pin-assertion irq */
665 dev
->irq
= desc
->msi_attrib
.default_irq
;
668 void pci_disable_msi(struct pci_dev
* dev
)
670 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
673 pci_msi_shutdown(dev
);
676 EXPORT_SYMBOL(pci_disable_msi
);
679 * pci_msix_table_size - return the number of device's MSI-X table entries
680 * @dev: pointer to the pci_dev data structure of MSI-X device function
682 int pci_msix_table_size(struct pci_dev
*dev
)
687 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
691 pci_read_config_word(dev
, msi_control_reg(pos
), &control
);
692 return multi_msix_capable(control
);
696 * pci_enable_msix - configure device's MSI-X capability structure
697 * @dev: pointer to the pci_dev data structure of MSI-X device function
698 * @entries: pointer to an array of MSI-X entries
699 * @nvec: number of MSI-X irqs requested for allocation by device driver
701 * Setup the MSI-X capability structure of device function with the number
702 * of requested irqs upon its software driver call to request for
703 * MSI-X mode enabled on its hardware device function. A return of zero
704 * indicates the successful configuration of MSI-X capability structure
705 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
706 * Or a return of > 0 indicates that driver request is exceeding the number
707 * of irqs or MSI-X vectors available. Driver should use the returned value to
708 * re-send its request.
710 int pci_enable_msix(struct pci_dev
* dev
, struct msix_entry
*entries
, int nvec
)
712 int status
, nr_entries
;
718 status
= pci_msi_check_device(dev
, nvec
, PCI_CAP_ID_MSIX
);
722 nr_entries
= pci_msix_table_size(dev
);
723 if (nvec
> nr_entries
)
726 /* Check for any invalid entries */
727 for (i
= 0; i
< nvec
; i
++) {
728 if (entries
[i
].entry
>= nr_entries
)
729 return -EINVAL
; /* invalid entry */
730 for (j
= i
+ 1; j
< nvec
; j
++) {
731 if (entries
[i
].entry
== entries
[j
].entry
)
732 return -EINVAL
; /* duplicate entry */
735 WARN_ON(!!dev
->msix_enabled
);
737 /* Check whether driver already requested for MSI irq */
738 if (dev
->msi_enabled
) {
739 dev_info(&dev
->dev
, "can't enable MSI-X "
740 "(MSI IRQ already assigned)\n");
743 status
= msix_capability_init(dev
, entries
, nvec
);
746 EXPORT_SYMBOL(pci_enable_msix
);
748 void pci_msix_shutdown(struct pci_dev
* dev
)
750 struct msi_desc
*entry
;
752 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
755 /* Return the device with MSI-X masked as initial states */
756 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
757 /* Keep cached states to be restored */
758 __msix_mask_irq(entry
, 1);
761 msix_set_enable(dev
, 0);
762 pci_intx_for_msi(dev
, 1);
763 dev
->msix_enabled
= 0;
766 void pci_disable_msix(struct pci_dev
* dev
)
768 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
771 pci_msix_shutdown(dev
);
774 EXPORT_SYMBOL(pci_disable_msix
);
777 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
778 * @dev: pointer to the pci_dev data structure of MSI(X) device function
780 * Being called during hotplug remove, from which the device function
781 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
782 * allocated for this device function, are reclaimed to unused state,
783 * which may be used later on.
785 void msi_remove_pci_irq_vectors(struct pci_dev
* dev
)
787 if (!pci_msi_enable
|| !dev
)
790 if (dev
->msi_enabled
|| dev
->msix_enabled
)
794 void pci_no_msi(void)
800 * pci_msi_enabled - is MSI enabled?
802 * Returns true if MSI has not been disabled by the command-line option
805 int pci_msi_enabled(void)
807 return pci_msi_enable
;
809 EXPORT_SYMBOL(pci_msi_enabled
);
811 void pci_msi_init_pci_dev(struct pci_dev
*dev
)
813 INIT_LIST_HEAD(&dev
->msi_list
);