2 * Handles the Intel 27x USB Device Controller (UDC)
4 * Inspired by original driver by Frank Becker, David Brownell, and others.
5 * Copyright (C) 2008 Robert Jarzmik
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/types.h>
25 #include <linux/errno.h>
26 #include <linux/platform_device.h>
27 #include <linux/delay.h>
28 #include <linux/list.h>
29 #include <linux/interrupt.h>
30 #include <linux/proc_fs.h>
31 #include <linux/clk.h>
32 #include <linux/irq.h>
34 #include <asm/byteorder.h>
35 #include <mach/hardware.h>
37 #include <linux/usb.h>
38 #include <linux/usb/ch9.h>
39 #include <linux/usb/gadget.h>
40 #include <mach/pxa2xx-regs.h> /* FIXME: for PSSR */
43 #include "pxa27x_udc.h"
46 * This driver handles the USB Device Controller (UDC) in Intel's PXA 27x
49 * Such controller drivers work with a gadget driver. The gadget driver
50 * returns descriptors, implements configuration and data protocols used
51 * by the host to interact with this device, and allocates endpoints to
52 * the different protocol interfaces. The controller driver virtualizes
53 * usb hardware so that the gadget drivers will be more portable.
55 * This UDC hardware wants to implement a bit too much USB protocol. The
56 * biggest issues are: that the endpoints have to be set up before the
57 * controller can be enabled (minor, and not uncommon); and each endpoint
58 * can only have one configuration, interface and alternative interface
59 * number (major, and very unusual). Once set up, these cannot be changed
60 * without a controller reset.
62 * The workaround is to setup all combinations necessary for the gadgets which
63 * will work with this driver. This is done in pxa_udc structure, statically.
64 * See pxa_udc, udc_usb_ep versus pxa_ep, and matching function find_pxa_ep.
65 * (You could modify this if needed. Some drivers have a "fifo_mode" module
66 * parameter to facilitate such changes.)
68 * The combinations have been tested with these gadgets :
70 * - file storage gadget
73 * The driver doesn't use DMA, only IO access and IRQ callbacks. No use is
74 * made of UDC's double buffering either. USB "On-The-Go" is not implemented.
76 * All the requests are handled the same way :
77 * - the drivers tries to handle the request directly to the IO
78 * - if the IO fifo is not big enough, the remaining is send/received in
82 #define DRIVER_VERSION "2008-04-18"
83 #define DRIVER_DESC "PXA 27x USB Device Controller driver"
85 static const char driver_name
[] = "pxa27x_udc";
86 static struct pxa_udc
*the_controller
;
88 static void handle_ep(struct pxa_ep
*ep
);
93 #ifdef CONFIG_USB_GADGET_DEBUG_FS
95 #include <linux/debugfs.h>
96 #include <linux/uaccess.h>
97 #include <linux/seq_file.h>
99 static int state_dbg_show(struct seq_file
*s
, void *p
)
101 struct pxa_udc
*udc
= s
->private;
109 /* basic device status */
110 pos
+= seq_printf(s
, DRIVER_DESC
"\n"
111 "%s version: %s\nGadget driver: %s\n",
112 driver_name
, DRIVER_VERSION
,
113 udc
->driver
? udc
->driver
->driver
.name
: "(none)");
115 tmp
= udc_readl(udc
, UDCCR
);
117 "udccr=0x%0x(%s%s%s%s%s%s%s%s%s%s), "
118 "con=%d,inter=%d,altinter=%d\n", tmp
,
119 (tmp
& UDCCR_OEN
) ? " oen":"",
120 (tmp
& UDCCR_AALTHNP
) ? " aalthnp":"",
121 (tmp
& UDCCR_AHNP
) ? " rem" : "",
122 (tmp
& UDCCR_BHNP
) ? " rstir" : "",
123 (tmp
& UDCCR_DWRE
) ? " dwre" : "",
124 (tmp
& UDCCR_SMAC
) ? " smac" : "",
125 (tmp
& UDCCR_EMCE
) ? " emce" : "",
126 (tmp
& UDCCR_UDR
) ? " udr" : "",
127 (tmp
& UDCCR_UDA
) ? " uda" : "",
128 (tmp
& UDCCR_UDE
) ? " ude" : "",
129 (tmp
& UDCCR_ACN
) >> UDCCR_ACN_S
,
130 (tmp
& UDCCR_AIN
) >> UDCCR_AIN_S
,
131 (tmp
& UDCCR_AAISN
) >> UDCCR_AAISN_S
);
132 /* registers for device and ep0 */
133 pos
+= seq_printf(s
, "udcicr0=0x%08x udcicr1=0x%08x\n",
134 udc_readl(udc
, UDCICR0
), udc_readl(udc
, UDCICR1
));
135 pos
+= seq_printf(s
, "udcisr0=0x%08x udcisr1=0x%08x\n",
136 udc_readl(udc
, UDCISR0
), udc_readl(udc
, UDCISR1
));
137 pos
+= seq_printf(s
, "udcfnr=%d\n", udc_readl(udc
, UDCFNR
));
138 pos
+= seq_printf(s
, "irqs: reset=%lu, suspend=%lu, resume=%lu, "
140 udc
->stats
.irqs_reset
, udc
->stats
.irqs_suspend
,
141 udc
->stats
.irqs_resume
, udc
->stats
.irqs_reconfig
);
148 static int queues_dbg_show(struct seq_file
*s
, void *p
)
150 struct pxa_udc
*udc
= s
->private;
152 struct pxa27x_request
*req
;
153 int pos
= 0, i
, maxpkt
, ret
;
159 /* dump endpoint queues */
160 for (i
= 0; i
< NR_PXA_ENDPOINTS
; i
++) {
161 ep
= &udc
->pxa_ep
[i
];
162 maxpkt
= ep
->fifo_size
;
163 pos
+= seq_printf(s
, "%-12s max_pkt=%d %s\n",
164 EPNAME(ep
), maxpkt
, "pio");
166 if (list_empty(&ep
->queue
)) {
167 pos
+= seq_printf(s
, "\t(nothing queued)\n");
171 list_for_each_entry(req
, &ep
->queue
, queue
) {
172 pos
+= seq_printf(s
, "\treq %p len %d/%d buf %p\n",
173 &req
->req
, req
->req
.actual
,
174 req
->req
.length
, req
->req
.buf
);
183 static int eps_dbg_show(struct seq_file
*s
, void *p
)
185 struct pxa_udc
*udc
= s
->private;
194 ep
= &udc
->pxa_ep
[0];
195 tmp
= udc_ep_readl(ep
, UDCCSR
);
196 pos
+= seq_printf(s
, "udccsr0=0x%03x(%s%s%s%s%s%s%s)\n", tmp
,
197 (tmp
& UDCCSR0_SA
) ? " sa" : "",
198 (tmp
& UDCCSR0_RNE
) ? " rne" : "",
199 (tmp
& UDCCSR0_FST
) ? " fst" : "",
200 (tmp
& UDCCSR0_SST
) ? " sst" : "",
201 (tmp
& UDCCSR0_DME
) ? " dme" : "",
202 (tmp
& UDCCSR0_IPR
) ? " ipr" : "",
203 (tmp
& UDCCSR0_OPC
) ? " opc" : "");
204 for (i
= 0; i
< NR_PXA_ENDPOINTS
; i
++) {
205 ep
= &udc
->pxa_ep
[i
];
206 tmp
= i
? udc_ep_readl(ep
, UDCCR
) : udc_readl(udc
, UDCCR
);
207 pos
+= seq_printf(s
, "%-12s: "
208 "IN %lu(%lu reqs), OUT %lu(%lu reqs), "
209 "irqs=%lu, udccr=0x%08x, udccsr=0x%03x, "
212 ep
->stats
.in_bytes
, ep
->stats
.in_ops
,
213 ep
->stats
.out_bytes
, ep
->stats
.out_ops
,
215 tmp
, udc_ep_readl(ep
, UDCCSR
),
216 udc_ep_readl(ep
, UDCBCR
));
224 static int eps_dbg_open(struct inode
*inode
, struct file
*file
)
226 return single_open(file
, eps_dbg_show
, inode
->i_private
);
229 static int queues_dbg_open(struct inode
*inode
, struct file
*file
)
231 return single_open(file
, queues_dbg_show
, inode
->i_private
);
234 static int state_dbg_open(struct inode
*inode
, struct file
*file
)
236 return single_open(file
, state_dbg_show
, inode
->i_private
);
239 static const struct file_operations state_dbg_fops
= {
240 .owner
= THIS_MODULE
,
241 .open
= state_dbg_open
,
244 .release
= single_release
,
247 static const struct file_operations queues_dbg_fops
= {
248 .owner
= THIS_MODULE
,
249 .open
= queues_dbg_open
,
252 .release
= single_release
,
255 static const struct file_operations eps_dbg_fops
= {
256 .owner
= THIS_MODULE
,
257 .open
= eps_dbg_open
,
260 .release
= single_release
,
263 static void pxa_init_debugfs(struct pxa_udc
*udc
)
265 struct dentry
*root
, *state
, *queues
, *eps
;
267 root
= debugfs_create_dir(udc
->gadget
.name
, NULL
);
268 if (IS_ERR(root
) || !root
)
271 state
= debugfs_create_file("udcstate", 0400, root
, udc
,
275 queues
= debugfs_create_file("queues", 0400, root
, udc
,
279 eps
= debugfs_create_file("epstate", 0400, root
, udc
,
284 udc
->debugfs_root
= root
;
285 udc
->debugfs_state
= state
;
286 udc
->debugfs_queues
= queues
;
287 udc
->debugfs_eps
= eps
;
292 debugfs_remove(queues
);
294 debugfs_remove(root
);
296 dev_err(udc
->dev
, "debugfs is not available\n");
299 static void pxa_cleanup_debugfs(struct pxa_udc
*udc
)
301 debugfs_remove(udc
->debugfs_eps
);
302 debugfs_remove(udc
->debugfs_queues
);
303 debugfs_remove(udc
->debugfs_state
);
304 debugfs_remove(udc
->debugfs_root
);
305 udc
->debugfs_eps
= NULL
;
306 udc
->debugfs_queues
= NULL
;
307 udc
->debugfs_state
= NULL
;
308 udc
->debugfs_root
= NULL
;
312 static inline void pxa_init_debugfs(struct pxa_udc
*udc
)
316 static inline void pxa_cleanup_debugfs(struct pxa_udc
*udc
)
322 * is_match_usb_pxa - check if usb_ep and pxa_ep match
323 * @udc_usb_ep: usb endpoint
325 * @config: configuration required in pxa_ep
326 * @interface: interface required in pxa_ep
327 * @altsetting: altsetting required in pxa_ep
329 * Returns 1 if all criteria match between pxa and usb endpoint, 0 otherwise
331 static int is_match_usb_pxa(struct udc_usb_ep
*udc_usb_ep
, struct pxa_ep
*ep
,
332 int config
, int interface
, int altsetting
)
334 if (usb_endpoint_num(&udc_usb_ep
->desc
) != ep
->addr
)
336 if (usb_endpoint_dir_in(&udc_usb_ep
->desc
) != ep
->dir_in
)
338 if (usb_endpoint_type(&udc_usb_ep
->desc
) != ep
->type
)
340 if ((ep
->config
!= config
) || (ep
->interface
!= interface
)
341 || (ep
->alternate
!= altsetting
))
347 * find_pxa_ep - find pxa_ep structure matching udc_usb_ep
349 * @udc_usb_ep: udc_usb_ep structure
351 * Match udc_usb_ep and all pxa_ep available, to see if one matches.
352 * This is necessary because of the strong pxa hardware restriction requiring
353 * that once pxa endpoints are initialized, their configuration is freezed, and
354 * no change can be made to their address, direction, or in which configuration,
355 * interface or altsetting they are active ... which differs from more usual
356 * models which have endpoints be roughly just addressable fifos, and leave
357 * configuration events up to gadget drivers (like all control messages).
359 * Note that there is still a blurred point here :
360 * - we rely on UDCCR register "active interface" and "active altsetting".
361 * This is a nonsense in regard of USB spec, where multiple interfaces are
362 * active at the same time.
363 * - if we knew for sure that the pxa can handle multiple interface at the
364 * same time, assuming Intel's Developer Guide is wrong, this function
365 * should be reviewed, and a cache of couples (iface, altsetting) should
366 * be kept in the pxa_udc structure. In this case this function would match
367 * against the cache of couples instead of the "last altsetting" set up.
369 * Returns the matched pxa_ep structure or NULL if none found
371 static struct pxa_ep
*find_pxa_ep(struct pxa_udc
*udc
,
372 struct udc_usb_ep
*udc_usb_ep
)
376 int cfg
= udc
->config
;
377 int iface
= udc
->last_interface
;
378 int alt
= udc
->last_alternate
;
380 if (udc_usb_ep
== &udc
->udc_usb_ep
[0])
381 return &udc
->pxa_ep
[0];
383 for (i
= 1; i
< NR_PXA_ENDPOINTS
; i
++) {
384 ep
= &udc
->pxa_ep
[i
];
385 if (is_match_usb_pxa(udc_usb_ep
, ep
, cfg
, iface
, alt
))
392 * update_pxa_ep_matches - update pxa_ep cached values in all udc_usb_ep
395 * Context: in_interrupt()
397 * Updates all pxa_ep fields in udc_usb_ep structures, if this field was
398 * previously set up (and is not NULL). The update is necessary is a
399 * configuration change or altsetting change was issued by the USB host.
401 static void update_pxa_ep_matches(struct pxa_udc
*udc
)
404 struct udc_usb_ep
*udc_usb_ep
;
406 for (i
= 1; i
< NR_USB_ENDPOINTS
; i
++) {
407 udc_usb_ep
= &udc
->udc_usb_ep
[i
];
408 if (udc_usb_ep
->pxa_ep
)
409 udc_usb_ep
->pxa_ep
= find_pxa_ep(udc
, udc_usb_ep
);
414 * pio_irq_enable - Enables irq generation for one endpoint
417 static void pio_irq_enable(struct pxa_ep
*ep
)
419 struct pxa_udc
*udc
= ep
->dev
;
420 int index
= EPIDX(ep
);
421 u32 udcicr0
= udc_readl(udc
, UDCICR0
);
422 u32 udcicr1
= udc_readl(udc
, UDCICR1
);
425 udc_writel(udc
, UDCICR0
, udcicr0
| (3 << (index
* 2)));
427 udc_writel(udc
, UDCICR1
, udcicr1
| (3 << ((index
- 16) * 2)));
431 * pio_irq_disable - Disables irq generation for one endpoint
433 * @index: endpoint number
435 static void pio_irq_disable(struct pxa_ep
*ep
)
437 struct pxa_udc
*udc
= ep
->dev
;
438 int index
= EPIDX(ep
);
439 u32 udcicr0
= udc_readl(udc
, UDCICR0
);
440 u32 udcicr1
= udc_readl(udc
, UDCICR1
);
443 udc_writel(udc
, UDCICR0
, udcicr0
& ~(3 << (index
* 2)));
445 udc_writel(udc
, UDCICR1
, udcicr1
& ~(3 << ((index
- 16) * 2)));
449 * udc_set_mask_UDCCR - set bits in UDCCR
451 * @mask: bits to set in UDCCR
453 * Sets bits in UDCCR, leaving DME and FST bits as they were.
455 static inline void udc_set_mask_UDCCR(struct pxa_udc
*udc
, int mask
)
457 u32 udccr
= udc_readl(udc
, UDCCR
);
458 udc_writel(udc
, UDCCR
,
459 (udccr
& UDCCR_MASK_BITS
) | (mask
& UDCCR_MASK_BITS
));
463 * udc_clear_mask_UDCCR - clears bits in UDCCR
465 * @mask: bit to clear in UDCCR
467 * Clears bits in UDCCR, leaving DME and FST bits as they were.
469 static inline void udc_clear_mask_UDCCR(struct pxa_udc
*udc
, int mask
)
471 u32 udccr
= udc_readl(udc
, UDCCR
);
472 udc_writel(udc
, UDCCR
,
473 (udccr
& UDCCR_MASK_BITS
) & ~(mask
& UDCCR_MASK_BITS
));
477 * ep_count_bytes_remain - get how many bytes in udc endpoint
480 * Returns number of bytes in OUT fifos. Broken for IN fifos (-EOPNOTSUPP)
482 static int ep_count_bytes_remain(struct pxa_ep
*ep
)
486 return udc_ep_readl(ep
, UDCBCR
) & 0x3ff;
490 * ep_is_empty - checks if ep has byte ready for reading
493 * If endpoint is the control endpoint, checks if there are bytes in the
494 * control endpoint fifo. If endpoint is a data endpoint, checks if bytes
495 * are ready for reading on OUT endpoint.
497 * Returns 0 if ep not empty, 1 if ep empty, -EOPNOTSUPP if IN endpoint
499 static int ep_is_empty(struct pxa_ep
*ep
)
503 if (!is_ep0(ep
) && ep
->dir_in
)
506 ret
= !(udc_ep_readl(ep
, UDCCSR
) & UDCCSR0_RNE
);
508 ret
= !(udc_ep_readl(ep
, UDCCSR
) & UDCCSR_BNE
);
513 * ep_is_full - checks if ep has place to write bytes
516 * If endpoint is not the control endpoint and is an IN endpoint, checks if
517 * there is place to write bytes into the endpoint.
519 * Returns 0 if ep not full, 1 if ep full, -EOPNOTSUPP if OUT endpoint
521 static int ep_is_full(struct pxa_ep
*ep
)
524 return (udc_ep_readl(ep
, UDCCSR
) & UDCCSR0_IPR
);
527 return (!(udc_ep_readl(ep
, UDCCSR
) & UDCCSR_BNF
));
531 * epout_has_pkt - checks if OUT endpoint fifo has a packet available
534 * Returns 1 if a complete packet is available, 0 if not, -EOPNOTSUPP for IN ep.
536 static int epout_has_pkt(struct pxa_ep
*ep
)
538 if (!is_ep0(ep
) && ep
->dir_in
)
541 return (udc_ep_readl(ep
, UDCCSR
) & UDCCSR0_OPC
);
542 return (udc_ep_readl(ep
, UDCCSR
) & UDCCSR_PC
);
546 * set_ep0state - Set ep0 automata state
550 static void set_ep0state(struct pxa_udc
*udc
, int state
)
552 struct pxa_ep
*ep
= &udc
->pxa_ep
[0];
553 char *old_stname
= EP0_STNAME(udc
);
555 udc
->ep0state
= state
;
556 ep_dbg(ep
, "state=%s->%s, udccsr0=0x%03x, udcbcr=%d\n", old_stname
,
557 EP0_STNAME(udc
), udc_ep_readl(ep
, UDCCSR
),
558 udc_ep_readl(ep
, UDCBCR
));
562 * ep0_idle - Put control endpoint into idle state
565 static void ep0_idle(struct pxa_udc
*dev
)
567 set_ep0state(dev
, WAIT_FOR_SETUP
);
571 * inc_ep_stats_reqs - Update ep stats counts
572 * @ep: physical endpoint
574 * @is_in: ep direction (USB_DIR_IN or 0)
577 static void inc_ep_stats_reqs(struct pxa_ep
*ep
, int is_in
)
586 * inc_ep_stats_bytes - Update ep stats counts
587 * @ep: physical endpoint
588 * @count: bytes transfered on endpoint
590 * @is_in: ep direction (USB_DIR_IN or 0)
592 static void inc_ep_stats_bytes(struct pxa_ep
*ep
, int count
, int is_in
)
595 ep
->stats
.in_bytes
+= count
;
597 ep
->stats
.out_bytes
+= count
;
601 * pxa_ep_setup - Sets up an usb physical endpoint
602 * @ep: pxa27x physical endpoint
604 * Find the physical pxa27x ep, and setup its UDCCR
606 static __init
void pxa_ep_setup(struct pxa_ep
*ep
)
610 new_udccr
= ((ep
->config
<< UDCCONR_CN_S
) & UDCCONR_CN
)
611 | ((ep
->interface
<< UDCCONR_IN_S
) & UDCCONR_IN
)
612 | ((ep
->alternate
<< UDCCONR_AISN_S
) & UDCCONR_AISN
)
613 | ((EPADDR(ep
) << UDCCONR_EN_S
) & UDCCONR_EN
)
614 | ((EPXFERTYPE(ep
) << UDCCONR_ET_S
) & UDCCONR_ET
)
615 | ((ep
->dir_in
) ? UDCCONR_ED
: 0)
616 | ((ep
->fifo_size
<< UDCCONR_MPS_S
) & UDCCONR_MPS
)
619 udc_ep_writel(ep
, UDCCR
, new_udccr
);
623 * pxa_eps_setup - Sets up all usb physical endpoints
626 * Setup all pxa physical endpoints, except ep0
628 static __init
void pxa_eps_setup(struct pxa_udc
*dev
)
632 dev_dbg(dev
->dev
, "%s: dev=%p\n", __func__
, dev
);
634 for (i
= 1; i
< NR_PXA_ENDPOINTS
; i
++)
635 pxa_ep_setup(&dev
->pxa_ep
[i
]);
639 * pxa_ep_alloc_request - Allocate usb request
643 * For the pxa27x, these can just wrap kmalloc/kfree. gadget drivers
644 * must still pass correctly initialized endpoints, since other controller
645 * drivers may care about how it's currently set up (dma issues etc).
647 static struct usb_request
*
648 pxa_ep_alloc_request(struct usb_ep
*_ep
, gfp_t gfp_flags
)
650 struct pxa27x_request
*req
;
652 req
= kzalloc(sizeof *req
, gfp_flags
);
656 INIT_LIST_HEAD(&req
->queue
);
658 req
->udc_usb_ep
= container_of(_ep
, struct udc_usb_ep
, usb_ep
);
664 * pxa_ep_free_request - Free usb request
668 * Wrapper around kfree to free _req
670 static void pxa_ep_free_request(struct usb_ep
*_ep
, struct usb_request
*_req
)
672 struct pxa27x_request
*req
;
674 req
= container_of(_req
, struct pxa27x_request
, req
);
675 WARN_ON(!list_empty(&req
->queue
));
680 * ep_add_request - add a request to the endpoint's queue
684 * Context: ep->lock held
686 * Queues the request in the endpoint's queue, and enables the interrupts
689 static void ep_add_request(struct pxa_ep
*ep
, struct pxa27x_request
*req
)
693 ep_vdbg(ep
, "req:%p, lg=%d, udccsr=0x%03x\n", req
,
694 req
->req
.length
, udc_ep_readl(ep
, UDCCSR
));
697 list_add_tail(&req
->queue
, &ep
->queue
);
702 * ep_del_request - removes a request from the endpoint's queue
706 * Context: ep->lock held
708 * Unqueue the request from the endpoint's queue. If there are no more requests
709 * on the endpoint, and if it's not the control endpoint, interrupts are
710 * disabled on the endpoint.
712 static void ep_del_request(struct pxa_ep
*ep
, struct pxa27x_request
*req
)
716 ep_vdbg(ep
, "req:%p, lg=%d, udccsr=0x%03x\n", req
,
717 req
->req
.length
, udc_ep_readl(ep
, UDCCSR
));
719 list_del_init(&req
->queue
);
721 if (!is_ep0(ep
) && list_empty(&ep
->queue
))
726 * req_done - Complete an usb request
727 * @ep: pxa physical endpoint
729 * @status: usb request status sent to gadget API
731 * Context: ep->lock held
733 * Retire a pxa27x usb request. Endpoint must be locked.
735 static void req_done(struct pxa_ep
*ep
, struct pxa27x_request
*req
, int status
)
737 ep_del_request(ep
, req
);
738 if (likely(req
->req
.status
== -EINPROGRESS
))
739 req
->req
.status
= status
;
741 status
= req
->req
.status
;
743 if (status
&& status
!= -ESHUTDOWN
)
744 ep_dbg(ep
, "complete req %p stat %d len %u/%u\n",
746 req
->req
.actual
, req
->req
.length
);
748 req
->req
.complete(&req
->udc_usb_ep
->usb_ep
, &req
->req
);
752 * ep_end_out_req - Ends control endpoint in request
753 * @ep: physical endpoint
756 * Context: ep->lock held
758 * Ends endpoint in request (completes usb request).
760 static void ep_end_out_req(struct pxa_ep
*ep
, struct pxa27x_request
*req
)
762 inc_ep_stats_reqs(ep
, !USB_DIR_IN
);
763 req_done(ep
, req
, 0);
767 * ep0_end_out_req - Ends control endpoint in request (ends data stage)
768 * @ep: physical endpoint
771 * Context: ep->lock held
773 * Ends control endpoint in request (completes usb request), and puts
774 * control endpoint into idle state
776 static void ep0_end_out_req(struct pxa_ep
*ep
, struct pxa27x_request
*req
)
778 set_ep0state(ep
->dev
, OUT_STATUS_STAGE
);
779 ep_end_out_req(ep
, req
);
784 * ep_end_in_req - Ends endpoint out request
785 * @ep: physical endpoint
788 * Context: ep->lock held
790 * Ends endpoint out request (completes usb request).
792 static void ep_end_in_req(struct pxa_ep
*ep
, struct pxa27x_request
*req
)
794 inc_ep_stats_reqs(ep
, USB_DIR_IN
);
795 req_done(ep
, req
, 0);
799 * ep0_end_in_req - Ends control endpoint out request (ends data stage)
800 * @ep: physical endpoint
803 * Context: ep->lock held
805 * Ends control endpoint out request (completes usb request), and puts
806 * control endpoint into status state
808 static void ep0_end_in_req(struct pxa_ep
*ep
, struct pxa27x_request
*req
)
810 struct pxa_udc
*udc
= ep
->dev
;
812 set_ep0state(udc
, IN_STATUS_STAGE
);
813 ep_end_in_req(ep
, req
);
817 * nuke - Dequeue all requests
819 * @status: usb request status
821 * Context: ep->lock held
823 * Dequeues all requests on an endpoint. As a side effect, interrupts will be
824 * disabled on that endpoint (because no more requests).
826 static void nuke(struct pxa_ep
*ep
, int status
)
828 struct pxa27x_request
*req
;
830 while (!list_empty(&ep
->queue
)) {
831 req
= list_entry(ep
->queue
.next
, struct pxa27x_request
, queue
);
832 req_done(ep
, req
, status
);
837 * read_packet - transfer 1 packet from an OUT endpoint into request
838 * @ep: pxa physical endpoint
841 * Takes bytes from OUT endpoint and transfers them info the usb request.
842 * If there is less space in request than bytes received in OUT endpoint,
843 * bytes are left in the OUT endpoint.
845 * Returns how many bytes were actually transfered
847 static int read_packet(struct pxa_ep
*ep
, struct pxa27x_request
*req
)
850 int bytes_ep
, bufferspace
, count
, i
;
852 bytes_ep
= ep_count_bytes_remain(ep
);
853 bufferspace
= req
->req
.length
- req
->req
.actual
;
855 buf
= (u32
*)(req
->req
.buf
+ req
->req
.actual
);
858 if (likely(!ep_is_empty(ep
)))
859 count
= min(bytes_ep
, bufferspace
);
863 for (i
= count
; i
> 0; i
-= 4)
864 *buf
++ = udc_ep_readl(ep
, UDCDR
);
865 req
->req
.actual
+= count
;
867 udc_ep_writel(ep
, UDCCSR
, UDCCSR_PC
);
873 * write_packet - transfer 1 packet from request into an IN endpoint
874 * @ep: pxa physical endpoint
876 * @max: max bytes that fit into endpoint
878 * Takes bytes from usb request, and transfers them into the physical
879 * endpoint. If there are no bytes to transfer, doesn't write anything
880 * to physical endpoint.
882 * Returns how many bytes were actually transfered.
884 static int write_packet(struct pxa_ep
*ep
, struct pxa27x_request
*req
,
887 int length
, count
, remain
, i
;
891 buf
= (u32
*)(req
->req
.buf
+ req
->req
.actual
);
894 length
= min(req
->req
.length
- req
->req
.actual
, max
);
895 req
->req
.actual
+= length
;
897 remain
= length
& 0x3;
898 count
= length
& ~(0x3);
899 for (i
= count
; i
> 0 ; i
-= 4)
900 udc_ep_writel(ep
, UDCDR
, *buf
++);
903 for (i
= remain
; i
> 0; i
--)
904 udc_ep_writeb(ep
, UDCDR
, *buf_8
++);
906 ep_vdbg(ep
, "length=%d+%d, udccsr=0x%03x\n", count
, remain
,
907 udc_ep_readl(ep
, UDCCSR
));
913 * read_fifo - Transfer packets from OUT endpoint into usb request
914 * @ep: pxa physical endpoint
917 * Context: callable when in_interrupt()
919 * Unload as many packets as possible from the fifo we use for usb OUT
920 * transfers and put them into the request. Caller should have made sure
921 * there's at least one packet ready.
922 * Doesn't complete the request, that's the caller's job
924 * Returns 1 if the request completed, 0 otherwise
926 static int read_fifo(struct pxa_ep
*ep
, struct pxa27x_request
*req
)
928 int count
, is_short
, completed
= 0;
930 while (epout_has_pkt(ep
)) {
931 count
= read_packet(ep
, req
);
932 inc_ep_stats_bytes(ep
, count
, !USB_DIR_IN
);
934 is_short
= (count
< ep
->fifo_size
);
935 ep_dbg(ep
, "read udccsr:%03x, count:%d bytes%s req %p %d/%d\n",
936 udc_ep_readl(ep
, UDCCSR
), count
, is_short
? "/S" : "",
937 &req
->req
, req
->req
.actual
, req
->req
.length
);
940 if (is_short
|| req
->req
.actual
== req
->req
.length
) {
944 /* finished that packet. the next one may be waiting... */
950 * write_fifo - transfer packets from usb request into an IN endpoint
951 * @ep: pxa physical endpoint
952 * @req: pxa usb request
954 * Write to an IN endpoint fifo, as many packets as possible.
955 * irqs will use this to write the rest later.
956 * caller guarantees at least one packet buffer is ready (or a zlp).
957 * Doesn't complete the request, that's the caller's job
959 * Returns 1 if request fully transfered, 0 if partial transfer
961 static int write_fifo(struct pxa_ep
*ep
, struct pxa27x_request
*req
)
964 int count
, is_short
, is_last
= 0, completed
= 0, totcount
= 0;
971 udccsr
= udc_ep_readl(ep
, UDCCSR
);
972 if (udccsr
& UDCCSR_PC
) {
973 ep_vdbg(ep
, "Clearing Transmit Complete, udccsr=%x\n",
975 udc_ep_writel(ep
, UDCCSR
, UDCCSR_PC
);
977 if (udccsr
& UDCCSR_TRN
) {
978 ep_vdbg(ep
, "Clearing Underrun on, udccsr=%x\n",
980 udc_ep_writel(ep
, UDCCSR
, UDCCSR_TRN
);
983 count
= write_packet(ep
, req
, max
);
984 inc_ep_stats_bytes(ep
, count
, USB_DIR_IN
);
987 /* last packet is usually short (or a zlp) */
988 if (unlikely(count
< max
)) {
992 if (likely(req
->req
.length
> req
->req
.actual
)
997 /* interrupt/iso maxpacket may not fill the fifo */
998 is_short
= unlikely(max
< ep
->fifo_size
);
1002 udc_ep_writel(ep
, UDCCSR
, UDCCSR_SP
);
1004 /* requests complete when all IN data is in the FIFO */
1009 } while (!ep_is_full(ep
));
1011 ep_dbg(ep
, "wrote count:%d bytes%s%s, left:%d req=%p\n",
1012 totcount
, is_last
? "/L" : "", is_short
? "/S" : "",
1013 req
->req
.length
- req
->req
.actual
, &req
->req
);
1019 * read_ep0_fifo - Transfer packets from control endpoint into usb request
1020 * @ep: control endpoint
1021 * @req: pxa usb request
1023 * Special ep0 version of the above read_fifo. Reads as many bytes from control
1024 * endpoint as can be read, and stores them into usb request (limited by request
1027 * Returns 0 if usb request only partially filled, 1 if fully filled
1029 static int read_ep0_fifo(struct pxa_ep
*ep
, struct pxa27x_request
*req
)
1031 int count
, is_short
, completed
= 0;
1033 while (epout_has_pkt(ep
)) {
1034 count
= read_packet(ep
, req
);
1035 udc_ep_writel(ep
, UDCCSR
, UDCCSR0_OPC
);
1036 inc_ep_stats_bytes(ep
, count
, !USB_DIR_IN
);
1038 is_short
= (count
< ep
->fifo_size
);
1039 ep_dbg(ep
, "read udccsr:%03x, count:%d bytes%s req %p %d/%d\n",
1040 udc_ep_readl(ep
, UDCCSR
), count
, is_short
? "/S" : "",
1041 &req
->req
, req
->req
.actual
, req
->req
.length
);
1043 if (is_short
|| req
->req
.actual
>= req
->req
.length
) {
1053 * write_ep0_fifo - Send a request to control endpoint (ep0 in)
1054 * @ep: control endpoint
1057 * Context: callable when in_interrupt()
1059 * Sends a request (or a part of the request) to the control endpoint (ep0 in).
1060 * If the request doesn't fit, the remaining part will be sent from irq.
1061 * The request is considered fully written only if either :
1062 * - last write transfered all remaining bytes, but fifo was not fully filled
1063 * - last write was a 0 length write
1065 * Returns 1 if request fully written, 0 if request only partially sent
1067 static int write_ep0_fifo(struct pxa_ep
*ep
, struct pxa27x_request
*req
)
1070 int is_last
, is_short
;
1072 count
= write_packet(ep
, req
, EP0_FIFO_SIZE
);
1073 inc_ep_stats_bytes(ep
, count
, USB_DIR_IN
);
1075 is_short
= (count
< EP0_FIFO_SIZE
);
1076 is_last
= ((count
== 0) || (count
< EP0_FIFO_SIZE
));
1078 /* Sends either a short packet or a 0 length packet */
1079 if (unlikely(is_short
))
1080 udc_ep_writel(ep
, UDCCSR
, UDCCSR0_IPR
);
1082 ep_dbg(ep
, "in %d bytes%s%s, %d left, req=%p, udccsr0=0x%03x\n",
1083 count
, is_short
? "/S" : "", is_last
? "/L" : "",
1084 req
->req
.length
- req
->req
.actual
,
1085 &req
->req
, udc_ep_readl(ep
, UDCCSR
));
1091 * pxa_ep_queue - Queue a request into an IN endpoint
1092 * @_ep: usb endpoint
1093 * @_req: usb request
1096 * Context: normally called when !in_interrupt, but callable when in_interrupt()
1097 * in the special case of ep0 setup :
1098 * (irq->handle_ep0_ctrl_req->gadget_setup->pxa_ep_queue)
1100 * Returns 0 if succedeed, error otherwise
1102 static int pxa_ep_queue(struct usb_ep
*_ep
, struct usb_request
*_req
,
1105 struct udc_usb_ep
*udc_usb_ep
;
1107 struct pxa27x_request
*req
;
1108 struct pxa_udc
*dev
;
1109 unsigned long flags
;
1114 req
= container_of(_req
, struct pxa27x_request
, req
);
1115 udc_usb_ep
= container_of(_ep
, struct udc_usb_ep
, usb_ep
);
1117 if (unlikely(!_req
|| !_req
->complete
|| !_req
->buf
))
1123 dev
= udc_usb_ep
->dev
;
1124 ep
= udc_usb_ep
->pxa_ep
;
1129 if (unlikely(!dev
->driver
|| dev
->gadget
.speed
== USB_SPEED_UNKNOWN
)) {
1130 ep_dbg(ep
, "bogus device state\n");
1134 /* iso is always one packet per request, that's the only way
1135 * we can report per-packet status. that also helps with dma.
1137 if (unlikely(EPXFERTYPE_is_ISO(ep
)
1138 && req
->req
.length
> ep
->fifo_size
))
1141 spin_lock_irqsave(&ep
->lock
, flags
);
1143 is_first_req
= list_empty(&ep
->queue
);
1144 ep_dbg(ep
, "queue req %p(first=%s), len %d buf %p\n",
1145 _req
, is_first_req
? "yes" : "no",
1146 _req
->length
, _req
->buf
);
1149 _req
->status
= -ESHUTDOWN
;
1155 ep_err(ep
, "refusing to queue req %p (already queued)\n", req
);
1159 length
= _req
->length
;
1160 _req
->status
= -EINPROGRESS
;
1163 ep_add_request(ep
, req
);
1166 switch (dev
->ep0state
) {
1167 case WAIT_ACK_SET_CONF_INTERF
:
1169 ep_end_in_req(ep
, req
);
1171 ep_err(ep
, "got a request of %d bytes while"
1172 "in state WATI_ACK_SET_CONF_INTERF\n",
1174 ep_del_request(ep
, req
);
1180 if (!ep_is_full(ep
))
1181 if (write_ep0_fifo(ep
, req
))
1182 ep0_end_in_req(ep
, req
);
1184 case OUT_DATA_STAGE
:
1185 if ((length
== 0) || !epout_has_pkt(ep
))
1186 if (read_ep0_fifo(ep
, req
))
1187 ep0_end_out_req(ep
, req
);
1190 ep_err(ep
, "odd state %s to send me a request\n",
1191 EP0_STNAME(ep
->dev
));
1192 ep_del_request(ep
, req
);
1201 spin_unlock_irqrestore(&ep
->lock
, flags
);
1206 * pxa_ep_dequeue - Dequeue one request
1207 * @_ep: usb endpoint
1208 * @_req: usb request
1210 * Return 0 if no error, -EINVAL or -ECONNRESET otherwise
1212 static int pxa_ep_dequeue(struct usb_ep
*_ep
, struct usb_request
*_req
)
1215 struct udc_usb_ep
*udc_usb_ep
;
1216 struct pxa27x_request
*req
;
1217 unsigned long flags
;
1222 udc_usb_ep
= container_of(_ep
, struct udc_usb_ep
, usb_ep
);
1223 ep
= udc_usb_ep
->pxa_ep
;
1224 if (!ep
|| is_ep0(ep
))
1227 spin_lock_irqsave(&ep
->lock
, flags
);
1229 /* make sure it's actually queued on this endpoint */
1230 list_for_each_entry(req
, &ep
->queue
, queue
) {
1231 if (&req
->req
== _req
)
1236 if (&req
->req
!= _req
)
1240 req_done(ep
, req
, -ECONNRESET
);
1242 spin_unlock_irqrestore(&ep
->lock
, flags
);
1247 * pxa_ep_set_halt - Halts operations on one endpoint
1248 * @_ep: usb endpoint
1251 * Returns 0 if no error, -EINVAL, -EROFS, -EAGAIN otherwise
1253 static int pxa_ep_set_halt(struct usb_ep
*_ep
, int value
)
1256 struct udc_usb_ep
*udc_usb_ep
;
1257 unsigned long flags
;
1263 udc_usb_ep
= container_of(_ep
, struct udc_usb_ep
, usb_ep
);
1264 ep
= udc_usb_ep
->pxa_ep
;
1265 if (!ep
|| is_ep0(ep
))
1270 * This path (reset toggle+halt) is needed to implement
1271 * SET_INTERFACE on normal hardware. but it can't be
1272 * done from software on the PXA UDC, and the hardware
1273 * forgets to do it as part of SET_INTERFACE automagic.
1275 ep_dbg(ep
, "only host can clear halt\n");
1279 spin_lock_irqsave(&ep
->lock
, flags
);
1282 if (ep
->dir_in
&& (ep_is_full(ep
) || !list_empty(&ep
->queue
)))
1285 /* FST, FEF bits are the same for control and non control endpoints */
1287 udc_ep_writel(ep
, UDCCSR
, UDCCSR_FST
| UDCCSR_FEF
);
1289 set_ep0state(ep
->dev
, STALL
);
1292 spin_unlock_irqrestore(&ep
->lock
, flags
);
1297 * pxa_ep_fifo_status - Get how many bytes in physical endpoint
1298 * @_ep: usb endpoint
1300 * Returns number of bytes in OUT fifos. Broken for IN fifos.
1302 static int pxa_ep_fifo_status(struct usb_ep
*_ep
)
1305 struct udc_usb_ep
*udc_usb_ep
;
1309 udc_usb_ep
= container_of(_ep
, struct udc_usb_ep
, usb_ep
);
1310 ep
= udc_usb_ep
->pxa_ep
;
1311 if (!ep
|| is_ep0(ep
))
1316 if (ep
->dev
->gadget
.speed
== USB_SPEED_UNKNOWN
|| ep_is_empty(ep
))
1319 return ep_count_bytes_remain(ep
) + 1;
1323 * pxa_ep_fifo_flush - Flushes one endpoint
1324 * @_ep: usb endpoint
1326 * Discards all data in one endpoint(IN or OUT), except control endpoint.
1328 static void pxa_ep_fifo_flush(struct usb_ep
*_ep
)
1331 struct udc_usb_ep
*udc_usb_ep
;
1332 unsigned long flags
;
1336 udc_usb_ep
= container_of(_ep
, struct udc_usb_ep
, usb_ep
);
1337 ep
= udc_usb_ep
->pxa_ep
;
1338 if (!ep
|| is_ep0(ep
))
1341 spin_lock_irqsave(&ep
->lock
, flags
);
1343 if (unlikely(!list_empty(&ep
->queue
)))
1344 ep_dbg(ep
, "called while queue list not empty\n");
1345 ep_dbg(ep
, "called\n");
1347 /* for OUT, just read and discard the FIFO contents. */
1349 while (!ep_is_empty(ep
))
1350 udc_ep_readl(ep
, UDCDR
);
1352 /* most IN status is the same, but ISO can't stall */
1353 udc_ep_writel(ep
, UDCCSR
,
1354 UDCCSR_PC
| UDCCSR_FEF
| UDCCSR_TRN
1355 | (EPXFERTYPE_is_ISO(ep
) ? 0 : UDCCSR_SST
));
1358 spin_unlock_irqrestore(&ep
->lock
, flags
);
1364 * pxa_ep_enable - Enables usb endpoint
1365 * @_ep: usb endpoint
1366 * @desc: usb endpoint descriptor
1368 * Nothing much to do here, as ep configuration is done once and for all
1369 * before udc is enabled. After udc enable, no physical endpoint configuration
1371 * Function makes sanity checks and flushes the endpoint.
1373 static int pxa_ep_enable(struct usb_ep
*_ep
,
1374 const struct usb_endpoint_descriptor
*desc
)
1377 struct udc_usb_ep
*udc_usb_ep
;
1378 struct pxa_udc
*udc
;
1383 udc_usb_ep
= container_of(_ep
, struct udc_usb_ep
, usb_ep
);
1384 if (udc_usb_ep
->pxa_ep
) {
1385 ep
= udc_usb_ep
->pxa_ep
;
1386 ep_warn(ep
, "usb_ep %s already enabled, doing nothing\n",
1389 ep
= find_pxa_ep(udc_usb_ep
->dev
, udc_usb_ep
);
1392 if (!ep
|| is_ep0(ep
)) {
1393 dev_err(udc_usb_ep
->dev
->dev
,
1394 "unable to match pxa_ep for ep %s\n",
1399 if ((desc
->bDescriptorType
!= USB_DT_ENDPOINT
)
1400 || (ep
->type
!= usb_endpoint_type(desc
))) {
1401 ep_err(ep
, "type mismatch\n");
1405 if (ep
->fifo_size
< le16_to_cpu(desc
->wMaxPacketSize
)) {
1406 ep_err(ep
, "bad maxpacket\n");
1410 udc_usb_ep
->pxa_ep
= ep
;
1413 if (!udc
->driver
|| udc
->gadget
.speed
== USB_SPEED_UNKNOWN
) {
1414 ep_err(ep
, "bogus device state\n");
1420 /* flush fifo (mostly for OUT buffers) */
1421 pxa_ep_fifo_flush(_ep
);
1423 ep_dbg(ep
, "enabled\n");
1428 * pxa_ep_disable - Disable usb endpoint
1429 * @_ep: usb endpoint
1431 * Same as for pxa_ep_enable, no physical endpoint configuration can be
1433 * Function flushes the endpoint and related requests.
1435 static int pxa_ep_disable(struct usb_ep
*_ep
)
1438 struct udc_usb_ep
*udc_usb_ep
;
1439 unsigned long flags
;
1444 udc_usb_ep
= container_of(_ep
, struct udc_usb_ep
, usb_ep
);
1445 ep
= udc_usb_ep
->pxa_ep
;
1446 if (!ep
|| is_ep0(ep
) || !list_empty(&ep
->queue
))
1449 spin_lock_irqsave(&ep
->lock
, flags
);
1451 nuke(ep
, -ESHUTDOWN
);
1452 spin_unlock_irqrestore(&ep
->lock
, flags
);
1454 pxa_ep_fifo_flush(_ep
);
1455 udc_usb_ep
->pxa_ep
= NULL
;
1457 ep_dbg(ep
, "disabled\n");
1461 static struct usb_ep_ops pxa_ep_ops
= {
1462 .enable
= pxa_ep_enable
,
1463 .disable
= pxa_ep_disable
,
1465 .alloc_request
= pxa_ep_alloc_request
,
1466 .free_request
= pxa_ep_free_request
,
1468 .queue
= pxa_ep_queue
,
1469 .dequeue
= pxa_ep_dequeue
,
1471 .set_halt
= pxa_ep_set_halt
,
1472 .fifo_status
= pxa_ep_fifo_status
,
1473 .fifo_flush
= pxa_ep_fifo_flush
,
1478 * pxa_udc_get_frame - Returns usb frame number
1479 * @_gadget: usb gadget
1481 static int pxa_udc_get_frame(struct usb_gadget
*_gadget
)
1483 struct pxa_udc
*udc
= to_gadget_udc(_gadget
);
1485 return (udc_readl(udc
, UDCFNR
) & 0x7ff);
1489 * pxa_udc_wakeup - Force udc device out of suspend
1490 * @_gadget: usb gadget
1492 * Returns 0 if succesfull, error code otherwise
1494 static int pxa_udc_wakeup(struct usb_gadget
*_gadget
)
1496 struct pxa_udc
*udc
= to_gadget_udc(_gadget
);
1498 /* host may not have enabled remote wakeup */
1499 if ((udc_readl(udc
, UDCCR
) & UDCCR_DWRE
) == 0)
1500 return -EHOSTUNREACH
;
1501 udc_set_mask_UDCCR(udc
, UDCCR_UDR
);
1505 static const struct usb_gadget_ops pxa_udc_ops
= {
1506 .get_frame
= pxa_udc_get_frame
,
1507 .wakeup
= pxa_udc_wakeup
,
1508 /* current versions must always be self-powered */
1512 * udc_disable - disable udc device controller
1515 * Disables the udc device : disables clocks, udc interrupts, control endpoint
1518 static void udc_disable(struct pxa_udc
*udc
)
1520 udc_writel(udc
, UDCICR0
, 0);
1521 udc_writel(udc
, UDCICR1
, 0);
1523 udc_clear_mask_UDCCR(udc
, UDCCR_UDE
);
1524 clk_disable(udc
->clk
);
1527 udc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1528 if (udc
->mach
->udc_command
)
1529 udc
->mach
->udc_command(PXA2XX_UDC_CMD_DISCONNECT
);
1533 * udc_init_data - Initialize udc device data structures
1536 * Initializes gadget endpoint list, endpoints locks. No action is taken
1539 static __init
void udc_init_data(struct pxa_udc
*dev
)
1544 /* device/ep0 records init */
1545 INIT_LIST_HEAD(&dev
->gadget
.ep_list
);
1546 INIT_LIST_HEAD(&dev
->gadget
.ep0
->ep_list
);
1547 dev
->udc_usb_ep
[0].pxa_ep
= &dev
->pxa_ep
[0];
1550 /* PXA endpoints init */
1551 for (i
= 0; i
< NR_PXA_ENDPOINTS
; i
++) {
1552 ep
= &dev
->pxa_ep
[i
];
1554 ep
->enabled
= is_ep0(ep
);
1555 INIT_LIST_HEAD(&ep
->queue
);
1556 spin_lock_init(&ep
->lock
);
1559 /* USB endpoints init */
1560 for (i
= 0; i
< NR_USB_ENDPOINTS
; i
++)
1562 list_add_tail(&dev
->udc_usb_ep
[i
].usb_ep
.ep_list
,
1563 &dev
->gadget
.ep_list
);
1567 * udc_enable - Enables the udc device
1570 * Enables the udc device : enables clocks, udc interrupts, control endpoint
1571 * interrupts, sets usb as UDC client and setups endpoints.
1573 static void udc_enable(struct pxa_udc
*udc
)
1575 udc_writel(udc
, UDCICR0
, 0);
1576 udc_writel(udc
, UDCICR1
, 0);
1577 udc_clear_mask_UDCCR(udc
, UDCCR_UDE
);
1579 clk_enable(udc
->clk
);
1582 udc
->gadget
.speed
= USB_SPEED_FULL
;
1583 memset(&udc
->stats
, 0, sizeof(udc
->stats
));
1585 udc_set_mask_UDCCR(udc
, UDCCR_UDE
);
1587 if (udc_readl(udc
, UDCCR
) & UDCCR_EMCE
)
1588 dev_err(udc
->dev
, "Configuration errors, udc disabled\n");
1591 * Caller must be able to sleep in order to cope with startup transients
1595 /* enable suspend/resume and reset irqs */
1596 udc_writel(udc
, UDCICR1
,
1597 UDCICR1_IECC
| UDCICR1_IERU
1598 | UDCICR1_IESU
| UDCICR1_IERS
);
1600 /* enable ep0 irqs */
1601 pio_irq_enable(&udc
->pxa_ep
[0]);
1603 dev_info(udc
->dev
, "UDC connecting\n");
1604 if (udc
->mach
->udc_command
)
1605 udc
->mach
->udc_command(PXA2XX_UDC_CMD_CONNECT
);
1609 * usb_gadget_register_driver - Register gadget driver
1610 * @driver: gadget driver
1612 * When a driver is successfully registered, it will receive control requests
1613 * including set_configuration(), which enables non-control requests. Then
1614 * usb traffic follows until a disconnect is reported. Then a host may connect
1615 * again, or the driver might get unbound.
1617 * Returns 0 if no error, -EINVAL, -ENODEV, -EBUSY otherwise
1619 int usb_gadget_register_driver(struct usb_gadget_driver
*driver
)
1621 struct pxa_udc
*udc
= the_controller
;
1624 if (!driver
|| driver
->speed
< USB_SPEED_FULL
|| !driver
->bind
1625 || !driver
->disconnect
|| !driver
->setup
)
1632 /* first hook up the driver ... */
1633 udc
->driver
= driver
;
1634 udc
->gadget
.dev
.driver
= &driver
->driver
;
1636 retval
= device_add(&udc
->gadget
.dev
);
1638 dev_err(udc
->dev
, "device_add error %d\n", retval
);
1641 retval
= driver
->bind(&udc
->gadget
);
1643 dev_err(udc
->dev
, "bind to driver %s --> error %d\n",
1644 driver
->driver
.name
, retval
);
1647 dev_dbg(udc
->dev
, "registered gadget driver '%s'\n",
1648 driver
->driver
.name
);
1654 device_del(&udc
->gadget
.dev
);
1657 udc
->gadget
.dev
.driver
= NULL
;
1660 EXPORT_SYMBOL(usb_gadget_register_driver
);
1664 * stop_activity - Stops udc endpoints
1666 * @driver: gadget driver
1668 * Disables all udc endpoints (even control endpoint), report disconnect to
1671 static void stop_activity(struct pxa_udc
*udc
, struct usb_gadget_driver
*driver
)
1675 /* don't disconnect drivers more than once */
1676 if (udc
->gadget
.speed
== USB_SPEED_UNKNOWN
)
1678 udc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1680 for (i
= 0; i
< NR_USB_ENDPOINTS
; i
++)
1681 pxa_ep_disable(&udc
->udc_usb_ep
[i
].usb_ep
);
1684 driver
->disconnect(&udc
->gadget
);
1688 * usb_gadget_unregister_driver - Unregister the gadget driver
1689 * @driver: gadget driver
1691 * Returns 0 if no error, -ENODEV, -EINVAL otherwise
1693 int usb_gadget_unregister_driver(struct usb_gadget_driver
*driver
)
1695 struct pxa_udc
*udc
= the_controller
;
1699 if (!driver
|| driver
!= udc
->driver
|| !driver
->unbind
)
1702 stop_activity(udc
, driver
);
1705 driver
->unbind(&udc
->gadget
);
1708 device_del(&udc
->gadget
.dev
);
1710 dev_info(udc
->dev
, "unregistered gadget driver '%s'\n",
1711 driver
->driver
.name
);
1714 EXPORT_SYMBOL(usb_gadget_unregister_driver
);
1717 * handle_ep0_ctrl_req - handle control endpoint control request
1719 * @req: control request
1721 static void handle_ep0_ctrl_req(struct pxa_udc
*udc
,
1722 struct pxa27x_request
*req
)
1724 struct pxa_ep
*ep
= &udc
->pxa_ep
[0];
1726 struct usb_ctrlrequest r
;
1730 int have_extrabytes
= 0;
1734 /* read SETUP packet */
1735 for (i
= 0; i
< 2; i
++) {
1736 if (unlikely(ep_is_empty(ep
)))
1738 u
.word
[i
] = udc_ep_readl(ep
, UDCDR
);
1741 have_extrabytes
= !ep_is_empty(ep
);
1742 while (!ep_is_empty(ep
)) {
1743 i
= udc_ep_readl(ep
, UDCDR
);
1744 ep_err(ep
, "wrong to have extra bytes for setup : 0x%08x\n", i
);
1747 ep_dbg(ep
, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1748 u
.r
.bRequestType
, u
.r
.bRequest
,
1749 le16_to_cpu(u
.r
.wValue
), le16_to_cpu(u
.r
.wIndex
),
1750 le16_to_cpu(u
.r
.wLength
));
1751 if (unlikely(have_extrabytes
))
1754 if (u
.r
.bRequestType
& USB_DIR_IN
)
1755 set_ep0state(udc
, IN_DATA_STAGE
);
1757 set_ep0state(udc
, OUT_DATA_STAGE
);
1759 /* Tell UDC to enter Data Stage */
1760 udc_ep_writel(ep
, UDCCSR
, UDCCSR0_SA
| UDCCSR0_OPC
);
1762 i
= udc
->driver
->setup(&udc
->gadget
, &u
.r
);
1768 ep_dbg(ep
, "protocol STALL, udccsr0=%03x err %d\n",
1769 udc_ep_readl(ep
, UDCCSR
), i
);
1770 udc_ep_writel(ep
, UDCCSR
, UDCCSR0_FST
| UDCCSR0_FTF
);
1771 set_ep0state(udc
, STALL
);
1776 * handle_ep0 - Handle control endpoint data transfers
1778 * @fifo_irq: 1 if triggered by fifo service type irq
1779 * @opc_irq: 1 if triggered by output packet complete type irq
1781 * Context : when in_interrupt() or with ep->lock held
1783 * Tries to transfer all pending request data into the endpoint and/or
1784 * transfer all pending data in the endpoint into usb requests.
1785 * Handles states of ep0 automata.
1787 * PXA27x hardware handles several standard usb control requests without
1788 * driver notification. The requests fully handled by hardware are :
1789 * SET_ADDRESS, SET_FEATURE, CLEAR_FEATURE, GET_CONFIGURATION, GET_INTERFACE,
1791 * The requests handled by hardware, but with irq notification are :
1792 * SYNCH_FRAME, SET_CONFIGURATION, SET_INTERFACE
1793 * The remaining standard requests really handled by handle_ep0 are :
1794 * GET_DESCRIPTOR, SET_DESCRIPTOR, specific requests.
1795 * Requests standardized outside of USB 2.0 chapter 9 are handled more
1796 * uniformly, by gadget drivers.
1798 * The control endpoint state machine is _not_ USB spec compliant, it's even
1799 * hardly compliant with Intel PXA270 developers guide.
1800 * The key points which inferred this state machine are :
1801 * - on every setup token, bit UDCCSR0_SA is raised and held until cleared by
1803 * - on every OUT packet received, UDCCSR0_OPC is raised and held until
1804 * cleared by software.
1805 * - clearing UDCCSR0_OPC always flushes ep0. If in setup stage, never do it
1806 * before reading ep0.
1807 * - irq can be called on a "packet complete" event (opc_irq=1), while
1808 * UDCCSR0_OPC is not yet raised (delta can be as big as 100ms
1809 * from experimentation).
1810 * - as UDCCSR0_SA can be activated while in irq handling, and clearing
1811 * UDCCSR0_OPC would flush the setup data, we almost never clear UDCCSR0_OPC
1812 * => we never actually read the "status stage" packet of an IN data stage
1813 * => this is not documented in Intel documentation
1814 * - hardware as no idea of STATUS STAGE, it only handle SETUP STAGE and DATA
1815 * STAGE. The driver add STATUS STAGE to send last zero length packet in
1817 * - special attention was needed for IN_STATUS_STAGE. If a packet complete
1818 * event is detected, we terminate the status stage without ackowledging the
1819 * packet (not to risk to loose a potential SETUP packet)
1821 static void handle_ep0(struct pxa_udc
*udc
, int fifo_irq
, int opc_irq
)
1824 struct pxa_ep
*ep
= &udc
->pxa_ep
[0];
1825 struct pxa27x_request
*req
= NULL
;
1828 udccsr0
= udc_ep_readl(ep
, UDCCSR
);
1829 ep_dbg(ep
, "state=%s, req=%p, udccsr0=0x%03x, udcbcr=%d, irq_msk=%x\n",
1830 EP0_STNAME(udc
), req
, udccsr0
, udc_ep_readl(ep
, UDCBCR
),
1831 (fifo_irq
<< 1 | opc_irq
));
1833 if (!list_empty(&ep
->queue
))
1834 req
= list_entry(ep
->queue
.next
, struct pxa27x_request
, queue
);
1836 if (udccsr0
& UDCCSR0_SST
) {
1837 ep_dbg(ep
, "clearing stall status\n");
1839 udc_ep_writel(ep
, UDCCSR
, UDCCSR0_SST
);
1843 if (udccsr0
& UDCCSR0_SA
) {
1845 set_ep0state(udc
, SETUP_STAGE
);
1848 switch (udc
->ep0state
) {
1849 case WAIT_FOR_SETUP
:
1851 * Hardware bug : beware, we cannot clear OPC, since we would
1852 * miss a potential OPC irq for a setup packet.
1853 * So, we only do ... nothing, and hope for a next irq with
1858 udccsr0
&= UDCCSR0_CTRL_REQ_MASK
;
1859 if (likely(udccsr0
== UDCCSR0_CTRL_REQ_MASK
))
1860 handle_ep0_ctrl_req(udc
, req
);
1862 case IN_DATA_STAGE
: /* GET_DESCRIPTOR */
1863 if (epout_has_pkt(ep
))
1864 udc_ep_writel(ep
, UDCCSR
, UDCCSR0_OPC
);
1865 if (req
&& !ep_is_full(ep
))
1866 completed
= write_ep0_fifo(ep
, req
);
1868 ep0_end_in_req(ep
, req
);
1870 case OUT_DATA_STAGE
: /* SET_DESCRIPTOR */
1871 if (epout_has_pkt(ep
) && req
)
1872 completed
= read_ep0_fifo(ep
, req
);
1874 ep0_end_out_req(ep
, req
);
1877 udc_ep_writel(ep
, UDCCSR
, UDCCSR0_FST
);
1879 case IN_STATUS_STAGE
:
1881 * Hardware bug : beware, we cannot clear OPC, since we would
1882 * miss a potential PC irq for a setup packet.
1883 * So, we only put the ep0 into WAIT_FOR_SETUP state.
1888 case OUT_STATUS_STAGE
:
1889 case WAIT_ACK_SET_CONF_INTERF
:
1890 ep_warn(ep
, "should never get in %s state here!!!\n",
1891 EP0_STNAME(ep
->dev
));
1898 * handle_ep - Handle endpoint data tranfers
1899 * @ep: pxa physical endpoint
1901 * Tries to transfer all pending request data into the endpoint and/or
1902 * transfer all pending data in the endpoint into usb requests.
1904 * Is always called when in_interrupt() or with ep->lock held.
1906 static void handle_ep(struct pxa_ep
*ep
)
1908 struct pxa27x_request
*req
;
1911 int is_in
= ep
->dir_in
;
1916 udccsr
= udc_ep_readl(ep
, UDCCSR
);
1917 if (likely(!list_empty(&ep
->queue
)))
1918 req
= list_entry(ep
->queue
.next
,
1919 struct pxa27x_request
, queue
);
1923 ep_dbg(ep
, "req:%p, udccsr 0x%03x loop=%d\n",
1924 req
, udccsr
, loop
++);
1926 if (unlikely(udccsr
& (UDCCSR_SST
| UDCCSR_TRN
)))
1927 udc_ep_writel(ep
, UDCCSR
,
1928 udccsr
& (UDCCSR_SST
| UDCCSR_TRN
));
1932 if (unlikely(is_in
)) {
1933 if (likely(!ep_is_full(ep
)))
1934 completed
= write_fifo(ep
, req
);
1936 ep_end_in_req(ep
, req
);
1938 if (likely(epout_has_pkt(ep
)))
1939 completed
= read_fifo(ep
, req
);
1941 ep_end_out_req(ep
, req
);
1943 } while (completed
);
1947 * pxa27x_change_configuration - Handle SET_CONF usb request notification
1949 * @config: usb configuration
1951 * Post the request to upper level.
1952 * Don't use any pxa specific harware configuration capabilities
1954 static void pxa27x_change_configuration(struct pxa_udc
*udc
, int config
)
1956 struct usb_ctrlrequest req
;
1958 dev_dbg(udc
->dev
, "config=%d\n", config
);
1960 udc
->config
= config
;
1961 udc
->last_interface
= 0;
1962 udc
->last_alternate
= 0;
1964 req
.bRequestType
= 0;
1965 req
.bRequest
= USB_REQ_SET_CONFIGURATION
;
1966 req
.wValue
= config
;
1970 set_ep0state(udc
, WAIT_ACK_SET_CONF_INTERF
);
1971 udc
->driver
->setup(&udc
->gadget
, &req
);
1975 * pxa27x_change_interface - Handle SET_INTERF usb request notification
1977 * @iface: interface number
1978 * @alt: alternate setting number
1980 * Post the request to upper level.
1981 * Don't use any pxa specific harware configuration capabilities
1983 static void pxa27x_change_interface(struct pxa_udc
*udc
, int iface
, int alt
)
1985 struct usb_ctrlrequest req
;
1987 dev_dbg(udc
->dev
, "interface=%d, alternate setting=%d\n", iface
, alt
);
1989 udc
->last_interface
= iface
;
1990 udc
->last_alternate
= alt
;
1992 req
.bRequestType
= USB_RECIP_INTERFACE
;
1993 req
.bRequest
= USB_REQ_SET_INTERFACE
;
1998 set_ep0state(udc
, WAIT_ACK_SET_CONF_INTERF
);
1999 udc
->driver
->setup(&udc
->gadget
, &req
);
2003 * irq_handle_data - Handle data transfer
2004 * @irq: irq IRQ number
2005 * @udc: dev pxa_udc device structure
2007 * Called from irq handler, transferts data to or from endpoint to queue
2009 static void irq_handle_data(int irq
, struct pxa_udc
*udc
)
2013 u32 udcisr0
= udc_readl(udc
, UDCISR0
) & UDCCISR0_EP_MASK
;
2014 u32 udcisr1
= udc_readl(udc
, UDCISR1
) & UDCCISR1_EP_MASK
;
2016 if (udcisr0
& UDCISR_INT_MASK
) {
2017 udc
->pxa_ep
[0].stats
.irqs
++;
2018 udc_writel(udc
, UDCISR0
, UDCISR_INT(0, UDCISR_INT_MASK
));
2019 handle_ep0(udc
, !!(udcisr0
& UDCICR_FIFOERR
),
2020 !!(udcisr0
& UDCICR_PKTCOMPL
));
2024 for (i
= 1; udcisr0
!= 0 && i
< 16; udcisr0
>>= 2, i
++) {
2025 if (!(udcisr0
& UDCISR_INT_MASK
))
2028 udc_writel(udc
, UDCISR0
, UDCISR_INT(i
, UDCISR_INT_MASK
));
2029 ep
= &udc
->pxa_ep
[i
];
2034 for (i
= 16; udcisr1
!= 0 && i
< 24; udcisr1
>>= 2, i
++) {
2035 udc_writel(udc
, UDCISR1
, UDCISR_INT(i
- 16, UDCISR_INT_MASK
));
2036 if (!(udcisr1
& UDCISR_INT_MASK
))
2039 ep
= &udc
->pxa_ep
[i
];
2047 * irq_udc_suspend - Handle IRQ "UDC Suspend"
2050 static void irq_udc_suspend(struct pxa_udc
*udc
)
2052 udc_writel(udc
, UDCISR1
, UDCISR1_IRSU
);
2053 udc
->stats
.irqs_suspend
++;
2055 if (udc
->gadget
.speed
!= USB_SPEED_UNKNOWN
2056 && udc
->driver
&& udc
->driver
->suspend
)
2057 udc
->driver
->suspend(&udc
->gadget
);
2062 * irq_udc_resume - Handle IRQ "UDC Resume"
2065 static void irq_udc_resume(struct pxa_udc
*udc
)
2067 udc_writel(udc
, UDCISR1
, UDCISR1_IRRU
);
2068 udc
->stats
.irqs_resume
++;
2070 if (udc
->gadget
.speed
!= USB_SPEED_UNKNOWN
2071 && udc
->driver
&& udc
->driver
->resume
)
2072 udc
->driver
->resume(&udc
->gadget
);
2076 * irq_udc_reconfig - Handle IRQ "UDC Change Configuration"
2079 static void irq_udc_reconfig(struct pxa_udc
*udc
)
2081 unsigned config
, interface
, alternate
, config_change
;
2082 u32 udccr
= udc_readl(udc
, UDCCR
);
2084 udc_writel(udc
, UDCISR1
, UDCISR1_IRCC
);
2085 udc
->stats
.irqs_reconfig
++;
2087 config
= (udccr
& UDCCR_ACN
) >> UDCCR_ACN_S
;
2088 config_change
= (config
!= udc
->config
);
2089 pxa27x_change_configuration(udc
, config
);
2091 interface
= (udccr
& UDCCR_AIN
) >> UDCCR_AIN_S
;
2092 alternate
= (udccr
& UDCCR_AAISN
) >> UDCCR_AAISN_S
;
2093 pxa27x_change_interface(udc
, interface
, alternate
);
2096 update_pxa_ep_matches(udc
);
2097 udc_set_mask_UDCCR(udc
, UDCCR_SMAC
);
2101 * irq_udc_reset - Handle IRQ "UDC Reset"
2104 static void irq_udc_reset(struct pxa_udc
*udc
)
2106 u32 udccr
= udc_readl(udc
, UDCCR
);
2107 struct pxa_ep
*ep
= &udc
->pxa_ep
[0];
2109 dev_info(udc
->dev
, "USB reset\n");
2110 udc_writel(udc
, UDCISR1
, UDCISR1_IRRS
);
2111 udc
->stats
.irqs_reset
++;
2113 if ((udccr
& UDCCR_UDA
) == 0) {
2114 dev_dbg(udc
->dev
, "USB reset start\n");
2115 stop_activity(udc
, udc
->driver
);
2117 udc
->gadget
.speed
= USB_SPEED_FULL
;
2118 memset(&udc
->stats
, 0, sizeof udc
->stats
);
2121 udc_ep_writel(ep
, UDCCSR
, UDCCSR0_FTF
| UDCCSR0_OPC
);
2126 * pxa_udc_irq - Main irq handler
2130 * Handles all udc interrupts
2132 static irqreturn_t
pxa_udc_irq(int irq
, void *_dev
)
2134 struct pxa_udc
*udc
= _dev
;
2135 u32 udcisr0
= udc_readl(udc
, UDCISR0
);
2136 u32 udcisr1
= udc_readl(udc
, UDCISR1
);
2137 u32 udccr
= udc_readl(udc
, UDCCR
);
2140 dev_vdbg(udc
->dev
, "Interrupt, UDCISR0:0x%08x, UDCISR1:0x%08x, "
2141 "UDCCR:0x%08x\n", udcisr0
, udcisr1
, udccr
);
2143 udcisr1_spec
= udcisr1
& 0xf8000000;
2144 if (unlikely(udcisr1_spec
& UDCISR1_IRSU
))
2145 irq_udc_suspend(udc
);
2146 if (unlikely(udcisr1_spec
& UDCISR1_IRRU
))
2147 irq_udc_resume(udc
);
2148 if (unlikely(udcisr1_spec
& UDCISR1_IRCC
))
2149 irq_udc_reconfig(udc
);
2150 if (unlikely(udcisr1_spec
& UDCISR1_IRRS
))
2153 if ((udcisr0
& UDCCISR0_EP_MASK
) | (udcisr1
& UDCCISR1_EP_MASK
))
2154 irq_handle_data(irq
, udc
);
2159 static struct pxa_udc memory
= {
2161 .ops
= &pxa_udc_ops
,
2162 .ep0
= &memory
.udc_usb_ep
[0].usb_ep
,
2163 .name
= driver_name
,
2180 /* Endpoints for gadget zero */
2181 PXA_EP_OUT_BULK(1, 1, 3, 0, 0),
2182 PXA_EP_IN_BULK(2, 2, 3, 0, 0),
2183 /* Endpoints for ether gadget, file storage gadget */
2184 PXA_EP_OUT_BULK(3, 1, 1, 0, 0),
2185 PXA_EP_IN_BULK(4, 2, 1, 0, 0),
2186 PXA_EP_IN_ISO(5, 3, 1, 0, 0),
2187 PXA_EP_OUT_ISO(6, 4, 1, 0, 0),
2188 PXA_EP_IN_INT(7, 5, 1, 0, 0),
2189 /* Endpoints for RNDIS, serial */
2190 PXA_EP_OUT_BULK(8, 1, 2, 0, 0),
2191 PXA_EP_IN_BULK(9, 2, 2, 0, 0),
2192 PXA_EP_IN_INT(10, 5, 2, 0, 0),
2194 * All the following endpoints are only for completion. They
2195 * won't never work, as multiple interfaces are really broken on
2198 PXA_EP_OUT_BULK(11, 1, 2, 1, 0),
2199 PXA_EP_IN_BULK(12, 2, 2, 1, 0),
2200 /* Endpoint for CDC Ether */
2201 PXA_EP_OUT_BULK(13, 1, 1, 1, 1),
2202 PXA_EP_IN_BULK(14, 2, 1, 1, 1),
2207 * pxa_udc_probe - probes the udc device
2208 * @_dev: platform device
2210 * Perform basic init : allocates udc clock, creates sysfs files, requests
2213 static int __init
pxa_udc_probe(struct platform_device
*pdev
)
2215 struct resource
*regs
;
2216 struct pxa_udc
*udc
= &memory
;
2219 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2222 udc
->irq
= platform_get_irq(pdev
, 0);
2226 udc
->dev
= &pdev
->dev
;
2227 udc
->mach
= pdev
->dev
.platform_data
;
2229 udc
->clk
= clk_get(&pdev
->dev
, "UDCCLK");
2230 if (IS_ERR(udc
->clk
)) {
2231 retval
= PTR_ERR(udc
->clk
);
2236 udc
->regs
= ioremap(regs
->start
, regs
->end
- regs
->start
+ 1);
2238 dev_err(&pdev
->dev
, "Unable to map UDC I/O memory\n");
2242 device_initialize(&udc
->gadget
.dev
);
2243 udc
->gadget
.dev
.parent
= &pdev
->dev
;
2244 udc
->gadget
.dev
.dma_mask
= NULL
;
2246 the_controller
= udc
;
2247 platform_set_drvdata(pdev
, udc
);
2251 /* irq setup after old hardware state is cleaned up */
2252 retval
= request_irq(udc
->irq
, pxa_udc_irq
,
2253 IRQF_SHARED
, driver_name
, udc
);
2255 dev_err(udc
->dev
, "%s: can't get irq %i, err %d\n",
2256 driver_name
, IRQ_USB
, retval
);
2260 pxa_init_debugfs(udc
);
2272 * pxa_udc_remove - removes the udc device driver
2273 * @_dev: platform device
2275 static int __exit
pxa_udc_remove(struct platform_device
*_dev
)
2277 struct pxa_udc
*udc
= platform_get_drvdata(_dev
);
2279 usb_gadget_unregister_driver(udc
->driver
);
2280 free_irq(udc
->irq
, udc
);
2281 pxa_cleanup_debugfs(udc
);
2283 platform_set_drvdata(_dev
, NULL
);
2284 the_controller
= NULL
;
2290 static void pxa_udc_shutdown(struct platform_device
*_dev
)
2292 struct pxa_udc
*udc
= platform_get_drvdata(_dev
);
2294 if (udc_readl(udc
, UDCCR
) & UDCCR_UDE
)
2300 * pxa_udc_suspend - Suspend udc device
2301 * @_dev: platform device
2302 * @state: suspend state
2304 * Suspends udc : saves configuration registers (UDCCR*), then disables the udc
2307 static int pxa_udc_suspend(struct platform_device
*_dev
, pm_message_t state
)
2310 struct pxa_udc
*udc
= platform_get_drvdata(_dev
);
2313 ep
= &udc
->pxa_ep
[0];
2314 udc
->udccsr0
= udc_ep_readl(ep
, UDCCSR
);
2315 for (i
= 1; i
< NR_PXA_ENDPOINTS
; i
++) {
2316 ep
= &udc
->pxa_ep
[i
];
2317 ep
->udccsr_value
= udc_ep_readl(ep
, UDCCSR
);
2318 ep
->udccr_value
= udc_ep_readl(ep
, UDCCR
);
2319 ep_dbg(ep
, "udccsr:0x%03x, udccr:0x%x\n",
2320 ep
->udccsr_value
, ep
->udccr_value
);
2329 * pxa_udc_resume - Resume udc device
2330 * @_dev: platform device
2332 * Resumes udc : restores configuration registers (UDCCR*), then enables the udc
2335 static int pxa_udc_resume(struct platform_device
*_dev
)
2338 struct pxa_udc
*udc
= platform_get_drvdata(_dev
);
2341 ep
= &udc
->pxa_ep
[0];
2342 udc_ep_writel(ep
, UDCCSR
, udc
->udccsr0
& (UDCCSR0_FST
| UDCCSR0_DME
));
2343 for (i
= 1; i
< NR_PXA_ENDPOINTS
; i
++) {
2344 ep
= &udc
->pxa_ep
[i
];
2345 udc_ep_writel(ep
, UDCCSR
, ep
->udccsr_value
);
2346 udc_ep_writel(ep
, UDCCR
, ep
->udccr_value
);
2347 ep_dbg(ep
, "udccsr:0x%03x, udccr:0x%x\n",
2348 ep
->udccsr_value
, ep
->udccr_value
);
2353 * We do not handle OTG yet.
2355 * OTGPH bit is set when sleep mode is entered.
2356 * it indicates that OTG pad is retaining its state.
2357 * Upon exit from sleep mode and before clearing OTGPH,
2358 * Software must configure the USB OTG pad, UDC, and UHC
2359 * to the state they were in before entering sleep mode.
2361 if (cpu_is_pxa27x())
2368 /* work with hotplug and coldplug */
2369 MODULE_ALIAS("platform:pxa27x-udc");
2371 static struct platform_driver udc_driver
= {
2373 .name
= "pxa27x-udc",
2374 .owner
= THIS_MODULE
,
2376 .remove
= __exit_p(pxa_udc_remove
),
2377 .shutdown
= pxa_udc_shutdown
,
2379 .suspend
= pxa_udc_suspend
,
2380 .resume
= pxa_udc_resume
2384 static int __init
udc_init(void)
2386 if (!cpu_is_pxa27x())
2389 printk(KERN_INFO
"%s: version %s\n", driver_name
, DRIVER_VERSION
);
2390 return platform_driver_probe(&udc_driver
, pxa_udc_probe
);
2392 module_init(udc_init
);
2395 static void __exit
udc_exit(void)
2397 platform_driver_unregister(&udc_driver
);
2399 module_exit(udc_exit
);
2401 MODULE_DESCRIPTION(DRIVER_DESC
);
2402 MODULE_AUTHOR("Robert Jarzmik");
2403 MODULE_LICENSE("GPL");